Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_reg_core

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.86 100.00 99.43 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.30 99.00 98.60 100.00 98.92 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr 100.00 100.00 100.00 100.00
u_alert_test_fatal_err 100.00 100.00
u_alert_test_fatal_prim_flash_alert 100.00 100.00
u_alert_test_fatal_std_err 100.00 100.00
u_alert_test_recov_err 100.00 100.00
u_alert_test_recov_prim_flash_alert 100.00 100.00
u_bank0_info0_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_he_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_he_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_he_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_he_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_he_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_he_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_ecc_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_erase_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_he_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_prog_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_rd_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_8_scramble_en_8 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_ecc_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_erase_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_he_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_prog_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_rd_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_page_cfg_9_scramble_en_9 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_0 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_1 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_2 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_3 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_4 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_5 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_6 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_7 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_8 100.00 100.00 100.00 100.00
u_bank0_info0_regwen_9 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_ecc_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_erase_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_he_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_prog_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_rd_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_page_cfg_scramble_en_0 100.00 100.00 100.00 100.00
u_bank0_info1_regwen 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_bank0_info2_regwen_0 100.00 100.00 100.00 100.00
u_bank0_info2_regwen_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_he_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_he_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_he_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_he_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_he_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_he_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_ecc_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_erase_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_he_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_prog_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_rd_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_8_scramble_en_8 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_ecc_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_erase_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_he_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_prog_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_rd_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_page_cfg_9_scramble_en_9 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_0 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_1 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_2 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_3 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_4 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_5 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_6 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_7 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_8 100.00 100.00 100.00 100.00
u_bank1_info0_regwen_9 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_ecc_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_erase_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_he_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_prog_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_rd_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_page_cfg_scramble_en_0 100.00 100.00 100.00 100.00
u_bank1_info1_regwen 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_page_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_bank1_info2_regwen_0 100.00 100.00 100.00 100.00
u_bank1_info2_regwen_1 100.00 100.00 100.00 100.00
u_bank_cfg_regwen 100.00 100.00 100.00 100.00
u_chk 100.00 100.00 100.00 100.00
u_control_erase_sel 100.00 100.00 100.00 100.00
u_control_info_sel 100.00 100.00 100.00 100.00
u_control_num 100.00 100.00 100.00 100.00
u_control_op 100.00 100.00 100.00 100.00
u_control_partition_sel 100.00 100.00 100.00 100.00
u_control_prog_sel 100.00 100.00 100.00 100.00
u_control_start 100.00 100.00 100.00 100.00
u_ctrl_regwen 100.00 100.00
u_curr_fifo_lvl_prog 100.00 100.00
u_curr_fifo_lvl_rd 100.00 100.00
u_debug_state 100.00 100.00
u_default_region_ecc_en 100.00 100.00 100.00 100.00
u_default_region_erase_en 100.00 100.00 100.00 100.00
u_default_region_he_en 100.00 100.00 100.00 100.00
u_default_region_prog_en 100.00 100.00 100.00 100.00
u_default_region_rd_en 100.00 100.00 100.00 100.00
u_default_region_scramble_en 100.00 100.00 100.00 100.00
u_dis 100.00 100.00 100.00 100.00
u_ecc_single_err_addr_0 100.00 100.00 100.00 100.00
u_ecc_single_err_addr_1 100.00 100.00 100.00 100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_0 100.00 100.00 100.00 100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_1 100.00 100.00 100.00 100.00
u_erase_suspend 100.00 100.00 100.00 100.00
u_err_addr 100.00 100.00 100.00 100.00
u_err_code_macro_err 88.89 100.00 66.67 100.00
u_err_code_mp_err 100.00 100.00 100.00 100.00
u_err_code_op_err 100.00 100.00 100.00 100.00
u_err_code_prog_err 100.00 100.00 100.00 100.00
u_err_code_prog_type_err 100.00 100.00 100.00 100.00
u_err_code_prog_win_err 100.00 100.00 100.00 100.00
u_err_code_rd_err 100.00 100.00 100.00 100.00
u_err_code_update_err 88.89 100.00 66.67 100.00
u_exec 100.00 100.00 100.00 100.00
u_fault_status_arb_err 96.30 88.89 100.00 100.00
u_fault_status_host_gnt_err 96.30 88.89 100.00 100.00
u_fault_status_mp_err 96.30 88.89 100.00 100.00
u_fault_status_op_err 96.30 88.89 100.00 100.00
u_fault_status_phy_relbl_err 97.22 100.00 91.67 100.00
u_fault_status_phy_storage_err 97.22 100.00 91.67 100.00
u_fault_status_prog_err 96.30 88.89 100.00 100.00
u_fault_status_prog_type_err 96.30 88.89 100.00 100.00
u_fault_status_prog_win_err 96.30 88.89 100.00 100.00
u_fault_status_rd_err 96.30 88.89 100.00 100.00
u_fault_status_seed_err 96.30 88.89 100.00 100.00
u_fault_status_spurious_ack 96.30 88.89 100.00 100.00
u_fifo_lvl_prog 100.00 100.00 100.00 100.00
u_fifo_lvl_rd 100.00 100.00 100.00 100.00
u_fifo_rst 100.00 100.00 100.00 100.00
u_hw_info_cfg_override_ecc_dis 100.00 100.00 100.00 100.00
u_hw_info_cfg_override_scramble_dis 100.00 100.00 100.00 100.00
u_init 100.00 100.00 100.00 100.00
u_intr_enable_corr_err 100.00 100.00 100.00 100.00
u_intr_enable_op_done 100.00 100.00 100.00 100.00
u_intr_enable_prog_empty 100.00 100.00 100.00 100.00
u_intr_enable_prog_lvl 100.00 100.00 100.00 100.00
u_intr_enable_rd_full 100.00 100.00 100.00 100.00
u_intr_enable_rd_lvl 100.00 100.00 100.00 100.00
u_intr_state_corr_err 100.00 100.00 100.00 100.00
u_intr_state_op_done 100.00 100.00 100.00 100.00
u_intr_state_prog_empty 62.59 77.78 50.00 60.00
u_intr_state_prog_lvl 62.59 77.78 50.00 60.00
u_intr_state_rd_full 62.59 77.78 50.00 60.00
u_intr_state_rd_lvl 62.59 77.78 50.00 60.00
u_intr_test_corr_err 100.00 100.00
u_intr_test_op_done 100.00 100.00
u_intr_test_prog_empty 100.00 100.00
u_intr_test_prog_lvl 100.00 100.00
u_intr_test_rd_full 100.00 100.00
u_intr_test_rd_lvl 100.00 100.00
u_mp_bank_cfg_shadowed_erase_en_0 96.88 100.00 87.50 100.00 100.00
u_mp_bank_cfg_shadowed_erase_en_1 96.88 100.00 87.50 100.00 100.00
u_mp_region_0_base_0 100.00 100.00 100.00 100.00
u_mp_region_0_size_0 100.00 100.00 100.00 100.00
u_mp_region_1_base_1 100.00 100.00 100.00 100.00
u_mp_region_1_size_1 100.00 100.00 100.00 100.00
u_mp_region_2_base_2 100.00 100.00 100.00 100.00
u_mp_region_2_size_2 100.00 100.00 100.00 100.00
u_mp_region_3_base_3 100.00 100.00 100.00 100.00
u_mp_region_3_size_3 100.00 100.00 100.00 100.00
u_mp_region_4_base_4 100.00 100.00 100.00 100.00
u_mp_region_4_size_4 100.00 100.00 100.00 100.00
u_mp_region_5_base_5 100.00 100.00 100.00 100.00
u_mp_region_5_size_5 100.00 100.00 100.00 100.00
u_mp_region_6_base_6 100.00 100.00 100.00 100.00
u_mp_region_6_size_6 100.00 100.00 100.00 100.00
u_mp_region_7_base_7 100.00 100.00 100.00 100.00
u_mp_region_7_size_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_ecc_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_erase_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_he_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_prog_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_rd_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_0_scramble_en_0 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_ecc_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_erase_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_he_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_prog_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_rd_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_1_scramble_en_1 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_ecc_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_erase_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_he_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_prog_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_rd_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_2_scramble_en_2 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_ecc_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_erase_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_he_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_prog_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_rd_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_3_scramble_en_3 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_ecc_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_erase_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_he_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_prog_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_rd_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_4_scramble_en_4 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_ecc_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_erase_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_he_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_prog_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_rd_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_5_scramble_en_5 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_ecc_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_erase_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_he_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_prog_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_rd_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_6_scramble_en_6 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_ecc_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_erase_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_he_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_prog_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_rd_en_7 100.00 100.00 100.00 100.00
u_mp_region_cfg_7_scramble_en_7 100.00 100.00 100.00 100.00
u_op_status_done 100.00 100.00 100.00 100.00
u_op_status_err 100.00 100.00 100.00 100.00
u_phy_alert_cfg_alert_ack 65.34 88.89 50.00 57.14
u_phy_alert_cfg_alert_trig 65.34 88.89 50.00 57.14
u_phy_status_init_wip 62.59 77.78 50.00 60.00
u_phy_status_prog_normal_avail 58.89 66.67 50.00 60.00
u_phy_status_prog_repair_avail 58.89 66.67 50.00 60.00
u_prim_reg_we_check 100.00 100.00 100.00
u_prog_type_en_normal 100.00 100.00 100.00 100.00
u_prog_type_en_repair 100.00 100.00 100.00 100.00
u_reg_if 98.49 98.72 95.24 100.00 100.00
u_region_cfg_regwen_0 100.00 100.00 100.00 100.00
u_region_cfg_regwen_1 100.00 100.00 100.00 100.00
u_region_cfg_regwen_2 100.00 100.00 100.00 100.00
u_region_cfg_regwen_3 100.00 100.00 100.00 100.00
u_region_cfg_regwen_4 100.00 100.00 100.00 100.00
u_region_cfg_regwen_5 100.00 100.00 100.00 100.00
u_region_cfg_regwen_6 100.00 100.00 100.00 100.00
u_region_cfg_regwen_7 100.00 100.00 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00
u_scratch 100.00 100.00 100.00 100.00
u_socket 94.37 96.05 89.53 91.89 100.00
u_status_init_wip 62.59 77.78 50.00 60.00
u_status_initialized 62.59 77.78 50.00 60.00
u_status_prog_empty 100.00 100.00 100.00 100.00
u_status_prog_full 100.00 100.00 100.00 100.00
u_status_rd_empty 100.00 100.00 100.00 100.00
u_status_rd_full 100.00 100.00 100.00 100.00
u_std_fault_status_arb_fsm_err 96.30 88.89 100.00 100.00
u_std_fault_status_ctrl_cnt_err 96.30 88.89 100.00 100.00
u_std_fault_status_fifo_err 96.30 88.89 100.00 100.00
u_std_fault_status_lcmgr_err 96.30 88.89 100.00 100.00
u_std_fault_status_lcmgr_intg_err 96.30 88.89 100.00 100.00
u_std_fault_status_phy_fsm_err 96.30 88.89 100.00 100.00
u_std_fault_status_prog_intg_err 96.30 88.89 100.00 100.00
u_std_fault_status_reg_intg_err 96.30 88.89 100.00 100.00
u_std_fault_status_storage_err 62.59 77.78 50.00 60.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_core_reg_top
Line No.TotalCoveredPercent
TOTAL11551155100.00
ALWAYS7744100.00
CONT_ASSIGN8611100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN10911100.00
CONT_ASSIGN11011100.00
ALWAYS13633100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17511100.00
CONT_ASSIGN135211100.00
CONT_ASSIGN136711100.00
CONT_ASSIGN138311100.00
CONT_ASSIGN139911100.00
CONT_ASSIGN141511100.00
CONT_ASSIGN143111100.00
CONT_ASSIGN144711100.00
CONT_ASSIGN145311100.00
CONT_ASSIGN146811100.00
CONT_ASSIGN148411100.00
CONT_ASSIGN150011100.00
CONT_ASSIGN151611100.00
CONT_ASSIGN153211100.00
CONT_ASSIGN163811100.00
CONT_ASSIGN183211100.00
CONT_ASSIGN186311100.00
CONT_ASSIGN218311100.00
CONT_ASSIGN237811100.00
CONT_ASSIGN257311100.00
CONT_ASSIGN276811100.00
CONT_ASSIGN296311100.00
CONT_ASSIGN315811100.00
CONT_ASSIGN335311100.00
CONT_ASSIGN354811100.00
CONT_ASSIGN374311100.00
CONT_ASSIGN380311100.00
CONT_ASSIGN386311100.00
CONT_ASSIGN392311100.00
CONT_ASSIGN398311100.00
CONT_ASSIGN404311100.00
CONT_ASSIGN410311100.00
CONT_ASSIGN416311100.00
CONT_ASSIGN467711100.00
CONT_ASSIGN487211100.00
CONT_ASSIGN506711100.00
CONT_ASSIGN526211100.00
CONT_ASSIGN545711100.00
CONT_ASSIGN565211100.00
CONT_ASSIGN584711100.00
CONT_ASSIGN604211100.00
CONT_ASSIGN623711100.00
CONT_ASSIGN643211100.00
CONT_ASSIGN665611100.00
CONT_ASSIGN690911100.00
CONT_ASSIGN710411100.00
CONT_ASSIGN758911100.00
CONT_ASSIGN778411100.00
CONT_ASSIGN797911100.00
CONT_ASSIGN817411100.00
CONT_ASSIGN836911100.00
CONT_ASSIGN856411100.00
CONT_ASSIGN875911100.00
CONT_ASSIGN895411100.00
CONT_ASSIGN914911100.00
CONT_ASSIGN934411100.00
CONT_ASSIGN956811100.00
CONT_ASSIGN982111100.00
CONT_ASSIGN1001611100.00
CONT_ASSIGN1029511100.00
ALWAYS11823109109100.00
CONT_ASSIGN1193411100.00
ALWAYS1193811100.00
CONT_ASSIGN1205011100.00
CONT_ASSIGN1205211100.00
CONT_ASSIGN1205411100.00
CONT_ASSIGN1205511100.00
CONT_ASSIGN1205711100.00
CONT_ASSIGN1205911100.00
CONT_ASSIGN1206111100.00
CONT_ASSIGN1206311100.00
CONT_ASSIGN1206511100.00
CONT_ASSIGN1206711100.00
CONT_ASSIGN1206811100.00
CONT_ASSIGN1207011100.00
CONT_ASSIGN1207211100.00
CONT_ASSIGN1207411100.00
CONT_ASSIGN1207611100.00
CONT_ASSIGN1207811100.00
CONT_ASSIGN1208011100.00
CONT_ASSIGN1208111100.00
CONT_ASSIGN1208311100.00
CONT_ASSIGN1208511100.00
CONT_ASSIGN1208711100.00
CONT_ASSIGN1208911100.00
CONT_ASSIGN1209111100.00
CONT_ASSIGN1209211100.00
CONT_ASSIGN1209411100.00
CONT_ASSIGN1209511100.00
CONT_ASSIGN1209711100.00
CONT_ASSIGN1209811100.00
CONT_ASSIGN1210011100.00
CONT_ASSIGN1210111100.00
CONT_ASSIGN1210211100.00
CONT_ASSIGN1210411100.00
CONT_ASSIGN1210611100.00
CONT_ASSIGN1210811100.00
CONT_ASSIGN1211011100.00
CONT_ASSIGN1211211100.00
CONT_ASSIGN1211411100.00
CONT_ASSIGN1211611100.00
CONT_ASSIGN1211711100.00
CONT_ASSIGN1211911100.00
CONT_ASSIGN1212011100.00
CONT_ASSIGN1212211100.00
CONT_ASSIGN1212411100.00
CONT_ASSIGN1212511100.00
CONT_ASSIGN1212711100.00
CONT_ASSIGN1212811100.00
CONT_ASSIGN1213011100.00
CONT_ASSIGN1213111100.00
CONT_ASSIGN1213311100.00
CONT_ASSIGN1213411100.00
CONT_ASSIGN1213611100.00
CONT_ASSIGN1213711100.00
CONT_ASSIGN1213911100.00
CONT_ASSIGN1214011100.00
CONT_ASSIGN1214211100.00
CONT_ASSIGN1214311100.00
CONT_ASSIGN1214511100.00
CONT_ASSIGN1214611100.00
CONT_ASSIGN1214811100.00
CONT_ASSIGN1214911100.00
CONT_ASSIGN1215111100.00
CONT_ASSIGN1215211100.00
CONT_ASSIGN1215411100.00
CONT_ASSIGN1215611100.00
CONT_ASSIGN1215811100.00
CONT_ASSIGN1216011100.00
CONT_ASSIGN1216211100.00
CONT_ASSIGN1216411100.00
CONT_ASSIGN1216611100.00
CONT_ASSIGN1216711100.00
CONT_ASSIGN1216911100.00
CONT_ASSIGN1217111100.00
CONT_ASSIGN1217311100.00
CONT_ASSIGN1217511100.00
CONT_ASSIGN1217711100.00
CONT_ASSIGN1217911100.00
CONT_ASSIGN1218111100.00
CONT_ASSIGN1218211100.00
CONT_ASSIGN1218411100.00
CONT_ASSIGN1218611100.00
CONT_ASSIGN1218811100.00
CONT_ASSIGN1219011100.00
CONT_ASSIGN1219211100.00
CONT_ASSIGN1219411100.00
CONT_ASSIGN1219611100.00
CONT_ASSIGN1219711100.00
CONT_ASSIGN1219911100.00
CONT_ASSIGN1220111100.00
CONT_ASSIGN1220311100.00
CONT_ASSIGN1220511100.00
CONT_ASSIGN1220711100.00
CONT_ASSIGN1220911100.00
CONT_ASSIGN1221111100.00
CONT_ASSIGN1221211100.00
CONT_ASSIGN1221411100.00
CONT_ASSIGN1221611100.00
CONT_ASSIGN1221811100.00
CONT_ASSIGN1222011100.00
CONT_ASSIGN1222211100.00
CONT_ASSIGN1222411100.00
CONT_ASSIGN1222611100.00
CONT_ASSIGN1222711100.00
CONT_ASSIGN1222911100.00
CONT_ASSIGN1223111100.00
CONT_ASSIGN1223311100.00
CONT_ASSIGN1223511100.00
CONT_ASSIGN1223711100.00
CONT_ASSIGN1223911100.00
CONT_ASSIGN1224111100.00
CONT_ASSIGN1224211100.00
CONT_ASSIGN1224411100.00
CONT_ASSIGN1224611100.00
CONT_ASSIGN1224811100.00
CONT_ASSIGN1225011100.00
CONT_ASSIGN1225211100.00
CONT_ASSIGN1225411100.00
CONT_ASSIGN1225611100.00
CONT_ASSIGN1225711100.00
CONT_ASSIGN1225911100.00
CONT_ASSIGN1226111100.00
CONT_ASSIGN1226311100.00
CONT_ASSIGN1226511100.00
CONT_ASSIGN1226711100.00
CONT_ASSIGN1226911100.00
CONT_ASSIGN1227111100.00
CONT_ASSIGN1227211100.00
CONT_ASSIGN1227411100.00
CONT_ASSIGN1227611100.00
CONT_ASSIGN1227711100.00
CONT_ASSIGN1227911100.00
CONT_ASSIGN1228111100.00
CONT_ASSIGN1228211100.00
CONT_ASSIGN1228411100.00
CONT_ASSIGN1228611100.00
CONT_ASSIGN1228711100.00
CONT_ASSIGN1228911100.00
CONT_ASSIGN1229111100.00
CONT_ASSIGN1229211100.00
CONT_ASSIGN1229411100.00
CONT_ASSIGN1229611100.00
CONT_ASSIGN1229711100.00
CONT_ASSIGN1229911100.00
CONT_ASSIGN1230111100.00
CONT_ASSIGN1230211100.00
CONT_ASSIGN1230411100.00
CONT_ASSIGN1230611100.00
CONT_ASSIGN1230711100.00
CONT_ASSIGN1230911100.00
CONT_ASSIGN1231111100.00
CONT_ASSIGN1231211100.00
CONT_ASSIGN1231411100.00
CONT_ASSIGN1231611100.00
CONT_ASSIGN1231811100.00
CONT_ASSIGN1232011100.00
CONT_ASSIGN1232211100.00
CONT_ASSIGN1232411100.00
CONT_ASSIGN1232511100.00
CONT_ASSIGN1232711100.00
CONT_ASSIGN1232811100.00
CONT_ASSIGN1233011100.00
CONT_ASSIGN1233111100.00
CONT_ASSIGN1233311100.00
CONT_ASSIGN1233411100.00
CONT_ASSIGN1233611100.00
CONT_ASSIGN1233711100.00
CONT_ASSIGN1233911100.00
CONT_ASSIGN1234011100.00
CONT_ASSIGN1234211100.00
CONT_ASSIGN1234311100.00
CONT_ASSIGN1234511100.00
CONT_ASSIGN1234611100.00
CONT_ASSIGN1234811100.00
CONT_ASSIGN1234911100.00
CONT_ASSIGN1235111100.00
CONT_ASSIGN1235211100.00
CONT_ASSIGN1235411100.00
CONT_ASSIGN1235511100.00
CONT_ASSIGN1235711100.00
CONT_ASSIGN1235911100.00
CONT_ASSIGN1236111100.00
CONT_ASSIGN1236311100.00
CONT_ASSIGN1236511100.00
CONT_ASSIGN1236711100.00
CONT_ASSIGN1236911100.00
CONT_ASSIGN1237011100.00
CONT_ASSIGN1237211100.00
CONT_ASSIGN1237411100.00
CONT_ASSIGN1237611100.00
CONT_ASSIGN1237811100.00
CONT_ASSIGN1238011100.00
CONT_ASSIGN1238211100.00
CONT_ASSIGN1238411100.00
CONT_ASSIGN1238511100.00
CONT_ASSIGN1238711100.00
CONT_ASSIGN1238911100.00
CONT_ASSIGN1239111100.00
CONT_ASSIGN1239311100.00
CONT_ASSIGN1239511100.00
CONT_ASSIGN1239711100.00
CONT_ASSIGN1239911100.00
CONT_ASSIGN1240011100.00
CONT_ASSIGN1240211100.00
CONT_ASSIGN1240411100.00
CONT_ASSIGN1240611100.00
CONT_ASSIGN1240811100.00
CONT_ASSIGN1241011100.00
CONT_ASSIGN1241211100.00
CONT_ASSIGN1241411100.00
CONT_ASSIGN1241511100.00
CONT_ASSIGN1241711100.00
CONT_ASSIGN1241911100.00
CONT_ASSIGN1242111100.00
CONT_ASSIGN1242311100.00
CONT_ASSIGN1242511100.00
CONT_ASSIGN1242711100.00
CONT_ASSIGN1242911100.00
CONT_ASSIGN1243011100.00
CONT_ASSIGN1243211100.00
CONT_ASSIGN1243411100.00
CONT_ASSIGN1243611100.00
CONT_ASSIGN1243811100.00
CONT_ASSIGN1244011100.00
CONT_ASSIGN1244211100.00
CONT_ASSIGN1244411100.00
CONT_ASSIGN1244511100.00
CONT_ASSIGN1244711100.00
CONT_ASSIGN1244911100.00
CONT_ASSIGN1245111100.00
CONT_ASSIGN1245311100.00
CONT_ASSIGN1245511100.00
CONT_ASSIGN1245711100.00
CONT_ASSIGN1245911100.00
CONT_ASSIGN1246011100.00
CONT_ASSIGN1246211100.00
CONT_ASSIGN1246411100.00
CONT_ASSIGN1246611100.00
CONT_ASSIGN1246811100.00
CONT_ASSIGN1247011100.00
CONT_ASSIGN1247211100.00
CONT_ASSIGN1247411100.00
CONT_ASSIGN1247511100.00
CONT_ASSIGN1247711100.00
CONT_ASSIGN1247911100.00
CONT_ASSIGN1248111100.00
CONT_ASSIGN1248311100.00
CONT_ASSIGN1248511100.00
CONT_ASSIGN1248711100.00
CONT_ASSIGN1248911100.00
CONT_ASSIGN1249011100.00
CONT_ASSIGN1249211100.00
CONT_ASSIGN1249411100.00
CONT_ASSIGN1249611100.00
CONT_ASSIGN1249811100.00
CONT_ASSIGN1250011100.00
CONT_ASSIGN1250211100.00
CONT_ASSIGN1250411100.00
CONT_ASSIGN1250511100.00
CONT_ASSIGN1250711100.00
CONT_ASSIGN1250811100.00
CONT_ASSIGN1251011100.00
CONT_ASSIGN1251211100.00
CONT_ASSIGN1251411100.00
CONT_ASSIGN1251611100.00
CONT_ASSIGN1251811100.00
CONT_ASSIGN1252011100.00
CONT_ASSIGN1252211100.00
CONT_ASSIGN1252311100.00
CONT_ASSIGN1252511100.00
CONT_ASSIGN1252611100.00
CONT_ASSIGN1252811100.00
CONT_ASSIGN1252911100.00
CONT_ASSIGN1253111100.00
CONT_ASSIGN1253311100.00
CONT_ASSIGN1253511100.00
CONT_ASSIGN1253711100.00
CONT_ASSIGN1253911100.00
CONT_ASSIGN1254111100.00
CONT_ASSIGN1254311100.00
CONT_ASSIGN1254411100.00
CONT_ASSIGN1254611100.00
CONT_ASSIGN1254811100.00
CONT_ASSIGN1255011100.00
CONT_ASSIGN1255211100.00
CONT_ASSIGN1255411100.00
CONT_ASSIGN1255611100.00
CONT_ASSIGN1255811100.00
CONT_ASSIGN1255911100.00
CONT_ASSIGN1256111100.00
CONT_ASSIGN1256211100.00
CONT_ASSIGN1256411100.00
CONT_ASSIGN1256511100.00
CONT_ASSIGN1256711100.00
CONT_ASSIGN1256811100.00
CONT_ASSIGN1257011100.00
CONT_ASSIGN1257111100.00
CONT_ASSIGN1257311100.00
CONT_ASSIGN1257411100.00
CONT_ASSIGN1257611100.00
CONT_ASSIGN1257711100.00
CONT_ASSIGN1257911100.00
CONT_ASSIGN1258011100.00
CONT_ASSIGN1258211100.00
CONT_ASSIGN1258311100.00
CONT_ASSIGN1258511100.00
CONT_ASSIGN1258611100.00
CONT_ASSIGN1258811100.00
CONT_ASSIGN1258911100.00
CONT_ASSIGN1259111100.00
CONT_ASSIGN1259311100.00
CONT_ASSIGN1259511100.00
CONT_ASSIGN1259711100.00
CONT_ASSIGN1259911100.00
CONT_ASSIGN1260111100.00
CONT_ASSIGN1260311100.00
CONT_ASSIGN1260411100.00
CONT_ASSIGN1260611100.00
CONT_ASSIGN1260811100.00
CONT_ASSIGN1261011100.00
CONT_ASSIGN1261211100.00
CONT_ASSIGN1261411100.00
CONT_ASSIGN1261611100.00
CONT_ASSIGN1261811100.00
CONT_ASSIGN1261911100.00
CONT_ASSIGN1262111100.00
CONT_ASSIGN1262311100.00
CONT_ASSIGN1262511100.00
CONT_ASSIGN1262711100.00
CONT_ASSIGN1262911100.00
CONT_ASSIGN1263111100.00
CONT_ASSIGN1263311100.00
CONT_ASSIGN1263411100.00
CONT_ASSIGN1263611100.00
CONT_ASSIGN1263811100.00
CONT_ASSIGN1264011100.00
CONT_ASSIGN1264211100.00
CONT_ASSIGN1264411100.00
CONT_ASSIGN1264611100.00
CONT_ASSIGN1264811100.00
CONT_ASSIGN1264911100.00
CONT_ASSIGN1265111100.00
CONT_ASSIGN1265311100.00
CONT_ASSIGN1265511100.00
CONT_ASSIGN1265711100.00
CONT_ASSIGN1265911100.00
CONT_ASSIGN1266111100.00
CONT_ASSIGN1266311100.00
CONT_ASSIGN1266411100.00
CONT_ASSIGN1266611100.00
CONT_ASSIGN1266811100.00
CONT_ASSIGN1267011100.00
CONT_ASSIGN1267211100.00
CONT_ASSIGN1267411100.00
CONT_ASSIGN1267611100.00
CONT_ASSIGN1267811100.00
CONT_ASSIGN1267911100.00
CONT_ASSIGN1268111100.00
CONT_ASSIGN1268311100.00
CONT_ASSIGN1268511100.00
CONT_ASSIGN1268711100.00
CONT_ASSIGN1268911100.00
CONT_ASSIGN1269111100.00
CONT_ASSIGN1269311100.00
CONT_ASSIGN1269411100.00
CONT_ASSIGN1269611100.00
CONT_ASSIGN1269811100.00
CONT_ASSIGN1270011100.00
CONT_ASSIGN1270211100.00
CONT_ASSIGN1270411100.00
CONT_ASSIGN1270611100.00
CONT_ASSIGN1270811100.00
CONT_ASSIGN1270911100.00
CONT_ASSIGN1271111100.00
CONT_ASSIGN1271311100.00
CONT_ASSIGN1271511100.00
CONT_ASSIGN1271711100.00
CONT_ASSIGN1271911100.00
CONT_ASSIGN1272111100.00
CONT_ASSIGN1272311100.00
CONT_ASSIGN1272411100.00
CONT_ASSIGN1272611100.00
CONT_ASSIGN1272811100.00
CONT_ASSIGN1273011100.00
CONT_ASSIGN1273211100.00
CONT_ASSIGN1273411100.00
CONT_ASSIGN1273611100.00
CONT_ASSIGN1273811100.00
CONT_ASSIGN1273911100.00
CONT_ASSIGN1274111100.00
CONT_ASSIGN1274211100.00
CONT_ASSIGN1274411100.00
CONT_ASSIGN1274611100.00
CONT_ASSIGN1274811100.00
CONT_ASSIGN1275011100.00
CONT_ASSIGN1275211100.00
CONT_ASSIGN1275411100.00
CONT_ASSIGN1275611100.00
CONT_ASSIGN1275711100.00
CONT_ASSIGN1275911100.00
CONT_ASSIGN1276011100.00
CONT_ASSIGN1276211100.00
CONT_ASSIGN1276311100.00
CONT_ASSIGN1276511100.00
CONT_ASSIGN1276711100.00
CONT_ASSIGN1276911100.00
CONT_ASSIGN1277111100.00
CONT_ASSIGN1277311100.00
CONT_ASSIGN1277511100.00
CONT_ASSIGN1277711100.00
CONT_ASSIGN1277811100.00
CONT_ASSIGN1278011100.00
CONT_ASSIGN1278211100.00
CONT_ASSIGN1278411100.00
CONT_ASSIGN1278611100.00
CONT_ASSIGN1278811100.00
CONT_ASSIGN1279011100.00
CONT_ASSIGN1279211100.00
CONT_ASSIGN1279311100.00
CONT_ASSIGN1279511100.00
CONT_ASSIGN1279711100.00
CONT_ASSIGN1279811100.00
CONT_ASSIGN1280011100.00
CONT_ASSIGN1280111100.00
CONT_ASSIGN1280211100.00
CONT_ASSIGN1280411100.00
CONT_ASSIGN1280611100.00
CONT_ASSIGN1280711100.00
CONT_ASSIGN1280911100.00
CONT_ASSIGN1281111100.00
CONT_ASSIGN1281211100.00
CONT_ASSIGN1281311100.00
CONT_ASSIGN1281511100.00
CONT_ASSIGN1281711100.00
CONT_ASSIGN1281911100.00
CONT_ASSIGN1282111100.00
CONT_ASSIGN1282311100.00
CONT_ASSIGN1282511100.00
CONT_ASSIGN1282711100.00
CONT_ASSIGN1282911100.00
CONT_ASSIGN1283011100.00
CONT_ASSIGN1283211100.00
CONT_ASSIGN1283411100.00
CONT_ASSIGN1283511100.00
CONT_ASSIGN1283711100.00
CONT_ASSIGN1283911100.00
CONT_ASSIGN1284011100.00
CONT_ASSIGN1284211100.00
CONT_ASSIGN1284411100.00
CONT_ASSIGN1284511100.00
CONT_ASSIGN1284711100.00
CONT_ASSIGN1284811100.00
CONT_ASSIGN1285011100.00
CONT_ASSIGN1285211100.00
CONT_ASSIGN1285311100.00
CONT_ASSIGN1285511100.00
CONT_ASSIGN1285611100.00
ALWAYS12860109109100.00
ALWAYS12973393393100.00
ALWAYS1370133100.00
ALWAYS1370933100.00
CONT_ASSIGN1371711100.00
CONT_ASSIGN1372011100.00
CONT_ASSIGN1372411100.00
CONT_ASSIGN1373011100.00
CONT_ASSIGN1373811100.00
CONT_ASSIGN1373911100.00

Click here to see the source line report.

Cond Coverage for Module : flash_ctrl_core_reg_top
TotalCoveredPercent
Conditions1228122199.43
Logical1228122199.43
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
67-1189799.67
11898-11938100.00
11938-12227100.00
12242-1371798.07

Branch Coverage for Module : flash_ctrl_core_reg_top
Line No.TotalCoveredPercent
Branches 123 123 100.00
TERNARY 11934 2 2 100.00
IF 77 3 3 100.00
TERNARY 136 3 3 100.00
IF 143 2 2 100.00
CASE 12974 109 109 100.00
IF 13701 2 2 100.00
IF 13709 2 2 100.00


11934 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


77 if (!rst_ni) begin -1- 78 err_q <= '0; ==> 79 end else if (intg_err || reg_we_err) begin -2- 80 err_q <= 1'b1; ==> 81 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T16,T17,T53
0 0 Covered T1,T2,T3


136 reg_steer = 137 tl_i.a_address[AW-1:0] inside {[432:435]} ? 2'd0 : -1- ==> 138 tl_i.a_address[AW-1:0] inside {[436:439]} ? 2'd1 : -2- ==> ==>

Branches:
-1--2-StatusTests
1 - Covered T2,T3,T13
0 1 Covered T2,T3,T13
0 0 Covered T1,T2,T3


143 if (intg_err) begin -1- 144 reg_steer = 2'd2; ==> 145 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T237,T238,T239
0 Covered T1,T2,T3


12974 unique case (1'b1) -1- 12975 addr_hit[0]: begin 12976 reg_rdata_next[0] = intr_state_prog_empty_qs; ==> 12977 reg_rdata_next[1] = intr_state_prog_lvl_qs; 12978 reg_rdata_next[2] = intr_state_rd_full_qs; 12979 reg_rdata_next[3] = intr_state_rd_lvl_qs; 12980 reg_rdata_next[4] = intr_state_op_done_qs; 12981 reg_rdata_next[5] = intr_state_corr_err_qs; 12982 end 12983 12984 addr_hit[1]: begin 12985 reg_rdata_next[0] = intr_enable_prog_empty_qs; ==> 12986 reg_rdata_next[1] = intr_enable_prog_lvl_qs; 12987 reg_rdata_next[2] = intr_enable_rd_full_qs; 12988 reg_rdata_next[3] = intr_enable_rd_lvl_qs; 12989 reg_rdata_next[4] = intr_enable_op_done_qs; 12990 reg_rdata_next[5] = intr_enable_corr_err_qs; 12991 end 12992 12993 addr_hit[2]: begin 12994 reg_rdata_next[0] = '0; ==> 12995 reg_rdata_next[1] = '0; 12996 reg_rdata_next[2] = '0; 12997 reg_rdata_next[3] = '0; 12998 reg_rdata_next[4] = '0; 12999 reg_rdata_next[5] = '0; 13000 end 13001 13002 addr_hit[3]: begin 13003 reg_rdata_next[0] = '0; ==> 13004 reg_rdata_next[1] = '0; 13005 reg_rdata_next[2] = '0; 13006 reg_rdata_next[3] = '0; 13007 reg_rdata_next[4] = '0; 13008 end 13009 13010 addr_hit[4]: begin 13011 reg_rdata_next[3:0] = dis_qs; ==> 13012 end 13013 13014 addr_hit[5]: begin 13015 reg_rdata_next[31:0] = exec_qs; ==> 13016 end 13017 13018 addr_hit[6]: begin 13019 reg_rdata_next[0] = init_qs; ==> 13020 end 13021 13022 addr_hit[7]: begin 13023 reg_rdata_next[0] = ctrl_regwen_qs; ==> 13024 end 13025 13026 addr_hit[8]: begin 13027 reg_rdata_next[0] = control_start_qs; ==> 13028 reg_rdata_next[5:4] = control_op_qs; 13029 reg_rdata_next[6] = control_prog_sel_qs; 13030 reg_rdata_next[7] = control_erase_sel_qs; 13031 reg_rdata_next[8] = control_partition_sel_qs; 13032 reg_rdata_next[10:9] = control_info_sel_qs; 13033 reg_rdata_next[27:16] = control_num_qs; 13034 end 13035 13036 addr_hit[9]: begin 13037 reg_rdata_next[19:0] = addr_qs; ==> 13038 end 13039 13040 addr_hit[10]: begin 13041 reg_rdata_next[0] = prog_type_en_normal_qs; ==> 13042 reg_rdata_next[1] = prog_type_en_repair_qs; 13043 end 13044 13045 addr_hit[11]: begin 13046 reg_rdata_next[0] = erase_suspend_qs; ==> 13047 end 13048 13049 addr_hit[12]: begin 13050 reg_rdata_next[0] = region_cfg_regwen_0_qs; ==> 13051 end 13052 13053 addr_hit[13]: begin 13054 reg_rdata_next[0] = region_cfg_regwen_1_qs; ==> 13055 end 13056 13057 addr_hit[14]: begin 13058 reg_rdata_next[0] = region_cfg_regwen_2_qs; ==> 13059 end 13060 13061 addr_hit[15]: begin 13062 reg_rdata_next[0] = region_cfg_regwen_3_qs; ==> 13063 end 13064 13065 addr_hit[16]: begin 13066 reg_rdata_next[0] = region_cfg_regwen_4_qs; ==> 13067 end 13068 13069 addr_hit[17]: begin 13070 reg_rdata_next[0] = region_cfg_regwen_5_qs; ==> 13071 end 13072 13073 addr_hit[18]: begin 13074 reg_rdata_next[0] = region_cfg_regwen_6_qs; ==> 13075 end 13076 13077 addr_hit[19]: begin 13078 reg_rdata_next[0] = region_cfg_regwen_7_qs; ==> 13079 end 13080 13081 addr_hit[20]: begin 13082 reg_rdata_next[3:0] = mp_region_cfg_0_en_0_qs; ==> 13083 reg_rdata_next[7:4] = mp_region_cfg_0_rd_en_0_qs; 13084 reg_rdata_next[11:8] = mp_region_cfg_0_prog_en_0_qs; 13085 reg_rdata_next[15:12] = mp_region_cfg_0_erase_en_0_qs; 13086 reg_rdata_next[19:16] = mp_region_cfg_0_scramble_en_0_qs; 13087 reg_rdata_next[23:20] = mp_region_cfg_0_ecc_en_0_qs; 13088 reg_rdata_next[27:24] = mp_region_cfg_0_he_en_0_qs; 13089 end 13090 13091 addr_hit[21]: begin 13092 reg_rdata_next[3:0] = mp_region_cfg_1_en_1_qs; ==> 13093 reg_rdata_next[7:4] = mp_region_cfg_1_rd_en_1_qs; 13094 reg_rdata_next[11:8] = mp_region_cfg_1_prog_en_1_qs; 13095 reg_rdata_next[15:12] = mp_region_cfg_1_erase_en_1_qs; 13096 reg_rdata_next[19:16] = mp_region_cfg_1_scramble_en_1_qs; 13097 reg_rdata_next[23:20] = mp_region_cfg_1_ecc_en_1_qs; 13098 reg_rdata_next[27:24] = mp_region_cfg_1_he_en_1_qs; 13099 end 13100 13101 addr_hit[22]: begin 13102 reg_rdata_next[3:0] = mp_region_cfg_2_en_2_qs; ==> 13103 reg_rdata_next[7:4] = mp_region_cfg_2_rd_en_2_qs; 13104 reg_rdata_next[11:8] = mp_region_cfg_2_prog_en_2_qs; 13105 reg_rdata_next[15:12] = mp_region_cfg_2_erase_en_2_qs; 13106 reg_rdata_next[19:16] = mp_region_cfg_2_scramble_en_2_qs; 13107 reg_rdata_next[23:20] = mp_region_cfg_2_ecc_en_2_qs; 13108 reg_rdata_next[27:24] = mp_region_cfg_2_he_en_2_qs; 13109 end 13110 13111 addr_hit[23]: begin 13112 reg_rdata_next[3:0] = mp_region_cfg_3_en_3_qs; ==> 13113 reg_rdata_next[7:4] = mp_region_cfg_3_rd_en_3_qs; 13114 reg_rdata_next[11:8] = mp_region_cfg_3_prog_en_3_qs; 13115 reg_rdata_next[15:12] = mp_region_cfg_3_erase_en_3_qs; 13116 reg_rdata_next[19:16] = mp_region_cfg_3_scramble_en_3_qs; 13117 reg_rdata_next[23:20] = mp_region_cfg_3_ecc_en_3_qs; 13118 reg_rdata_next[27:24] = mp_region_cfg_3_he_en_3_qs; 13119 end 13120 13121 addr_hit[24]: begin 13122 reg_rdata_next[3:0] = mp_region_cfg_4_en_4_qs; ==> 13123 reg_rdata_next[7:4] = mp_region_cfg_4_rd_en_4_qs; 13124 reg_rdata_next[11:8] = mp_region_cfg_4_prog_en_4_qs; 13125 reg_rdata_next[15:12] = mp_region_cfg_4_erase_en_4_qs; 13126 reg_rdata_next[19:16] = mp_region_cfg_4_scramble_en_4_qs; 13127 reg_rdata_next[23:20] = mp_region_cfg_4_ecc_en_4_qs; 13128 reg_rdata_next[27:24] = mp_region_cfg_4_he_en_4_qs; 13129 end 13130 13131 addr_hit[25]: begin 13132 reg_rdata_next[3:0] = mp_region_cfg_5_en_5_qs; ==> 13133 reg_rdata_next[7:4] = mp_region_cfg_5_rd_en_5_qs; 13134 reg_rdata_next[11:8] = mp_region_cfg_5_prog_en_5_qs; 13135 reg_rdata_next[15:12] = mp_region_cfg_5_erase_en_5_qs; 13136 reg_rdata_next[19:16] = mp_region_cfg_5_scramble_en_5_qs; 13137 reg_rdata_next[23:20] = mp_region_cfg_5_ecc_en_5_qs; 13138 reg_rdata_next[27:24] = mp_region_cfg_5_he_en_5_qs; 13139 end 13140 13141 addr_hit[26]: begin 13142 reg_rdata_next[3:0] = mp_region_cfg_6_en_6_qs; ==> 13143 reg_rdata_next[7:4] = mp_region_cfg_6_rd_en_6_qs; 13144 reg_rdata_next[11:8] = mp_region_cfg_6_prog_en_6_qs; 13145 reg_rdata_next[15:12] = mp_region_cfg_6_erase_en_6_qs; 13146 reg_rdata_next[19:16] = mp_region_cfg_6_scramble_en_6_qs; 13147 reg_rdata_next[23:20] = mp_region_cfg_6_ecc_en_6_qs; 13148 reg_rdata_next[27:24] = mp_region_cfg_6_he_en_6_qs; 13149 end 13150 13151 addr_hit[27]: begin 13152 reg_rdata_next[3:0] = mp_region_cfg_7_en_7_qs; ==> 13153 reg_rdata_next[7:4] = mp_region_cfg_7_rd_en_7_qs; 13154 reg_rdata_next[11:8] = mp_region_cfg_7_prog_en_7_qs; 13155 reg_rdata_next[15:12] = mp_region_cfg_7_erase_en_7_qs; 13156 reg_rdata_next[19:16] = mp_region_cfg_7_scramble_en_7_qs; 13157 reg_rdata_next[23:20] = mp_region_cfg_7_ecc_en_7_qs; 13158 reg_rdata_next[27:24] = mp_region_cfg_7_he_en_7_qs; 13159 end 13160 13161 addr_hit[28]: begin 13162 reg_rdata_next[8:0] = mp_region_0_base_0_qs; ==> 13163 reg_rdata_next[18:9] = mp_region_0_size_0_qs; 13164 end 13165 13166 addr_hit[29]: begin 13167 reg_rdata_next[8:0] = mp_region_1_base_1_qs; ==> 13168 reg_rdata_next[18:9] = mp_region_1_size_1_qs; 13169 end 13170 13171 addr_hit[30]: begin 13172 reg_rdata_next[8:0] = mp_region_2_base_2_qs; ==> 13173 reg_rdata_next[18:9] = mp_region_2_size_2_qs; 13174 end 13175 13176 addr_hit[31]: begin 13177 reg_rdata_next[8:0] = mp_region_3_base_3_qs; ==> 13178 reg_rdata_next[18:9] = mp_region_3_size_3_qs; 13179 end 13180 13181 addr_hit[32]: begin 13182 reg_rdata_next[8:0] = mp_region_4_base_4_qs; ==> 13183 reg_rdata_next[18:9] = mp_region_4_size_4_qs; 13184 end 13185 13186 addr_hit[33]: begin 13187 reg_rdata_next[8:0] = mp_region_5_base_5_qs; ==> 13188 reg_rdata_next[18:9] = mp_region_5_size_5_qs; 13189 end 13190 13191 addr_hit[34]: begin 13192 reg_rdata_next[8:0] = mp_region_6_base_6_qs; ==> 13193 reg_rdata_next[18:9] = mp_region_6_size_6_qs; 13194 end 13195 13196 addr_hit[35]: begin 13197 reg_rdata_next[8:0] = mp_region_7_base_7_qs; ==> 13198 reg_rdata_next[18:9] = mp_region_7_size_7_qs; 13199 end 13200 13201 addr_hit[36]: begin 13202 reg_rdata_next[3:0] = default_region_rd_en_qs; ==> 13203 reg_rdata_next[7:4] = default_region_prog_en_qs; 13204 reg_rdata_next[11:8] = default_region_erase_en_qs; 13205 reg_rdata_next[15:12] = default_region_scramble_en_qs; 13206 reg_rdata_next[19:16] = default_region_ecc_en_qs; 13207 reg_rdata_next[23:20] = default_region_he_en_qs; 13208 end 13209 13210 addr_hit[37]: begin 13211 reg_rdata_next[0] = bank0_info0_regwen_0_qs; ==> 13212 end 13213 13214 addr_hit[38]: begin 13215 reg_rdata_next[0] = bank0_info0_regwen_1_qs; ==> 13216 end 13217 13218 addr_hit[39]: begin 13219 reg_rdata_next[0] = bank0_info0_regwen_2_qs; ==> 13220 end 13221 13222 addr_hit[40]: begin 13223 reg_rdata_next[0] = bank0_info0_regwen_3_qs; ==> 13224 end 13225 13226 addr_hit[41]: begin 13227 reg_rdata_next[0] = bank0_info0_regwen_4_qs; ==> 13228 end 13229 13230 addr_hit[42]: begin 13231 reg_rdata_next[0] = bank0_info0_regwen_5_qs; ==> 13232 end 13233 13234 addr_hit[43]: begin 13235 reg_rdata_next[0] = bank0_info0_regwen_6_qs; ==> 13236 end 13237 13238 addr_hit[44]: begin 13239 reg_rdata_next[0] = bank0_info0_regwen_7_qs; ==> 13240 end 13241 13242 addr_hit[45]: begin 13243 reg_rdata_next[0] = bank0_info0_regwen_8_qs; ==> 13244 end 13245 13246 addr_hit[46]: begin 13247 reg_rdata_next[0] = bank0_info0_regwen_9_qs; ==> 13248 end 13249 13250 addr_hit[47]: begin 13251 reg_rdata_next[3:0] = bank0_info0_page_cfg_0_en_0_qs; ==> 13252 reg_rdata_next[7:4] = bank0_info0_page_cfg_0_rd_en_0_qs; 13253 reg_rdata_next[11:8] = bank0_info0_page_cfg_0_prog_en_0_qs; 13254 reg_rdata_next[15:12] = bank0_info0_page_cfg_0_erase_en_0_qs; 13255 reg_rdata_next[19:16] = bank0_info0_page_cfg_0_scramble_en_0_qs; 13256 reg_rdata_next[23:20] = bank0_info0_page_cfg_0_ecc_en_0_qs; 13257 reg_rdata_next[27:24] = bank0_info0_page_cfg_0_he_en_0_qs; 13258 end 13259 13260 addr_hit[48]: begin 13261 reg_rdata_next[3:0] = bank0_info0_page_cfg_1_en_1_qs; ==> 13262 reg_rdata_next[7:4] = bank0_info0_page_cfg_1_rd_en_1_qs; 13263 reg_rdata_next[11:8] = bank0_info0_page_cfg_1_prog_en_1_qs; 13264 reg_rdata_next[15:12] = bank0_info0_page_cfg_1_erase_en_1_qs; 13265 reg_rdata_next[19:16] = bank0_info0_page_cfg_1_scramble_en_1_qs; 13266 reg_rdata_next[23:20] = bank0_info0_page_cfg_1_ecc_en_1_qs; 13267 reg_rdata_next[27:24] = bank0_info0_page_cfg_1_he_en_1_qs; 13268 end 13269 13270 addr_hit[49]: begin 13271 reg_rdata_next[3:0] = bank0_info0_page_cfg_2_en_2_qs; ==> 13272 reg_rdata_next[7:4] = bank0_info0_page_cfg_2_rd_en_2_qs; 13273 reg_rdata_next[11:8] = bank0_info0_page_cfg_2_prog_en_2_qs; 13274 reg_rdata_next[15:12] = bank0_info0_page_cfg_2_erase_en_2_qs; 13275 reg_rdata_next[19:16] = bank0_info0_page_cfg_2_scramble_en_2_qs; 13276 reg_rdata_next[23:20] = bank0_info0_page_cfg_2_ecc_en_2_qs; 13277 reg_rdata_next[27:24] = bank0_info0_page_cfg_2_he_en_2_qs; 13278 end 13279 13280 addr_hit[50]: begin 13281 reg_rdata_next[3:0] = bank0_info0_page_cfg_3_en_3_qs; ==> 13282 reg_rdata_next[7:4] = bank0_info0_page_cfg_3_rd_en_3_qs; 13283 reg_rdata_next[11:8] = bank0_info0_page_cfg_3_prog_en_3_qs; 13284 reg_rdata_next[15:12] = bank0_info0_page_cfg_3_erase_en_3_qs; 13285 reg_rdata_next[19:16] = bank0_info0_page_cfg_3_scramble_en_3_qs; 13286 reg_rdata_next[23:20] = bank0_info0_page_cfg_3_ecc_en_3_qs; 13287 reg_rdata_next[27:24] = bank0_info0_page_cfg_3_he_en_3_qs; 13288 end 13289 13290 addr_hit[51]: begin 13291 reg_rdata_next[3:0] = bank0_info0_page_cfg_4_en_4_qs; ==> 13292 reg_rdata_next[7:4] = bank0_info0_page_cfg_4_rd_en_4_qs; 13293 reg_rdata_next[11:8] = bank0_info0_page_cfg_4_prog_en_4_qs; 13294 reg_rdata_next[15:12] = bank0_info0_page_cfg_4_erase_en_4_qs; 13295 reg_rdata_next[19:16] = bank0_info0_page_cfg_4_scramble_en_4_qs; 13296 reg_rdata_next[23:20] = bank0_info0_page_cfg_4_ecc_en_4_qs; 13297 reg_rdata_next[27:24] = bank0_info0_page_cfg_4_he_en_4_qs; 13298 end 13299 13300 addr_hit[52]: begin 13301 reg_rdata_next[3:0] = bank0_info0_page_cfg_5_en_5_qs; ==> 13302 reg_rdata_next[7:4] = bank0_info0_page_cfg_5_rd_en_5_qs; 13303 reg_rdata_next[11:8] = bank0_info0_page_cfg_5_prog_en_5_qs; 13304 reg_rdata_next[15:12] = bank0_info0_page_cfg_5_erase_en_5_qs; 13305 reg_rdata_next[19:16] = bank0_info0_page_cfg_5_scramble_en_5_qs; 13306 reg_rdata_next[23:20] = bank0_info0_page_cfg_5_ecc_en_5_qs; 13307 reg_rdata_next[27:24] = bank0_info0_page_cfg_5_he_en_5_qs; 13308 end 13309 13310 addr_hit[53]: begin 13311 reg_rdata_next[3:0] = bank0_info0_page_cfg_6_en_6_qs; ==> 13312 reg_rdata_next[7:4] = bank0_info0_page_cfg_6_rd_en_6_qs; 13313 reg_rdata_next[11:8] = bank0_info0_page_cfg_6_prog_en_6_qs; 13314 reg_rdata_next[15:12] = bank0_info0_page_cfg_6_erase_en_6_qs; 13315 reg_rdata_next[19:16] = bank0_info0_page_cfg_6_scramble_en_6_qs; 13316 reg_rdata_next[23:20] = bank0_info0_page_cfg_6_ecc_en_6_qs; 13317 reg_rdata_next[27:24] = bank0_info0_page_cfg_6_he_en_6_qs; 13318 end 13319 13320 addr_hit[54]: begin 13321 reg_rdata_next[3:0] = bank0_info0_page_cfg_7_en_7_qs; ==> 13322 reg_rdata_next[7:4] = bank0_info0_page_cfg_7_rd_en_7_qs; 13323 reg_rdata_next[11:8] = bank0_info0_page_cfg_7_prog_en_7_qs; 13324 reg_rdata_next[15:12] = bank0_info0_page_cfg_7_erase_en_7_qs; 13325 reg_rdata_next[19:16] = bank0_info0_page_cfg_7_scramble_en_7_qs; 13326 reg_rdata_next[23:20] = bank0_info0_page_cfg_7_ecc_en_7_qs; 13327 reg_rdata_next[27:24] = bank0_info0_page_cfg_7_he_en_7_qs; 13328 end 13329 13330 addr_hit[55]: begin 13331 reg_rdata_next[3:0] = bank0_info0_page_cfg_8_en_8_qs; ==> 13332 reg_rdata_next[7:4] = bank0_info0_page_cfg_8_rd_en_8_qs; 13333 reg_rdata_next[11:8] = bank0_info0_page_cfg_8_prog_en_8_qs; 13334 reg_rdata_next[15:12] = bank0_info0_page_cfg_8_erase_en_8_qs; 13335 reg_rdata_next[19:16] = bank0_info0_page_cfg_8_scramble_en_8_qs; 13336 reg_rdata_next[23:20] = bank0_info0_page_cfg_8_ecc_en_8_qs; 13337 reg_rdata_next[27:24] = bank0_info0_page_cfg_8_he_en_8_qs; 13338 end 13339 13340 addr_hit[56]: begin 13341 reg_rdata_next[3:0] = bank0_info0_page_cfg_9_en_9_qs; ==> 13342 reg_rdata_next[7:4] = bank0_info0_page_cfg_9_rd_en_9_qs; 13343 reg_rdata_next[11:8] = bank0_info0_page_cfg_9_prog_en_9_qs; 13344 reg_rdata_next[15:12] = bank0_info0_page_cfg_9_erase_en_9_qs; 13345 reg_rdata_next[19:16] = bank0_info0_page_cfg_9_scramble_en_9_qs; 13346 reg_rdata_next[23:20] = bank0_info0_page_cfg_9_ecc_en_9_qs; 13347 reg_rdata_next[27:24] = bank0_info0_page_cfg_9_he_en_9_qs; 13348 end 13349 13350 addr_hit[57]: begin 13351 reg_rdata_next[0] = bank0_info1_regwen_qs; ==> 13352 end 13353 13354 addr_hit[58]: begin 13355 reg_rdata_next[3:0] = bank0_info1_page_cfg_en_0_qs; ==> 13356 reg_rdata_next[7:4] = bank0_info1_page_cfg_rd_en_0_qs; 13357 reg_rdata_next[11:8] = bank0_info1_page_cfg_prog_en_0_qs; 13358 reg_rdata_next[15:12] = bank0_info1_page_cfg_erase_en_0_qs; 13359 reg_rdata_next[19:16] = bank0_info1_page_cfg_scramble_en_0_qs; 13360 reg_rdata_next[23:20] = bank0_info1_page_cfg_ecc_en_0_qs; 13361 reg_rdata_next[27:24] = bank0_info1_page_cfg_he_en_0_qs; 13362 end 13363 13364 addr_hit[59]: begin 13365 reg_rdata_next[0] = bank0_info2_regwen_0_qs; ==> 13366 end 13367 13368 addr_hit[60]: begin 13369 reg_rdata_next[0] = bank0_info2_regwen_1_qs; ==> 13370 end 13371 13372 addr_hit[61]: begin 13373 reg_rdata_next[3:0] = bank0_info2_page_cfg_0_en_0_qs; ==> 13374 reg_rdata_next[7:4] = bank0_info2_page_cfg_0_rd_en_0_qs; 13375 reg_rdata_next[11:8] = bank0_info2_page_cfg_0_prog_en_0_qs; 13376 reg_rdata_next[15:12] = bank0_info2_page_cfg_0_erase_en_0_qs; 13377 reg_rdata_next[19:16] = bank0_info2_page_cfg_0_scramble_en_0_qs; 13378 reg_rdata_next[23:20] = bank0_info2_page_cfg_0_ecc_en_0_qs; 13379 reg_rdata_next[27:24] = bank0_info2_page_cfg_0_he_en_0_qs; 13380 end 13381 13382 addr_hit[62]: begin 13383 reg_rdata_next[3:0] = bank0_info2_page_cfg_1_en_1_qs; ==> 13384 reg_rdata_next[7:4] = bank0_info2_page_cfg_1_rd_en_1_qs; 13385 reg_rdata_next[11:8] = bank0_info2_page_cfg_1_prog_en_1_qs; 13386 reg_rdata_next[15:12] = bank0_info2_page_cfg_1_erase_en_1_qs; 13387 reg_rdata_next[19:16] = bank0_info2_page_cfg_1_scramble_en_1_qs; 13388 reg_rdata_next[23:20] = bank0_info2_page_cfg_1_ecc_en_1_qs; 13389 reg_rdata_next[27:24] = bank0_info2_page_cfg_1_he_en_1_qs; 13390 end 13391 13392 addr_hit[63]: begin 13393 reg_rdata_next[0] = bank1_info0_regwen_0_qs; ==> 13394 end 13395 13396 addr_hit[64]: begin 13397 reg_rdata_next[0] = bank1_info0_regwen_1_qs; ==> 13398 end 13399 13400 addr_hit[65]: begin 13401 reg_rdata_next[0] = bank1_info0_regwen_2_qs; ==> 13402 end 13403 13404 addr_hit[66]: begin 13405 reg_rdata_next[0] = bank1_info0_regwen_3_qs; ==> 13406 end 13407 13408 addr_hit[67]: begin 13409 reg_rdata_next[0] = bank1_info0_regwen_4_qs; ==> 13410 end 13411 13412 addr_hit[68]: begin 13413 reg_rdata_next[0] = bank1_info0_regwen_5_qs; ==> 13414 end 13415 13416 addr_hit[69]: begin 13417 reg_rdata_next[0] = bank1_info0_regwen_6_qs; ==> 13418 end 13419 13420 addr_hit[70]: begin 13421 reg_rdata_next[0] = bank1_info0_regwen_7_qs; ==> 13422 end 13423 13424 addr_hit[71]: begin 13425 reg_rdata_next[0] = bank1_info0_regwen_8_qs; ==> 13426 end 13427 13428 addr_hit[72]: begin 13429 reg_rdata_next[0] = bank1_info0_regwen_9_qs; ==> 13430 end 13431 13432 addr_hit[73]: begin 13433 reg_rdata_next[3:0] = bank1_info0_page_cfg_0_en_0_qs; ==> 13434 reg_rdata_next[7:4] = bank1_info0_page_cfg_0_rd_en_0_qs; 13435 reg_rdata_next[11:8] = bank1_info0_page_cfg_0_prog_en_0_qs; 13436 reg_rdata_next[15:12] = bank1_info0_page_cfg_0_erase_en_0_qs; 13437 reg_rdata_next[19:16] = bank1_info0_page_cfg_0_scramble_en_0_qs; 13438 reg_rdata_next[23:20] = bank1_info0_page_cfg_0_ecc_en_0_qs; 13439 reg_rdata_next[27:24] = bank1_info0_page_cfg_0_he_en_0_qs; 13440 end 13441 13442 addr_hit[74]: begin 13443 reg_rdata_next[3:0] = bank1_info0_page_cfg_1_en_1_qs; ==> 13444 reg_rdata_next[7:4] = bank1_info0_page_cfg_1_rd_en_1_qs; 13445 reg_rdata_next[11:8] = bank1_info0_page_cfg_1_prog_en_1_qs; 13446 reg_rdata_next[15:12] = bank1_info0_page_cfg_1_erase_en_1_qs; 13447 reg_rdata_next[19:16] = bank1_info0_page_cfg_1_scramble_en_1_qs; 13448 reg_rdata_next[23:20] = bank1_info0_page_cfg_1_ecc_en_1_qs; 13449 reg_rdata_next[27:24] = bank1_info0_page_cfg_1_he_en_1_qs; 13450 end 13451 13452 addr_hit[75]: begin 13453 reg_rdata_next[3:0] = bank1_info0_page_cfg_2_en_2_qs; ==> 13454 reg_rdata_next[7:4] = bank1_info0_page_cfg_2_rd_en_2_qs; 13455 reg_rdata_next[11:8] = bank1_info0_page_cfg_2_prog_en_2_qs; 13456 reg_rdata_next[15:12] = bank1_info0_page_cfg_2_erase_en_2_qs; 13457 reg_rdata_next[19:16] = bank1_info0_page_cfg_2_scramble_en_2_qs; 13458 reg_rdata_next[23:20] = bank1_info0_page_cfg_2_ecc_en_2_qs; 13459 reg_rdata_next[27:24] = bank1_info0_page_cfg_2_he_en_2_qs; 13460 end 13461 13462 addr_hit[76]: begin 13463 reg_rdata_next[3:0] = bank1_info0_page_cfg_3_en_3_qs; ==> 13464 reg_rdata_next[7:4] = bank1_info0_page_cfg_3_rd_en_3_qs; 13465 reg_rdata_next[11:8] = bank1_info0_page_cfg_3_prog_en_3_qs; 13466 reg_rdata_next[15:12] = bank1_info0_page_cfg_3_erase_en_3_qs; 13467 reg_rdata_next[19:16] = bank1_info0_page_cfg_3_scramble_en_3_qs; 13468 reg_rdata_next[23:20] = bank1_info0_page_cfg_3_ecc_en_3_qs; 13469 reg_rdata_next[27:24] = bank1_info0_page_cfg_3_he_en_3_qs; 13470 end 13471 13472 addr_hit[77]: begin 13473 reg_rdata_next[3:0] = bank1_info0_page_cfg_4_en_4_qs; ==> 13474 reg_rdata_next[7:4] = bank1_info0_page_cfg_4_rd_en_4_qs; 13475 reg_rdata_next[11:8] = bank1_info0_page_cfg_4_prog_en_4_qs; 13476 reg_rdata_next[15:12] = bank1_info0_page_cfg_4_erase_en_4_qs; 13477 reg_rdata_next[19:16] = bank1_info0_page_cfg_4_scramble_en_4_qs; 13478 reg_rdata_next[23:20] = bank1_info0_page_cfg_4_ecc_en_4_qs; 13479 reg_rdata_next[27:24] = bank1_info0_page_cfg_4_he_en_4_qs; 13480 end 13481 13482 addr_hit[78]: begin 13483 reg_rdata_next[3:0] = bank1_info0_page_cfg_5_en_5_qs; ==> 13484 reg_rdata_next[7:4] = bank1_info0_page_cfg_5_rd_en_5_qs; 13485 reg_rdata_next[11:8] = bank1_info0_page_cfg_5_prog_en_5_qs; 13486 reg_rdata_next[15:12] = bank1_info0_page_cfg_5_erase_en_5_qs; 13487 reg_rdata_next[19:16] = bank1_info0_page_cfg_5_scramble_en_5_qs; 13488 reg_rdata_next[23:20] = bank1_info0_page_cfg_5_ecc_en_5_qs; 13489 reg_rdata_next[27:24] = bank1_info0_page_cfg_5_he_en_5_qs; 13490 end 13491 13492 addr_hit[79]: begin 13493 reg_rdata_next[3:0] = bank1_info0_page_cfg_6_en_6_qs; ==> 13494 reg_rdata_next[7:4] = bank1_info0_page_cfg_6_rd_en_6_qs; 13495 reg_rdata_next[11:8] = bank1_info0_page_cfg_6_prog_en_6_qs; 13496 reg_rdata_next[15:12] = bank1_info0_page_cfg_6_erase_en_6_qs; 13497 reg_rdata_next[19:16] = bank1_info0_page_cfg_6_scramble_en_6_qs; 13498 reg_rdata_next[23:20] = bank1_info0_page_cfg_6_ecc_en_6_qs; 13499 reg_rdata_next[27:24] = bank1_info0_page_cfg_6_he_en_6_qs; 13500 end 13501 13502 addr_hit[80]: begin 13503 reg_rdata_next[3:0] = bank1_info0_page_cfg_7_en_7_qs; ==> 13504 reg_rdata_next[7:4] = bank1_info0_page_cfg_7_rd_en_7_qs; 13505 reg_rdata_next[11:8] = bank1_info0_page_cfg_7_prog_en_7_qs; 13506 reg_rdata_next[15:12] = bank1_info0_page_cfg_7_erase_en_7_qs; 13507 reg_rdata_next[19:16] = bank1_info0_page_cfg_7_scramble_en_7_qs; 13508 reg_rdata_next[23:20] = bank1_info0_page_cfg_7_ecc_en_7_qs; 13509 reg_rdata_next[27:24] = bank1_info0_page_cfg_7_he_en_7_qs; 13510 end 13511 13512 addr_hit[81]: begin 13513 reg_rdata_next[3:0] = bank1_info0_page_cfg_8_en_8_qs; ==> 13514 reg_rdata_next[7:4] = bank1_info0_page_cfg_8_rd_en_8_qs; 13515 reg_rdata_next[11:8] = bank1_info0_page_cfg_8_prog_en_8_qs; 13516 reg_rdata_next[15:12] = bank1_info0_page_cfg_8_erase_en_8_qs; 13517 reg_rdata_next[19:16] = bank1_info0_page_cfg_8_scramble_en_8_qs; 13518 reg_rdata_next[23:20] = bank1_info0_page_cfg_8_ecc_en_8_qs; 13519 reg_rdata_next[27:24] = bank1_info0_page_cfg_8_he_en_8_qs; 13520 end 13521 13522 addr_hit[82]: begin 13523 reg_rdata_next[3:0] = bank1_info0_page_cfg_9_en_9_qs; ==> 13524 reg_rdata_next[7:4] = bank1_info0_page_cfg_9_rd_en_9_qs; 13525 reg_rdata_next[11:8] = bank1_info0_page_cfg_9_prog_en_9_qs; 13526 reg_rdata_next[15:12] = bank1_info0_page_cfg_9_erase_en_9_qs; 13527 reg_rdata_next[19:16] = bank1_info0_page_cfg_9_scramble_en_9_qs; 13528 reg_rdata_next[23:20] = bank1_info0_page_cfg_9_ecc_en_9_qs; 13529 reg_rdata_next[27:24] = bank1_info0_page_cfg_9_he_en_9_qs; 13530 end 13531 13532 addr_hit[83]: begin 13533 reg_rdata_next[0] = bank1_info1_regwen_qs; ==> 13534 end 13535 13536 addr_hit[84]: begin 13537 reg_rdata_next[3:0] = bank1_info1_page_cfg_en_0_qs; ==> 13538 reg_rdata_next[7:4] = bank1_info1_page_cfg_rd_en_0_qs; 13539 reg_rdata_next[11:8] = bank1_info1_page_cfg_prog_en_0_qs; 13540 reg_rdata_next[15:12] = bank1_info1_page_cfg_erase_en_0_qs; 13541 reg_rdata_next[19:16] = bank1_info1_page_cfg_scramble_en_0_qs; 13542 reg_rdata_next[23:20] = bank1_info1_page_cfg_ecc_en_0_qs; 13543 reg_rdata_next[27:24] = bank1_info1_page_cfg_he_en_0_qs; 13544 end 13545 13546 addr_hit[85]: begin 13547 reg_rdata_next[0] = bank1_info2_regwen_0_qs; ==> 13548 end 13549 13550 addr_hit[86]: begin 13551 reg_rdata_next[0] = bank1_info2_regwen_1_qs; ==> 13552 end 13553 13554 addr_hit[87]: begin 13555 reg_rdata_next[3:0] = bank1_info2_page_cfg_0_en_0_qs; ==> 13556 reg_rdata_next[7:4] = bank1_info2_page_cfg_0_rd_en_0_qs; 13557 reg_rdata_next[11:8] = bank1_info2_page_cfg_0_prog_en_0_qs; 13558 reg_rdata_next[15:12] = bank1_info2_page_cfg_0_erase_en_0_qs; 13559 reg_rdata_next[19:16] = bank1_info2_page_cfg_0_scramble_en_0_qs; 13560 reg_rdata_next[23:20] = bank1_info2_page_cfg_0_ecc_en_0_qs; 13561 reg_rdata_next[27:24] = bank1_info2_page_cfg_0_he_en_0_qs; 13562 end 13563 13564 addr_hit[88]: begin 13565 reg_rdata_next[3:0] = bank1_info2_page_cfg_1_en_1_qs; ==> 13566 reg_rdata_next[7:4] = bank1_info2_page_cfg_1_rd_en_1_qs; 13567 reg_rdata_next[11:8] = bank1_info2_page_cfg_1_prog_en_1_qs; 13568 reg_rdata_next[15:12] = bank1_info2_page_cfg_1_erase_en_1_qs; 13569 reg_rdata_next[19:16] = bank1_info2_page_cfg_1_scramble_en_1_qs; 13570 reg_rdata_next[23:20] = bank1_info2_page_cfg_1_ecc_en_1_qs; 13571 reg_rdata_next[27:24] = bank1_info2_page_cfg_1_he_en_1_qs; 13572 end 13573 13574 addr_hit[89]: begin 13575 reg_rdata_next[3:0] = hw_info_cfg_override_scramble_dis_qs; ==> 13576 reg_rdata_next[7:4] = hw_info_cfg_override_ecc_dis_qs; 13577 end 13578 13579 addr_hit[90]: begin 13580 reg_rdata_next[0] = bank_cfg_regwen_qs; ==> 13581 end 13582 13583 addr_hit[91]: begin 13584 reg_rdata_next[0] = mp_bank_cfg_shadowed_erase_en_0_qs; ==> 13585 reg_rdata_next[1] = mp_bank_cfg_shadowed_erase_en_1_qs; 13586 end 13587 13588 addr_hit[92]: begin 13589 reg_rdata_next[0] = op_status_done_qs; ==> 13590 reg_rdata_next[1] = op_status_err_qs; 13591 end 13592 13593 addr_hit[93]: begin 13594 reg_rdata_next[0] = status_rd_full_qs; ==> 13595 reg_rdata_next[1] = status_rd_empty_qs; 13596 reg_rdata_next[2] = status_prog_full_qs; 13597 reg_rdata_next[3] = status_prog_empty_qs; 13598 reg_rdata_next[4] = status_init_wip_qs; 13599 reg_rdata_next[5] = status_initialized_qs; 13600 end 13601 13602 addr_hit[94]: begin 13603 reg_rdata_next[10:0] = debug_state_qs; ==> 13604 end 13605 13606 addr_hit[95]: begin 13607 reg_rdata_next[0] = err_code_op_err_qs; ==> 13608 reg_rdata_next[1] = err_code_mp_err_qs; 13609 reg_rdata_next[2] = err_code_rd_err_qs; 13610 reg_rdata_next[3] = err_code_prog_err_qs; 13611 reg_rdata_next[4] = err_code_prog_win_err_qs; 13612 reg_rdata_next[5] = err_code_prog_type_err_qs; 13613 reg_rdata_next[6] = err_code_update_err_qs; 13614 reg_rdata_next[7] = err_code_macro_err_qs; 13615 end 13616 13617 addr_hit[96]: begin 13618 reg_rdata_next[0] = std_fault_status_reg_intg_err_qs; ==> 13619 reg_rdata_next[1] = std_fault_status_prog_intg_err_qs; 13620 reg_rdata_next[2] = std_fault_status_lcmgr_err_qs; 13621 reg_rdata_next[3] = std_fault_status_lcmgr_intg_err_qs; 13622 reg_rdata_next[4] = std_fault_status_arb_fsm_err_qs; 13623 reg_rdata_next[5] = std_fault_status_storage_err_qs; 13624 reg_rdata_next[6] = std_fault_status_phy_fsm_err_qs; 13625 reg_rdata_next[7] = std_fault_status_ctrl_cnt_err_qs; 13626 reg_rdata_next[8] = std_fault_status_fifo_err_qs; 13627 end 13628 13629 addr_hit[97]: begin 13630 reg_rdata_next[0] = fault_status_op_err_qs; ==> 13631 reg_rdata_next[1] = fault_status_mp_err_qs; 13632 reg_rdata_next[2] = fault_status_rd_err_qs; 13633 reg_rdata_next[3] = fault_status_prog_err_qs; 13634 reg_rdata_next[4] = fault_status_prog_win_err_qs; 13635 reg_rdata_next[5] = fault_status_prog_type_err_qs; 13636 reg_rdata_next[6] = fault_status_seed_err_qs; 13637 reg_rdata_next[7] = fault_status_phy_relbl_err_qs; 13638 reg_rdata_next[8] = fault_status_phy_storage_err_qs; 13639 reg_rdata_next[9] = fault_status_spurious_ack_qs; 13640 reg_rdata_next[10] = fault_status_arb_err_qs; 13641 reg_rdata_next[11] = fault_status_host_gnt_err_qs; 13642 end 13643 13644 addr_hit[98]: begin 13645 reg_rdata_next[19:0] = err_addr_qs; ==> 13646 end 13647 13648 addr_hit[99]: begin 13649 reg_rdata_next[7:0] = ecc_single_err_cnt_ecc_single_err_cnt_0_qs; ==> 13650 reg_rdata_next[15:8] = ecc_single_err_cnt_ecc_single_err_cnt_1_qs; 13651 end 13652 13653 addr_hit[100]: begin 13654 reg_rdata_next[19:0] = ecc_single_err_addr_0_qs; ==> 13655 end 13656 13657 addr_hit[101]: begin 13658 reg_rdata_next[19:0] = ecc_single_err_addr_1_qs; ==> 13659 end 13660 13661 addr_hit[102]: begin 13662 reg_rdata_next[0] = phy_alert_cfg_alert_ack_qs; ==> 13663 reg_rdata_next[1] = phy_alert_cfg_alert_trig_qs; 13664 end 13665 13666 addr_hit[103]: begin 13667 reg_rdata_next[0] = phy_status_init_wip_qs; ==> 13668 reg_rdata_next[1] = phy_status_prog_normal_avail_qs; 13669 reg_rdata_next[2] = phy_status_prog_repair_avail_qs; 13670 end 13671 13672 addr_hit[104]: begin 13673 reg_rdata_next[31:0] = scratch_qs; ==> 13674 end 13675 13676 addr_hit[105]: begin 13677 reg_rdata_next[4:0] = fifo_lvl_prog_qs; ==> 13678 reg_rdata_next[12:8] = fifo_lvl_rd_qs; 13679 end 13680 13681 addr_hit[106]: begin 13682 reg_rdata_next[0] = fifo_rst_qs; ==> 13683 end 13684 13685 addr_hit[107]: begin 13686 reg_rdata_next[4:0] = curr_fifo_lvl_prog_qs; ==> 13687 reg_rdata_next[12:8] = curr_fifo_lvl_rd_qs; 13688 end 13689 13690 default: begin 13691 reg_rdata_next = '1; ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
addr_hit[21] Covered T1,T2,T3
addr_hit[22] Covered T1,T2,T3
addr_hit[23] Covered T1,T2,T3
addr_hit[24] Covered T1,T2,T3
addr_hit[25] Covered T1,T2,T3
addr_hit[26] Covered T1,T2,T3
addr_hit[27] Covered T1,T2,T3
addr_hit[28] Covered T1,T2,T3
addr_hit[29] Covered T1,T2,T3
addr_hit[30] Covered T1,T2,T3
addr_hit[31] Covered T1,T2,T3
addr_hit[32] Covered T1,T2,T3
addr_hit[33] Covered T1,T2,T3
addr_hit[34] Covered T1,T2,T3
addr_hit[35] Covered T1,T2,T3
addr_hit[36] Covered T1,T2,T3
addr_hit[37] Covered T1,T2,T3
addr_hit[38] Covered T1,T2,T3
addr_hit[39] Covered T1,T2,T3
addr_hit[40] Covered T1,T2,T3
addr_hit[41] Covered T1,T2,T3
addr_hit[42] Covered T1,T2,T3
addr_hit[43] Covered T1,T2,T3
addr_hit[44] Covered T1,T2,T3
addr_hit[45] Covered T1,T2,T3
addr_hit[46] Covered T1,T2,T3
addr_hit[47] Covered T1,T2,T3
addr_hit[48] Covered T1,T2,T3
addr_hit[49] Covered T1,T2,T3
addr_hit[50] Covered T1,T2,T3
addr_hit[51] Covered T1,T2,T3
addr_hit[52] Covered T1,T2,T3
addr_hit[53] Covered T1,T2,T3
addr_hit[54] Covered T1,T2,T3
addr_hit[55] Covered T1,T2,T3
addr_hit[56] Covered T1,T2,T3
addr_hit[57] Covered T1,T2,T3
addr_hit[58] Covered T1,T2,T3
addr_hit[59] Covered T1,T2,T3
addr_hit[60] Covered T1,T2,T3
addr_hit[61] Covered T1,T2,T3
addr_hit[62] Covered T1,T2,T3
addr_hit[63] Covered T1,T2,T3
addr_hit[64] Covered T1,T2,T3
addr_hit[65] Covered T1,T2,T3
addr_hit[66] Covered T1,T2,T3
addr_hit[67] Covered T1,T2,T3
addr_hit[68] Covered T1,T2,T3
addr_hit[69] Covered T1,T2,T3
addr_hit[70] Covered T1,T2,T3
addr_hit[71] Covered T1,T2,T3
addr_hit[72] Covered T1,T2,T3
addr_hit[73] Covered T1,T2,T3
addr_hit[74] Covered T1,T2,T3
addr_hit[75] Covered T1,T2,T3
addr_hit[76] Covered T1,T2,T3
addr_hit[77] Covered T1,T2,T3
addr_hit[78] Covered T1,T2,T3
addr_hit[79] Covered T1,T2,T3
addr_hit[80] Covered T1,T2,T3
addr_hit[81] Covered T1,T2,T3
addr_hit[82] Covered T1,T2,T3
addr_hit[83] Covered T1,T2,T3
addr_hit[84] Covered T1,T2,T3
addr_hit[85] Covered T1,T2,T3
addr_hit[86] Covered T1,T2,T3
addr_hit[87] Covered T1,T2,T3
addr_hit[88] Covered T1,T2,T3
addr_hit[89] Covered T1,T2,T3
addr_hit[90] Covered T1,T2,T3
addr_hit[91] Covered T1,T2,T3
addr_hit[92] Covered T1,T2,T3
addr_hit[93] Covered T1,T2,T3
addr_hit[94] Covered T1,T2,T3
addr_hit[95] Covered T1,T2,T3
addr_hit[96] Covered T1,T2,T3
addr_hit[97] Covered T1,T2,T3
addr_hit[98] Covered T1,T2,T3
addr_hit[99] Covered T1,T2,T3
addr_hit[100] Covered T1,T2,T3
addr_hit[101] Covered T1,T2,T3
addr_hit[102] Covered T1,T2,T3
addr_hit[103] Covered T1,T2,T3
addr_hit[104] Covered T1,T2,T3
addr_hit[105] Covered T1,T2,T3
addr_hit[106] Covered T1,T2,T3
addr_hit[107] Covered T1,T2,T3
default Covered T1,T2,T3


13701 if (!rst_ni) begin -1- 13702 rst_done <= '0; ==> 13703 end else begin 13704 rst_done <= 1'b1; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


13709 if (!rst_shadowed_ni) begin -1- 13710 shadow_rst_done <= '0; ==> 13711 end else begin 13712 shadow_rst_done <= 1'b1; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl_core_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 387235479 25364931 0 0
reAfterRv 387235479 25364912 0 0
rePulse 387235479 22990443 0 0
wePulse 387235479 2374469 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 387235479 25364931 0 0
T1 1636 61 0 0
T2 1951 120 0 0
T3 3382 172 0 0
T7 4246 112 0 0
T13 23710 2319 0 0
T14 6246 2106 0 0
T15 3415 955 0 0
T18 2946 153 0 0
T19 485911 34461 0 0
T20 70358 34126 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 387235479 25364912 0 0
T1 1636 61 0 0
T2 1951 120 0 0
T3 3382 172 0 0
T7 4246 112 0 0
T13 23710 2319 0 0
T14 6246 2106 0 0
T15 3415 955 0 0
T18 2946 153 0 0
T19 485911 34461 0 0
T20 70358 34126 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 387235479 22990443 0 0
T1 1636 57 0 0
T2 1951 89 0 0
T3 3382 59 0 0
T7 4246 104 0 0
T13 23710 553 0 0
T14 6246 1744 0 0
T15 3415 629 0 0
T18 2946 49 0 0
T19 485911 23458 0 0
T20 70358 34057 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 387235479 2374469 0 0
T1 1636 4 0 0
T2 1951 31 0 0
T3 3382 113 0 0
T7 4246 8 0 0
T13 23710 1766 0 0
T14 6246 362 0 0
T15 3415 326 0 0
T18 2946 104 0 0
T19 485911 11003 0 0
T20 70358 69 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%