Module Definition
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Module Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 73.08 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.86 100.00 99.43 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00



Module Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.27 100.00 73.08 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.88 100.00 87.50 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.86 100.00 99.43 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
committed_reg 100.00 100.00 100.00 100.00
shadow_reg 100.00 100.00 100.00 100.00
staged_reg 100.00 100.00 100.00 100.00
wr_en_data_arb 100.00 100.00 100.00 100.00

Line Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00

93 // - In case of RO, SW should not interfere with update process. 94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re; Tests: T79 T80 T81  95 96 // Phase tracker: 97 // - Reads from SW clear the phase back to 0. 98 // - Writes have priority (can come from SW or HW). 99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg 100 1/1 if (!rst_ni) begin Tests: T1 T2 T3  101 1/1 phase_q <= 1'b0; Tests: T1 T2 T3  102 1/1 end else if (wr_en && !err_storage) begin Tests: T1 T2 T3  103 1/1 phase_q <= ~phase_q; Tests: T3 T13 T18  104 1/1 end else if (phase_clear || err_storage) begin Tests: T1 T2 T3  105 1/1 phase_q <= 1'b0; Tests: T79 T80 T81  106 end MISSING_ELSE 107 end 108 109 // The staged register: 110 // - Holds the 1's complement value. 111 // - Written in Phase 0. 112 // - Once storage error occurs, do not allow any further update until reset 113 1/1 assign staged_we = we & ~phase_q & ~err_storage; Tests: T1 T2 T3  114 unreachable assign staged_de = de & ~phase_q & ~err_storage; 115 prim_subreg #( 116 .DW ( DW ), 117 .SwAccess ( StagedSwAccess ), 118 .RESVAL ( ~RESVAL ) 119 ) staged_reg ( 120 .clk_i ( clk_i ), 121 .rst_ni ( rst_ni ), 122 .we ( staged_we ), 123 .wd ( ~wr_data ), 124 .de ( staged_de ), 125 .d ( ~d ), 126 .qe ( ), 127 .q ( staged_q ), 128 .ds ( ), 129 .qs ( ) 130 ); 131 132 // The shadow register: 133 // - Holds the 1's complement value. 134 // - Written in Phase 1. 135 // - Writes are ignored in case of update errors. 136 // - Gets the value from the staged register. 137 // - Once storage error occurs, do not allow any further update until reset 138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage; Tests: T1 T2 T3  139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage; 140 prim_subreg #( 141 .DW ( DW ), 142 .SwAccess ( InvertedSwAccess ), 143 .RESVAL ( ~RESVAL ) 144 ) shadow_reg ( 145 .clk_i ( clk_i ), 146 .rst_ni ( rst_shadowed_ni ), 147 .we ( shadow_we ), 148 .wd ( staged_q ), 149 .de ( shadow_de ), 150 .d ( staged_q ), 151 .qe ( ), 152 .q ( shadow_q ), 153 .ds ( ), 154 .qs ( ) 155 ); 156 157 // The committed register: 158 // - Written in Phase 1. 159 // - Writes are ignored in case of update errors. 160 1/1 assign committed_we = shadow_we; Tests: T3 T13 T18  161 unreachable assign committed_de = shadow_de; 162 prim_subreg #( 163 .DW ( DW ), 164 .SwAccess ( SwAccess ), 165 .RESVAL ( RESVAL ) 166 ) committed_reg ( 167 .clk_i ( clk_i ), 168 .rst_ni ( rst_ni ), 169 .we ( committed_we ), 170 .wd ( wr_data ), 171 .de ( committed_de ), 172 .d ( d ), 173 .qe ( committed_qe ), 174 .q ( committed_q ), 175 .ds ( ds ), 176 .qs ( committed_qs ) 177 ); 178 179 // Output phase for hwext. 180 1/1 assign phase = phase_q; Tests: T1 T2 T3  181 182 // Error detection - all bits must match. 183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0; Tests: T1 T2 T3  184 1/1 assign err_storage = (~shadow_q != committed_q); Tests: T1 T2 T3  185 186 // Remaining output assignments 187 1/1 assign qe = committed_qe; Tests: T3 T13 T18  188 1/1 assign q = committed_q; Tests: T1 T2 T3  189 1/1 assign qs = committed_qs; Tests: T1 T2 T3 

Cond Coverage for Module : prim_subreg_shadow
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T13,T18

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT79,T80,T81

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T13,T18
110Not Covered
111CoveredT3,T13,T18

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT3,T13,T18
1011CoveredT3,T13,T18
1101Not Covered
1110Not Covered
1111CoveredT3,T13,T18

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT3,T13,T18
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T18

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T18

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT3,T13,T18
10CoveredT3,T13,T18
11Not Covered

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Module : prim_subreg_shadow
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00


183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T13,T18
0 Covered T1,T2,T3


100 if (!rst_ni) begin -1- 101 phase_q <= 1'b0; ==> 102 end else if (wr_en && !err_storage) begin -2- 103 phase_q <= ~phase_q; ==> 104 end else if (phase_clear || err_storage) begin -3- 105 phase_q <= 1'b0; ==> 106 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T13,T18
0 0 1 Covered T79,T80,T81
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : prim_subreg_shadow
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 2514 2514 0 0
MubiIsNotYetSupported_A 774470958 772660204 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 2514 2514 0 0
T1 2 2 0 0
T2 2 2 0 0
T3 2 2 0 0
T7 2 2 0 0
T13 2 2 0 0
T14 2 2 0 0
T15 2 2 0 0
T18 2 2 0 0
T19 2 2 0 0
T20 2 2 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 774470958 772660204 0 0
T1 3272 3124 0 0
T2 3902 3752 0 0
T3 6764 6620 0 0
T7 8492 7188 0 0
T13 47420 47280 0 0
T14 12492 12296 0 0
T15 6830 6714 0 0
T18 5892 5724 0 0
T19 971822 935742 0 0
T20 140716 140562 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00

93 // - In case of RO, SW should not interfere with update process. 94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re; Tests: T79 T80 T81  95 96 // Phase tracker: 97 // - Reads from SW clear the phase back to 0. 98 // - Writes have priority (can come from SW or HW). 99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg 100 1/1 if (!rst_ni) begin Tests: T1 T2 T3  101 1/1 phase_q <= 1'b0; Tests: T1 T2 T3  102 1/1 end else if (wr_en && !err_storage) begin Tests: T1 T2 T3  103 1/1 phase_q <= ~phase_q; Tests: T3 T13 T18  104 1/1 end else if (phase_clear || err_storage) begin Tests: T1 T2 T3  105 1/1 phase_q <= 1'b0; Tests: T79 T80 T81  106 end MISSING_ELSE 107 end 108 109 // The staged register: 110 // - Holds the 1's complement value. 111 // - Written in Phase 0. 112 // - Once storage error occurs, do not allow any further update until reset 113 1/1 assign staged_we = we & ~phase_q & ~err_storage; Tests: T1 T2 T3  114 unreachable assign staged_de = de & ~phase_q & ~err_storage; 115 prim_subreg #( 116 .DW ( DW ), 117 .SwAccess ( StagedSwAccess ), 118 .RESVAL ( ~RESVAL ) 119 ) staged_reg ( 120 .clk_i ( clk_i ), 121 .rst_ni ( rst_ni ), 122 .we ( staged_we ), 123 .wd ( ~wr_data ), 124 .de ( staged_de ), 125 .d ( ~d ), 126 .qe ( ), 127 .q ( staged_q ), 128 .ds ( ), 129 .qs ( ) 130 ); 131 132 // The shadow register: 133 // - Holds the 1's complement value. 134 // - Written in Phase 1. 135 // - Writes are ignored in case of update errors. 136 // - Gets the value from the staged register. 137 // - Once storage error occurs, do not allow any further update until reset 138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage; Tests: T1 T2 T3  139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage; 140 prim_subreg #( 141 .DW ( DW ), 142 .SwAccess ( InvertedSwAccess ), 143 .RESVAL ( ~RESVAL ) 144 ) shadow_reg ( 145 .clk_i ( clk_i ), 146 .rst_ni ( rst_shadowed_ni ), 147 .we ( shadow_we ), 148 .wd ( staged_q ), 149 .de ( shadow_de ), 150 .d ( staged_q ), 151 .qe ( ), 152 .q ( shadow_q ), 153 .ds ( ), 154 .qs ( ) 155 ); 156 157 // The committed register: 158 // - Written in Phase 1. 159 // - Writes are ignored in case of update errors. 160 1/1 assign committed_we = shadow_we; Tests: T3 T13 T18  161 unreachable assign committed_de = shadow_de; 162 prim_subreg #( 163 .DW ( DW ), 164 .SwAccess ( SwAccess ), 165 .RESVAL ( RESVAL ) 166 ) committed_reg ( 167 .clk_i ( clk_i ), 168 .rst_ni ( rst_ni ), 169 .we ( committed_we ), 170 .wd ( wr_data ), 171 .de ( committed_de ), 172 .d ( d ), 173 .qe ( committed_qe ), 174 .q ( committed_q ), 175 .ds ( ds ), 176 .qs ( committed_qs ) 177 ); 178 179 // Output phase for hwext. 180 1/1 assign phase = phase_q; Tests: T1 T2 T3  181 182 // Error detection - all bits must match. 183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0; Tests: T1 T2 T3  184 1/1 assign err_storage = (~shadow_q != committed_q); Tests: T1 T2 T3  185 186 // Remaining output assignments 187 1/1 assign qe = committed_qe; Tests: T3 T13 T18  188 1/1 assign q = committed_q; Tests: T1 T2 T3  189 1/1 assign qs = committed_qs; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T13,T18

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT79,T80,T81

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T13,T18
110Not Covered
111CoveredT3,T13,T18

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT3,T13,T18
1011CoveredT3,T13,T18
1101Not Covered
1110Not Covered
1111CoveredT3,T13,T18

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT3,T13,T18
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T18

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T18

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT3,T13,T18
10CoveredT3,T13,T18
11Not Covered

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00


183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T13,T18
0 Covered T1,T2,T3


100 if (!rst_ni) begin -1- 101 phase_q <= 1'b0; ==> 102 end else if (wr_en && !err_storage) begin -2- 103 phase_q <= ~phase_q; ==> 104 end else if (phase_clear || err_storage) begin -3- 105 phase_q <= 1'b0; ==> 106 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T13,T18
0 0 1 Covered T79,T80,T81
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1257 1257 0 0
MubiIsNotYetSupported_A 387235479 386330102 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387235479 386330102 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

Line Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1
Line No.TotalCoveredPercent
TOTAL1616100.00
CONT_ASSIGN9411100.00
ALWAYS10066100.00
CONT_ASSIGN11311100.00
CONT_ASSIGN11400
CONT_ASSIGN13811100.00
CONT_ASSIGN13900
CONT_ASSIGN16011100.00
CONT_ASSIGN16100
CONT_ASSIGN18011100.00
CONT_ASSIGN18311100.00
CONT_ASSIGN18411100.00
CONT_ASSIGN18711100.00
CONT_ASSIGN18811100.00
CONT_ASSIGN18911100.00

93 // - In case of RO, SW should not interfere with update process. 94 1/1 assign phase_clear = (SwAccess == SwAccessRO) ? 1'b0 : re; Tests: T79 T80 T81  95 96 // Phase tracker: 97 // - Reads from SW clear the phase back to 0. 98 // - Writes have priority (can come from SW or HW). 99 always_ff @(posedge clk_i or negedge rst_ni) begin : phase_reg 100 1/1 if (!rst_ni) begin Tests: T1 T2 T3  101 1/1 phase_q <= 1'b0; Tests: T1 T2 T3  102 1/1 end else if (wr_en && !err_storage) begin Tests: T1 T2 T3  103 1/1 phase_q <= ~phase_q; Tests: T3 T13 T18  104 1/1 end else if (phase_clear || err_storage) begin Tests: T1 T2 T3  105 1/1 phase_q <= 1'b0; Tests: T79 T80 T81  106 end MISSING_ELSE 107 end 108 109 // The staged register: 110 // - Holds the 1's complement value. 111 // - Written in Phase 0. 112 // - Once storage error occurs, do not allow any further update until reset 113 1/1 assign staged_we = we & ~phase_q & ~err_storage; Tests: T1 T2 T3  114 unreachable assign staged_de = de & ~phase_q & ~err_storage; 115 prim_subreg #( 116 .DW ( DW ), 117 .SwAccess ( StagedSwAccess ), 118 .RESVAL ( ~RESVAL ) 119 ) staged_reg ( 120 .clk_i ( clk_i ), 121 .rst_ni ( rst_ni ), 122 .we ( staged_we ), 123 .wd ( ~wr_data ), 124 .de ( staged_de ), 125 .d ( ~d ), 126 .qe ( ), 127 .q ( staged_q ), 128 .ds ( ), 129 .qs ( ) 130 ); 131 132 // The shadow register: 133 // - Holds the 1's complement value. 134 // - Written in Phase 1. 135 // - Writes are ignored in case of update errors. 136 // - Gets the value from the staged register. 137 // - Once storage error occurs, do not allow any further update until reset 138 1/1 assign shadow_we = we & phase_q & ~err_update & ~err_storage; Tests: T1 T2 T3  139 unreachable assign shadow_de = de & phase_q & ~err_update & ~err_storage; 140 prim_subreg #( 141 .DW ( DW ), 142 .SwAccess ( InvertedSwAccess ), 143 .RESVAL ( ~RESVAL ) 144 ) shadow_reg ( 145 .clk_i ( clk_i ), 146 .rst_ni ( rst_shadowed_ni ), 147 .we ( shadow_we ), 148 .wd ( staged_q ), 149 .de ( shadow_de ), 150 .d ( staged_q ), 151 .qe ( ), 152 .q ( shadow_q ), 153 .ds ( ), 154 .qs ( ) 155 ); 156 157 // The committed register: 158 // - Written in Phase 1. 159 // - Writes are ignored in case of update errors. 160 1/1 assign committed_we = shadow_we; Tests: T3 T13 T18  161 unreachable assign committed_de = shadow_de; 162 prim_subreg #( 163 .DW ( DW ), 164 .SwAccess ( SwAccess ), 165 .RESVAL ( RESVAL ) 166 ) committed_reg ( 167 .clk_i ( clk_i ), 168 .rst_ni ( rst_ni ), 169 .we ( committed_we ), 170 .wd ( wr_data ), 171 .de ( committed_de ), 172 .d ( d ), 173 .qe ( committed_qe ), 174 .q ( committed_q ), 175 .ds ( ds ), 176 .qs ( committed_qs ) 177 ); 178 179 // Output phase for hwext. 180 1/1 assign phase = phase_q; Tests: T1 T2 T3  181 182 // Error detection - all bits must match. 183 1/1 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0; Tests: T1 T2 T3  184 1/1 assign err_storage = (~shadow_q != committed_q); Tests: T1 T2 T3  185 186 // Remaining output assignments 187 1/1 assign qe = committed_qe; Tests: T3 T13 T18  188 1/1 assign q = committed_q; Tests: T1 T2 T3  189 1/1 assign qs = committed_qs; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1
TotalCoveredPercent
Conditions261973.08
Logical261973.08
Non-Logical00
Event00

 LINE       102
 EXPRESSION (wr_en && ((!err_storage)))
             --1--    --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11CoveredT3,T13,T18

 LINE       104
 EXPRESSION (phase_clear || err_storage)
             -----1-----    -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT79,T80,T81

 LINE       113
 EXPRESSION (we & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT3,T13,T18
110Not Covered
111CoveredT3,T13,T18

 LINE       114
 EXPRESSION (de & ((~phase_q)) & ((~err_storage)))
             -1   ------2-----   --------3-------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Unreachable
110Unreachable
111Unreachable

 LINE       138
 EXPRESSION (we & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT3,T13,T18
1011CoveredT3,T13,T18
1101Not Covered
1110Not Covered
1111CoveredT3,T13,T18

 LINE       139
 EXPRESSION (de & phase_q & ((~err_update)) & ((~err_storage)))
             -1   ---2---   -------3-------   --------4-------
-1--2--3--4-StatusTests
0111CoveredT3,T13,T18
1011Unreachable
1101Unreachable
1110Unreachable
1111Unreachable

 LINE       183
 EXPRESSION (((~staged_q) != wr_data) ? (phase_q & wr_en) : 1'b0)
             ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T18

 LINE       183
 SUB-EXPRESSION ((~staged_q) != wr_data)
                ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T13,T18

 LINE       183
 SUB-EXPRESSION (phase_q & wr_en)
                 ---1---   --2--
-1--2-StatusTests
01CoveredT3,T13,T18
10CoveredT3,T13,T18
11Not Covered

 LINE       184
 EXPRESSION ((~shadow_q) != committed_q)
            --------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1Not Covered

Branch Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1
Line No.TotalCoveredPercent
Branches 6 6 100.00
TERNARY 183 2 2 100.00
IF 100 4 4 100.00


183 assign err_update = (~staged_q != wr_data) ? phase_q & wr_en : 1'b0; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T3,T13,T18
0 Covered T1,T2,T3


100 if (!rst_ni) begin -1- 101 phase_q <= 1'b0; ==> 102 end else if (wr_en && !err_storage) begin -2- 103 phase_q <= ~phase_q; ==> 104 end else if (phase_clear || err_storage) begin -3- 105 phase_q <= 1'b0; ==> 106 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T3,T13,T18
0 0 1 Covered T79,T80,T81
0 0 0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 2 2 100.00 2 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 2 2 100.00 2 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
CheckSwAccessIsLegal_A 1257 1257 0 0
MubiIsNotYetSupported_A 387235479 386330102 0 0


CheckSwAccessIsLegal_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1257 1257 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T13 1 1 0 0
T14 1 1 0 0
T15 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

MubiIsNotYetSupported_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387235479 386330102 0 0
T1 1636 1562 0 0
T2 1951 1876 0 0
T3 3382 3310 0 0
T7 4246 3594 0 0
T13 23710 23640 0 0
T14 6246 6148 0 0
T15 3415 3357 0 0
T18 2946 2862 0 0
T19 485911 467871 0 0
T20 70358 70281 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%