Unified Coverage Report :: Module :: prim_lc_sync

Module : prim_lc_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_22/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_prim_lc_sync_0.1/rtl/prim_lc_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync	100.00	100.00					100.00
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync	100.00	100.00					100.00
tb.dut.u_lc_seed_hw_rd_en_sync	100.00	100.00					100.00
tb.dut.u_flash_hw_if.u_sync_rma_req	100.00	100.00					100.00
tb.dut.u_prog_tl_gate.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_lc_escalation_en_sync	100.00	100.00					100.00
tb.dut.u_tl_gate.u_err_en_sync	100.00	100.00					100.00
tb.dut.u_eflash.u_lc_nvm_debug_en_sync	100.00	100.00					100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
52.96	52.96						u_region_cfg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_lc_seed_hw_rd_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.96	100.00	93.75		92.11	98.94	100.00	u_flash_hw_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
78.37	100.00	88.89		57.14	95.83	50.00	u_prog_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_lc_escalation_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.85	97.12	94.40	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

---

Module Instance : tb.dut.u_tl_gate.u_err_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.60	100.00	100.00		57.14	95.83	50.00	u_tl_gate

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00				100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.56	97.67	86.00			100.00		u_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[0].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[1].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[2].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[3].gen_bits[3].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[0].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[1].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[2].u_prim_buf	100.00	100.00
gen_buffs[4].gen_bits[3].u_prim_buf	100.00	100.00
gen_flops.u_prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_lc_seed_hw_rd_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_lc_escalation_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=3,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_flash_hw_if.u_sync_rma_req

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        3/3              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=2,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_prog_tl_gate.u_err_en_sync

SCORE	LINE
100.00	100.00

tb.dut.u_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Line Coverage for Module : prim_lc_sync ( parameter NumCopies=5,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        5/5              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Module : prim_lc_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	10420	10420	0	0
OutputsKnown_A	2147483647	2147483647	0	0
gen_flops.OutputDelay_A	2147483647	2147483647	0	21618
gen_no_flops.OutputDelay_A	756664410	754997206	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	10420	10420	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T7	10	10	0	0
T13	10	10	0	0
T14	10	10	0	0
T15	10	10	0	0
T18	10	10	0	0
T19	10	10	0	0
T20	10	10	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	16360	15620	0	0
T2	19510	18760	0	0
T3	33820	33100	0	0
T7	42460	35940	0	0
T13	237100	236400	0	0
T14	62460	61480	0	0
T15	34150	33570	0	0
T18	29460	28620	0	0
T19	4859110	4678710	0	0
T20	703580	702810	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	21618
T1	13088	12472	0	24
T2	15608	14984	0	24
T3	27056	26456	0	24
T7	33968	28536	0	24
T13	189680	189096	0	24
T14	49968	49160	0	24
T15	27320	26832	0	24
T18	23568	22872	0	24
T19	3887288	3737184	0	24
T20	562864	562224	0	24

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	756664410	754997206	0	0
T1	3272	3124	0	0
T2	3902	3752	0	0
T3	6764	6620	0	0
T7	8492	7188	0	0
T13	47420	47280	0	0
T14	12492	12296	0	0
T15	6830	6714	0	0
T18	5892	5724	0	0
T19	971822	935742	0	0
T20	140716	140562	0	0

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332305	377498703	0	0
gen_flops.OutputDelay_A	378332305	377465922	0	2721

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377498703	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377465922	0	2721
T1	1636	1559	0	3
T2	1951	1873	0	3
T3	3382	3307	0	3
T7	4246	3567	0	3
T13	23710	23637	0	3
T14	6246	6145	0	3
T15	3415	3354	0	3
T18	2946	2859	0	3
T19	485911	467148	0	3
T20	70358	70278	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332305	377498703	0	0
gen_flops.OutputDelay_A	378332305	377465922	0	2721

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377498703	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377465922	0	2721
T1	1636	1559	0	3
T2	1951	1873	0	3
T3	3382	3307	0	3
T7	4246	3567	0	3
T13	23710	23637	0	3
T14	6246	6145	0	3
T15	3415	3354	0	3
T18	2946	2859	0	3
T19	485911	467148	0	3
T20	70358	70278	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332305	377498703	0	0
gen_flops.OutputDelay_A	378332305	377465922	0	2721

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377498703	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377465922	0	2721
T1	1636	1559	0	3
T2	1951	1873	0	3
T3	3382	3307	0	3
T7	4246	3567	0	3
T13	23710	23637	0	3
T14	6246	6145	0	3
T15	3415	3354	0	3
T18	2946	2859	0	3
T19	485911	467148	0	3
T20	70358	70278	0	3

Line Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332305	377498703	0	0
gen_flops.OutputDelay_A	378332305	377465922	0	2721

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377498703	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377465922	0	2721
T1	1636	1559	0	3
T2	1951	1873	0	3
T3	3382	3307	0	3
T7	4246	3567	0	3
T13	23710	23637	0	3
T14	6246	6145	0	3
T15	3415	3354	0	3
T18	2946	2859	0	3
T19	485911	467148	0	3
T20	70358	70278	0	3

Line Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_seed_hw_rd_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332305	377498703	0	0
gen_flops.OutputDelay_A	378332305	377465922	0	2721

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377498703	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377465922	0	2721
T1	1636	1559	0	3
T2	1951	1873	0	3
T3	3382	3307	0	3
T7	4246	3567	0	3
T13	23710	23637	0	3
T14	6246	6145	0	3
T15	3415	3354	0	3
T18	2946	2859	0	3
T19	485911	467148	0	3
T20	70358	70278	0	3

Line Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        3/3              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_flash_hw_if.u_sync_rma_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332305	377498703	0	0
gen_flops.OutputDelay_A	378332305	377465922	0	2721

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377498703	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332305	377465922	0	2721
T1	1636	1559	0	3
T2	1951	1873	0	3
T3	3382	3307	0	3
T7	4246	3567	0	3
T13	23710	23637	0	3
T14	6246	6145	0	3
T15	3415	3354	0	3
T18	2946	2859	0	3
T19	485911	467148	0	3
T20	70358	70278	0	3

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332205	377498603	0	0
gen_no_flops.OutputDelay_A	378332205	377498603	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332205	377498603	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332205	377498603	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

Line Coverage for Instance : tb.dut.u_lc_escalation_en_sync

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        1/1              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_lc_escalation_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378308495	377474893	0	0
gen_flops.OutputDelay_A	378308495	377442262	0	2571

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378308495	377474893	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378308495	377442262	0	2571
T1	1636	1559	0	3
T2	1951	1873	0	3
T3	3382	3307	0	3
T7	4246	3567	0	3
T13	23710	23637	0	3
T14	6246	6145	0	3
T15	3415	3354	0	3
T18	2946	2859	0	3
T19	485911	467148	0	3
T20	70358	70278	0	3

Line Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
ALWAYS	84	0	0
CONT_ASSIGN	93	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84         unreachable        if (!rst_ni) begin
85         unreachable           unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87         unreachable           unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93         1/1              assign lc_en = lc_en_i;
           Tests:       T1 T2 T3 
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        2/2              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_tl_gate.u_err_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332205	377498603	0	0
gen_no_flops.OutputDelay_A	378332205	377498603	0	0

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332205	377498603	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_no_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332205	377498603	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

Line Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
ALWAYS	68	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00
CONT_ASSIGN	106	1	1	100.00

67                            always_ff @(posedge clk_i) begin
68         1/1                  lc_en_in_sva_q <= lc_en_i;
           Tests:       T1 T2 T3 
69                            end
70                          `ASSERT(OutputDelay_A,
71                                  rst_ni |-> ##3 lc_en_o == {NumCopies{$past(lc_en_in_sva_q, 2)}} ||
72                                                 ($past(lc_en_in_sva_q, 2) != $past(lc_en_in_sva_q, 1)))
73                      `endif
74                        end else begin : gen_no_flops
75                          //VCS coverage off
76                          // pragma coverage off
77                      
78                          // This unused companion logic helps remove lint errors
79                          // for modules where clock and reset are used for assertions only
80                          // or nothing at all.
81                          // This logic will be removed for sythesis since it is unloaded.
82                          lc_ctrl_pkg::lc_tx_t unused_logic;
83                          always_ff @(posedge clk_i or negedge rst_ni) begin
84                            if (!rst_ni) begin
85                               unused_logic <= lc_ctrl_pkg::Off;
86                            end else begin
87                               unused_logic <= lc_en_i;
88                            end
89                          end
90                          //VCS coverage on
91                          // pragma coverage on
92                      
93                          assign lc_en = lc_en_i;
94                      
95                          `ASSERT(OutputDelay_A, lc_en_o == {NumCopies{lc_en_i}})
96                        end
97                      
98                        for (genvar j = 0; j < NumCopies; j++) begin : gen_buffs
99                          logic [lc_ctrl_pkg::TxWidth-1:0] lc_en_out;
100                         for (genvar k = 0; k < lc_ctrl_pkg::TxWidth; k++) begin : gen_bits
101                           prim_sec_anchor_buf u_prim_buf (
102                             .in_i(lc_en[k]),
103                             .out_o(lc_en_out[k])
104                           );
105                         end
106        5/5              assign lc_en_o[j] = lc_ctrl_pkg::lc_tx_t'(lc_en_out);
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3 

---

Assert Coverage for Instance : tb.dut.u_eflash.u_lc_nvm_debug_en_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
NumCopiesMustBeGreaterZero_A	1042	1042	0	0
OutputsKnown_A	378332205	377498603	0	0
gen_flops.OutputDelay_A	378332205	377465837	0	2721

NumCopiesMustBeGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1042	1042	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T13	1	1	0	0
T14	1	1	0	0
T15	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

OutputsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332205	377498603	0	0
T1	1636	1562	0	0
T2	1951	1876	0	0
T3	3382	3310	0	0
T7	4246	3594	0	0
T13	23710	23640	0	0
T14	6246	6148	0	0
T15	3415	3357	0	0
T18	2946	2862	0	0
T19	485911	467871	0	0
T20	70358	70281	0	0

gen_flops.OutputDelay_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	378332205	377465837	0	2721
T1	1636	1559	0	3
T2	1951	1873	0	3
T3	3382	3307	0	3
T7	4246	3567	0	3
T13	23710	23637	0	3
T14	6246	6145	0	3
T15	3415	3354	0	3
T18	2946	2859	0	3
T19	485911	467148	0	3
T20	70358	70278	0	3