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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 95.73 93.98 98.31 92.52 98.25 96.99 98.21


Total test records in report: 1267
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T279 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.587314356 Aug 27 12:41:20 PM UTC 24 Aug 27 12:41:42 PM UTC 24 47696000 ps
T286 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.157084898 Aug 27 12:41:15 PM UTC 24 Aug 27 12:41:44 PM UTC 24 49156900 ps
T150 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2916443752 Aug 27 12:34:19 PM UTC 24 Aug 27 12:41:46 PM UTC 24 8179030000 ps
T494 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.4195972761 Aug 27 12:41:23 PM UTC 24 Aug 27 12:41:52 PM UTC 24 56569600 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1433131486 Aug 27 12:39:39 PM UTC 24 Aug 27 12:41:57 PM UTC 24 664307400 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.1224593508 Aug 27 12:40:40 PM UTC 24 Aug 27 12:41:58 PM UTC 24 3255285500 ps
T495 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1505324239 Aug 27 12:41:01 PM UTC 24 Aug 27 12:42:01 PM UTC 24 318637600 ps
T496 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.394662535 Aug 27 12:41:45 PM UTC 24 Aug 27 12:42:20 PM UTC 24 283156700 ps
T497 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.1603845753 Aug 27 12:41:37 PM UTC 24 Aug 27 12:42:34 PM UTC 24 4277120100 ps
T217 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.11401398 Aug 27 12:38:51 PM UTC 24 Aug 27 12:42:49 PM UTC 24 2974842300 ps
T498 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.3138066035 Aug 27 12:39:12 PM UTC 24 Aug 27 12:43:03 PM UTC 24 24174171800 ps
T80 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2019859505 Aug 27 12:14:07 PM UTC 24 Aug 27 12:43:05 PM UTC 24 84597640600 ps
T499 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3504151643 Aug 27 12:39:10 PM UTC 24 Aug 27 12:43:09 PM UTC 24 4281499900 ps
T414 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.1503034217 Aug 27 12:41:58 PM UTC 24 Aug 27 12:43:37 PM UTC 24 2990981700 ps
T500 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.247161674 Aug 27 12:40:04 PM UTC 24 Aug 27 12:43:50 PM UTC 24 26433428600 ps
T501 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.231569827 Aug 27 12:42:01 PM UTC 24 Aug 27 12:43:58 PM UTC 24 5474623900 ps
T502 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.3958442098 Aug 27 12:28:10 PM UTC 24 Aug 27 12:44:24 PM UTC 24 572590300 ps
T503 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.3419865230 Aug 27 12:43:59 PM UTC 24 Aug 27 12:44:25 PM UTC 24 35767600 ps
T504 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.4051591359 Aug 27 12:42:35 PM UTC 24 Aug 27 12:44:33 PM UTC 24 1205401500 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1420903165 Aug 27 12:39:50 PM UTC 24 Aug 27 12:44:34 PM UTC 24 23713561400 ps
T170 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.3672841994 Aug 27 12:41:39 PM UTC 24 Aug 27 12:44:50 PM UTC 24 138392000 ps
T439 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.706758218 Aug 27 12:44:11 PM UTC 24 Aug 27 12:44:57 PM UTC 24 44406100 ps
T505 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.4146476264 Aug 27 12:43:39 PM UTC 24 Aug 27 12:45:00 PM UTC 24 2361397800 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.3830785857 Aug 27 12:44:25 PM UTC 24 Aug 27 12:45:03 PM UTC 24 86293600 ps
T102 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1530709615 Aug 27 12:44:34 PM UTC 24 Aug 27 12:45:12 PM UTC 24 15574300 ps
T506 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.82367049 Aug 27 12:44:51 PM UTC 24 Aug 27 12:45:13 PM UTC 24 53698400 ps
T88 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1639285755 Aug 27 12:41:21 PM UTC 24 Aug 27 12:45:20 PM UTC 24 10014785900 ps
T287 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1835538478 Aug 27 12:44:58 PM UTC 24 Aug 27 12:45:22 PM UTC 24 24286300 ps
T437 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.3824561795 Aug 27 12:44:26 PM UTC 24 Aug 27 12:45:27 PM UTC 24 153936900 ps
T280 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.1639095339 Aug 27 12:45:01 PM UTC 24 Aug 27 12:45:30 PM UTC 24 14949100 ps
T507 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2198663300 Aug 27 12:45:13 PM UTC 24 Aug 27 12:45:38 PM UTC 24 56462200 ps
T508 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.1161555780 Aug 27 12:41:23 PM UTC 24 Aug 27 12:46:07 PM UTC 24 37347800 ps
T210 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.1299298699 Aug 27 12:43:04 PM UTC 24 Aug 27 12:46:08 PM UTC 24 2572418100 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.913512179 Aug 27 12:43:10 PM UTC 24 Aug 27 12:46:09 PM UTC 24 1171523900 ps
T401 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.251101367 Aug 27 12:44:34 PM UTC 24 Aug 27 12:46:11 PM UTC 24 2081087600 ps
T509 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.3766390194 Aug 27 12:34:09 PM UTC 24 Aug 27 12:46:32 PM UTC 24 1396421100 ps
T226 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.3419893378 Aug 27 12:43:05 PM UTC 24 Aug 27 12:46:43 PM UTC 24 2952015500 ps
T510 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.572003762 Aug 27 12:42:50 PM UTC 24 Aug 27 12:46:44 PM UTC 24 2180905200 ps
T54 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2290116145 Aug 27 12:46:09 PM UTC 24 Aug 27 12:46:51 PM UTC 24 96535200 ps
T511 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.616978342 Aug 27 12:45:27 PM UTC 24 Aug 27 12:46:57 PM UTC 24 1462195300 ps
T512 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.652806218 Aug 27 12:43:51 PM UTC 24 Aug 27 12:47:16 PM UTC 24 5525017200 ps
T513 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.1661162149 Aug 27 12:39:18 PM UTC 24 Aug 27 12:47:31 PM UTC 24 7757576500 ps
T514 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.4269923488 Aug 27 12:45:14 PM UTC 24 Aug 27 12:48:00 PM UTC 24 52834700 ps
T415 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.310502406 Aug 27 12:46:33 PM UTC 24 Aug 27 12:48:13 PM UTC 24 2795073700 ps
T117 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1293868073 Aug 27 12:19:07 PM UTC 24 Aug 27 12:48:26 PM UTC 24 355446607000 ps
T223 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.1516516594 Aug 27 12:41:33 PM UTC 24 Aug 27 12:48:30 PM UTC 24 735994000 ps
T190 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.1818431642 Aug 27 12:34:22 PM UTC 24 Aug 27 12:48:40 PM UTC 24 40126869700 ps
T89 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3300041511 Aug 27 12:45:04 PM UTC 24 Aug 27 12:48:44 PM UTC 24 10017010500 ps
T515 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.1277939186 Aug 27 12:46:44 PM UTC 24 Aug 27 12:48:48 PM UTC 24 583022300 ps
T516 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.1755104089 Aug 27 12:48:45 PM UTC 24 Aug 27 12:49:14 PM UTC 24 164952100 ps
T517 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1069464069 Aug 27 12:42:21 PM UTC 24 Aug 27 12:49:16 PM UTC 24 3265703300 ps
T518 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.2205537923 Aug 27 12:46:58 PM UTC 24 Aug 27 12:49:34 PM UTC 24 653476300 ps
T519 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.191224610 Aug 27 12:17:38 PM UTC 24 Aug 27 12:49:38 PM UTC 24 2737953200 ps
T520 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.82136694 Aug 27 12:43:58 PM UTC 24 Aug 27 12:49:39 PM UTC 24 20866239800 ps
T430 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.2355844551 Aug 27 12:48:49 PM UTC 24 Aug 27 12:49:41 PM UTC 24 53878900 ps
T171 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3412505033 Aug 27 12:45:40 PM UTC 24 Aug 27 12:49:46 PM UTC 24 44973100 ps
T221 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3134136312 Aug 27 12:47:31 PM UTC 24 Aug 27 12:49:55 PM UTC 24 3306761400 ps
T521 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.700083852 Aug 27 12:48:27 PM UTC 24 Aug 27 12:49:55 PM UTC 24 4627944200 ps
T188 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.2612584656 Aug 27 12:49:35 PM UTC 24 Aug 27 12:50:06 PM UTC 24 11052700 ps
T522 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.1495758155 Aug 27 12:49:17 PM UTC 24 Aug 27 12:50:07 PM UTC 24 203870400 ps
T523 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.67508225 Aug 27 12:47:17 PM UTC 24 Aug 27 12:50:07 PM UTC 24 1784966000 ps
T524 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.2007395571 Aug 27 12:49:41 PM UTC 24 Aug 27 12:50:07 PM UTC 24 34979800 ps
T525 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.1484531840 Aug 27 12:49:15 PM UTC 24 Aug 27 12:50:08 PM UTC 24 31831700 ps
T526 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.438177533 Aug 27 12:49:42 PM UTC 24 Aug 27 12:50:09 PM UTC 24 45045700 ps
T527 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1101520243 Aug 27 12:49:47 PM UTC 24 Aug 27 12:50:10 PM UTC 24 25563000 ps
T528 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3792269271 Aug 27 12:49:56 PM UTC 24 Aug 27 12:50:21 PM UTC 24 126882200 ps
T529 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.236315493 Aug 27 12:26:16 PM UTC 24 Aug 27 12:50:37 PM UTC 24 376797800 ps
T530 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.879635035 Aug 27 12:46:44 PM UTC 24 Aug 27 12:50:41 PM UTC 24 5544120400 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.222134987 Aug 27 12:49:40 PM UTC 24 Aug 27 12:50:47 PM UTC 24 2148803600 ps
T55 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.2986560593 Aug 27 12:50:22 PM UTC 24 Aug 27 12:51:01 PM UTC 24 686831100 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3775736555 Aug 27 12:48:32 PM UTC 24 Aug 27 12:51:14 PM UTC 24 12242582100 ps
T283 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2751189229 Aug 27 12:49:56 PM UTC 24 Aug 27 12:51:18 PM UTC 24 10018888300 ps
T531 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.2568754937 Aug 27 12:51:15 PM UTC 24 Aug 27 12:53:04 PM UTC 24 619654700 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.4192455768 Aug 27 12:48:13 PM UTC 24 Aug 27 12:51:29 PM UTC 24 8097936100 ps
T532 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.2707831544 Aug 27 12:50:08 PM UTC 24 Aug 27 12:51:30 PM UTC 24 29380000 ps
T533 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.2706696593 Aug 27 12:50:08 PM UTC 24 Aug 27 12:51:57 PM UTC 24 2921272500 ps
T127 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.2210828449 Aug 27 12:41:43 PM UTC 24 Aug 27 12:51:59 PM UTC 24 27675141900 ps
T534 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2454617699 Aug 27 12:48:41 PM UTC 24 Aug 27 12:52:32 PM UTC 24 80106136700 ps
T535 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.3347721393 Aug 27 12:50:48 PM UTC 24 Aug 27 12:52:48 PM UTC 24 1364200700 ps
T151 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.418181850 Aug 27 12:46:09 PM UTC 24 Aug 27 12:52:54 PM UTC 24 12627139400 ps
T536 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.608890931 Aug 27 12:48:01 PM UTC 24 Aug 27 12:52:55 PM UTC 24 1693305800 ps
T288 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.4107340040 Aug 27 12:08:57 PM UTC 24 Aug 27 12:53:31 PM UTC 24 21444940700 ps
T175 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3761110375 Aug 27 12:50:10 PM UTC 24 Aug 27 12:53:37 PM UTC 24 402454700 ps
T537 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1167037947 Aug 27 12:51:30 PM UTC 24 Aug 27 12:53:51 PM UTC 24 1791290800 ps
T538 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2525020425 Aug 27 12:50:07 PM UTC 24 Aug 27 12:54:05 PM UTC 24 66431300 ps
T539 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.1226691466 Aug 27 12:50:11 PM UTC 24 Aug 27 12:54:13 PM UTC 24 30704793900 ps
T191 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.3369270556 Aug 27 12:41:38 PM UTC 24 Aug 27 12:54:18 PM UTC 24 40125662700 ps
T540 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.737787628 Aug 27 12:51:58 PM UTC 24 Aug 27 12:54:22 PM UTC 24 586238000 ps
T541 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.1222044969 Aug 27 12:53:31 PM UTC 24 Aug 27 12:54:24 PM UTC 24 31470300 ps
T128 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.1383525027 Aug 27 12:19:40 PM UTC 24 Aug 27 12:54:31 PM UTC 24 88284781700 ps
T434 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.3111137455 Aug 27 12:53:37 PM UTC 24 Aug 27 12:54:31 PM UTC 24 30021500 ps
T542 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.4261867737 Aug 27 12:51:01 PM UTC 24 Aug 27 12:54:35 PM UTC 24 2051525800 ps
T418 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.317583219 Aug 27 12:53:53 PM UTC 24 Aug 27 12:54:35 PM UTC 24 130778000 ps
T543 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.4290686857 Aug 27 12:46:53 PM UTC 24 Aug 27 12:54:41 PM UTC 24 15276582800 ps
T544 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.896687154 Aug 27 12:54:18 PM UTC 24 Aug 27 12:54:41 PM UTC 24 46509000 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1555386409 Aug 27 12:54:25 PM UTC 24 Aug 27 12:54:44 PM UTC 24 50894500 ps
T189 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.198107105 Aug 27 12:54:06 PM UTC 24 Aug 27 12:54:44 PM UTC 24 29836700 ps
T545 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.3140693748 Aug 27 12:54:23 PM UTC 24 Aug 27 12:54:49 PM UTC 24 21498500 ps
T90 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.2372901995 Aug 27 12:14:33 PM UTC 24 Aug 27 12:55:01 PM UTC 24 412459500 ps
T546 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1268089573 Aug 27 12:54:40 PM UTC 24 Aug 27 12:55:08 PM UTC 24 43461100 ps
T547 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.1617853891 Aug 27 12:45:23 PM UTC 24 Aug 27 12:55:16 PM UTC 24 1137938400 ps
T129 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.1886127666 Aug 27 12:08:46 PM UTC 24 Aug 27 12:55:21 PM UTC 24 367398709300 ps
T548 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.1556756611 Aug 27 12:51:31 PM UTC 24 Aug 27 12:55:24 PM UTC 24 1332481400 ps
T549 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.541933197 Aug 27 12:55:02 PM UTC 24 Aug 27 12:55:31 PM UTC 24 347489600 ps
T550 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.4053090623 Aug 27 12:33:48 PM UTC 24 Aug 27 12:55:33 PM UTC 24 82467800 ps
T551 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.1841754520 Aug 27 12:35:14 PM UTC 24 Aug 27 12:55:39 PM UTC 24 2292101000 ps
T212 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3622390794 Aug 27 12:52:01 PM UTC 24 Aug 27 12:55:40 PM UTC 24 6347049700 ps
T552 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.2975167179 Aug 27 12:52:55 PM UTC 24 Aug 27 12:55:56 PM UTC 24 22705626300 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2454092685 Aug 27 12:54:14 PM UTC 24 Aug 27 12:55:59 PM UTC 24 2111478500 ps
T553 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.2855487122 Aug 27 12:53:05 PM UTC 24 Aug 27 12:56:22 PM UTC 24 9275459400 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1198219667 Aug 27 12:54:42 PM UTC 24 Aug 27 12:56:48 PM UTC 24 1412933200 ps
T554 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.2875232205 Aug 27 12:55:30 PM UTC 24 Aug 27 12:56:50 PM UTC 24 973838400 ps
T347 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2193664777 Aug 27 12:52:33 PM UTC 24 Aug 27 12:56:51 PM UTC 24 25545418500 ps
T555 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.2955120720 Aug 27 12:54:40 PM UTC 24 Aug 27 12:56:55 PM UTC 24 33142200 ps
T556 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.866360759 Aug 27 12:52:56 PM UTC 24 Aug 27 12:57:01 PM UTC 24 90746463800 ps
T557 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1237479453 Aug 27 12:56:55 PM UTC 24 Aug 27 12:57:26 PM UTC 24 100762100 ps
T192 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2721152581 Aug 27 12:54:40 PM UTC 24 Aug 27 12:57:42 PM UTC 24 10012197800 ps
T558 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.740198361 Aug 27 12:55:39 PM UTC 24 Aug 27 12:57:52 PM UTC 24 588891600 ps
T559 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.853413591 Aug 27 12:55:32 PM UTC 24 Aug 27 12:57:56 PM UTC 24 548430700 ps
T182 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.4158062841 Aug 27 12:54:45 PM UTC 24 Aug 27 12:57:57 PM UTC 24 80353400 ps
T560 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3231516935 Aug 27 12:54:49 PM UTC 24 Aug 27 12:58:04 PM UTC 24 12752756200 ps
T561 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.4131335657 Aug 27 12:57:02 PM UTC 24 Aug 27 12:58:05 PM UTC 24 103886300 ps
T562 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.998593369 Aug 27 12:14:18 PM UTC 24 Aug 27 12:58:06 PM UTC 24 358993655100 ps
T130 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.3157101139 Aug 27 12:08:34 PM UTC 24 Aug 27 12:58:07 PM UTC 24 374086254300 ps
T425 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.2686526821 Aug 27 12:57:27 PM UTC 24 Aug 27 12:58:10 PM UTC 24 39211700 ps
T563 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.783102756 Aug 27 12:45:21 PM UTC 24 Aug 27 12:58:10 PM UTC 24 794369400 ps
T385 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3600801662 Aug 27 12:57:43 PM UTC 24 Aug 27 12:58:16 PM UTC 24 11456200 ps
T564 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.519771150 Aug 27 12:57:41 PM UTC 24 Aug 27 12:58:22 PM UTC 24 134425000 ps
T565 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.1753967257 Aug 27 12:57:56 PM UTC 24 Aug 27 12:58:22 PM UTC 24 67083500 ps
T566 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.2780336986 Aug 27 12:57:57 PM UTC 24 Aug 27 12:58:24 PM UTC 24 214356800 ps
T567 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3459738753 Aug 27 12:56:49 PM UTC 24 Aug 27 12:58:25 PM UTC 24 3247297700 ps
T568 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.436687020 Aug 27 12:55:30 PM UTC 24 Aug 27 12:58:26 PM UTC 24 7351676300 ps
T569 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.902259312 Aug 27 12:58:07 PM UTC 24 Aug 27 12:58:32 PM UTC 24 107694100 ps
T570 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.3856524007 Aug 27 12:58:06 PM UTC 24 Aug 27 12:58:35 PM UTC 24 50190300 ps
T571 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.1072236898 Aug 27 12:55:57 PM UTC 24 Aug 27 12:58:58 PM UTC 24 688727300 ps
T572 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.3338709044 Aug 27 12:57:53 PM UTC 24 Aug 27 12:59:01 PM UTC 24 1321209600 ps
T573 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1971662122 Aug 27 12:58:26 PM UTC 24 Aug 27 12:59:01 PM UTC 24 613496400 ps
T574 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3944174630 Aug 27 12:58:08 PM UTC 24 Aug 27 12:59:11 PM UTC 24 25565800 ps
T575 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1464140559 Aug 27 12:51:19 PM UTC 24 Aug 27 12:59:32 PM UTC 24 3625409200 ps
T576 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1157172570 Aug 27 12:56:00 PM UTC 24 Aug 27 12:59:43 PM UTC 24 4104263800 ps
T577 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1767541968 Aug 27 12:56:51 PM UTC 24 Aug 27 12:59:52 PM UTC 24 22898389700 ps
T578 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.4074695936 Aug 27 12:58:17 PM UTC 24 Aug 27 01:00:02 PM UTC 24 810871200 ps
T185 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1135677001 Aug 27 12:45:30 PM UTC 24 Aug 27 01:00:14 PM UTC 24 160169796100 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3022423466 Aug 27 12:56:23 PM UTC 24 Aug 27 01:00:20 PM UTC 24 1321486600 ps
T579 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1062868490 Aug 27 12:58:25 PM UTC 24 Aug 27 01:00:28 PM UTC 24 3533240000 ps
T580 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2375763790 Aug 27 12:58:35 PM UTC 24 Aug 27 01:00:36 PM UTC 24 1463329400 ps
T581 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.88754286 Aug 27 12:54:41 PM UTC 24 Aug 27 01:00:48 PM UTC 24 61338500 ps
T582 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.2218493375 Aug 27 12:59:02 PM UTC 24 Aug 27 01:00:54 PM UTC 24 1124620900 ps
T583 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.862313835 Aug 27 12:41:46 PM UTC 24 Aug 27 01:01:06 PM UTC 24 1181401400 ps
T310 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.2649916718 Aug 27 01:00:36 PM UTC 24 Aug 27 01:01:07 PM UTC 24 27902400 ps
T584 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.4186836918 Aug 27 12:55:40 PM UTC 24 Aug 27 01:01:20 PM UTC 24 20912016700 ps
T585 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.1983521216 Aug 27 01:00:15 PM UTC 24 Aug 27 01:01:35 PM UTC 24 4931048000 ps
T586 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.1358656709 Aug 27 12:59:12 PM UTC 24 Aug 27 01:01:37 PM UTC 24 1224064600 ps
T419 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.383262952 Aug 27 01:00:49 PM UTC 24 Aug 27 01:01:39 PM UTC 24 55413200 ps
T587 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.3530229388 Aug 27 01:00:50 PM UTC 24 Aug 27 01:01:41 PM UTC 24 38175800 ps
T103 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2125455256 Aug 27 01:01:07 PM UTC 24 Aug 27 01:01:42 PM UTC 24 16103300 ps
T417 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.1059551882 Aug 27 01:00:55 PM UTC 24 Aug 27 01:01:46 PM UTC 24 230126100 ps
T588 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.370060948 Aug 27 12:56:52 PM UTC 24 Aug 27 01:01:47 PM UTC 24 41009074300 ps
T589 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.576663863 Aug 27 01:01:20 PM UTC 24 Aug 27 01:01:48 PM UTC 24 59500000 ps
T590 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3359753630 Aug 27 01:01:38 PM UTC 24 Aug 27 01:01:58 PM UTC 24 26164700 ps
T591 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2444962741 Aug 27 12:59:43 PM UTC 24 Aug 27 01:02:02 PM UTC 24 515781200 ps
T592 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.2876450168 Aug 27 01:01:36 PM UTC 24 Aug 27 01:02:03 PM UTC 24 15623700 ps
T593 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.3511413476 Aug 27 01:01:42 PM UTC 24 Aug 27 01:02:05 PM UTC 24 31852200 ps
T594 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.4192746894 Aug 27 12:59:33 PM UTC 24 Aug 27 01:02:18 PM UTC 24 2249558100 ps
T177 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.2273292670 Aug 27 12:58:23 PM UTC 24 Aug 27 01:02:22 PM UTC 24 38765000 ps
T595 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3995285896 Aug 27 01:01:08 PM UTC 24 Aug 27 01:02:46 PM UTC 24 1468326500 ps
T596 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.2119234440 Aug 27 12:59:52 PM UTC 24 Aug 27 01:02:55 PM UTC 24 1296929600 ps
T440 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.49816131 Aug 27 12:55:34 PM UTC 24 Aug 27 01:02:56 PM UTC 24 3606949500 ps
T597 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.4022864197 Aug 27 12:58:59 PM UTC 24 Aug 27 01:03:07 PM UTC 24 2384899500 ps
T598 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2860060597 Aug 27 01:00:21 PM UTC 24 Aug 27 01:03:22 PM UTC 24 5820725200 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1952374737 Aug 27 01:00:06 PM UTC 24 Aug 27 01:03:33 PM UTC 24 1386163000 ps
T599 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.914851694 Aug 27 01:03:08 PM UTC 24 Aug 27 01:03:34 PM UTC 24 59364100 ps
T600 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.620899451 Aug 27 12:58:10 PM UTC 24 Aug 27 01:03:37 PM UTC 24 74062200 ps
T183 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2553367685 Aug 27 12:19:14 PM UTC 24 Aug 27 01:03:48 PM UTC 24 429629135600 ps
T601 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3679951958 Aug 27 12:58:06 PM UTC 24 Aug 27 01:03:50 PM UTC 24 10011581700 ps
T184 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.1839073055 Aug 27 12:27:08 PM UTC 24 Aug 27 01:03:51 PM UTC 24 551946147500 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.1605811937 Aug 27 01:01:48 PM UTC 24 Aug 27 01:03:52 PM UTC 24 7601665500 ps
T602 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.4055104181 Aug 27 01:02:06 PM UTC 24 Aug 27 01:03:53 PM UTC 24 32508105700 ps
T603 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.1058248799 Aug 27 12:50:08 PM UTC 24 Aug 27 01:04:14 PM UTC 24 160157349300 ps
T435 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2491234933 Aug 27 01:03:22 PM UTC 24 Aug 27 01:04:15 PM UTC 24 29071500 ps
T604 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3647677874 Aug 27 01:03:35 PM UTC 24 Aug 27 01:04:15 PM UTC 24 72152800 ps
T411 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.2915078254 Aug 27 01:03:38 PM UTC 24 Aug 27 01:04:17 PM UTC 24 31609600 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2754502350 Aug 27 01:03:53 PM UTC 24 Aug 27 01:04:18 PM UTC 24 15344800 ps
T605 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.1041725572 Aug 27 01:03:51 PM UTC 24 Aug 27 01:04:21 PM UTC 24 26532100 ps
T606 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.1570675068 Aug 27 01:03:52 PM UTC 24 Aug 27 01:04:21 PM UTC 24 25844200 ps
T607 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.3906498784 Aug 27 01:02:02 PM UTC 24 Aug 27 01:04:29 PM UTC 24 245563600 ps
T608 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.1442995524 Aug 27 01:02:23 PM UTC 24 Aug 27 01:04:32 PM UTC 24 506577800 ps
T609 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.2099324895 Aug 27 01:04:15 PM UTC 24 Aug 27 01:04:42 PM UTC 24 170468400 ps
T610 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.3181331511 Aug 27 01:03:35 PM UTC 24 Aug 27 01:04:44 PM UTC 24 151054100 ps
T611 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3900957527 Aug 27 01:01:40 PM UTC 24 Aug 27 01:04:50 PM UTC 24 10014363400 ps
T612 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.848768691 Aug 27 01:02:20 PM UTC 24 Aug 27 01:04:50 PM UTC 24 2404800400 ps
T613 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.2537606515 Aug 27 12:54:40 PM UTC 24 Aug 27 01:04:53 PM UTC 24 395086800 ps
T614 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2664409962 Aug 27 01:02:03 PM UTC 24 Aug 27 01:05:09 PM UTC 24 10773778900 ps
T402 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.3332379377 Aug 27 01:03:49 PM UTC 24 Aug 27 01:05:22 PM UTC 24 13262284900 ps
T615 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3374181653 Aug 27 01:00:30 PM UTC 24 Aug 27 01:05:23 PM UTC 24 137156847100 ps
T616 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.1382494870 Aug 27 01:04:16 PM UTC 24 Aug 27 01:05:30 PM UTC 24 28190500 ps
T441 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1537745674 Aug 27 01:05:10 PM UTC 24 Aug 27 01:05:43 PM UTC 24 28865900 ps
T617 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.1729454266 Aug 27 01:04:53 PM UTC 24 Aug 27 01:05:43 PM UTC 24 503507800 ps
T618 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1408527943 Aug 27 01:02:57 PM UTC 24 Aug 27 01:05:46 PM UTC 24 32676645300 ps
T619 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1641514515 Aug 27 01:03:55 PM UTC 24 Aug 27 01:05:52 PM UTC 24 10034545000 ps
T620 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.918074555 Aug 27 01:04:43 PM UTC 24 Aug 27 01:06:03 PM UTC 24 5432891900 ps
T621 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.2706744830 Aug 27 01:05:22 PM UTC 24 Aug 27 01:06:08 PM UTC 24 27109000 ps
T622 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1999105976 Aug 27 01:04:19 PM UTC 24 Aug 27 01:06:08 PM UTC 24 1364645100 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.26779415 Aug 27 01:05:31 PM UTC 24 Aug 27 01:06:09 PM UTC 24 13299400 ps
T623 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.4071065936 Aug 27 01:05:45 PM UTC 24 Aug 27 01:06:09 PM UTC 24 16040800 ps
T624 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.1103581544 Aug 27 01:05:43 PM UTC 24 Aug 27 01:06:10 PM UTC 24 14988500 ps
T625 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.446221387 Aug 27 01:05:47 PM UTC 24 Aug 27 01:06:12 PM UTC 24 208612100 ps
T626 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.3535474625 Aug 27 01:01:47 PM UTC 24 Aug 27 01:06:13 PM UTC 24 296726700 ps
T627 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.859093357 Aug 27 01:04:30 PM UTC 24 Aug 27 01:06:20 PM UTC 24 4035345300 ps
T289 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.2279050315 Aug 27 12:14:40 PM UTC 24 Aug 27 01:06:22 PM UTC 24 10404066000 ps
T628 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3073431815 Aug 27 01:05:24 PM UTC 24 Aug 27 01:06:23 PM UTC 24 75445300 ps
T629 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.361197269 Aug 27 12:46:10 PM UTC 24 Aug 27 01:06:27 PM UTC 24 817088700 ps
T630 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.3296970968 Aug 27 01:06:04 PM UTC 24 Aug 27 01:06:28 PM UTC 24 78935300 ps
T392 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2423130908 Aug 27 01:05:31 PM UTC 24 Aug 27 01:06:42 PM UTC 24 1390840700 ps
T631 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.1083393886 Aug 27 01:01:43 PM UTC 24 Aug 27 01:06:48 PM UTC 24 37956500 ps
T186 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3113626571 Aug 27 01:04:22 PM UTC 24 Aug 27 01:07:03 PM UTC 24 151411400 ps
T632 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.397458972 Aug 27 01:06:50 PM UTC 24 Aug 27 01:07:27 PM UTC 24 828178400 ps
T633 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.1461221761 Aug 27 01:04:33 PM UTC 24 Aug 27 01:07:28 PM UTC 24 3295415100 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.1100751170 Aug 27 01:06:10 PM UTC 24 Aug 27 01:07:37 PM UTC 24 12725474200 ps
T634 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.2570598681 Aug 27 01:06:21 PM UTC 24 Aug 27 01:07:50 PM UTC 24 1666537800 ps
T635 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1856645573 Aug 27 01:07:04 PM UTC 24 Aug 27 01:07:54 PM UTC 24 74195400 ps
T636 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.2755134658 Aug 27 01:04:50 PM UTC 24 Aug 27 01:07:59 PM UTC 24 1905967500 ps
T637 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.4189614334 Aug 27 01:01:48 PM UTC 24 Aug 27 01:08:08 PM UTC 24 59320700 ps
T638 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1327665732 Aug 27 12:59:02 PM UTC 24 Aug 27 01:08:08 PM UTC 24 8847494300 ps
T639 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3249018431 Aug 27 01:07:37 PM UTC 24 Aug 27 01:08:11 PM UTC 24 39066900 ps
T640 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.3028849532 Aug 27 01:07:28 PM UTC 24 Aug 27 01:08:25 PM UTC 24 41979300 ps
T641 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.567805402 Aug 27 01:08:00 PM UTC 24 Aug 27 01:08:25 PM UTC 24 15438400 ps
T642 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2672999301 Aug 27 01:07:29 PM UTC 24 Aug 27 01:08:26 PM UTC 24 47192500 ps
T643 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1784266578 Aug 27 01:07:55 PM UTC 24 Aug 27 01:08:28 PM UTC 24 120895500 ps
T131 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.3141367066 Aug 27 12:41:31 PM UTC 24 Aug 27 01:08:30 PM UTC 24 6150273800 ps
T644 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1864010562 Aug 27 01:08:09 PM UTC 24 Aug 27 01:08:33 PM UTC 24 91652200 ps
T645 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.2610163144 Aug 27 01:06:24 PM UTC 24 Aug 27 01:08:41 PM UTC 24 1064536700 ps
T646 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.4281460275 Aug 27 01:05:53 PM UTC 24 Aug 27 01:08:41 PM UTC 24 10019396200 ps
T647 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.2042012147 Aug 27 01:08:12 PM UTC 24 Aug 27 01:08:43 PM UTC 24 66671800 ps
T648 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2456851989 Aug 27 12:54:44 PM UTC 24 Aug 27 01:08:47 PM UTC 24 40123878100 ps
T649 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.1069753031 Aug 27 01:06:08 PM UTC 24 Aug 27 01:08:48 PM UTC 24 36911600 ps
T650 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.74329777 Aug 27 01:06:42 PM UTC 24 Aug 27 01:09:00 PM UTC 24 8831015500 ps
T78 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1740318525 Aug 27 01:06:13 PM UTC 24 Aug 27 01:09:21 PM UTC 24 75194100 ps
T651 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.2024367082 Aug 27 01:07:50 PM UTC 24 Aug 27 01:09:22 PM UTC 24 374576500 ps
T152 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.4117602510 Aug 27 01:04:26 PM UTC 24 Aug 27 01:09:24 PM UTC 24 10042357200 ps
T652 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.1676084232 Aug 27 01:08:28 PM UTC 24 Aug 27 01:09:25 PM UTC 24 3227418100 ps
T36 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3230507788 Aug 27 01:06:28 PM UTC 24 Aug 27 01:09:30 PM UTC 24 3023264000 ps
T653 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1667781889 Aug 27 12:50:08 PM UTC 24 Aug 27 01:09:33 PM UTC 24 108368600 ps
T654 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.3345699498 Aug 27 01:06:23 PM UTC 24 Aug 27 01:09:46 PM UTC 24 9196788900 ps
T655 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.1860709974 Aug 27 01:09:23 PM UTC 24 Aug 27 01:09:46 PM UTC 24 232131900 ps
T656 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.1335725293 Aug 27 01:02:47 PM UTC 24 Aug 27 01:09:52 PM UTC 24 5947830300 ps
T657 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.4185066233 Aug 27 01:09:47 PM UTC 24 Aug 27 01:10:04 PM UTC 24 46189100 ps
T658 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3301182309 Aug 27 01:09:23 PM UTC 24 Aug 27 01:10:05 PM UTC 24 95741900 ps
T92 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2818642148 Aug 27 01:04:51 PM UTC 24 Aug 27 01:10:06 PM UTC 24 50052876400 ps
T659 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.853228758 Aug 27 01:09:36 PM UTC 24 Aug 27 01:10:10 PM UTC 24 22990500 ps
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