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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 95.73 93.98 98.31 92.52 98.25 96.99 98.21


Total test records in report: 1267
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
T363 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1283915539 Aug 27 06:31:45 PM UTC 24 Aug 27 06:42:55 PM UTC 24 795588200 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2762988024 Aug 27 06:32:42 PM UTC 24 Aug 27 06:42:59 PM UTC 24 2247636300 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2895569099 Aug 27 06:33:57 PM UTC 24 Aug 27 06:43:06 PM UTC 24 212779300 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1290080158 Aug 27 06:33:50 PM UTC 24 Aug 27 06:43:39 PM UTC 24 906116200 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.362285788 Aug 27 06:34:04 PM UTC 24 Aug 27 06:45:04 PM UTC 24 181545400 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1546499021 Aug 27 06:34:37 PM UTC 24 Aug 27 06:46:17 PM UTC 24 725880200 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.947660414 Aug 27 06:34:21 PM UTC 24 Aug 27 06:46:40 PM UTC 24 350161100 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2857515452 Aug 27 06:33:37 PM UTC 24 Aug 27 06:48:15 PM UTC 24 862524800 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1631327374 Aug 27 06:30:12 PM UTC 24 Aug 27 06:49:54 PM UTC 24 899555500 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2899778384 Aug 27 06:32:33 PM UTC 24 Aug 27 06:50:52 PM UTC 24 1192318300 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3177556861 Aug 27 06:33:07 PM UTC 24 Aug 27 06:51:16 PM UTC 24 346458300 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.630165548 Aug 27 06:32:21 PM UTC 24 Aug 27 06:51:45 PM UTC 24 349271300 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.717700630 Aug 27 06:33:29 PM UTC 24 Aug 27 06:52:00 PM UTC 24 755828500 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3301721084 Aug 27 06:34:14 PM UTC 24 Aug 27 06:52:37 PM UTC 24 412976400 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.583091025 Aug 27 06:32:01 PM UTC 24 Aug 27 06:54:03 PM UTC 24 1336747800 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1370560426 Aug 27 06:33:21 PM UTC 24 Aug 27 06:55:00 PM UTC 24 3233472300 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4274397628 Aug 27 06:34:28 PM UTC 24 Aug 27 06:55:22 PM UTC 24 7397984500 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.2835916419
Short name T20
Test name
Test status
Simulation time 3914431300 ps
CPU time 102.73 seconds
Started Aug 27 12:09:10 PM UTC 24
Finished Aug 27 12:10:55 PM UTC 24
Peak memory 271064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835916419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.2835916419
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2098792802
Short name T109
Test name
Test status
Simulation time 101735700 ps
CPU time 31.27 seconds
Started Aug 27 06:31:18 PM UTC 24
Finished Aug 27 06:31:50 PM UTC 24
Peak memory 283984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2098792802 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.2098792802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.498320029
Short name T14
Test name
Test status
Simulation time 5560238800 ps
CPU time 57.08 seconds
Started Aug 27 12:10:57 PM UTC 24
Finished Aug 27 12:11:56 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49
8320029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser
r_counter.498320029
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.883995255
Short name T12
Test name
Test status
Simulation time 3432650700 ps
CPU time 64.39 seconds
Started Aug 27 12:08:16 PM UTC 24
Finished Aug 27 12:09:22 PM UTC 24
Peak memory 273420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883995255 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.883995255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2161241973
Short name T32
Test name
Test status
Simulation time 11622246000 ps
CPU time 361.94 seconds
Started Aug 27 12:08:42 PM UTC 24
Finished Aug 27 12:14:49 PM UTC 24
Peak memory 283528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2161241973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_mp_regions.2161241973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.1305217637
Short name T118
Test name
Test status
Simulation time 40121443400 ps
CPU time 821.27 seconds
Started Aug 27 12:08:24 PM UTC 24
Finished Aug 27 12:22:14 PM UTC 24
Peak memory 275264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305217637
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.1305217637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.4108051401
Short name T100
Test name
Test status
Simulation time 8533172200 ps
CPU time 239.11 seconds
Started Aug 27 12:10:29 PM UTC 24
Finished Aug 27 12:14:32 PM UTC 24
Peak memory 306172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4108051401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.4108051401
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.3941506247
Short name T15
Test name
Test status
Simulation time 25660402200 ps
CPU time 6465.4 seconds
Started Aug 27 12:12:32 PM UTC 24
Finished Aug 27 02:01:23 PM UTC 24
Peak memory 316532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941506247 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.3941506247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.858868744
Short name T261
Test name
Test status
Simulation time 2623519300 ps
CPU time 90.25 seconds
Started Aug 27 06:30:32 PM UTC 24
Finished Aug 27 06:32:04 PM UTC 24
Peak memory 271440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858868744 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.858868744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.1853568570
Short name T10
Test name
Test status
Simulation time 43198500 ps
CPU time 22.34 seconds
Started Aug 27 12:13:10 PM UTC 24
Finished Aug 27 12:13:33 PM UTC 24
Peak memory 273844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1853568570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.1853568570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.2253546876
Short name T72
Test name
Test status
Simulation time 2844820000 ps
CPU time 474.46 seconds
Started Aug 27 12:08:17 PM UTC 24
Finished Aug 27 12:16:17 PM UTC 24
Peak memory 275276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2253546876 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2253546876
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.2035367400
Short name T114
Test name
Test status
Simulation time 141614700 ps
CPU time 171.2 seconds
Started Aug 27 12:19:14 PM UTC 24
Finished Aug 27 12:22:08 PM UTC 24
Peak memory 271276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2035367400 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.2035367400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.2843258543
Short name T24
Test name
Test status
Simulation time 184729100 ps
CPU time 39.86 seconds
Started Aug 27 12:12:19 PM UTC 24
Finished Aug 27 12:13:01 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2843258543 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw_evict_all_en.2843258543
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3140930955
Short name T115
Test name
Test status
Simulation time 10031918800 ps
CPU time 101.62 seconds
Started Aug 27 12:13:22 PM UTC 24
Finished Aug 27 12:15:06 PM UTC 24
Peak memory 302120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3140930955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3140930955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2336118143
Short name T331
Test name
Test status
Simulation time 27819700 ps
CPU time 18.68 seconds
Started Aug 27 06:31:49 PM UTC 24
Finished Aug 27 06:32:09 PM UTC 24
Peak memory 271360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336118143 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.2336118143
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.3695575007
Short name T124
Test name
Test status
Simulation time 2428315300 ps
CPU time 183.95 seconds
Started Aug 27 12:11:33 PM UTC 24
Finished Aug 27 12:14:40 PM UTC 24
Peak memory 291832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3695575007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 0.flash_ctrl_derr_detect.3695575007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.3667036527
Short name T1043
Test name
Test status
Simulation time 180487000 ps
CPU time 127.93 seconds
Started Aug 27 01:34:10 PM UTC 24
Finished Aug 27 01:36:20 PM UTC 24
Peak memory 271288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667036527 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.3667036527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.293681727
Short name T762
Test name
Test status
Simulation time 88139000 ps
CPU time 173.2 seconds
Started Aug 27 01:19:13 PM UTC 24
Finished Aug 27 01:22:09 PM UTC 24
Peak memory 271264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=293681727 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.293681727
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.3067520794
Short name T3
Test name
Test status
Simulation time 521166300 ps
CPU time 24.85 seconds
Started Aug 27 12:08:43 PM UTC 24
Finished Aug 27 12:09:09 PM UTC 24
Peak memory 273420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30
67520794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc
h_code.3067520794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.947660414
Short name T365
Test name
Test status
Simulation time 350161100 ps
CPU time 729.85 seconds
Started Aug 27 06:34:21 PM UTC 24
Finished Aug 27 06:46:40 PM UTC 24
Peak memory 273504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947660414 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.947660414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.830750424
Short name T37
Test name
Test status
Simulation time 2558089500 ps
CPU time 156.18 seconds
Started Aug 27 12:16:28 PM UTC 24
Finished Aug 27 12:19:07 PM UTC 24
Peak memory 304312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830750424 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.830750424
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1661063744
Short name T107
Test name
Test status
Simulation time 46085500 ps
CPU time 16.74 seconds
Started Aug 27 12:13:17 PM UTC 24
Finished Aug 27 12:13:35 PM UTC 24
Peak memory 271304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1661063744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_lcmgr_intg.1661063744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1356852221
Short name T47
Test name
Test status
Simulation time 1713198000 ps
CPU time 94.09 seconds
Started Aug 27 12:17:37 PM UTC 24
Finished Aug 27 12:19:14 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356852221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1356852221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.2393544247
Short name T8
Test name
Test status
Simulation time 43196100 ps
CPU time 17.49 seconds
Started Aug 27 12:12:57 PM UTC 24
Finished Aug 27 12:13:16 PM UTC 24
Peak memory 275660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2393544247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_wr_intg.2393544247
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.3427033432
Short name T82
Test name
Test status
Simulation time 94653107400 ps
CPU time 1062.61 seconds
Started Aug 27 12:13:17 PM UTC 24
Finished Aug 27 12:31:11 PM UTC 24
Peak memory 316232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3427033432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.
flash_ctrl_rma_err.3427033432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.2697396722
Short name T98
Test name
Test status
Simulation time 98303400 ps
CPU time 24.09 seconds
Started Aug 27 12:26:09 PM UTC 24
Finished Aug 27 12:26:35 PM UTC 24
Peak memory 269304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697396722 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.2697396722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2553367685
Short name T183
Test name
Test status
Simulation time 429629135600 ps
CPU time 2646.66 seconds
Started Aug 27 12:19:14 PM UTC 24
Finished Aug 27 01:03:48 PM UTC 24
Peak memory 278260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553367685 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.2553367685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.878847215
Short name T180
Test name
Test status
Simulation time 360772500 ps
CPU time 186.16 seconds
Started Aug 27 01:14:35 PM UTC 24
Finished Aug 27 01:17:44 PM UTC 24
Peak memory 275168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=878847215 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.878847215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2245337571
Short name T229
Test name
Test status
Simulation time 112681600 ps
CPU time 23.55 seconds
Started Aug 27 06:31:41 PM UTC 24
Finished Aug 27 06:32:06 PM UTC 24
Peak memory 273668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245337571 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2245337571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.1659458421
Short name T48
Test name
Test status
Simulation time 1833088900 ps
CPU time 118.23 seconds
Started Aug 27 12:14:43 PM UTC 24
Finished Aug 27 12:16:44 PM UTC 24
Peak memory 271256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659458421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1659458421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.3652129593
Short name T167
Test name
Test status
Simulation time 2198751500 ps
CPU time 99.45 seconds
Started Aug 27 12:36:32 PM UTC 24
Finished Aug 27 12:38:14 PM UTC 24
Peak memory 271068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652129593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3652129593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.899542804
Short name T201
Test name
Test status
Simulation time 1560072700 ps
CPU time 183.54 seconds
Started Aug 27 12:15:56 PM UTC 24
Finished Aug 27 12:19:02 PM UTC 24
Peak memory 291860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=899542804 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_rw_derr.899542804
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.1605811937
Short name T317
Test name
Test status
Simulation time 7601665500 ps
CPU time 121.89 seconds
Started Aug 27 01:01:48 PM UTC 24
Finished Aug 27 01:03:52 PM UTC 24
Peak memory 273356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1605811937 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.1605811937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2124914993
Short name T45
Test name
Test status
Simulation time 2992174600 ps
CPU time 177.9 seconds
Started Aug 27 12:11:41 PM UTC 24
Finished Aug 27 12:14:42 PM UTC 24
Peak memory 291820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2124914993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_oversize_error.2124914993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3577901618
Short name T273
Test name
Test status
Simulation time 67001300 ps
CPU time 24.52 seconds
Started Aug 27 06:34:19 PM UTC 24
Finished Aug 27 06:34:45 PM UTC 24
Peak memory 273076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577901618 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.3577901618
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1293809802
Short name T247
Test name
Test status
Simulation time 142943100 ps
CPU time 29.23 seconds
Started Aug 27 06:30:23 PM UTC 24
Finished Aug 27 06:30:53 PM UTC 24
Peak memory 273616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293809802 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.1293809802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.2372901995
Short name T90
Test name
Test status
Simulation time 412459500 ps
CPU time 2403.61 seconds
Started Aug 27 12:14:33 PM UTC 24
Finished Aug 27 12:55:01 PM UTC 24
Peak memory 278136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=23
72901995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_error_prog_type.2372901995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.1468861974
Short name T413
Test name
Test status
Simulation time 134660400 ps
CPU time 52.78 seconds
Started Aug 27 12:24:16 PM UTC 24
Finished Aug 27 12:25:10 PM UTC 24
Peak memory 289776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468861974 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.1468861974
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4217656737
Short name T16
Test name
Test status
Simulation time 1615018100 ps
CPU time 65.05 seconds
Started Aug 27 12:08:57 PM UTC 24
Finished Aug 27 12:10:03 PM UTC 24
Peak memory 271116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217656737 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.4217656737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.2636140440
Short name T38
Test name
Test status
Simulation time 45257997000 ps
CPU time 454.16 seconds
Started Aug 27 12:16:29 PM UTC 24
Finished Aug 27 12:24:09 PM UTC 24
Peak memory 302228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2636140440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_intr_rd_slow_flash.2636140440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.183323743
Short name T34
Test name
Test status
Simulation time 75042701900 ps
CPU time 206.43 seconds
Started Aug 27 12:14:22 PM UTC 24
Finished Aug 27 12:17:51 PM UTC 24
Peak memory 275340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=183323743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 1.flash_ctrl_mp_regions.183323743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.1764342783
Short name T1177
Test name
Test status
Simulation time 16871900 ps
CPU time 17.23 seconds
Started Aug 27 06:33:34 PM UTC 24
Finished Aug 27 06:33:52 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764342783 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.1764342783
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2857515452
Short name T356
Test name
Test status
Simulation time 862524800 ps
CPU time 868.84 seconds
Started Aug 27 06:33:37 PM UTC 24
Finished Aug 27 06:48:15 PM UTC 24
Peak memory 273620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857515452 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.2857515452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.1231540094
Short name T53
Test name
Test status
Simulation time 666346500 ps
CPU time 29.16 seconds
Started Aug 27 12:17:53 PM UTC 24
Finished Aug 27 12:18:24 PM UTC 24
Peak memory 275576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1231540094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.1231540094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.3652288554
Short name T209
Test name
Test status
Simulation time 2650904800 ps
CPU time 153.78 seconds
Started Aug 27 12:22:36 PM UTC 24
Finished Aug 27 12:25:13 PM UTC 24
Peak memory 291832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652288554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3652288554
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.1948056315
Short name T172
Test name
Test status
Simulation time 59762300 ps
CPU time 17.47 seconds
Started Aug 27 12:18:20 PM UTC 24
Finished Aug 27 12:18:39 PM UTC 24
Peak memory 271344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1948056315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.flash_ctrl_hw_read_seed_err.1948056315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.3301721084
Short name T360
Test name
Test status
Simulation time 412976400 ps
CPU time 1090.74 seconds
Started Aug 27 06:34:14 PM UTC 24
Finished Aug 27 06:52:37 PM UTC 24
Peak memory 271700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301721084 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.3301721084
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.64377383
Short name T423
Test name
Test status
Simulation time 140544900 ps
CPU time 53.24 seconds
Started Aug 27 01:28:50 PM UTC 24
Finished Aug 27 01:29:45 PM UTC 24
Peak memory 287724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64377383 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.64377383
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.913512179
Short name T336
Test name
Test status
Simulation time 1171523900 ps
CPU time 175.4 seconds
Started Aug 27 12:43:10 PM UTC 24
Finished Aug 27 12:46:09 PM UTC 24
Peak memory 304152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913512179 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.913512179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.3157101139
Short name T130
Test name
Test status
Simulation time 374086254300 ps
CPU time 2941.87 seconds
Started Aug 27 12:08:34 PM UTC 24
Finished Aug 27 12:58:07 PM UTC 24
Peak memory 278256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157101139 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.3157101139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.3562518519
Short name T33
Test name
Test status
Simulation time 1952065400 ps
CPU time 244.76 seconds
Started Aug 27 12:11:57 PM UTC 24
Finished Aug 27 12:16:05 PM UTC 24
Peak memory 302104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562518519 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.3562518519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1936563280
Short name T271
Test name
Test status
Simulation time 77351300 ps
CPU time 20.65 seconds
Started Aug 27 06:34:34 PM UTC 24
Finished Aug 27 06:34:56 PM UTC 24
Peak memory 273532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936563280 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.1936563280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.317583219
Short name T418
Test name
Test status
Simulation time 130778000 ps
CPU time 41.15 seconds
Started Aug 27 12:53:53 PM UTC 24
Finished Aug 27 12:54:35 PM UTC 24
Peak memory 287724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317583219 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.317583219
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.1624863063
Short name T9
Test name
Test status
Simulation time 66379800 ps
CPU time 20.39 seconds
Started Aug 27 12:13:00 PM UTC 24
Finished Aug 27 12:13:22 PM UTC 24
Peak memory 273380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1624863063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.1624863063
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.3725352391
Short name T61
Test name
Test status
Simulation time 45850000 ps
CPU time 18.31 seconds
Started Aug 27 12:33:16 PM UTC 24
Finished Aug 27 12:33:35 PM UTC 24
Peak memory 293264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725352391 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.3725352391
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.4104232533
Short name T304
Test name
Test status
Simulation time 1207441500 ps
CPU time 56.78 seconds
Started Aug 27 12:32:55 PM UTC 24
Finished Aug 27 12:33:54 PM UTC 24
Peak memory 273360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4104232
533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f
s_sup.4104232533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.337543873
Short name T886
Test name
Test status
Simulation time 27153100 ps
CPU time 26.83 seconds
Started Aug 27 01:29:26 PM UTC 24
Finished Aug 27 01:29:54 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=337543873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c
trl_disable.337543873
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.360638522
Short name T246
Test name
Test status
Simulation time 62273800 ps
CPU time 24.95 seconds
Started Aug 27 06:32:10 PM UTC 24
Finished Aug 27 06:32:37 PM UTC 24
Peak memory 273480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360638522 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.360638522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.2813612286
Short name T60
Test name
Test status
Simulation time 815705000 ps
CPU time 31.7 seconds
Started Aug 27 12:13:05 PM UTC 24
Finished Aug 27 12:13:39 PM UTC 24
Peak memory 275628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2813612286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2813612286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.132142917
Short name T241
Test name
Test status
Simulation time 24409900 ps
CPU time 34.16 seconds
Started Aug 27 06:31:57 PM UTC 24
Finished Aug 27 06:32:32 PM UTC 24
Peak memory 273804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=132142917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.132142917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.2899778384
Short name T359
Test name
Test status
Simulation time 1192318300 ps
CPU time 1087.87 seconds
Started Aug 27 06:32:33 PM UTC 24
Finished Aug 27 06:50:52 PM UTC 24
Peak memory 273556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2899778384 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.2899778384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2669476180
Short name T211
Test name
Test status
Simulation time 88358000 ps
CPU time 52.13 seconds
Started Aug 27 12:16:45 PM UTC 24
Finished Aug 27 12:17:39 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669476180 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.2669476180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.3332379377
Short name T402
Test name
Test status
Simulation time 13262284900 ps
CPU time 90.84 seconds
Started Aug 27 01:03:49 PM UTC 24
Finished Aug 27 01:05:22 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332379377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.3332379377
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.125017343
Short name T153
Test name
Test status
Simulation time 2100549700 ps
CPU time 98.8 seconds
Started Aug 27 01:08:43 PM UTC 24
Finished Aug 27 01:10:24 PM UTC 24
Peak memory 271116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=125017343 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.125017343
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.3182452950
Short name T4
Test name
Test status
Simulation time 16168200 ps
CPU time 23.61 seconds
Started Aug 27 12:12:51 PM UTC 24
Finished Aug 27 12:13:15 PM UTC 24
Peak memory 295116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182452950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.3182452950
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.3449449483
Short name T116
Test name
Test status
Simulation time 70134082700 ps
CPU time 728.3 seconds
Started Aug 27 12:14:07 PM UTC 24
Finished Aug 27 12:26:24 PM UTC 24
Peak memory 274944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449449483
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.3449449483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.1620398481
Short name T121
Test name
Test status
Simulation time 696212700 ps
CPU time 34.71 seconds
Started Aug 27 12:25:18 PM UTC 24
Finished Aug 27 12:25:54 PM UTC 24
Peak memory 275648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1620398481 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.1620398481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.1544066034
Short name T291
Test name
Test status
Simulation time 5734393200 ps
CPU time 1238.62 seconds
Started Aug 27 12:08:55 PM UTC 24
Finished Aug 27 12:29:46 PM UTC 24
Peak memory 286260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544066034 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.1544066034
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3437555487
Short name T120
Test name
Test status
Simulation time 4423667100 ps
CPU time 6352.08 seconds
Started Aug 27 12:40:36 PM UTC 24
Finished Aug 27 02:27:31 PM UTC 24
Peak memory 316532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437555487 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.3437555487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2491234933
Short name T435
Test name
Test status
Simulation time 29071500 ps
CPU time 50.79 seconds
Started Aug 27 01:03:22 PM UTC 24
Finished Aug 27 01:04:15 PM UTC 24
Peak memory 281844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491234933 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.2491234933
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.567805402
Short name T641
Test name
Test status
Simulation time 15438400 ps
CPU time 24.41 seconds
Started Aug 27 01:08:00 PM UTC 24
Finished Aug 27 01:08:25 PM UTC 24
Peak memory 271360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=567805402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flas
h_ctrl_lcmgr_intg.567805402
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.750554529
Short name T50
Test name
Test status
Simulation time 442373200 ps
CPU time 136.66 seconds
Started Aug 27 12:10:04 PM UTC 24
Finished Aug 27 12:12:23 PM UTC 24
Peak memory 292052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=750554529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.750554529
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3068920140
Short name T87
Test name
Test status
Simulation time 10037874900 ps
CPU time 135.02 seconds
Started Aug 27 12:18:25 PM UTC 24
Finished Aug 27 12:20:43 PM UTC 24
Peak memory 281560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3068920140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3068920140
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.446221387
Short name T625
Test name
Test status
Simulation time 208612100 ps
CPU time 24.01 seconds
Started Aug 27 01:05:47 PM UTC 24
Finished Aug 27 01:06:12 PM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=446221387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
1.flash_ctrl_hw_read_seed_err.446221387
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2327336001
Short name T284
Test name
Test status
Simulation time 10032191100 ps
CPU time 54.88 seconds
Started Aug 27 01:12:22 PM UTC 24
Finished Aug 27 01:13:19 PM UTC 24
Peak memory 277864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2327336001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.2327336001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.4034800182
Short name T1217
Test name
Test status
Simulation time 15743600 ps
CPU time 19.26 seconds
Started Aug 27 06:34:22 PM UTC 24
Finished Aug 27 06:34:43 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034800182 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.4034800182
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.909069065
Short name T398
Test name
Test status
Simulation time 16161967200 ps
CPU time 80.64 seconds
Started Aug 27 01:11:58 PM UTC 24
Finished Aug 27 01:13:21 PM UTC 24
Peak memory 271112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=909069065 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.909069065
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.3119937914
Short name T396
Test name
Test status
Simulation time 2365460800 ps
CPU time 94.07 seconds
Started Aug 27 01:23:57 PM UTC 24
Finished Aug 27 01:25:33 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119937914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.3119937914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.1967613537
Short name T990
Test name
Test status
Simulation time 1312649600 ps
CPU time 74.69 seconds
Started Aug 27 01:33:23 PM UTC 24
Finished Aug 27 01:34:40 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967613537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.1967613537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1353133834
Short name T51
Test name
Test status
Simulation time 1061968300 ps
CPU time 45.9 seconds
Started Aug 27 12:14:27 PM UTC 24
Finished Aug 27 12:15:14 PM UTC 24
Peak memory 273492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13
53133834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetc
h_code.1353133834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_host_grant_err.81320085
Short name T11
Test name
Test status
Simulation time 18738400 ps
CPU time 29.71 seconds
Started Aug 27 12:25:21 PM UTC 24
Finished Aug 27 12:25:52 PM UTC 24
Peak memory 273752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=81320085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_phy_host_grant_err.81320085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.4217332230
Short name T219
Test name
Test status
Simulation time 21502000 ps
CPU time 29.7 seconds
Started Aug 27 12:13:15 PM UTC 24
Finished Aug 27 12:13:46 PM UTC 24
Peak memory 273292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4217332230 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.4217332230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3211519861
Short name T267
Test name
Test status
Simulation time 30185500 ps
CPU time 21.27 seconds
Started Aug 27 06:32:41 PM UTC 24
Finished Aug 27 06:33:04 PM UTC 24
Peak memory 273532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211519861 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.3211519861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.152872342
Short name T105
Test name
Test status
Simulation time 16065000 ps
CPU time 43.05 seconds
Started Aug 27 01:11:47 PM UTC 24
Finished Aug 27 01:12:32 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=152872342 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_disable.152872342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.2881027991
Short name T881
Test name
Test status
Simulation time 26211732500 ps
CPU time 231.08 seconds
Started Aug 27 01:25:30 PM UTC 24
Finished Aug 27 01:29:25 PM UTC 24
Peak memory 302072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881027991 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.2881027991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.4111611745
Short name T160
Test name
Test status
Simulation time 3399331500 ps
CPU time 79.22 seconds
Started Aug 27 12:36:15 PM UTC 24
Finished Aug 27 12:37:36 PM UTC 24
Peak memory 271108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111611745 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.4111611745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.2263550447
Short name T213
Test name
Test status
Simulation time 117705900 ps
CPU time 63.25 seconds
Started Aug 27 12:25:05 PM UTC 24
Finished Aug 27 12:26:10 PM UTC 24
Peak memory 285716 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226355044
7 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.2263550447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.4071065936
Short name T623
Test name
Test status
Simulation time 16040800 ps
CPU time 23.15 seconds
Started Aug 27 01:05:45 PM UTC 24
Finished Aug 27 01:06:09 PM UTC 24
Peak memory 271656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4071065936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_lcmgr_intg.4071065936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.1631327374
Short name T354
Test name
Test status
Simulation time 899555500 ps
CPU time 1169.06 seconds
Started Aug 27 06:30:12 PM UTC 24
Finished Aug 27 06:49:54 PM UTC 24
Peak memory 273556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1631327374 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.1631327374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.1290080158
Short name T352
Test name
Test status
Simulation time 906116200 ps
CPU time 581.68 seconds
Started Aug 27 06:33:50 PM UTC 24
Finished Aug 27 06:43:39 PM UTC 24
Peak memory 273748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290080158 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.1290080158
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.362285788
Short name T368
Test name
Test status
Simulation time 181545400 ps
CPU time 651.93 seconds
Started Aug 27 06:34:04 PM UTC 24
Finished Aug 27 06:45:04 PM UTC 24
Peak memory 273356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362285788 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.362285788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.222144270
Short name T268
Test name
Test status
Simulation time 12091200 ps
CPU time 42.7 seconds
Started Aug 27 12:17:08 PM UTC 24
Finished Aug 27 12:17:52 PM UTC 24
Peak memory 285684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=222144270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_disable.222144270
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.2423130908
Short name T392
Test name
Test status
Simulation time 1390840700 ps
CPU time 68.64 seconds
Started Aug 27 01:05:31 PM UTC 24
Finished Aug 27 01:06:42 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423130908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.2423130908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3192117646
Short name T81
Test name
Test status
Simulation time 37567200 ps
CPU time 36.56 seconds
Started Aug 27 12:24:30 PM UTC 24
Finished Aug 27 12:25:08 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3192117646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_disable.3192117646
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.3046514905
Short name T406
Test name
Test status
Simulation time 443044400 ps
CPU time 65.92 seconds
Started Aug 27 01:25:52 PM UTC 24
Finished Aug 27 01:27:00 PM UTC 24
Peak memory 275216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046514905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.3046514905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.1411275930
Short name T426
Test name
Test status
Simulation time 25851900 ps
CPU time 47.63 seconds
Started Aug 27 01:26:14 PM UTC 24
Finished Aug 27 01:27:03 PM UTC 24
Peak memory 281608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1411275930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c
trl_rw_evict_all_en.1411275930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.684113936
Short name T371
Test name
Test status
Simulation time 27799500 ps
CPU time 24.9 seconds
Started Aug 27 01:29:56 PM UTC 24
Finished Aug 27 01:30:22 PM UTC 24
Peak memory 285684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=684113936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c
trl_disable.684113936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.3352063997
Short name T373
Test name
Test status
Simulation time 32304900 ps
CPU time 37.63 seconds
Started Aug 27 01:32:24 PM UTC 24
Finished Aug 27 01:33:03 PM UTC 24
Peak memory 275516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3352063997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_
ctrl_disable.3352063997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.2382169512
Short name T26
Test name
Test status
Simulation time 2123321800 ps
CPU time 70.28 seconds
Started Aug 27 12:12:00 PM UTC 24
Finished Aug 27 12:13:12 PM UTC 24
Peak memory 271408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382169512 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.2382169512
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1305387153
Short name T243
Test name
Test status
Simulation time 125944100 ps
CPU time 34.97 seconds
Started Aug 27 06:32:20 PM UTC 24
Finished Aug 27 06:32:56 PM UTC 24
Peak memory 273532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1305387153 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.1305387153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.2285122250
Short name T13
Test name
Test status
Simulation time 122577500 ps
CPU time 105.92 seconds
Started Aug 27 12:08:10 PM UTC 24
Finished Aug 27 12:09:58 PM UTC 24
Peak memory 273296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285122250 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.2285122250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3542070627
Short name T64
Test name
Test status
Simulation time 210370800 ps
CPU time 22.03 seconds
Started Aug 27 12:13:13 PM UTC 24
Finished Aug 27 12:13:36 PM UTC 24
Peak memory 271712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542070627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3542070627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.824805491
Short name T216
Test name
Test status
Simulation time 973271400 ps
CPU time 134.69 seconds
Started Aug 27 12:14:50 PM UTC 24
Finished Aug 27 12:17:07 PM UTC 24
Peak memory 302092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=824805491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.824805491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.2818642148
Short name T92
Test name
Test status
Simulation time 50052876400 ps
CPU time 311.02 seconds
Started Aug 27 01:04:51 PM UTC 24
Finished Aug 27 01:10:06 PM UTC 24
Peak memory 304040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2818642148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_intr_rd_slow_flash.2818642148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.4107340040
Short name T288
Test name
Test status
Simulation time 21444940700 ps
CPU time 2649.29 seconds
Started Aug 27 12:08:57 PM UTC 24
Finished Aug 27 12:53:31 PM UTC 24
Peak memory 278048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107340040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.4107340040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.3726166405
Short name T218
Test name
Test status
Simulation time 2493279100 ps
CPU time 240.91 seconds
Started Aug 27 12:16:06 PM UTC 24
Finished Aug 27 12:20:11 PM UTC 24
Peak memory 287736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3726166405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.flash_ctrl_derr_detect.3726166405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.965718218
Short name T154
Test name
Test status
Simulation time 325734948300 ps
CPU time 3532.35 seconds
Started Aug 27 12:14:32 PM UTC 24
Finished Aug 27 01:14:02 PM UTC 24
Peak memory 278016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965718218 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.965718218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.1887521468
Short name T99
Test name
Test status
Simulation time 163713000 ps
CPU time 30.96 seconds
Started Aug 27 12:25:09 PM UTC 24
Finished Aug 27 12:25:41 PM UTC 24
Peak memory 271380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1887521468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_wr_intg.1887521468
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.1839073055
Short name T184
Test name
Test status
Simulation time 551946147500 ps
CPU time 2180.35 seconds
Started Aug 27 12:27:08 PM UTC 24
Finished Aug 27 01:03:51 PM UTC 24
Peak memory 278188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839073055 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.1839073055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.3059933161
Short name T122
Test name
Test status
Simulation time 736718200 ps
CPU time 21.78 seconds
Started Aug 27 12:33:00 PM UTC 24
Finished Aug 27 12:33:23 PM UTC 24
Peak memory 273540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3059933161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.3059933161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3829876164
Short name T220
Test name
Test status
Simulation time 358562982300 ps
CPU time 2540.02 seconds
Started Aug 27 12:34:40 PM UTC 24
Finished Aug 27 01:17:26 PM UTC 24
Peak memory 278260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829876164 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.3829876164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.1166592587
Short name T123
Test name
Test status
Simulation time 902036900 ps
CPU time 29.59 seconds
Started Aug 27 12:41:05 PM UTC 24
Finished Aug 27 12:41:36 PM UTC 24
Peak memory 275816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1166592587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.1166592587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3622390794
Short name T212
Test name
Test status
Simulation time 6347049700 ps
CPU time 215.62 seconds
Started Aug 27 12:52:01 PM UTC 24
Finished Aug 27 12:55:40 PM UTC 24
Peak memory 297996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3622390794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 7.flash_ctrl_rw_derr.3622390794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1194589661
Short name T259
Test name
Test status
Simulation time 2645046400 ps
CPU time 55.89 seconds
Started Aug 27 06:30:41 PM UTC 24
Finished Aug 27 06:31:39 PM UTC 24
Peak memory 271440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194589661 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.1194589661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3806399314
Short name T260
Test name
Test status
Simulation time 168778700 ps
CPU time 76.83 seconds
Started Aug 27 06:30:26 PM UTC 24
Finished Aug 27 06:31:45 PM UTC 24
Peak memory 271440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806399314 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.3806399314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3860288909
Short name T71
Test name
Test status
Simulation time 190128200 ps
CPU time 31.58 seconds
Started Aug 27 06:30:45 PM UTC 24
Finished Aug 27 06:31:18 PM UTC 24
Peak memory 283856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3860288909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.3860288909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2278673260
Short name T69
Test name
Test status
Simulation time 118546100 ps
CPU time 33.57 seconds
Started Aug 27 06:30:30 PM UTC 24
Finished Aug 27 06:31:05 PM UTC 24
Peak memory 273488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278673260 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.2278673260
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.1618511354
Short name T257
Test name
Test status
Simulation time 20098800 ps
CPU time 29.72 seconds
Started Aug 27 06:30:17 PM UTC 24
Finished Aug 27 06:30:48 PM UTC 24
Peak memory 271364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618511354 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.1618511354
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3651190339
Short name T1131
Test name
Test status
Simulation time 44674500 ps
CPU time 20.65 seconds
Started Aug 27 06:30:19 PM UTC 24
Finished Aug 27 06:30:41 PM UTC 24
Peak memory 271496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651190339 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.3651190339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2999258868
Short name T70
Test name
Test status
Simulation time 260611900 ps
CPU time 31.5 seconds
Started Aug 27 06:30:41 PM UTC 24
Finished Aug 27 06:31:14 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2999258868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
same_csr_outstanding.2999258868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3567943302
Short name T1132
Test name
Test status
Simulation time 18667000 ps
CPU time 28.32 seconds
Started Aug 27 06:30:15 PM UTC 24
Finished Aug 27 06:30:45 PM UTC 24
Peak memory 261148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356
7943302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sha
dow_reg_errors.3567943302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2359466832
Short name T1130
Test name
Test status
Simulation time 94720100 ps
CPU time 22.14 seconds
Started Aug 27 06:30:16 PM UTC 24
Finished Aug 27 06:30:40 PM UTC 24
Peak memory 261328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2359466832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2359466832
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1972645175
Short name T108
Test name
Test status
Simulation time 39382200 ps
CPU time 32.86 seconds
Started Aug 27 06:30:12 PM UTC 24
Finished Aug 27 06:30:46 PM UTC 24
Peak memory 273540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972645175 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.1972645175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1969183631
Short name T370
Test name
Test status
Simulation time 2605319300 ps
CPU time 59.97 seconds
Started Aug 27 06:31:16 PM UTC 24
Finished Aug 27 06:32:18 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1969183631 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.1969183631
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2095583823
Short name T296
Test name
Test status
Simulation time 13093548700 ps
CPU time 107.63 seconds
Started Aug 27 06:31:16 PM UTC 24
Finished Aug 27 06:33:06 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095583823 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.2095583823
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2448242303
Short name T1142
Test name
Test status
Simulation time 221418400 ps
CPU time 65.66 seconds
Started Aug 27 06:31:10 PM UTC 24
Finished Aug 27 06:32:18 PM UTC 24
Peak memory 273492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448242303 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.2448242303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1193451185
Short name T112
Test name
Test status
Simulation time 471956400 ps
CPU time 19.64 seconds
Started Aug 27 06:31:15 PM UTC 24
Finished Aug 27 06:31:36 PM UTC 24
Peak memory 271440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1193451185 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.1193451185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3955958535
Short name T258
Test name
Test status
Simulation time 17457100 ps
CPU time 29.12 seconds
Started Aug 27 06:30:59 PM UTC 24
Finished Aug 27 06:31:29 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955958535 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3955958535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3406557272
Short name T248
Test name
Test status
Simulation time 63960300 ps
CPU time 18.16 seconds
Started Aug 27 06:31:07 PM UTC 24
Finished Aug 27 06:31:26 PM UTC 24
Peak memory 273480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3406557272 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.3406557272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2641385854
Short name T1135
Test name
Test status
Simulation time 13985800 ps
CPU time 21.11 seconds
Started Aug 27 06:31:07 PM UTC 24
Finished Aug 27 06:31:29 PM UTC 24
Peak memory 271496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641385854 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.2641385854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2102854409
Short name T251
Test name
Test status
Simulation time 194906200 ps
CPU time 26.49 seconds
Started Aug 27 06:31:16 PM UTC 24
Finished Aug 27 06:31:44 PM UTC 24
Peak memory 273492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2102854409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
same_csr_outstanding.2102854409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.459323535
Short name T1133
Test name
Test status
Simulation time 12598200 ps
CPU time 28.25 seconds
Started Aug 27 06:30:51 PM UTC 24
Finished Aug 27 06:31:21 PM UTC 24
Peak memory 261144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459
323535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shad
ow_reg_errors.459323535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1529129485
Short name T1134
Test name
Test status
Simulation time 21427900 ps
CPU time 27.4 seconds
Started Aug 27 06:30:54 PM UTC 24
Finished Aug 27 06:31:23 PM UTC 24
Peak memory 261128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1529129485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1529129485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3509375
Short name T111
Test name
Test status
Simulation time 106471700 ps
CPU time 34.42 seconds
Started Aug 27 06:30:47 PM UTC 24
Finished Aug 27 06:31:23 PM UTC 24
Peak memory 273656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509375 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.3509375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.4221565724
Short name T256
Test name
Test status
Simulation time 877442900 ps
CPU time 641.58 seconds
Started Aug 27 06:30:50 PM UTC 24
Finished Aug 27 06:41:39 PM UTC 24
Peak memory 273548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221565724 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.4221565724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1345678637
Short name T1181
Test name
Test status
Simulation time 140159700 ps
CPU time 27.36 seconds
Started Aug 27 06:33:26 PM UTC 24
Finished Aug 27 06:33:55 PM UTC 24
Peak memory 283856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1345678637 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1345678637
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.343747470
Short name T300
Test name
Test status
Simulation time 113904400 ps
CPU time 22.7 seconds
Started Aug 27 06:33:24 PM UTC 24
Finished Aug 27 06:33:48 PM UTC 24
Peak memory 273480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343747470 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.343747470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3249859249
Short name T1173
Test name
Test status
Simulation time 16824500 ps
CPU time 18.69 seconds
Started Aug 27 06:33:24 PM UTC 24
Finished Aug 27 06:33:44 PM UTC 24
Peak memory 271096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249859249 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.3249859249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3316690298
Short name T1175
Test name
Test status
Simulation time 129588100 ps
CPU time 20.98 seconds
Started Aug 27 06:33:25 PM UTC 24
Finished Aug 27 06:33:47 PM UTC 24
Peak memory 271440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3316690298 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_same_csr_outstanding.3316690298
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3562200435
Short name T1172
Test name
Test status
Simulation time 13378400 ps
CPU time 20.27 seconds
Started Aug 27 06:33:21 PM UTC 24
Finished Aug 27 06:33:43 PM UTC 24
Peak memory 261136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356
2200435 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh
adow_reg_errors.3562200435
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2361208444
Short name T1178
Test name
Test status
Simulation time 14076600 ps
CPU time 28.15 seconds
Started Aug 27 06:33:24 PM UTC 24
Finished Aug 27 06:33:53 PM UTC 24
Peak memory 260928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2361208444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f
lash_ctrl_shadow_reg_errors_with_csr_rw.2361208444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1689034986
Short name T270
Test name
Test status
Simulation time 32850100 ps
CPU time 30.57 seconds
Started Aug 27 06:33:19 PM UTC 24
Finished Aug 27 06:33:51 PM UTC 24
Peak memory 273532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689034986 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.1689034986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.1370560426
Short name T357
Test name
Test status
Simulation time 3233472300 ps
CPU time 1284.38 seconds
Started Aug 27 06:33:21 PM UTC 24
Finished Aug 27 06:55:00 PM UTC 24
Peak memory 273464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370560426 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.1370560426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3057002531
Short name T1179
Test name
Test status
Simulation time 810662300 ps
CPU time 16.42 seconds
Started Aug 27 06:33:36 PM UTC 24
Finished Aug 27 06:33:53 PM UTC 24
Peak memory 273612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3057002531 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.3057002531
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3598594160
Short name T1183
Test name
Test status
Simulation time 71149300 ps
CPU time 22.44 seconds
Started Aug 27 06:33:34 PM UTC 24
Finished Aug 27 06:33:57 PM UTC 24
Peak memory 273556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598594160 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.3598594160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3502172055
Short name T1201
Test name
Test status
Simulation time 340423700 ps
CPU time 50.14 seconds
Started Aug 27 06:33:35 PM UTC 24
Finished Aug 27 06:34:27 PM UTC 24
Peak memory 271436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3502172055 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl
_same_csr_outstanding.3502172055
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3972664659
Short name T1188
Test name
Test status
Simulation time 30389600 ps
CPU time 33.15 seconds
Started Aug 27 06:33:31 PM UTC 24
Finished Aug 27 06:34:06 PM UTC 24
Peak memory 261264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397
2664659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh
adow_reg_errors.3972664659
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.224816200
Short name T1184
Test name
Test status
Simulation time 34138800 ps
CPU time 24.78 seconds
Started Aug 27 06:33:32 PM UTC 24
Finished Aug 27 06:33:58 PM UTC 24
Peak memory 261136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=224816200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.224816200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.213598165
Short name T269
Test name
Test status
Simulation time 422433600 ps
CPU time 32.33 seconds
Started Aug 27 06:33:28 PM UTC 24
Finished Aug 27 06:34:01 PM UTC 24
Peak memory 273532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213598165 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.213598165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.717700630
Short name T367
Test name
Test status
Simulation time 755828500 ps
CPU time 1099.39 seconds
Started Aug 27 06:33:29 PM UTC 24
Finished Aug 27 06:52:00 PM UTC 24
Peak memory 273688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717700630 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.717700630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.904737406
Short name T1195
Test name
Test status
Simulation time 260094200 ps
CPU time 28.45 seconds
Started Aug 27 06:33:48 PM UTC 24
Finished Aug 27 06:34:18 PM UTC 24
Peak memory 283988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=904737406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.904737406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3925221265
Short name T1193
Test name
Test status
Simulation time 101144700 ps
CPU time 30.23 seconds
Started Aug 27 06:33:46 PM UTC 24
Finished Aug 27 06:34:18 PM UTC 24
Peak memory 273492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925221265 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.3925221265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.685721447
Short name T1186
Test name
Test status
Simulation time 27815900 ps
CPU time 18.78 seconds
Started Aug 27 06:33:45 PM UTC 24
Finished Aug 27 06:34:05 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=685721447 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.685721447
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1093465307
Short name T1191
Test name
Test status
Simulation time 188000400 ps
CPU time 22.56 seconds
Started Aug 27 06:33:48 PM UTC 24
Finished Aug 27 06:34:12 PM UTC 24
Peak memory 273484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1093465307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl
_same_csr_outstanding.1093465307
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2659976712
Short name T1182
Test name
Test status
Simulation time 35271300 ps
CPU time 15.7 seconds
Started Aug 27 06:33:39 PM UTC 24
Finished Aug 27 06:33:55 PM UTC 24
Peak memory 261128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=265
9976712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sh
adow_reg_errors.2659976712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1144726203
Short name T1190
Test name
Test status
Simulation time 19623300 ps
CPU time 26.61 seconds
Started Aug 27 06:33:44 PM UTC 24
Finished Aug 27 06:34:12 PM UTC 24
Peak memory 261136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1144726203 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1144726203
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2463007649
Short name T1185
Test name
Test status
Simulation time 122799600 ps
CPU time 23.5 seconds
Started Aug 27 06:33:37 PM UTC 24
Finished Aug 27 06:34:02 PM UTC 24
Peak memory 273536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463007649 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.2463007649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2797292874
Short name T1196
Test name
Test status
Simulation time 120927400 ps
CPU time 20.58 seconds
Started Aug 27 06:33:57 PM UTC 24
Finished Aug 27 06:34:19 PM UTC 24
Peak memory 283860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2797292874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2797292874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3588568921
Short name T1199
Test name
Test status
Simulation time 28397000 ps
CPU time 25.46 seconds
Started Aug 27 06:33:54 PM UTC 24
Finished Aug 27 06:34:21 PM UTC 24
Peak memory 273536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588568921 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.3588568921
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.687379653
Short name T1189
Test name
Test status
Simulation time 14574000 ps
CPU time 16.22 seconds
Started Aug 27 06:33:53 PM UTC 24
Finished Aug 27 06:34:10 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687379653 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.687379653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.698715246
Short name T1198
Test name
Test status
Simulation time 222695200 ps
CPU time 24.06 seconds
Started Aug 27 06:33:54 PM UTC 24
Finished Aug 27 06:34:20 PM UTC 24
Peak memory 273688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
698715246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_
same_csr_outstanding.698715246
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3706987728
Short name T1194
Test name
Test status
Simulation time 12462700 ps
CPU time 25 seconds
Started Aug 27 06:33:52 PM UTC 24
Finished Aug 27 06:34:18 PM UTC 24
Peak memory 261128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370
6987728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sh
adow_reg_errors.3706987728
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4053674042
Short name T1192
Test name
Test status
Simulation time 14546300 ps
CPU time 18.01 seconds
Started Aug 27 06:33:53 PM UTC 24
Finished Aug 27 06:34:12 PM UTC 24
Peak memory 261200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4053674042 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f
lash_ctrl_shadow_reg_errors_with_csr_rw.4053674042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1161641418
Short name T264
Test name
Test status
Simulation time 67533100 ps
CPU time 28.89 seconds
Started Aug 27 06:33:49 PM UTC 24
Finished Aug 27 06:34:19 PM UTC 24
Peak memory 273532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161641418 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.1161641418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3752356570
Short name T1203
Test name
Test status
Simulation time 95141600 ps
CPU time 24.12 seconds
Started Aug 27 06:34:02 PM UTC 24
Finished Aug 27 06:34:27 PM UTC 24
Peak memory 283852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3752356570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3752356570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1146871929
Short name T1205
Test name
Test status
Simulation time 18986400 ps
CPU time 26.5 seconds
Started Aug 27 06:34:01 PM UTC 24
Finished Aug 27 06:34:28 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1146871929 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.1146871929
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3173572061
Short name T1202
Test name
Test status
Simulation time 54558700 ps
CPU time 24.83 seconds
Started Aug 27 06:34:01 PM UTC 24
Finished Aug 27 06:34:27 PM UTC 24
Peak memory 271484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3173572061 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.3173572061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.108818680
Short name T1204
Test name
Test status
Simulation time 101774000 ps
CPU time 25.26 seconds
Started Aug 27 06:34:01 PM UTC 24
Finished Aug 27 06:34:27 PM UTC 24
Peak memory 273492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
108818680 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
same_csr_outstanding.108818680
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1097271657
Short name T1197
Test name
Test status
Simulation time 13079900 ps
CPU time 21.26 seconds
Started Aug 27 06:33:57 PM UTC 24
Finished Aug 27 06:34:19 PM UTC 24
Peak memory 261328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109
7271657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh
adow_reg_errors.1097271657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.139305491
Short name T1200
Test name
Test status
Simulation time 12250100 ps
CPU time 25.76 seconds
Started Aug 27 06:33:58 PM UTC 24
Finished Aug 27 06:34:25 PM UTC 24
Peak memory 261132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=139305491 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.139305491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1603581747
Short name T274
Test name
Test status
Simulation time 30965000 ps
CPU time 17.63 seconds
Started Aug 27 06:33:57 PM UTC 24
Finished Aug 27 06:34:15 PM UTC 24
Peak memory 273460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603581747 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.1603581747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.2895569099
Short name T353
Test name
Test status
Simulation time 212779300 ps
CPU time 542.88 seconds
Started Aug 27 06:33:57 PM UTC 24
Finished Aug 27 06:43:06 PM UTC 24
Peak memory 273432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895569099 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.2895569099
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1660661846
Short name T1210
Test name
Test status
Simulation time 31707200 ps
CPU time 20.34 seconds
Started Aug 27 06:34:14 PM UTC 24
Finished Aug 27 06:34:36 PM UTC 24
Peak memory 283920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1660661846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.1660661846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2286562149
Short name T1213
Test name
Test status
Simulation time 107932800 ps
CPU time 27.39 seconds
Started Aug 27 06:34:10 PM UTC 24
Finished Aug 27 06:34:38 PM UTC 24
Peak memory 271636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286562149 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.2286562149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.836049546
Short name T1209
Test name
Test status
Simulation time 77388500 ps
CPU time 25.47 seconds
Started Aug 27 06:34:07 PM UTC 24
Finished Aug 27 06:34:33 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836049546 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.836049546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1392485794
Short name T1227
Test name
Test status
Simulation time 117367000 ps
CPU time 40.65 seconds
Started Aug 27 06:34:12 PM UTC 24
Finished Aug 27 06:34:54 PM UTC 24
Peak memory 271436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1392485794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_same_csr_outstanding.1392485794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1175199913
Short name T1208
Test name
Test status
Simulation time 16408700 ps
CPU time 25.14 seconds
Started Aug 27 06:34:06 PM UTC 24
Finished Aug 27 06:34:33 PM UTC 24
Peak memory 261328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117
5199913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh
adow_reg_errors.1175199913
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.886716032
Short name T1207
Test name
Test status
Simulation time 15005100 ps
CPU time 21.22 seconds
Started Aug 27 06:34:06 PM UTC 24
Finished Aug 27 06:34:29 PM UTC 24
Peak memory 261132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=886716032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.886716032
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3866134971
Short name T1206
Test name
Test status
Simulation time 140210600 ps
CPU time 23.83 seconds
Started Aug 27 06:34:04 PM UTC 24
Finished Aug 27 06:34:29 PM UTC 24
Peak memory 273392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866134971 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.3866134971
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2882124520
Short name T1222
Test name
Test status
Simulation time 78170400 ps
CPU time 28.37 seconds
Started Aug 27 06:34:19 PM UTC 24
Finished Aug 27 06:34:49 PM UTC 24
Peak memory 273616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2882124520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2882124520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4240827483
Short name T1216
Test name
Test status
Simulation time 136178100 ps
CPU time 22.59 seconds
Started Aug 27 06:34:19 PM UTC 24
Finished Aug 27 06:34:43 PM UTC 24
Peak memory 271000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240827483 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.4240827483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3686664878
Short name T1211
Test name
Test status
Simulation time 93941800 ps
CPU time 18.01 seconds
Started Aug 27 06:34:17 PM UTC 24
Finished Aug 27 06:34:36 PM UTC 24
Peak memory 271352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686664878 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.3686664878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3026893665
Short name T1214
Test name
Test status
Simulation time 161794700 ps
CPU time 20.88 seconds
Started Aug 27 06:34:19 PM UTC 24
Finished Aug 27 06:34:41 PM UTC 24
Peak memory 273484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3026893665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_same_csr_outstanding.3026893665
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1908796656
Short name T1219
Test name
Test status
Simulation time 12229000 ps
CPU time 27.82 seconds
Started Aug 27 06:34:14 PM UTC 24
Finished Aug 27 06:34:44 PM UTC 24
Peak memory 261328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190
8796656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sh
adow_reg_errors.1908796656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1604105088
Short name T1212
Test name
Test status
Simulation time 35705400 ps
CPU time 21.49 seconds
Started Aug 27 06:34:14 PM UTC 24
Finished Aug 27 06:34:37 PM UTC 24
Peak memory 261132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1604105088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1604105088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2669676007
Short name T272
Test name
Test status
Simulation time 202614100 ps
CPU time 23.81 seconds
Started Aug 27 06:34:14 PM UTC 24
Finished Aug 27 06:34:39 PM UTC 24
Peak memory 273524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669676007 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.2669676007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3891802664
Short name T1231
Test name
Test status
Simulation time 55609500 ps
CPU time 31.35 seconds
Started Aug 27 06:34:26 PM UTC 24
Finished Aug 27 06:34:59 PM UTC 24
Peak memory 283924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3891802664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.3891802664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3391518127
Short name T1221
Test name
Test status
Simulation time 32481900 ps
CPU time 21.44 seconds
Started Aug 27 06:34:25 PM UTC 24
Finished Aug 27 06:34:48 PM UTC 24
Peak memory 273484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391518127 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.3391518127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1508033129
Short name T1220
Test name
Test status
Simulation time 330272000 ps
CPU time 20.05 seconds
Started Aug 27 06:34:25 PM UTC 24
Finished Aug 27 06:34:46 PM UTC 24
Peak memory 273484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1508033129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_same_csr_outstanding.1508033129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1051686694
Short name T1218
Test name
Test status
Simulation time 45017800 ps
CPU time 20.77 seconds
Started Aug 27 06:34:21 PM UTC 24
Finished Aug 27 06:34:43 PM UTC 24
Peak memory 261132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105
1686694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sh
adow_reg_errors.1051686694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.634024319
Short name T1215
Test name
Test status
Simulation time 14337700 ps
CPU time 19.96 seconds
Started Aug 27 06:34:21 PM UTC 24
Finished Aug 27 06:34:42 PM UTC 24
Peak memory 261264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=634024319 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.634024319
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.4146388900
Short name T1225
Test name
Test status
Simulation time 181223600 ps
CPU time 16.98 seconds
Started Aug 27 06:34:34 PM UTC 24
Finished Aug 27 06:34:52 PM UTC 24
Peak memory 273612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=4146388900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.4146388900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1582656151
Short name T1229
Test name
Test status
Simulation time 30493100 ps
CPU time 23.31 seconds
Started Aug 27 06:34:30 PM UTC 24
Finished Aug 27 06:34:55 PM UTC 24
Peak memory 273488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582656151 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.1582656151
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2287136695
Short name T1223
Test name
Test status
Simulation time 24089100 ps
CPU time 17.28 seconds
Started Aug 27 06:34:30 PM UTC 24
Finished Aug 27 06:34:49 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287136695 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.2287136695
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4175751106
Short name T1234
Test name
Test status
Simulation time 218675300 ps
CPU time 31.26 seconds
Started Aug 27 06:34:30 PM UTC 24
Finished Aug 27 06:35:03 PM UTC 24
Peak memory 271572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4175751106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_same_csr_outstanding.4175751106
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3226003464
Short name T1224
Test name
Test status
Simulation time 13375600 ps
CPU time 19.55 seconds
Started Aug 27 06:34:29 PM UTC 24
Finished Aug 27 06:34:50 PM UTC 24
Peak memory 261328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322
6003464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sh
adow_reg_errors.3226003464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1022117185
Short name T1226
Test name
Test status
Simulation time 139968200 ps
CPU time 22.92 seconds
Started Aug 27 06:34:29 PM UTC 24
Finished Aug 27 06:34:53 PM UTC 24
Peak memory 261328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1022117185 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1022117185
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.332507218
Short name T1228
Test name
Test status
Simulation time 54254600 ps
CPU time 24.94 seconds
Started Aug 27 06:34:27 PM UTC 24
Finished Aug 27 06:34:54 PM UTC 24
Peak memory 273460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=332507218 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.332507218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.4274397628
Short name T361
Test name
Test status
Simulation time 7397984500 ps
CPU time 1240.34 seconds
Started Aug 27 06:34:28 PM UTC 24
Finished Aug 27 06:55:22 PM UTC 24
Peak memory 273552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274397628 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.4274397628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2006021692
Short name T1240
Test name
Test status
Simulation time 383544300 ps
CPU time 24.26 seconds
Started Aug 27 06:34:43 PM UTC 24
Finished Aug 27 06:35:09 PM UTC 24
Peak memory 283860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2006021692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2006021692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1944051303
Short name T1236
Test name
Test status
Simulation time 106702300 ps
CPU time 22.14 seconds
Started Aug 27 06:34:41 PM UTC 24
Finished Aug 27 06:35:04 PM UTC 24
Peak memory 273488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1944051303 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.1944051303
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.4010809160
Short name T1230
Test name
Test status
Simulation time 56757200 ps
CPU time 16.54 seconds
Started Aug 27 06:34:40 PM UTC 24
Finished Aug 27 06:34:58 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010809160 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.4010809160
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1421616620
Short name T1241
Test name
Test status
Simulation time 166214600 ps
CPU time 25.34 seconds
Started Aug 27 06:34:42 PM UTC 24
Finished Aug 27 06:35:09 PM UTC 24
Peak memory 273488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1421616620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_same_csr_outstanding.1421616620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3443953449
Short name T1232
Test name
Test status
Simulation time 58843300 ps
CPU time 21.38 seconds
Started Aug 27 06:34:37 PM UTC 24
Finished Aug 27 06:35:00 PM UTC 24
Peak memory 261264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=344
3953449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh
adow_reg_errors.3443953449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2212354222
Short name T1238
Test name
Test status
Simulation time 63848300 ps
CPU time 26 seconds
Started Aug 27 06:34:38 PM UTC 24
Finished Aug 27 06:35:06 PM UTC 24
Peak memory 261264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2212354222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.f
lash_ctrl_shadow_reg_errors_with_csr_rw.2212354222
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.1546499021
Short name T364
Test name
Test status
Simulation time 725880200 ps
CPU time 691.83 seconds
Started Aug 27 06:34:37 PM UTC 24
Finished Aug 27 06:46:17 PM UTC 24
Peak memory 273548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1546499021 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.1546499021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4141109892
Short name T263
Test name
Test status
Simulation time 293591900 ps
CPU time 53.03 seconds
Started Aug 27 06:31:30 PM UTC 24
Finished Aug 27 06:32:25 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4141109892 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.4141109892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1023019082
Short name T369
Test name
Test status
Simulation time 646763800 ps
CPU time 58.39 seconds
Started Aug 27 06:31:30 PM UTC 24
Finished Aug 27 06:32:30 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023019082 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.1023019082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.488483405
Short name T262
Test name
Test status
Simulation time 336568600 ps
CPU time 38.52 seconds
Started Aug 27 06:31:28 PM UTC 24
Finished Aug 27 06:32:08 PM UTC 24
Peak memory 271568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488483405 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.488483405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4128774724
Short name T110
Test name
Test status
Simulation time 73802700 ps
CPU time 30.32 seconds
Started Aug 27 06:31:40 PM UTC 24
Finished Aug 27 06:32:12 PM UTC 24
Peak memory 290000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=4128774724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.4128774724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1819367083
Short name T252
Test name
Test status
Simulation time 106201200 ps
CPU time 21.68 seconds
Started Aug 27 06:31:28 PM UTC 24
Finished Aug 27 06:31:51 PM UTC 24
Peak memory 273496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819367083 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.1819367083
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.3432408951
Short name T330
Test name
Test status
Simulation time 31315100 ps
CPU time 25.67 seconds
Started Aug 27 06:31:24 PM UTC 24
Finished Aug 27 06:31:51 PM UTC 24
Peak memory 271364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432408951 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.3432408951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3738532326
Short name T249
Test name
Test status
Simulation time 41682300 ps
CPU time 22.46 seconds
Started Aug 27 06:31:24 PM UTC 24
Finished Aug 27 06:31:48 PM UTC 24
Peak memory 273480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738532326 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.3738532326
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3001269038
Short name T1136
Test name
Test status
Simulation time 16335600 ps
CPU time 25.09 seconds
Started Aug 27 06:31:24 PM UTC 24
Finished Aug 27 06:31:51 PM UTC 24
Peak memory 271504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001269038 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.3001269038
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2573734381
Short name T253
Test name
Test status
Simulation time 187154700 ps
CPU time 22.27 seconds
Started Aug 27 06:31:36 PM UTC 24
Finished Aug 27 06:32:00 PM UTC 24
Peak memory 271576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2573734381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
same_csr_outstanding.2573734381
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3223892218
Short name T1137
Test name
Test status
Simulation time 12728800 ps
CPU time 31.93 seconds
Started Aug 27 06:31:22 PM UTC 24
Finished Aug 27 06:31:55 PM UTC 24
Peak memory 261144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322
3892218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha
dow_reg_errors.3223892218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3496102790
Short name T1138
Test name
Test status
Simulation time 193787200 ps
CPU time 32.26 seconds
Started Aug 27 06:31:22 PM UTC 24
Finished Aug 27 06:31:55 PM UTC 24
Peak memory 261128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3496102790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.3496102790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.808928888
Short name T228
Test name
Test status
Simulation time 34414600 ps
CPU time 19.61 seconds
Started Aug 27 06:31:19 PM UTC 24
Finished Aug 27 06:31:40 PM UTC 24
Peak memory 273524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808928888 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.808928888
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2332851713
Short name T254
Test name
Test status
Simulation time 1548895700 ps
CPU time 599.22 seconds
Started Aug 27 06:31:19 PM UTC 24
Finished Aug 27 06:41:25 PM UTC 24
Peak memory 273684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332851713 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.2332851713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1983725452
Short name T1235
Test name
Test status
Simulation time 15126400 ps
CPU time 17.4 seconds
Started Aug 27 06:34:45 PM UTC 24
Finished Aug 27 06:35:03 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983725452 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.1983725452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.3472775336
Short name T1239
Test name
Test status
Simulation time 42112000 ps
CPU time 22.33 seconds
Started Aug 27 06:34:45 PM UTC 24
Finished Aug 27 06:35:08 PM UTC 24
Peak memory 271484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472775336 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.3472775336
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.999098990
Short name T1233
Test name
Test status
Simulation time 24426400 ps
CPU time 16.2 seconds
Started Aug 27 06:34:45 PM UTC 24
Finished Aug 27 06:35:02 PM UTC 24
Peak memory 271284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999098990 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.999098990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.514892912
Short name T1237
Test name
Test status
Simulation time 15374000 ps
CPU time 18.75 seconds
Started Aug 27 06:34:45 PM UTC 24
Finished Aug 27 06:35:05 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514892912 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.514892912
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.266674792
Short name T1246
Test name
Test status
Simulation time 17952700 ps
CPU time 25.07 seconds
Started Aug 27 06:34:46 PM UTC 24
Finished Aug 27 06:35:12 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266674792 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.266674792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.891427553
Short name T1244
Test name
Test status
Simulation time 17363100 ps
CPU time 22.7 seconds
Started Aug 27 06:34:48 PM UTC 24
Finished Aug 27 06:35:12 PM UTC 24
Peak memory 271352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891427553 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.891427553
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.1680410497
Short name T1253
Test name
Test status
Simulation time 36011300 ps
CPU time 28.5 seconds
Started Aug 27 06:34:48 PM UTC 24
Finished Aug 27 06:35:18 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680410497 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.1680410497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.2918679988
Short name T1243
Test name
Test status
Simulation time 18773400 ps
CPU time 21.16 seconds
Started Aug 27 06:34:50 PM UTC 24
Finished Aug 27 06:35:12 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918679988 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.2918679988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.4013190507
Short name T1242
Test name
Test status
Simulation time 24803300 ps
CPU time 18.2 seconds
Started Aug 27 06:34:50 PM UTC 24
Finished Aug 27 06:35:09 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013190507 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.4013190507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.649693542
Short name T1255
Test name
Test status
Simulation time 37043300 ps
CPU time 29.5 seconds
Started Aug 27 06:34:50 PM UTC 24
Finished Aug 27 06:35:20 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649693542 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.649693542
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.276009411
Short name T1163
Test name
Test status
Simulation time 20421735200 ps
CPU time 87.74 seconds
Started Aug 27 06:31:55 PM UTC 24
Finished Aug 27 06:33:25 PM UTC 24
Peak memory 271504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=276009411 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.276009411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1189626524
Short name T1180
Test name
Test status
Simulation time 14424164700 ps
CPU time 119.09 seconds
Started Aug 27 06:31:53 PM UTC 24
Finished Aug 27 06:33:54 PM UTC 24
Peak memory 271572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189626524 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.1189626524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.766832577
Short name T1145
Test name
Test status
Simulation time 34481200 ps
CPU time 39.15 seconds
Started Aug 27 06:31:52 PM UTC 24
Finished Aug 27 06:32:32 PM UTC 24
Peak memory 271432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766832577 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.766832577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3990485878
Short name T294
Test name
Test status
Simulation time 64894400 ps
CPU time 26.74 seconds
Started Aug 27 06:31:52 PM UTC 24
Finished Aug 27 06:32:20 PM UTC 24
Peak memory 271520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990485878 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.3990485878
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1574770724
Short name T250
Test name
Test status
Simulation time 17809700 ps
CPU time 22.2 seconds
Started Aug 27 06:31:52 PM UTC 24
Finished Aug 27 06:32:15 PM UTC 24
Peak memory 271360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574770724 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.1574770724
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.243588097
Short name T1140
Test name
Test status
Simulation time 50476800 ps
CPU time 22.47 seconds
Started Aug 27 06:31:52 PM UTC 24
Finished Aug 27 06:32:15 PM UTC 24
Peak memory 271504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243588097 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.243588097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3437171045
Short name T1147
Test name
Test status
Simulation time 156579200 ps
CPU time 41.18 seconds
Started Aug 27 06:31:57 PM UTC 24
Finished Aug 27 06:32:39 PM UTC 24
Peak memory 273496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3437171045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
same_csr_outstanding.3437171045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1756148951
Short name T1141
Test name
Test status
Simulation time 11557800 ps
CPU time 28.99 seconds
Started Aug 27 06:31:47 PM UTC 24
Finished Aug 27 06:32:17 PM UTC 24
Peak memory 261148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175
6148951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha
dow_reg_errors.1756148951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.560462633
Short name T1139
Test name
Test status
Simulation time 20120200 ps
CPU time 20.18 seconds
Started Aug 27 06:31:47 PM UTC 24
Finished Aug 27 06:32:08 PM UTC 24
Peak memory 261260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=560462633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.560462633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1283915539
Short name T363
Test name
Test status
Simulation time 795588200 ps
CPU time 661.23 seconds
Started Aug 27 06:31:45 PM UTC 24
Finished Aug 27 06:42:55 PM UTC 24
Peak memory 273556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283915539 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.1283915539
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1541779674
Short name T1250
Test name
Test status
Simulation time 47864000 ps
CPU time 21.62 seconds
Started Aug 27 06:34:51 PM UTC 24
Finished Aug 27 06:35:14 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541779674 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.1541779674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.456570593
Short name T1251
Test name
Test status
Simulation time 21595400 ps
CPU time 22.06 seconds
Started Aug 27 06:34:53 PM UTC 24
Finished Aug 27 06:35:16 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456570593 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.456570593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.939267138
Short name T1245
Test name
Test status
Simulation time 59608400 ps
CPU time 16.73 seconds
Started Aug 27 06:34:54 PM UTC 24
Finished Aug 27 06:35:12 PM UTC 24
Peak memory 271352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939267138 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.939267138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.3327674527
Short name T1248
Test name
Test status
Simulation time 16568500 ps
CPU time 17.63 seconds
Started Aug 27 06:34:55 PM UTC 24
Finished Aug 27 06:35:13 PM UTC 24
Peak memory 271352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327674527 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.3327674527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1058118720
Short name T1249
Test name
Test status
Simulation time 98929300 ps
CPU time 17.51 seconds
Started Aug 27 06:34:55 PM UTC 24
Finished Aug 27 06:35:13 PM UTC 24
Peak memory 271352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058118720 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.1058118720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2240171766
Short name T1247
Test name
Test status
Simulation time 20616300 ps
CPU time 16.25 seconds
Started Aug 27 06:34:56 PM UTC 24
Finished Aug 27 06:35:13 PM UTC 24
Peak memory 271352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240171766 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.2240171766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.4132242166
Short name T1254
Test name
Test status
Simulation time 14498500 ps
CPU time 21.2 seconds
Started Aug 27 06:34:57 PM UTC 24
Finished Aug 27 06:35:19 PM UTC 24
Peak memory 271352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132242166 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.4132242166
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.1016849775
Short name T1252
Test name
Test status
Simulation time 51426900 ps
CPU time 17.99 seconds
Started Aug 27 06:34:58 PM UTC 24
Finished Aug 27 06:35:17 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016849775 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.1016849775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2566716645
Short name T1257
Test name
Test status
Simulation time 17635300 ps
CPU time 22.31 seconds
Started Aug 27 06:35:00 PM UTC 24
Finished Aug 27 06:35:24 PM UTC 24
Peak memory 271360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566716645 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.2566716645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.1300965522
Short name T1260
Test name
Test status
Simulation time 17693100 ps
CPU time 23.18 seconds
Started Aug 27 06:35:02 PM UTC 24
Finished Aug 27 06:35:26 PM UTC 24
Peak memory 271360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300965522 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.1300965522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3557636101
Short name T298
Test name
Test status
Simulation time 6262642200 ps
CPU time 64.72 seconds
Started Aug 27 06:32:17 PM UTC 24
Finished Aug 27 06:33:23 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557636101 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.3557636101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3550291351
Short name T1187
Test name
Test status
Simulation time 14694118200 ps
CPU time 107.65 seconds
Started Aug 27 06:32:16 PM UTC 24
Finished Aug 27 06:34:06 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3550291351 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.3550291351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3137001470
Short name T1174
Test name
Test status
Simulation time 24979500 ps
CPU time 90.49 seconds
Started Aug 27 06:32:12 PM UTC 24
Finished Aug 27 06:33:45 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137001470 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.3137001470
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2948785514
Short name T242
Test name
Test status
Simulation time 303453800 ps
CPU time 18.03 seconds
Started Aug 27 06:32:20 PM UTC 24
Finished Aug 27 06:32:39 PM UTC 24
Peak memory 283852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2948785514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.2948785514
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.799108834
Short name T1148
Test name
Test status
Simulation time 52968200 ps
CPU time 23.37 seconds
Started Aug 27 06:32:16 PM UTC 24
Finished Aug 27 06:32:40 PM UTC 24
Peak memory 271440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799108834 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.799108834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2315047689
Short name T335
Test name
Test status
Simulation time 29091300 ps
CPU time 25.56 seconds
Started Aug 27 06:32:09 PM UTC 24
Finished Aug 27 06:32:36 PM UTC 24
Peak memory 271492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315047689 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2315047689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1831831299
Short name T1146
Test name
Test status
Simulation time 27700700 ps
CPU time 23.84 seconds
Started Aug 27 06:32:09 PM UTC 24
Finished Aug 27 06:32:34 PM UTC 24
Peak memory 271500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831831299 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.1831831299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3544866760
Short name T295
Test name
Test status
Simulation time 126255400 ps
CPU time 27.18 seconds
Started Aug 27 06:32:18 PM UTC 24
Finished Aug 27 06:32:47 PM UTC 24
Peak memory 273492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3544866760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
same_csr_outstanding.3544866760
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2413161201
Short name T1143
Test name
Test status
Simulation time 11291700 ps
CPU time 20.32 seconds
Started Aug 27 06:32:05 PM UTC 24
Finished Aug 27 06:32:27 PM UTC 24
Peak memory 261276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241
3161201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sha
dow_reg_errors.2413161201
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1646935521
Short name T1144
Test name
Test status
Simulation time 15066800 ps
CPU time 20.83 seconds
Started Aug 27 06:32:07 PM UTC 24
Finished Aug 27 06:32:29 PM UTC 24
Peak memory 261136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1646935521 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1646935521
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.74439858
Short name T230
Test name
Test status
Simulation time 61424800 ps
CPU time 22.56 seconds
Started Aug 27 06:32:00 PM UTC 24
Finished Aug 27 06:32:24 PM UTC 24
Peak memory 273528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74439858 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.74439858
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.583091025
Short name T362
Test name
Test status
Simulation time 1336747800 ps
CPU time 1307.19 seconds
Started Aug 27 06:32:01 PM UTC 24
Finished Aug 27 06:54:03 PM UTC 24
Peak memory 273544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583091025 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.583091025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.1700107250
Short name T1264
Test name
Test status
Simulation time 48162800 ps
CPU time 24.32 seconds
Started Aug 27 06:35:03 PM UTC 24
Finished Aug 27 06:35:28 PM UTC 24
Peak memory 271484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700107250 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.1700107250
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2775168995
Short name T1259
Test name
Test status
Simulation time 56302400 ps
CPU time 19.17 seconds
Started Aug 27 06:35:04 PM UTC 24
Finished Aug 27 06:35:24 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775168995 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.2775168995
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.1248976961
Short name T1256
Test name
Test status
Simulation time 28595500 ps
CPU time 18.29 seconds
Started Aug 27 06:35:04 PM UTC 24
Finished Aug 27 06:35:24 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248976961 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.1248976961
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.151356341
Short name T1258
Test name
Test status
Simulation time 52888200 ps
CPU time 17.45 seconds
Started Aug 27 06:35:05 PM UTC 24
Finished Aug 27 06:35:24 PM UTC 24
Peak memory 271284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151356341 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.151356341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.2028848483
Short name T1265
Test name
Test status
Simulation time 44261300 ps
CPU time 22.55 seconds
Started Aug 27 06:35:06 PM UTC 24
Finished Aug 27 06:35:29 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028848483 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.2028848483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.73964714
Short name T1262
Test name
Test status
Simulation time 17848600 ps
CPU time 17.78 seconds
Started Aug 27 06:35:08 PM UTC 24
Finished Aug 27 06:35:26 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73964714 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.73964714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1012780596
Short name T1261
Test name
Test status
Simulation time 57324200 ps
CPU time 17.55 seconds
Started Aug 27 06:35:08 PM UTC 24
Finished Aug 27 06:35:26 PM UTC 24
Peak memory 271360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012780596 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.1012780596
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2141441305
Short name T1267
Test name
Test status
Simulation time 17561400 ps
CPU time 23.01 seconds
Started Aug 27 06:35:09 PM UTC 24
Finished Aug 27 06:35:33 PM UTC 24
Peak memory 271484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2141441305 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.2141441305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.2478116025
Short name T1266
Test name
Test status
Simulation time 41742100 ps
CPU time 19.43 seconds
Started Aug 27 06:35:10 PM UTC 24
Finished Aug 27 06:35:31 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478116025 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.2478116025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.3931787799
Short name T1263
Test name
Test status
Simulation time 79631400 ps
CPU time 16.37 seconds
Started Aug 27 06:35:10 PM UTC 24
Finished Aug 27 06:35:28 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931787799 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.3931787799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4072300928
Short name T244
Test name
Test status
Simulation time 28511300 ps
CPU time 27.14 seconds
Started Aug 27 06:32:29 PM UTC 24
Finished Aug 27 06:32:58 PM UTC 24
Peak memory 283856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=4072300928 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.4072300928
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.126691100
Short name T1153
Test name
Test status
Simulation time 19097600 ps
CPU time 31.94 seconds
Started Aug 27 06:32:28 PM UTC 24
Finished Aug 27 06:33:01 PM UTC 24
Peak memory 271440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126691100 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.126691100
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.1832812653
Short name T334
Test name
Test status
Simulation time 106323000 ps
CPU time 28.49 seconds
Started Aug 27 06:32:25 PM UTC 24
Finished Aug 27 06:32:55 PM UTC 24
Peak memory 271360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832812653 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.1832812653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.903338047
Short name T1161
Test name
Test status
Simulation time 62652400 ps
CPU time 53.48 seconds
Started Aug 27 06:32:28 PM UTC 24
Finished Aug 27 06:33:23 PM UTC 24
Peak memory 273688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
903338047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_s
ame_csr_outstanding.903338047
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2914662764
Short name T1149
Test name
Test status
Simulation time 13977700 ps
CPU time 19.26 seconds
Started Aug 27 06:32:21 PM UTC 24
Finished Aug 27 06:32:41 PM UTC 24
Peak memory 261272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291
4662764 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha
dow_reg_errors.2914662764
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.161991684
Short name T1150
Test name
Test status
Simulation time 18362400 ps
CPU time 21.25 seconds
Started Aug 27 06:32:24 PM UTC 24
Finished Aug 27 06:32:47 PM UTC 24
Peak memory 261124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=161991684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.161991684
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.630165548
Short name T355
Test name
Test status
Simulation time 349271300 ps
CPU time 1151.05 seconds
Started Aug 27 06:32:21 PM UTC 24
Finished Aug 27 06:51:45 PM UTC 24
Peak memory 273680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630165548 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.630165548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1208701206
Short name T1155
Test name
Test status
Simulation time 24887100 ps
CPU time 25 seconds
Started Aug 27 06:32:40 PM UTC 24
Finished Aug 27 06:33:06 PM UTC 24
Peak memory 283856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1208701206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.1208701206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1793012426
Short name T1152
Test name
Test status
Simulation time 57564300 ps
CPU time 20.82 seconds
Started Aug 27 06:32:37 PM UTC 24
Finished Aug 27 06:32:59 PM UTC 24
Peak memory 273488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793012426 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.1793012426
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.2249799870
Short name T332
Test name
Test status
Simulation time 77955100 ps
CPU time 26.71 seconds
Started Aug 27 06:32:36 PM UTC 24
Finished Aug 27 06:33:04 PM UTC 24
Peak memory 271492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2249799870 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2249799870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1929369696
Short name T297
Test name
Test status
Simulation time 114954600 ps
CPU time 26.11 seconds
Started Aug 27 06:32:40 PM UTC 24
Finished Aug 27 06:33:07 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1929369696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
same_csr_outstanding.1929369696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2959855018
Short name T1151
Test name
Test status
Simulation time 47842500 ps
CPU time 16.7 seconds
Started Aug 27 06:32:33 PM UTC 24
Finished Aug 27 06:32:51 PM UTC 24
Peak memory 261276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295
9855018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sha
dow_reg_errors.2959855018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2024151238
Short name T1154
Test name
Test status
Simulation time 24973300 ps
CPU time 26.6 seconds
Started Aug 27 06:32:35 PM UTC 24
Finished Aug 27 06:33:03 PM UTC 24
Peak memory 261132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2024151238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2024151238
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3484059487
Short name T266
Test name
Test status
Simulation time 110738500 ps
CPU time 34.69 seconds
Started Aug 27 06:32:31 PM UTC 24
Finished Aug 27 06:33:08 PM UTC 24
Peak memory 273540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484059487 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3484059487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3249162277
Short name T299
Test name
Test status
Simulation time 100323400 ps
CPU time 34.56 seconds
Started Aug 27 06:32:57 PM UTC 24
Finished Aug 27 06:33:33 PM UTC 24
Peak memory 287948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3249162277 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3249162277
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.54416014
Short name T1160
Test name
Test status
Simulation time 90618700 ps
CPU time 24.12 seconds
Started Aug 27 06:32:55 PM UTC 24
Finished Aug 27 06:33:21 PM UTC 24
Peak memory 273492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54416014 -assert n
opostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.54416014
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2995060703
Short name T333
Test name
Test status
Simulation time 15502700 ps
CPU time 19.1 seconds
Started Aug 27 06:32:52 PM UTC 24
Finished Aug 27 06:33:12 PM UTC 24
Peak memory 271360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995060703 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.2995060703
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2154680907
Short name T1158
Test name
Test status
Simulation time 75175500 ps
CPU time 20.12 seconds
Started Aug 27 06:32:56 PM UTC 24
Finished Aug 27 06:33:18 PM UTC 24
Peak memory 271444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2154680907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
same_csr_outstanding.2154680907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.696646811
Short name T1156
Test name
Test status
Simulation time 41665000 ps
CPU time 17.7 seconds
Started Aug 27 06:32:48 PM UTC 24
Finished Aug 27 06:33:07 PM UTC 24
Peak memory 261272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696
646811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_shad
ow_reg_errors.696646811
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.886850546
Short name T1157
Test name
Test status
Simulation time 12486700 ps
CPU time 17.69 seconds
Started Aug 27 06:32:48 PM UTC 24
Finished Aug 27 06:33:07 PM UTC 24
Peak memory 261260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=886850546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.886850546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.2762988024
Short name T358
Test name
Test status
Simulation time 2247636300 ps
CPU time 609.84 seconds
Started Aug 27 06:32:42 PM UTC 24
Finished Aug 27 06:42:59 PM UTC 24
Peak memory 273548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2762988024 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.2762988024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.250274750
Short name T1166
Test name
Test status
Simulation time 82723200 ps
CPU time 24.15 seconds
Started Aug 27 06:33:06 PM UTC 24
Finished Aug 27 06:33:31 PM UTC 24
Peak memory 283852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=250274750 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.250274750
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1931575229
Short name T1162
Test name
Test status
Simulation time 21338800 ps
CPU time 17.66 seconds
Started Aug 27 06:33:04 PM UTC 24
Finished Aug 27 06:33:23 PM UTC 24
Peak memory 273488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931575229 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.1931575229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1150206018
Short name T1164
Test name
Test status
Simulation time 59163700 ps
CPU time 21.03 seconds
Started Aug 27 06:33:04 PM UTC 24
Finished Aug 27 06:33:26 PM UTC 24
Peak memory 271428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150206018 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1150206018
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3990182628
Short name T301
Test name
Test status
Simulation time 215460300 ps
CPU time 46.01 seconds
Started Aug 27 06:33:04 PM UTC 24
Finished Aug 27 06:33:52 PM UTC 24
Peak memory 273496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3990182628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_
same_csr_outstanding.3990182628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2688613905
Short name T1159
Test name
Test status
Simulation time 14009800 ps
CPU time 19.93 seconds
Started Aug 27 06:33:01 PM UTC 24
Finished Aug 27 06:33:23 PM UTC 24
Peak memory 261144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268
8613905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sha
dow_reg_errors.2688613905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1963490977
Short name T1169
Test name
Test status
Simulation time 26170100 ps
CPU time 32.08 seconds
Started Aug 27 06:33:03 PM UTC 24
Finished Aug 27 06:33:36 PM UTC 24
Peak memory 261128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1963490977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1963490977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2508012251
Short name T351
Test name
Test status
Simulation time 61343700 ps
CPU time 27.68 seconds
Started Aug 27 06:32:59 PM UTC 24
Finished Aug 27 06:33:28 PM UTC 24
Peak memory 273668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508012251 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.2508012251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3201126518
Short name T255
Test name
Test status
Simulation time 343775700 ps
CPU time 507.67 seconds
Started Aug 27 06:33:00 PM UTC 24
Finished Aug 27 06:41:34 PM UTC 24
Peak memory 273552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201126518 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.3201126518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1783898467
Short name T1176
Test name
Test status
Simulation time 92876400 ps
CPU time 34.19 seconds
Started Aug 27 06:33:14 PM UTC 24
Finished Aug 27 06:33:49 PM UTC 24
Peak memory 288016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1783898467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1783898467
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.957132267
Short name T1170
Test name
Test status
Simulation time 31366000 ps
CPU time 26.62 seconds
Started Aug 27 06:33:09 PM UTC 24
Finished Aug 27 06:33:37 PM UTC 24
Peak memory 273492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957132267 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.957132267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.691708872
Short name T1167
Test name
Test status
Simulation time 30667100 ps
CPU time 24.03 seconds
Started Aug 27 06:33:08 PM UTC 24
Finished Aug 27 06:33:34 PM UTC 24
Peak memory 271280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=691708872 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.691708872
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1798131321
Short name T1171
Test name
Test status
Simulation time 321325100 ps
CPU time 22.5 seconds
Started Aug 27 06:33:14 PM UTC 24
Finished Aug 27 06:33:38 PM UTC 24
Peak memory 273624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1798131321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
same_csr_outstanding.1798131321
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1947965560
Short name T1168
Test name
Test status
Simulation time 26681800 ps
CPU time 25.9 seconds
Started Aug 27 06:33:07 PM UTC 24
Finished Aug 27 06:33:35 PM UTC 24
Peak memory 261144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=194
7965560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha
dow_reg_errors.1947965560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2456106567
Short name T1165
Test name
Test status
Simulation time 11467300 ps
CPU time 21.24 seconds
Started Aug 27 06:33:07 PM UTC 24
Finished Aug 27 06:33:30 PM UTC 24
Peak memory 261136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2456106567 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2456106567
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1027263252
Short name T265
Test name
Test status
Simulation time 126902000 ps
CPU time 23.97 seconds
Started Aug 27 06:33:07 PM UTC 24
Finished Aug 27 06:33:33 PM UTC 24
Peak memory 273668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1027263252 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.1027263252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3177556861
Short name T366
Test name
Test status
Simulation time 346458300 ps
CPU time 1076.79 seconds
Started Aug 27 06:33:07 PM UTC 24
Finished Aug 27 06:51:16 PM UTC 24
Peak memory 273552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177556861 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.3177556861
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2311750111
Short name T96
Test name
Test status
Simulation time 73800800 ps
CPU time 15.44 seconds
Started Aug 27 12:13:34 PM UTC 24
Finished Aug 27 12:13:50 PM UTC 24
Peak memory 269304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311750111 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2311750111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.1389932398
Short name T7
Test name
Test status
Simulation time 128999300 ps
CPU time 28.34 seconds
Started Aug 27 12:12:27 PM UTC 24
Finished Aug 27 12:12:56 PM UTC 24
Peak memory 285816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1389932398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_disable.1389932398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2799038031
Short name T86
Test name
Test status
Simulation time 1284823400 ps
CPU time 58.13 seconds
Started Aug 27 12:13:01 PM UTC 24
Finished Aug 27 12:14:01 PM UTC 24
Peak memory 275560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799038
031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f
s_sup.2799038031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.1886127666
Short name T129
Test name
Test status
Simulation time 367398709300 ps
CPU time 2764.97 seconds
Started Aug 27 12:08:46 PM UTC 24
Finished Aug 27 12:55:21 PM UTC 24
Peak memory 278344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886127666 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.1886127666
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.3031840221
Short name T57
Test name
Test status
Simulation time 29987700 ps
CPU time 41.56 seconds
Started Aug 27 12:13:27 PM UTC 24
Finished Aug 27 12:14:10 PM UTC 24
Peak memory 287696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303184022
1 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho
st_addr_infection.3031840221
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3519064019
Short name T166
Test name
Test status
Simulation time 17113300 ps
CPU time 27.27 seconds
Started Aug 27 12:13:18 PM UTC 24
Finished Aug 27 12:13:47 PM UTC 24
Peak memory 269264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3519064019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_hw_read_seed_err.3519064019
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1178681704
Short name T76
Test name
Test status
Simulation time 83856080900 ps
CPU time 1794.45 seconds
Started Aug 27 12:08:22 PM UTC 24
Finished Aug 27 12:38:36 PM UTC 24
Peak memory 273852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178681704
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.1178681704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.545438368
Short name T193
Test name
Test status
Simulation time 10319695600 ps
CPU time 626.47 seconds
Started Aug 27 12:11:47 PM UTC 24
Finished Aug 27 12:22:21 PM UTC 24
Peak memory 338936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=545438368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integrity.545438368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.2056740886
Short name T155
Test name
Test status
Simulation time 6105439300 ps
CPU time 170.6 seconds
Started Aug 27 12:12:04 PM UTC 24
Finished Aug 27 12:14:57 PM UTC 24
Peak memory 304052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2056740886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_intr_rd_slow_flash.2056740886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.393008676
Short name T29
Test name
Test status
Simulation time 86784923200 ps
CPU time 259.68 seconds
Started Aug 27 12:12:05 PM UTC 24
Finished Aug 27 12:16:28 PM UTC 24
Peak memory 275384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393008676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.393008676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.2488742792
Short name T66
Test name
Test status
Simulation time 82518700 ps
CPU time 218.98 seconds
Started Aug 27 12:08:26 PM UTC 24
Finished Aug 27 12:12:09 PM UTC 24
Peak memory 275164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488742792 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.2488742792
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.3943718442
Short name T73
Test name
Test status
Simulation time 1609507400 ps
CPU time 644.1 seconds
Started Aug 27 12:08:10 PM UTC 24
Finished Aug 27 12:19:02 PM UTC 24
Peak memory 273284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943718442 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.3943718442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.2666025437
Short name T143
Test name
Test status
Simulation time 2535562600 ps
CPU time 219.75 seconds
Started Aug 27 12:12:10 PM UTC 24
Finished Aug 27 12:15:53 PM UTC 24
Peak memory 275540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666025437 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.2666025437
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.3421488760
Short name T146
Test name
Test status
Simulation time 345438400 ps
CPU time 577.07 seconds
Started Aug 27 12:08:08 PM UTC 24
Finished Aug 27 12:17:52 PM UTC 24
Peak memory 289680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3421488760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3421488760
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.3656352207
Short name T23
Test name
Test status
Simulation time 57148800 ps
CPU time 174.48 seconds
Started Aug 27 12:08:10 PM UTC 24
Finished Aug 27 12:11:08 PM UTC 24
Peak memory 273296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656352207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3656352207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.1624324714
Short name T40
Test name
Test status
Simulation time 147761700 ps
CPU time 49.28 seconds
Started Aug 27 12:12:55 PM UTC 24
Finished Aug 27 12:13:46 PM UTC 24
Peak memory 287756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162432471
4 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.1624324714
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.3442038540
Short name T68
Test name
Test status
Simulation time 88513000 ps
CPU time 62.12 seconds
Started Aug 27 12:13:22 PM UTC 24
Finished Aug 27 12:14:26 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442038540 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.3442038540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.274301734
Short name T28
Test name
Test status
Simulation time 149359500 ps
CPU time 47.13 seconds
Started Aug 27 12:12:24 PM UTC 24
Finished Aug 27 12:13:13 PM UTC 24
Peak memory 287756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274301734 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.274301734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.1573109609
Short name T19
Test name
Test status
Simulation time 47819600 ps
CPU time 28.17 seconds
Started Aug 27 12:09:59 PM UTC 24
Finished Aug 27 12:10:28 PM UTC 24
Peak memory 269428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573109609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.1573109609
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.1073790265
Short name T62
Test name
Test status
Simulation time 72756400 ps
CPU time 36.84 seconds
Started Aug 27 12:11:03 PM UTC 24
Finished Aug 27 12:11:41 PM UTC 24
Peak memory 275468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1073790265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_read_word_sweep_derr.1073790265
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.2034654056
Short name T58
Test name
Test status
Simulation time 82941400 ps
CPU time 40.64 seconds
Started Aug 27 12:10:20 PM UTC 24
Finished Aug 27 12:11:02 PM UTC 24
Peak memory 275732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034654056 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.2034654056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1035617538
Short name T200
Test name
Test status
Simulation time 1489955700 ps
CPU time 206.76 seconds
Started Aug 27 12:11:09 PM UTC 24
Finished Aug 27 12:14:39 PM UTC 24
Peak memory 292024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035617538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.1035617538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2773048251
Short name T39
Test name
Test status
Simulation time 2549204400 ps
CPU time 164.84 seconds
Started Aug 27 12:10:21 PM UTC 24
Finished Aug 27 12:13:09 PM UTC 24
Peak memory 291860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2773048251 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_ro_serr.2773048251
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.3720363152
Short name T214
Test name
Test status
Simulation time 15707047000 ps
CPU time 444.1 seconds
Started Aug 27 12:10:16 PM UTC 24
Finished Aug 27 12:17:46 PM UTC 24
Peak memory 320424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720363152 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.3720363152
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.1912568278
Short name T56
Test name
Test status
Simulation time 886671700 ps
CPU time 163.51 seconds
Started Aug 27 12:11:20 PM UTC 24
Finished Aug 27 12:14:06 PM UTC 24
Peak memory 293884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1912568278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rw_derr.1912568278
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.3121775746
Short name T25
Test name
Test status
Simulation time 83146800 ps
CPU time 51.2 seconds
Started Aug 27 12:12:12 PM UTC 24
Finished Aug 27 12:13:05 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121775746 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.3121775746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3786024428
Short name T31
Test name
Test status
Simulation time 2089021500 ps
CPU time 85.03 seconds
Started Aug 27 12:12:39 PM UTC 24
Finished Aug 27 12:14:06 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786024428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3786024428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.759720734
Short name T63
Test name
Test status
Simulation time 568377700 ps
CPU time 72.45 seconds
Started Aug 27 12:10:57 PM UTC 24
Finished Aug 27 12:12:11 PM UTC 24
Peak memory 275472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759
720734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_serr
_address.759720734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.836414134
Short name T18
Test name
Test status
Simulation time 113856100 ps
CPU time 132.59 seconds
Started Aug 27 12:08:06 PM UTC 24
Finished Aug 27 12:10:21 PM UTC 24
Peak memory 289688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836414134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.836414134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.1603426850
Short name T2
Test name
Test status
Simulation time 28464100 ps
CPU time 37.96 seconds
Started Aug 27 12:08:06 PM UTC 24
Finished Aug 27 12:08:45 PM UTC 24
Peak memory 271048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603426850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1603426850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1372470816
Short name T461
Test name
Test status
Simulation time 867600000 ps
CPU time 1078.56 seconds
Started Aug 27 12:12:45 PM UTC 24
Finished Aug 27 12:30:55 PM UTC 24
Peak memory 291756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372470816 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.1372470816
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.1197420432
Short name T1
Test name
Test status
Simulation time 37915800 ps
CPU time 31.56 seconds
Started Aug 27 12:08:08 PM UTC 24
Finished Aug 27 12:08:41 PM UTC 24
Peak memory 273164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197420432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.1197420432
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.3748340302
Short name T65
Test name
Test status
Simulation time 1669327300 ps
CPU time 159 seconds
Started Aug 27 12:09:22 PM UTC 24
Finished Aug 27 12:12:04 PM UTC 24
Peak memory 275336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3748340302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.3748340302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.4214613944
Short name T17
Test name
Test status
Simulation time 115327900 ps
CPU time 19.61 seconds
Started Aug 27 12:09:55 PM UTC 24
Finished Aug 27 12:10:16 PM UTC 24
Peak memory 269172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4214613944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.4214613944
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.378376031
Short name T22
Test name
Test status
Simulation time 27281600 ps
CPU time 16.21 seconds
Started Aug 27 12:17:52 PM UTC 24
Finished Aug 27 12:18:09 PM UTC 24
Peak memory 273512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=378376031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.378376031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.3740898538
Short name T97
Test name
Test status
Simulation time 114424300 ps
CPU time 17.26 seconds
Started Aug 27 12:18:32 PM UTC 24
Finished Aug 27 12:18:51 PM UTC 24
Peak memory 269324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740898538 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.3740898538
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.381633341
Short name T311
Test name
Test status
Simulation time 47087300 ps
CPU time 19.05 seconds
Started Aug 27 12:18:11 PM UTC 24
Finished Aug 27 12:18:31 PM UTC 24
Peak memory 273240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381633341 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.381633341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.1085726504
Short name T5
Test name
Test status
Simulation time 15261800 ps
CPU time 28.13 seconds
Started Aug 27 12:17:40 PM UTC 24
Finished Aug 27 12:18:09 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085726504 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1085726504
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.2503895162
Short name T74
Test name
Test status
Simulation time 5609912500 ps
CPU time 523.27 seconds
Started Aug 27 12:14:02 PM UTC 24
Finished Aug 27 12:22:51 PM UTC 24
Peak memory 275276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503895162 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.2503895162
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.2279050315
Short name T289
Test name
Test status
Simulation time 10404066000 ps
CPU time 3066.68 seconds
Started Aug 27 12:14:40 PM UTC 24
Finished Aug 27 01:06:22 PM UTC 24
Peak memory 276188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279050315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.2279050315
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.2190516655
Short name T292
Test name
Test status
Simulation time 1424467100 ps
CPU time 1165.26 seconds
Started Aug 27 12:14:39 PM UTC 24
Finished Aug 27 12:34:18 PM UTC 24
Peak memory 283476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190516655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2190516655
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.2265264493
Short name T277
Test name
Test status
Simulation time 1356970100 ps
CPU time 39.52 seconds
Started Aug 27 12:17:52 PM UTC 24
Finished Aug 27 12:18:33 PM UTC 24
Peak memory 273360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2265264
493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f
s_sup.2265264493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2802530174
Short name T305
Test name
Test status
Simulation time 27891000 ps
CPU time 33.06 seconds
Started Aug 27 12:18:32 PM UTC 24
Finished Aug 27 12:19:07 PM UTC 24
Peak memory 285552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280253017
4 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho
st_addr_infection.2802530174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.998593369
Short name T562
Test name
Test status
Simulation time 358993655100 ps
CPU time 2600.99 seconds
Started Aug 27 12:14:18 PM UTC 24
Finished Aug 27 12:58:06 PM UTC 24
Peak memory 278260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998593369 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.998593369
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.1565354803
Short name T157
Test name
Test status
Simulation time 199741400 ps
CPU time 125.62 seconds
Started Aug 27 12:13:46 PM UTC 24
Finished Aug 27 12:15:54 PM UTC 24
Peak memory 275336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565354803 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.1565354803
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2019859505
Short name T80
Test name
Test status
Simulation time 84597640600 ps
CPU time 1719.72 seconds
Started Aug 27 12:14:07 PM UTC 24
Finished Aug 27 12:43:05 PM UTC 24
Peak memory 277612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2019859505
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.2019859505
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.3926795712
Short name T46
Test name
Test status
Simulation time 1770449500 ps
CPU time 55.54 seconds
Started Aug 27 12:13:52 PM UTC 24
Finished Aug 27 12:14:49 PM UTC 24
Peak memory 275408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926795712 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.3926795712
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.1679833070
Short name T442
Test name
Test status
Simulation time 4174609600 ps
CPU time 502.04 seconds
Started Aug 27 12:16:19 PM UTC 24
Finished Aug 27 12:24:46 PM UTC 24
Peak memory 345084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1679833070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr
ity.1679833070
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.3679737389
Short name T30
Test name
Test status
Simulation time 8162573600 ps
CPU time 71.9 seconds
Started Aug 27 12:16:29 PM UTC 24
Finished Aug 27 12:17:42 PM UTC 24
Peak memory 275320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3679737389 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.3679737389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.951846681
Short name T163
Test name
Test status
Simulation time 21753917200 ps
CPU time 207.72 seconds
Started Aug 27 12:16:30 PM UTC 24
Finished Aug 27 12:20:01 PM UTC 24
Peak memory 271308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=951846681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.951846681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.1402103692
Short name T145
Test name
Test status
Simulation time 1944129500 ps
CPU time 90.42 seconds
Started Aug 27 12:14:40 PM UTC 24
Finished Aug 27 12:16:13 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1402103692 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.1402103692
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.1645688080
Short name T173
Test name
Test status
Simulation time 25083800 ps
CPU time 25.38 seconds
Started Aug 27 12:18:11 PM UTC 24
Finished Aug 27 12:18:38 PM UTC 24
Peak memory 271396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1645688080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_lcmgr_intg.1645688080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.3912012969
Short name T113
Test name
Test status
Simulation time 245281300 ps
CPU time 202.69 seconds
Started Aug 27 12:14:11 PM UTC 24
Finished Aug 27 12:17:37 PM UTC 24
Peak memory 271588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912012969 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.3912012969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3277769005
Short name T202
Test name
Test status
Simulation time 1270073100 ps
CPU time 202.01 seconds
Started Aug 27 12:16:14 PM UTC 24
Finished Aug 27 12:19:40 PM UTC 24
Peak memory 306380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3277769005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_oversize_error.3277769005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.1357284755
Short name T231
Test name
Test status
Simulation time 33518900 ps
CPU time 22.62 seconds
Started Aug 27 12:18:09 PM UTC 24
Finished Aug 27 12:18:34 PM UTC 24
Peak memory 275612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357284755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.1357284755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.1997401817
Short name T236
Test name
Test status
Simulation time 1652899800 ps
CPU time 816.88 seconds
Started Aug 27 12:13:52 PM UTC 24
Finished Aug 27 12:27:38 PM UTC 24
Peak memory 275464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997401817 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.1997401817
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.806802067
Short name T165
Test name
Test status
Simulation time 42876200 ps
CPU time 24.31 seconds
Started Aug 27 12:17:53 PM UTC 24
Finished Aug 27 12:18:19 PM UTC 24
Peak memory 273520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=806802067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.806802067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.2071142088
Short name T383
Test name
Test status
Simulation time 39232826500 ps
CPU time 202.41 seconds
Started Aug 27 12:16:37 PM UTC 24
Finished Aug 27 12:20:03 PM UTC 24
Peak memory 271412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071142088 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.2071142088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.563611422
Short name T149
Test name
Test status
Simulation time 3151043000 ps
CPU time 1006.42 seconds
Started Aug 27 12:13:39 PM UTC 24
Finished Aug 27 12:30:36 PM UTC 24
Peak memory 295824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563611422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.563611422
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.4019904694
Short name T233
Test name
Test status
Simulation time 294193100 ps
CPU time 158.65 seconds
Started Aug 27 12:13:47 PM UTC 24
Finished Aug 27 12:16:29 PM UTC 24
Peak memory 273292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4019904694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.4019904694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1032448717
Short name T349
Test name
Test status
Simulation time 211660400 ps
CPU time 45.65 seconds
Started Aug 27 12:17:44 PM UTC 24
Finished Aug 27 12:18:31 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=103244871
7 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.1032448717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.3566466483
Short name T159
Test name
Test status
Simulation time 187246400 ps
CPU time 35.2 seconds
Started Aug 27 12:16:53 PM UTC 24
Finished Aug 27 12:17:30 PM UTC 24
Peak memory 283632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3566466483 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.3566466483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.3896389965
Short name T239
Test name
Test status
Simulation time 52514600 ps
CPU time 31.12 seconds
Started Aug 27 12:15:53 PM UTC 24
Finished Aug 27 12:16:26 PM UTC 24
Peak memory 275640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3896389965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_read_word_sweep_derr.3896389965
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.2755101889
Short name T158
Test name
Test status
Simulation time 187916300 ps
CPU time 45.46 seconds
Started Aug 27 12:15:07 PM UTC 24
Finished Aug 27 12:15:54 PM UTC 24
Peak memory 275448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755101889 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.2755101889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2102327673
Short name T83
Test name
Test status
Simulation time 82158753900 ps
CPU time 878.66 seconds
Started Aug 27 12:18:11 PM UTC 24
Finished Aug 27 12:32:59 PM UTC 24
Peak memory 273104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2102327673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.
flash_ctrl_rma_err.2102327673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.1415115209
Short name T215
Test name
Test status
Simulation time 706278100 ps
CPU time 186.28 seconds
Started Aug 27 12:15:55 PM UTC 24
Finished Aug 27 12:19:04 PM UTC 24
Peak memory 291852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415115209 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.1415115209
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.1306108007
Short name T101
Test name
Test status
Simulation time 1750804300 ps
CPU time 157.25 seconds
Started Aug 27 12:15:10 PM UTC 24
Finished Aug 27 12:17:50 PM UTC 24
Peak memory 306368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1306108007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_ro_serr.1306108007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.846854442
Short name T196
Test name
Test status
Simulation time 4736442200 ps
CPU time 468.81 seconds
Started Aug 27 12:14:58 PM UTC 24
Finished Aug 27 12:22:53 PM UTC 24
Peak memory 324856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846854442 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.846854442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.4003700778
Short name T27
Test name
Test status
Simulation time 32178800 ps
CPU time 44.55 seconds
Started Aug 27 12:16:50 PM UTC 24
Finished Aug 27 12:17:36 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4003700778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw_evict_all_en.4003700778
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.706437348
Short name T245
Test name
Test status
Simulation time 2131409300 ps
CPU time 194.56 seconds
Started Aug 27 12:15:15 PM UTC 24
Finished Aug 27 12:18:32 PM UTC 24
Peak memory 291860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=706437348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.706437348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3653068161
Short name T44
Test name
Test status
Simulation time 3785417500 ps
CPU time 7193.96 seconds
Started Aug 27 12:17:30 PM UTC 24
Finished Aug 27 02:18:40 PM UTC 24
Peak memory 314416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653068161 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.3653068161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.3929610476
Short name T240
Test name
Test status
Simulation time 1395153400 ps
CPU time 71.96 seconds
Started Aug 27 12:15:38 PM UTC 24
Finished Aug 27 12:16:52 PM UTC 24
Peak memory 275644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=392
9610476 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser
r_address.3929610476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.3910546414
Short name T144
Test name
Test status
Simulation time 1134748100 ps
CPU time 63.07 seconds
Started Aug 27 12:15:31 PM UTC 24
Finished Aug 27 12:16:36 PM UTC 24
Peak memory 275640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39
10546414 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se
rr_counter.3910546414
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.1828161159
Short name T156
Test name
Test status
Simulation time 297757900 ps
CPU time 91.63 seconds
Started Aug 27 12:13:36 PM UTC 24
Finished Aug 27 12:15:09 PM UTC 24
Peak memory 287640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828161159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.1828161159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3859385983
Short name T67
Test name
Test status
Simulation time 14750400 ps
CPU time 39.16 seconds
Started Aug 27 12:13:37 PM UTC 24
Finished Aug 27 12:14:18 PM UTC 24
Peak memory 271052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859385983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3859385983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.191224610
Short name T519
Test name
Test status
Simulation time 2737953200 ps
CPU time 1901.4 seconds
Started Aug 27 12:17:38 PM UTC 24
Finished Aug 27 12:49:38 PM UTC 24
Peak memory 304676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=191224610 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.191224610
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.28717073
Short name T302
Test name
Test status
Simulation time 127958800 ps
CPU time 43.44 seconds
Started Aug 27 12:13:46 PM UTC 24
Finished Aug 27 12:14:31 PM UTC 24
Peak memory 273092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28717073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.28717073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.3705769587
Short name T443
Test name
Test status
Simulation time 6208896100 ps
CPU time 196.15 seconds
Started Aug 27 12:14:50 PM UTC 24
Finished Aug 27 12:18:09 PM UTC 24
Peak memory 275316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3705769587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.3705769587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.3792458040
Short name T21
Test name
Test status
Simulation time 156619600 ps
CPU time 22.3 seconds
Started Aug 27 12:17:47 PM UTC 24
Finished Aug 27 12:18:10 PM UTC 24
Peak memory 271376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3792458040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_wr_intg.3792458040
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.2099324895
Short name T609
Test name
Test status
Simulation time 170468400 ps
CPU time 26.2 seconds
Started Aug 27 01:04:15 PM UTC 24
Finished Aug 27 01:04:42 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099324895 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.2099324895
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.1041725572
Short name T605
Test name
Test status
Simulation time 26532100 ps
CPU time 28.65 seconds
Started Aug 27 01:03:51 PM UTC 24
Finished Aug 27 01:04:21 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1041725572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1041725572
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.2915078254
Short name T411
Test name
Test status
Simulation time 31609600 ps
CPU time 38.11 seconds
Started Aug 27 01:03:38 PM UTC 24
Finished Aug 27 01:04:17 PM UTC 24
Peak memory 285720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2915078254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_
ctrl_disable.2915078254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1641514515
Short name T619
Test name
Test status
Simulation time 10034545000 ps
CPU time 115.35 seconds
Started Aug 27 01:03:55 PM UTC 24
Finished Aug 27 01:05:52 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1641514515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1641514515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.2754502350
Short name T327
Test name
Test status
Simulation time 15344800 ps
CPU time 23.27 seconds
Started Aug 27 01:03:53 PM UTC 24
Finished Aug 27 01:04:18 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2754502350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_hw_read_seed_err.2754502350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.3107442551
Short name T705
Test name
Test status
Simulation time 160170561400 ps
CPU time 835.78 seconds
Started Aug 27 01:01:59 PM UTC 24
Finished Aug 27 01:16:04 PM UTC 24
Peak memory 275164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107442551
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_res
et.3107442551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1408527943
Short name T618
Test name
Test status
Simulation time 32676645300 ps
CPU time 165.84 seconds
Started Aug 27 01:02:57 PM UTC 24
Finished Aug 27 01:05:46 PM UTC 24
Peak memory 304040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1408527943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_intr_rd_slow_flash.1408527943
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.4055104181
Short name T602
Test name
Test status
Simulation time 32508105700 ps
CPU time 105.66 seconds
Started Aug 27 01:02:06 PM UTC 24
Finished Aug 27 01:03:53 PM UTC 24
Peak memory 271176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055104181 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.4055104181
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.1570675068
Short name T606
Test name
Test status
Simulation time 25844200 ps
CPU time 27.98 seconds
Started Aug 27 01:03:52 PM UTC 24
Finished Aug 27 01:04:21 PM UTC 24
Peak memory 271368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1570675068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_lcmgr_intg.1570675068
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2664409962
Short name T614
Test name
Test status
Simulation time 10773778900 ps
CPU time 182.67 seconds
Started Aug 27 01:02:03 PM UTC 24
Finished Aug 27 01:05:09 PM UTC 24
Peak memory 275332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2664409962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.flash_ctrl_mp_regions.2664409962
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.3906498784
Short name T607
Test name
Test status
Simulation time 245563600 ps
CPU time 144.48 seconds
Started Aug 27 01:02:02 PM UTC 24
Finished Aug 27 01:04:29 PM UTC 24
Peak memory 271284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906498784 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.3906498784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.4189614334
Short name T637
Test name
Test status
Simulation time 59320700 ps
CPU time 374.88 seconds
Started Aug 27 01:01:48 PM UTC 24
Finished Aug 27 01:08:08 PM UTC 24
Peak memory 275532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189614334 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.4189614334
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.914851694
Short name T599
Test name
Test status
Simulation time 59364100 ps
CPU time 24.27 seconds
Started Aug 27 01:03:08 PM UTC 24
Finished Aug 27 01:03:34 PM UTC 24
Peak memory 271224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914851694 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.914851694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.3535474625
Short name T626
Test name
Test status
Simulation time 296726700 ps
CPU time 262.28 seconds
Started Aug 27 01:01:47 PM UTC 24
Finished Aug 27 01:06:13 PM UTC 24
Peak memory 291924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535474625 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.3535474625
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.3181331511
Short name T610
Test name
Test status
Simulation time 151054100 ps
CPU time 68.06 seconds
Started Aug 27 01:03:35 PM UTC 24
Finished Aug 27 01:04:44 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181331511 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.3181331511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.1442995524
Short name T608
Test name
Test status
Simulation time 506577800 ps
CPU time 127.06 seconds
Started Aug 27 01:02:23 PM UTC 24
Finished Aug 27 01:04:32 PM UTC 24
Peak memory 291892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1442995524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.1442995524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.1335725293
Short name T656
Test name
Test status
Simulation time 5947830300 ps
CPU time 419.21 seconds
Started Aug 27 01:02:47 PM UTC 24
Finished Aug 27 01:09:52 PM UTC 24
Peak memory 320528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335725293 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.1335725293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3647677874
Short name T604
Test name
Test status
Simulation time 72152800 ps
CPU time 38.81 seconds
Started Aug 27 01:03:35 PM UTC 24
Finished Aug 27 01:04:15 PM UTC 24
Peak memory 281584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3647677874 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw_evict_all_en.3647677874
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.1083393886
Short name T631
Test name
Test status
Simulation time 37956500 ps
CPU time 301.41 seconds
Started Aug 27 01:01:43 PM UTC 24
Finished Aug 27 01:06:48 PM UTC 24
Peak memory 289676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083393886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.1083393886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.848768691
Short name T612
Test name
Test status
Simulation time 2404800400 ps
CPU time 147.98 seconds
Started Aug 27 01:02:20 PM UTC 24
Finished Aug 27 01:04:50 PM UTC 24
Peak memory 271220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=848768691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.848768691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.3296970968
Short name T630
Test name
Test status
Simulation time 78935300 ps
CPU time 22.79 seconds
Started Aug 27 01:06:04 PM UTC 24
Finished Aug 27 01:06:28 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296970968 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.3296970968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.1103581544
Short name T624
Test name
Test status
Simulation time 14988500 ps
CPU time 25.17 seconds
Started Aug 27 01:05:43 PM UTC 24
Finished Aug 27 01:06:10 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103581544 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.1103581544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.26779415
Short name T387
Test name
Test status
Simulation time 13299400 ps
CPU time 36.06 seconds
Started Aug 27 01:05:31 PM UTC 24
Finished Aug 27 01:06:09 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=26779415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ct
rl_disable.26779415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.4281460275
Short name T646
Test name
Test status
Simulation time 10019396200 ps
CPU time 166.01 seconds
Started Aug 27 01:05:53 PM UTC 24
Finished Aug 27 01:08:41 PM UTC 24
Peak memory 299964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4281460275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.4281460275
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.2922754908
Short name T735
Test name
Test status
Simulation time 40129092600 ps
CPU time 891.76 seconds
Started Aug 27 01:04:22 PM UTC 24
Finished Aug 27 01:19:24 PM UTC 24
Peak memory 273116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922754908
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res
et.2922754908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1999105976
Short name T622
Test name
Test status
Simulation time 1364645100 ps
CPU time 106.82 seconds
Started Aug 27 01:04:19 PM UTC 24
Finished Aug 27 01:06:08 PM UTC 24
Peak memory 273160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999105976 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.1999105976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.2755134658
Short name T636
Test name
Test status
Simulation time 1905967500 ps
CPU time 185.8 seconds
Started Aug 27 01:04:50 PM UTC 24
Finished Aug 27 01:07:59 PM UTC 24
Peak memory 302076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755134658 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.2755134658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.859093357
Short name T627
Test name
Test status
Simulation time 4035345300 ps
CPU time 108.07 seconds
Started Aug 27 01:04:30 PM UTC 24
Finished Aug 27 01:06:20 PM UTC 24
Peak memory 271116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859093357 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.859093357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.4117602510
Short name T152
Test name
Test status
Simulation time 10042357200 ps
CPU time 293.64 seconds
Started Aug 27 01:04:26 PM UTC 24
Finished Aug 27 01:09:24 PM UTC 24
Peak memory 283528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4117602510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_mp_regions.4117602510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3113626571
Short name T186
Test name
Test status
Simulation time 151411400 ps
CPU time 157.85 seconds
Started Aug 27 01:04:22 PM UTC 24
Finished Aug 27 01:07:03 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113626571 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.3113626571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.1112548494
Short name T668
Test name
Test status
Simulation time 167445100 ps
CPU time 431.77 seconds
Started Aug 27 01:04:18 PM UTC 24
Finished Aug 27 01:11:35 PM UTC 24
Peak memory 275336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112548494 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.1112548494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.1729454266
Short name T617
Test name
Test status
Simulation time 503507800 ps
CPU time 48.72 seconds
Started Aug 27 01:04:53 PM UTC 24
Finished Aug 27 01:05:43 PM UTC 24
Peak memory 275308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729454266 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.1729454266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1290396164
Short name T795
Test name
Test status
Simulation time 840618100 ps
CPU time 1214.81 seconds
Started Aug 27 01:04:16 PM UTC 24
Finished Aug 27 01:24:43 PM UTC 24
Peak memory 293776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290396164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1290396164
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3073431815
Short name T628
Test name
Test status
Simulation time 75445300 ps
CPU time 57.49 seconds
Started Aug 27 01:05:24 PM UTC 24
Finished Aug 27 01:06:23 PM UTC 24
Peak memory 287760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073431815 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.3073431815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.918074555
Short name T620
Test name
Test status
Simulation time 5432891900 ps
CPU time 78.91 seconds
Started Aug 27 01:04:43 PM UTC 24
Finished Aug 27 01:06:03 PM UTC 24
Peak memory 304188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=918074555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.918074555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.1475629699
Short name T684
Test name
Test status
Simulation time 8030759400 ps
CPU time 533.26 seconds
Started Aug 27 01:04:45 PM UTC 24
Finished Aug 27 01:13:45 PM UTC 24
Peak memory 320464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475629699 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.1475629699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1537745674
Short name T441
Test name
Test status
Simulation time 28865900 ps
CPU time 31.23 seconds
Started Aug 27 01:05:10 PM UTC 24
Finished Aug 27 01:05:43 PM UTC 24
Peak memory 287956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537745674 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.1537745674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.2706744830
Short name T621
Test name
Test status
Simulation time 27109000 ps
CPU time 44.22 seconds
Started Aug 27 01:05:22 PM UTC 24
Finished Aug 27 01:06:08 PM UTC 24
Peak memory 285904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2706744830 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw_evict_all_en.2706744830
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.1382494870
Short name T616
Test name
Test status
Simulation time 28190500 ps
CPU time 72.54 seconds
Started Aug 27 01:04:16 PM UTC 24
Finished Aug 27 01:05:30 PM UTC 24
Peak memory 283796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382494870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.1382494870
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.1461221761
Short name T633
Test name
Test status
Simulation time 3295415100 ps
CPU time 172.09 seconds
Started Aug 27 01:04:33 PM UTC 24
Finished Aug 27 01:07:28 PM UTC 24
Peak memory 275316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1461221761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.1461221761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.2042012147
Short name T647
Test name
Test status
Simulation time 66671800 ps
CPU time 29.65 seconds
Started Aug 27 01:08:12 PM UTC 24
Finished Aug 27 01:08:43 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042012147 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.2042012147
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1784266578
Short name T643
Test name
Test status
Simulation time 120895500 ps
CPU time 31.95 seconds
Started Aug 27 01:07:55 PM UTC 24
Finished Aug 27 01:08:28 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784266578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.1784266578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.3249018431
Short name T639
Test name
Test status
Simulation time 39066900 ps
CPU time 31.82 seconds
Started Aug 27 01:07:37 PM UTC 24
Finished Aug 27 01:08:11 PM UTC 24
Peak memory 275484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3249018431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_
ctrl_disable.3249018431
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2822335076
Short name T678
Test name
Test status
Simulation time 10012444100 ps
CPU time 274.43 seconds
Started Aug 27 01:08:09 PM UTC 24
Finished Aug 27 01:12:47 PM UTC 24
Peak memory 332924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2822335076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.2822335076
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1864010562
Short name T644
Test name
Test status
Simulation time 91652200 ps
CPU time 23.43 seconds
Started Aug 27 01:08:09 PM UTC 24
Finished Aug 27 01:08:33 PM UTC 24
Peak memory 275408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1864010562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
12.flash_ctrl_hw_read_seed_err.1864010562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.2959807968
Short name T176
Test name
Test status
Simulation time 80141227400 ps
CPU time 746.45 seconds
Started Aug 27 01:06:11 PM UTC 24
Finished Aug 27 01:18:46 PM UTC 24
Peak memory 275364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959807968
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_res
et.2959807968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.1100751170
Short name T313
Test name
Test status
Simulation time 12725474200 ps
CPU time 84.59 seconds
Started Aug 27 01:06:10 PM UTC 24
Finished Aug 27 01:07:37 PM UTC 24
Peak memory 273160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100751170 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.1100751170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3230507788
Short name T36
Test name
Test status
Simulation time 3023264000 ps
CPU time 178.6 seconds
Started Aug 27 01:06:28 PM UTC 24
Finished Aug 27 01:09:30 PM UTC 24
Peak memory 306164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230507788 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.3230507788
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.74329777
Short name T650
Test name
Test status
Simulation time 8831015500 ps
CPU time 135.58 seconds
Started Aug 27 01:06:42 PM UTC 24
Finished Aug 27 01:09:00 PM UTC 24
Peak memory 304240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=74329777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 12.flash_ctrl_intr_rd_slow_flash.74329777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.2570598681
Short name T634
Test name
Test status
Simulation time 1666537800 ps
CPU time 86.73 seconds
Started Aug 27 01:06:21 PM UTC 24
Finished Aug 27 01:07:50 PM UTC 24
Peak memory 271308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570598681 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.2570598681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.2667375691
Short name T133
Test name
Test status
Simulation time 34512069900 ps
CPU time 489.77 seconds
Started Aug 27 01:06:14 PM UTC 24
Finished Aug 27 01:14:30 PM UTC 24
Peak memory 283528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2667375691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.flash_ctrl_mp_regions.2667375691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1740318525
Short name T78
Test name
Test status
Simulation time 75194100 ps
CPU time 185.69 seconds
Started Aug 27 01:06:13 PM UTC 24
Finished Aug 27 01:09:21 PM UTC 24
Peak memory 271592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740318525 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.1740318525
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.1357849889
Short name T720
Test name
Test status
Simulation time 9187105800 ps
CPU time 692.64 seconds
Started Aug 27 01:06:09 PM UTC 24
Finished Aug 27 01:17:50 PM UTC 24
Peak memory 275344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1357849889 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.1357849889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.397458972
Short name T632
Test name
Test status
Simulation time 828178400 ps
CPU time 36.19 seconds
Started Aug 27 01:06:50 PM UTC 24
Finished Aug 27 01:07:27 PM UTC 24
Peak memory 275512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397458972 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.397458972
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.2729815685
Short name T820
Test name
Test status
Simulation time 852518900 ps
CPU time 1189.3 seconds
Started Aug 27 01:06:09 PM UTC 24
Finished Aug 27 01:26:12 PM UTC 24
Peak memory 297872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729815685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.2729815685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2672999301
Short name T642
Test name
Test status
Simulation time 47192500 ps
CPU time 55.24 seconds
Started Aug 27 01:07:29 PM UTC 24
Finished Aug 27 01:08:26 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672999301 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.2672999301
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.2610163144
Short name T645
Test name
Test status
Simulation time 1064536700 ps
CPU time 134.59 seconds
Started Aug 27 01:06:24 PM UTC 24
Finished Aug 27 01:08:41 PM UTC 24
Peak memory 291788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2610163144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.2610163144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.3475497243
Short name T685
Test name
Test status
Simulation time 7107475300 ps
CPU time 436.47 seconds
Started Aug 27 01:06:27 PM UTC 24
Finished Aug 27 01:13:49 PM UTC 24
Peak memory 330888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475497243 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.3475497243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1856645573
Short name T635
Test name
Test status
Simulation time 74195400 ps
CPU time 48.3 seconds
Started Aug 27 01:07:04 PM UTC 24
Finished Aug 27 01:07:54 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856645573 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.1856645573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.3028849532
Short name T640
Test name
Test status
Simulation time 41979300 ps
CPU time 55.11 seconds
Started Aug 27 01:07:28 PM UTC 24
Finished Aug 27 01:08:25 PM UTC 24
Peak memory 287924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3028849532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw_evict_all_en.3028849532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.2024367082
Short name T651
Test name
Test status
Simulation time 374576500 ps
CPU time 89.12 seconds
Started Aug 27 01:07:50 PM UTC 24
Finished Aug 27 01:09:22 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024367082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.2024367082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.1069753031
Short name T649
Test name
Test status
Simulation time 36911600 ps
CPU time 157.22 seconds
Started Aug 27 01:06:08 PM UTC 24
Finished Aug 27 01:08:48 PM UTC 24
Peak memory 287636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069753031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1069753031
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.3345699498
Short name T654
Test name
Test status
Simulation time 9196788900 ps
CPU time 199.58 seconds
Started Aug 27 01:06:23 PM UTC 24
Finished Aug 27 01:09:46 PM UTC 24
Peak memory 275316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3345699498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.3345699498
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.4121143483
Short name T663
Test name
Test status
Simulation time 129784000 ps
CPU time 26.25 seconds
Started Aug 27 01:10:05 PM UTC 24
Finished Aug 27 01:10:33 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121143483 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.4121143483
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.853228758
Short name T659
Test name
Test status
Simulation time 22990500 ps
CPU time 32.7 seconds
Started Aug 27 01:09:36 PM UTC 24
Finished Aug 27 01:10:10 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=853228758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.853228758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.4212956462
Short name T661
Test name
Test status
Simulation time 26902000 ps
CPU time 44.47 seconds
Started Aug 27 01:09:31 PM UTC 24
Finished Aug 27 01:10:17 PM UTC 24
Peak memory 285652 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4212956462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_
ctrl_disable.4212956462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2909293137
Short name T670
Test name
Test status
Simulation time 10034060300 ps
CPU time 107.21 seconds
Started Aug 27 01:09:53 PM UTC 24
Finished Aug 27 01:11:42 PM UTC 24
Peak memory 281532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2909293137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2909293137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.4185066233
Short name T657
Test name
Test status
Simulation time 46189100 ps
CPU time 16.34 seconds
Started Aug 27 01:09:47 PM UTC 24
Finished Aug 27 01:10:04 PM UTC 24
Peak memory 269480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4185066233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_hw_read_seed_err.4185066233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.1724898074
Short name T775
Test name
Test status
Simulation time 40125465000 ps
CPU time 854.83 seconds
Started Aug 27 01:08:31 PM UTC 24
Finished Aug 27 01:22:55 PM UTC 24
Peak memory 275180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724898074
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res
et.1724898074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.1676084232
Short name T652
Test name
Test status
Simulation time 3227418100 ps
CPU time 55.2 seconds
Started Aug 27 01:08:28 PM UTC 24
Finished Aug 27 01:09:25 PM UTC 24
Peak memory 275404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676084232 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.1676084232
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.2209500729
Short name T338
Test name
Test status
Simulation time 1589776900 ps
CPU time 258.53 seconds
Started Aug 27 01:08:50 PM UTC 24
Finished Aug 27 01:13:13 PM UTC 24
Peak memory 293876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2209500729 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.2209500729
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3388809616
Short name T666
Test name
Test status
Simulation time 15003232100 ps
CPU time 135.78 seconds
Started Aug 27 01:09:02 PM UTC 24
Finished Aug 27 01:11:20 PM UTC 24
Peak memory 304048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3388809616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_intr_rd_slow_flash.3388809616
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.32209439
Short name T660
Test name
Test status
Simulation time 15452100 ps
CPU time 23.04 seconds
Started Aug 27 01:09:47 PM UTC 24
Finished Aug 27 01:10:11 PM UTC 24
Peak memory 271436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=32209439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash
_ctrl_lcmgr_intg.32209439
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.4045488939
Short name T802
Test name
Test status
Simulation time 31307198200 ps
CPU time 969.74 seconds
Started Aug 27 01:08:42 PM UTC 24
Finished Aug 27 01:25:02 PM UTC 24
Peak memory 283592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4045488939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_mp_regions.4045488939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.1280306403
Short name T79
Test name
Test status
Simulation time 123756900 ps
CPU time 154.21 seconds
Started Aug 27 01:08:35 PM UTC 24
Finished Aug 27 01:11:11 PM UTC 24
Peak memory 275492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280306403 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.1280306403
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.738330312
Short name T745
Test name
Test status
Simulation time 2954183400 ps
CPU time 701.82 seconds
Started Aug 27 01:08:27 PM UTC 24
Finished Aug 27 01:20:18 PM UTC 24
Peak memory 275540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738330312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.738330312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.1860709974
Short name T655
Test name
Test status
Simulation time 232131900 ps
CPU time 21.58 seconds
Started Aug 27 01:09:23 PM UTC 24
Finished Aug 27 01:09:46 PM UTC 24
Peak memory 271332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1860709974 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.1860709974
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3749274673
Short name T843
Test name
Test status
Simulation time 780363300 ps
CPU time 1132.7 seconds
Started Aug 27 01:08:26 PM UTC 24
Finished Aug 27 01:27:31 PM UTC 24
Peak memory 293780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749274673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3749274673
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.2719253042
Short name T431
Test name
Test status
Simulation time 247322000 ps
CPU time 57.26 seconds
Started Aug 27 01:09:26 PM UTC 24
Finished Aug 27 01:10:25 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719253042 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.2719253042
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.549459636
Short name T710
Test name
Test status
Simulation time 38311390700 ps
CPU time 451.45 seconds
Started Aug 27 01:08:49 PM UTC 24
Finished Aug 27 01:16:26 PM UTC 24
Peak memory 322416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549459636 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.549459636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3301182309
Short name T658
Test name
Test status
Simulation time 95741900 ps
CPU time 40.63 seconds
Started Aug 27 01:09:23 PM UTC 24
Finished Aug 27 01:10:05 PM UTC 24
Peak memory 287664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301182309 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.3301182309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.2932269408
Short name T662
Test name
Test status
Simulation time 245045300 ps
CPU time 52.19 seconds
Started Aug 27 01:09:26 PM UTC 24
Finished Aug 27 01:10:20 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2932269408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw_evict_all_en.2932269408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2058357576
Short name T665
Test name
Test status
Simulation time 1730539400 ps
CPU time 67.17 seconds
Started Aug 27 01:09:34 PM UTC 24
Finished Aug 27 01:10:43 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2058357576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.2058357576
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.2208730768
Short name T664
Test name
Test status
Simulation time 20625900 ps
CPU time 132.26 seconds
Started Aug 27 01:08:26 PM UTC 24
Finished Aug 27 01:10:41 PM UTC 24
Peak memory 287636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208730768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2208730768
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.4249925645
Short name T672
Test name
Test status
Simulation time 25246162400 ps
CPU time 190.35 seconds
Started Aug 27 01:08:44 PM UTC 24
Finished Aug 27 01:11:58 PM UTC 24
Peak memory 271212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4249925645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.4249925645
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.516200001
Short name T679
Test name
Test status
Simulation time 85214900 ps
CPU time 22.35 seconds
Started Aug 27 01:12:25 PM UTC 24
Finished Aug 27 01:12:48 PM UTC 24
Peak memory 275644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516200001 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.516200001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.1096985575
Short name T676
Test name
Test status
Simulation time 32051600 ps
CPU time 27.46 seconds
Started Aug 27 01:12:00 PM UTC 24
Finished Aug 27 01:12:28 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096985575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.1096985575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.754665056
Short name T680
Test name
Test status
Simulation time 47145800 ps
CPU time 26.66 seconds
Started Aug 27 01:12:21 PM UTC 24
Finished Aug 27 01:12:49 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=754665056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.flash_ctrl_hw_read_seed_err.754665056
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.3096861071
Short name T810
Test name
Test status
Simulation time 40127277400 ps
CPU time 886.81 seconds
Started Aug 27 01:10:18 PM UTC 24
Finished Aug 27 01:25:15 PM UTC 24
Peak memory 275356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096861071
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_res
et.3096861071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.4185304269
Short name T324
Test name
Test status
Simulation time 3662237200 ps
CPU time 136.61 seconds
Started Aug 27 01:10:12 PM UTC 24
Finished Aug 27 01:12:31 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185304269 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.4185304269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.4184412214
Short name T348
Test name
Test status
Simulation time 1735879800 ps
CPU time 121.89 seconds
Started Aug 27 01:11:12 PM UTC 24
Finished Aug 27 01:13:16 PM UTC 24
Peak memory 302076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184412214 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.4184412214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.35224417
Short name T696
Test name
Test status
Simulation time 32326180900 ps
CPU time 197.45 seconds
Started Aug 27 01:11:21 PM UTC 24
Finished Aug 27 01:14:42 PM UTC 24
Peak memory 304036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=35224417 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 14.flash_ctrl_intr_rd_slow_flash.35224417
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.689422226
Short name T674
Test name
Test status
Simulation time 3111670600 ps
CPU time 115.55 seconds
Started Aug 27 01:10:25 PM UTC 24
Finished Aug 27 01:12:24 PM UTC 24
Peak memory 271124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689422226 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.689422226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.1006144318
Short name T677
Test name
Test status
Simulation time 15615100 ps
CPU time 15.7 seconds
Started Aug 27 01:12:18 PM UTC 24
Finished Aug 27 01:12:35 PM UTC 24
Peak memory 271564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1006144318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_lcmgr_intg.1006144318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.1278353591
Short name T699
Test name
Test status
Simulation time 12842288100 ps
CPU time 288.83 seconds
Started Aug 27 01:10:24 PM UTC 24
Finished Aug 27 01:15:17 PM UTC 24
Peak memory 283720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1278353591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_mp_regions.1278353591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.1766365482
Short name T686
Test name
Test status
Simulation time 36217700 ps
CPU time 216.23 seconds
Started Aug 27 01:10:21 PM UTC 24
Finished Aug 27 01:14:01 PM UTC 24
Peak memory 271076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766365482 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.1766365482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.2869985120
Short name T744
Test name
Test status
Simulation time 4059343800 ps
CPU time 596.45 seconds
Started Aug 27 01:10:12 PM UTC 24
Finished Aug 27 01:20:15 PM UTC 24
Peak memory 275340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869985120 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.2869985120
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.2927280441
Short name T671
Test name
Test status
Simulation time 71359100 ps
CPU time 23.22 seconds
Started Aug 27 01:11:22 PM UTC 24
Finished Aug 27 01:11:46 PM UTC 24
Peak memory 269356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927280441 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.2927280441
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.491268411
Short name T803
Test name
Test status
Simulation time 592698100 ps
CPU time 886.79 seconds
Started Aug 27 01:10:07 PM UTC 24
Finished Aug 27 01:25:03 PM UTC 24
Peak memory 293968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491268411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.491268411
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.4239761590
Short name T224
Test name
Test status
Simulation time 74755500 ps
CPU time 53.6 seconds
Started Aug 27 01:11:43 PM UTC 24
Finished Aug 27 01:12:38 PM UTC 24
Peak memory 289812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239761590 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.4239761590
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.514977776
Short name T681
Test name
Test status
Simulation time 2255572300 ps
CPU time 128.01 seconds
Started Aug 27 01:10:42 PM UTC 24
Finished Aug 27 01:12:52 PM UTC 24
Peak memory 291852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=514977776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.514977776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.3647350415
Short name T738
Test name
Test status
Simulation time 4469521300 ps
CPU time 529.03 seconds
Started Aug 27 01:10:44 PM UTC 24
Finished Aug 27 01:19:39 PM UTC 24
Peak memory 322420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647350415 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.3647350415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.3075010495
Short name T673
Test name
Test status
Simulation time 108204300 ps
CPU time 42.67 seconds
Started Aug 27 01:11:37 PM UTC 24
Finished Aug 27 01:12:21 PM UTC 24
Peak memory 285876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075010495 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.3075010495
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.4229768358
Short name T675
Test name
Test status
Simulation time 240376900 ps
CPU time 47.82 seconds
Started Aug 27 01:11:39 PM UTC 24
Finished Aug 27 01:12:28 PM UTC 24
Peak memory 281588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4229768358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw_evict_all_en.4229768358
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.3901572588
Short name T669
Test name
Test status
Simulation time 42022100 ps
CPU time 90.07 seconds
Started Aug 27 01:10:06 PM UTC 24
Finished Aug 27 01:11:38 PM UTC 24
Peak memory 283540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901572588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.3901572588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.244521540
Short name T682
Test name
Test status
Simulation time 7027682200 ps
CPU time 138.85 seconds
Started Aug 27 01:10:34 PM UTC 24
Finished Aug 27 01:12:55 PM UTC 24
Peak memory 271220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=244521540 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.244521540
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.3602800344
Short name T697
Test name
Test status
Simulation time 31440800 ps
CPU time 21.89 seconds
Started Aug 27 01:14:26 PM UTC 24
Finished Aug 27 01:14:49 PM UTC 24
Peak memory 269304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3602800344 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.3602800344
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.2789496535
Short name T690
Test name
Test status
Simulation time 21290900 ps
CPU time 15.79 seconds
Started Aug 27 01:14:10 PM UTC 24
Finished Aug 27 01:14:27 PM UTC 24
Peak memory 284940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789496535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.2789496535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.1313614732
Short name T693
Test name
Test status
Simulation time 25544500 ps
CPU time 40.63 seconds
Started Aug 27 01:13:51 PM UTC 24
Finished Aug 27 01:14:33 PM UTC 24
Peak memory 285688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1313614732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_
ctrl_disable.1313614732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3483755105
Short name T701
Test name
Test status
Simulation time 10048352000 ps
CPU time 88.51 seconds
Started Aug 27 01:14:18 PM UTC 24
Finished Aug 27 01:15:48 PM UTC 24
Peak memory 287752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3483755105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3483755105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.1112665053
Short name T694
Test name
Test status
Simulation time 47921900 ps
CPU time 18.36 seconds
Started Aug 27 01:14:15 PM UTC 24
Finished Aug 27 01:14:34 PM UTC 24
Peak memory 269496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1112665053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
15.flash_ctrl_hw_read_seed_err.1112665053
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.704797959
Short name T205
Test name
Test status
Simulation time 80143510700 ps
CPU time 808.13 seconds
Started Aug 27 01:12:36 PM UTC 24
Finished Aug 27 01:26:13 PM UTC 24
Peak memory 275180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704797959 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_reset.704797959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.305597906
Short name T321
Test name
Test status
Simulation time 1104760500 ps
CPU time 117.27 seconds
Started Aug 27 01:12:33 PM UTC 24
Finished Aug 27 01:14:33 PM UTC 24
Peak memory 275468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=305597906 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.305597906
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.3509135990
Short name T707
Test name
Test status
Simulation time 1281053300 ps
CPU time 170.8 seconds
Started Aug 27 01:13:14 PM UTC 24
Finished Aug 27 01:16:08 PM UTC 24
Peak memory 306172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509135990 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.3509135990
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3136849355
Short name T703
Test name
Test status
Simulation time 11708238300 ps
CPU time 155.39 seconds
Started Aug 27 01:13:17 PM UTC 24
Finished Aug 27 01:15:56 PM UTC 24
Peak memory 302000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3136849355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_intr_rd_slow_flash.3136849355
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.2364119263
Short name T688
Test name
Test status
Simulation time 4442337900 ps
CPU time 86.18 seconds
Started Aug 27 01:12:49 PM UTC 24
Finished Aug 27 01:14:17 PM UTC 24
Peak memory 271116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364119263 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.2364119263
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.3458658415
Short name T695
Test name
Test status
Simulation time 42915900 ps
CPU time 22.47 seconds
Started Aug 27 01:14:15 PM UTC 24
Finished Aug 27 01:14:38 PM UTC 24
Peak memory 271368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3458658415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_lcmgr_intg.3458658415
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.560056992
Short name T134
Test name
Test status
Simulation time 24236637300 ps
CPU time 393.86 seconds
Started Aug 27 01:12:48 PM UTC 24
Finished Aug 27 01:19:27 PM UTC 24
Peak memory 283520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=560056992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_mp_regions.560056992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.2177424351
Short name T178
Test name
Test status
Simulation time 85963600 ps
CPU time 205.06 seconds
Started Aug 27 01:12:39 PM UTC 24
Finished Aug 27 01:16:07 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177424351 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.2177424351
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.1938871767
Short name T704
Test name
Test status
Simulation time 112331700 ps
CPU time 204.72 seconds
Started Aug 27 01:12:31 PM UTC 24
Finished Aug 27 01:15:59 PM UTC 24
Peak memory 273224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938871767 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.1938871767
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.1117554763
Short name T683
Test name
Test status
Simulation time 152158700 ps
CPU time 23.54 seconds
Started Aug 27 01:13:20 PM UTC 24
Finished Aug 27 01:13:45 PM UTC 24
Peak memory 271204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117554763 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.1117554763
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.1565474522
Short name T722
Test name
Test status
Simulation time 181313500 ps
CPU time 341.38 seconds
Started Aug 27 01:12:29 PM UTC 24
Finished Aug 27 01:18:15 PM UTC 24
Peak memory 291988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565474522 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1565474522
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.4242161920
Short name T692
Test name
Test status
Simulation time 135293200 ps
CPU time 44.55 seconds
Started Aug 27 01:13:46 PM UTC 24
Finished Aug 27 01:14:32 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242161920 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.4242161920
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.2726710194
Short name T689
Test name
Test status
Simulation time 1943178700 ps
CPU time 89.65 seconds
Started Aug 27 01:12:53 PM UTC 24
Finished Aug 27 01:14:25 PM UTC 24
Peak memory 304120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2726710194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.2726710194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.699057282
Short name T760
Test name
Test status
Simulation time 3838812500 ps
CPU time 528.82 seconds
Started Aug 27 01:12:56 PM UTC 24
Finished Aug 27 01:21:51 PM UTC 24
Peak memory 330732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699057282 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.699057282
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.6090079
Short name T427
Test name
Test status
Simulation time 39582300 ps
CPU time 49.86 seconds
Started Aug 27 01:13:22 PM UTC 24
Finished Aug 27 01:14:14 PM UTC 24
Peak memory 287864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6090079 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.6090079
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.3188917073
Short name T691
Test name
Test status
Simulation time 37746200 ps
CPU time 43.45 seconds
Started Aug 27 01:13:46 PM UTC 24
Finished Aug 27 01:14:30 PM UTC 24
Peak memory 281780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3188917073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw_evict_all_en.3188917073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.2248011743
Short name T698
Test name
Test status
Simulation time 1389967000 ps
CPU time 67.59 seconds
Started Aug 27 01:14:02 PM UTC 24
Finished Aug 27 01:15:11 PM UTC 24
Peak memory 275412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248011743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2248011743
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.1579255793
Short name T702
Test name
Test status
Simulation time 24302300 ps
CPU time 197.76 seconds
Started Aug 27 01:12:29 PM UTC 24
Finished Aug 27 01:15:50 PM UTC 24
Peak memory 289676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579255793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1579255793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.236815388
Short name T708
Test name
Test status
Simulation time 2210743700 ps
CPU time 196.36 seconds
Started Aug 27 01:12:50 PM UTC 24
Finished Aug 27 01:16:10 PM UTC 24
Peak memory 271412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=236815388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.236815388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.3230112491
Short name T715
Test name
Test status
Simulation time 88365900 ps
CPU time 18.6 seconds
Started Aug 27 01:16:17 PM UTC 24
Finished Aug 27 01:16:37 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230112491 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.3230112491
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.242333758
Short name T713
Test name
Test status
Simulation time 24363300 ps
CPU time 23.31 seconds
Started Aug 27 01:16:09 PM UTC 24
Finished Aug 27 01:16:33 PM UTC 24
Peak memory 295312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242333758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.242333758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.54994305
Short name T714
Test name
Test status
Simulation time 12106000 ps
CPU time 27.52 seconds
Started Aug 27 01:16:05 PM UTC 24
Finished Aug 27 01:16:34 PM UTC 24
Peak memory 285724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=54994305 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ct
rl_disable.54994305
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2191683002
Short name T285
Test name
Test status
Simulation time 10012163000 ps
CPU time 151.67 seconds
Started Aug 27 01:16:17 PM UTC 24
Finished Aug 27 01:18:52 PM UTC 24
Peak memory 308388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2191683002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.2191683002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.2930527825
Short name T716
Test name
Test status
Simulation time 26881300 ps
CPU time 25.01 seconds
Started Aug 27 01:16:11 PM UTC 24
Finished Aug 27 01:16:37 PM UTC 24
Peak memory 275440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2930527825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
16.flash_ctrl_hw_read_seed_err.2930527825
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.1566711206
Short name T912
Test name
Test status
Simulation time 160190441000 ps
CPU time 995.45 seconds
Started Aug 27 01:14:33 PM UTC 24
Finished Aug 27 01:31:20 PM UTC 24
Peak memory 275428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566711206
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res
et.1566711206
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.3640078107
Short name T700
Test name
Test status
Simulation time 1994723400 ps
CPU time 69.07 seconds
Started Aug 27 01:14:32 PM UTC 24
Finished Aug 27 01:15:43 PM UTC 24
Peak memory 275200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640078107 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.3640078107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3951789423
Short name T732
Test name
Test status
Simulation time 1933161400 ps
CPU time 232.88 seconds
Started Aug 27 01:15:19 PM UTC 24
Finished Aug 27 01:19:16 PM UTC 24
Peak memory 294164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3951789423 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.3951789423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3819438696
Short name T733
Test name
Test status
Simulation time 39125084300 ps
CPU time 213.14 seconds
Started Aug 27 01:15:44 PM UTC 24
Finished Aug 27 01:19:21 PM UTC 24
Peak memory 304040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3819438696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_intr_rd_slow_flash.3819438696
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.2329903882
Short name T706
Test name
Test status
Simulation time 2931617100 ps
CPU time 83.79 seconds
Started Aug 27 01:14:39 PM UTC 24
Finished Aug 27 01:16:04 PM UTC 24
Peak memory 275404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329903882 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2329903882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.517844993
Short name T711
Test name
Test status
Simulation time 45201000 ps
CPU time 18.76 seconds
Started Aug 27 01:16:09 PM UTC 24
Finished Aug 27 01:16:29 PM UTC 24
Peak memory 271356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=517844993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_lcmgr_intg.517844993
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.548958619
Short name T742
Test name
Test status
Simulation time 21056039200 ps
CPU time 335.5 seconds
Started Aug 27 01:14:35 PM UTC 24
Finished Aug 27 01:20:14 PM UTC 24
Peak memory 283520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=548958619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_mp_regions.548958619
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.922336059
Short name T712
Test name
Test status
Simulation time 109478000 ps
CPU time 117.55 seconds
Started Aug 27 01:14:32 PM UTC 24
Finished Aug 27 01:16:32 PM UTC 24
Peak memory 275340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922336059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.922336059
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.3770014304
Short name T709
Test name
Test status
Simulation time 21242800 ps
CPU time 24.94 seconds
Started Aug 27 01:15:49 PM UTC 24
Finished Aug 27 01:16:16 PM UTC 24
Peak memory 271228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770014304 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.3770014304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.2822759045
Short name T1126
Test name
Test status
Simulation time 804568700 ps
CPU time 1531.85 seconds
Started Aug 27 01:14:32 PM UTC 24
Finished Aug 27 01:40:21 PM UTC 24
Peak memory 296020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822759045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.2822759045
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.3325111183
Short name T717
Test name
Test status
Simulation time 254825500 ps
CPU time 42.22 seconds
Started Aug 27 01:16:00 PM UTC 24
Finished Aug 27 01:16:44 PM UTC 24
Peak memory 289776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325111183 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.3325111183
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.166694352
Short name T718
Test name
Test status
Simulation time 4914069800 ps
CPU time 125.88 seconds
Started Aug 27 01:14:50 PM UTC 24
Finished Aug 27 01:16:58 PM UTC 24
Peak memory 302012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=166694352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.166694352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.1732765868
Short name T791
Test name
Test status
Simulation time 3861746300 ps
CPU time 542.81 seconds
Started Aug 27 01:15:12 PM UTC 24
Finished Aug 27 01:24:22 PM UTC 24
Peak memory 320472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732765868 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.1732765868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.3946353551
Short name T428
Test name
Test status
Simulation time 85432800 ps
CPU time 39.26 seconds
Started Aug 27 01:15:51 PM UTC 24
Finished Aug 27 01:16:31 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946353551 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.3946353551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3244480111
Short name T721
Test name
Test status
Simulation time 2433272000 ps
CPU time 126.24 seconds
Started Aug 27 01:16:05 PM UTC 24
Finished Aug 27 01:18:14 PM UTC 24
Peak memory 275216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244480111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3244480111
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.3598044528
Short name T737
Test name
Test status
Simulation time 45816500 ps
CPU time 302.91 seconds
Started Aug 27 01:14:28 PM UTC 24
Finished Aug 27 01:19:35 PM UTC 24
Peak memory 287636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598044528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.3598044528
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.1585170280
Short name T719
Test name
Test status
Simulation time 11737477600 ps
CPU time 140.64 seconds
Started Aug 27 01:14:43 PM UTC 24
Finished Aug 27 01:17:07 PM UTC 24
Peak memory 271216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1585170280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.1585170280
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.1424195103
Short name T731
Test name
Test status
Simulation time 91198500 ps
CPU time 23.96 seconds
Started Aug 27 01:18:47 PM UTC 24
Finished Aug 27 01:19:13 PM UTC 24
Peak memory 269300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424195103 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.1424195103
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.3240924884
Short name T729
Test name
Test status
Simulation time 28473400 ps
CPU time 19.9 seconds
Started Aug 27 01:18:45 PM UTC 24
Finished Aug 27 01:19:06 PM UTC 24
Peak memory 295176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240924884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.3240924884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.748918425
Short name T726
Test name
Test status
Simulation time 35878500 ps
CPU time 29.91 seconds
Started Aug 27 01:18:15 PM UTC 24
Finished Aug 27 01:18:47 PM UTC 24
Peak memory 285164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=748918425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_disable.748918425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1334109244
Short name T739
Test name
Test status
Simulation time 10060781900 ps
CPU time 53.07 seconds
Started Aug 27 01:18:47 PM UTC 24
Finished Aug 27 01:19:42 PM UTC 24
Peak memory 275588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1334109244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.1334109244
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.2280647037
Short name T728
Test name
Test status
Simulation time 29031400 ps
CPU time 16.05 seconds
Started Aug 27 01:18:47 PM UTC 24
Finished Aug 27 01:19:05 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2280647037 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
17.flash_ctrl_hw_read_seed_err.2280647037
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.426798905
Short name T893
Test name
Test status
Simulation time 40127253400 ps
CPU time 815.16 seconds
Started Aug 27 01:16:34 PM UTC 24
Finished Aug 27 01:30:18 PM UTC 24
Peak memory 275172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426798905 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_reset.426798905
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.1048189071
Short name T727
Test name
Test status
Simulation time 1977557000 ps
CPU time 145.86 seconds
Started Aug 27 01:16:33 PM UTC 24
Finished Aug 27 01:19:01 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048189071 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.1048189071
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.3468797958
Short name T734
Test name
Test status
Simulation time 1319916900 ps
CPU time 133.68 seconds
Started Aug 27 01:17:07 PM UTC 24
Finished Aug 27 01:19:23 PM UTC 24
Peak memory 306172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468797958 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.3468797958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1018256452
Short name T337
Test name
Test status
Simulation time 240037999700 ps
CPU time 497.82 seconds
Started Aug 27 01:17:27 PM UTC 24
Finished Aug 27 01:25:51 PM UTC 24
Peak memory 304172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1018256452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_intr_rd_slow_flash.1018256452
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.822719608
Short name T412
Test name
Test status
Simulation time 6074250800 ps
CPU time 72.74 seconds
Started Aug 27 01:16:39 PM UTC 24
Finished Aug 27 01:17:53 PM UTC 24
Peak memory 271120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822719608 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.822719608
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.2807357546
Short name T730
Test name
Test status
Simulation time 26474000 ps
CPU time 23.09 seconds
Started Aug 27 01:18:46 PM UTC 24
Finished Aug 27 01:19:11 PM UTC 24
Peak memory 271392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2807357546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_lcmgr_intg.2807357546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.1337545126
Short name T756
Test name
Test status
Simulation time 13843786100 ps
CPU time 281.66 seconds
Started Aug 27 01:16:39 PM UTC 24
Finished Aug 27 01:21:24 PM UTC 24
Peak memory 283656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1337545126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_mp_regions.1337545126
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.2985300818
Short name T181
Test name
Test status
Simulation time 70092100 ps
CPU time 233.15 seconds
Started Aug 27 01:16:35 PM UTC 24
Finished Aug 27 01:20:32 PM UTC 24
Peak memory 275240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985300818 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.2985300818
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.1016159733
Short name T779
Test name
Test status
Simulation time 615029300 ps
CPU time 404.66 seconds
Started Aug 27 01:16:32 PM UTC 24
Finished Aug 27 01:23:21 PM UTC 24
Peak memory 275336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016159733 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1016159733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.1321584405
Short name T743
Test name
Test status
Simulation time 8078017900 ps
CPU time 147.68 seconds
Started Aug 27 01:17:45 PM UTC 24
Finished Aug 27 01:20:15 PM UTC 24
Peak memory 271228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321584405 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.1321584405
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.493773838
Short name T953
Test name
Test status
Simulation time 7022181100 ps
CPU time 991.62 seconds
Started Aug 27 01:16:30 PM UTC 24
Finished Aug 27 01:33:13 PM UTC 24
Peak memory 291728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493773838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.493773838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.1006327118
Short name T736
Test name
Test status
Simulation time 90355600 ps
CPU time 67.33 seconds
Started Aug 27 01:18:15 PM UTC 24
Finished Aug 27 01:19:25 PM UTC 24
Peak memory 283268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006327118 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.1006327118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.751860074
Short name T725
Test name
Test status
Simulation time 616894100 ps
CPU time 112.25 seconds
Started Aug 27 01:16:51 PM UTC 24
Finished Aug 27 01:18:46 PM UTC 24
Peak memory 302028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=751860074 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.751860074
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.941405976
Short name T784
Test name
Test status
Simulation time 6266238700 ps
CPU time 410.96 seconds
Started Aug 27 01:16:59 PM UTC 24
Finished Aug 27 01:23:56 PM UTC 24
Peak memory 324600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941405976 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.941405976
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.1219237398
Short name T421
Test name
Test status
Simulation time 63570500 ps
CPU time 53 seconds
Started Aug 27 01:17:51 PM UTC 24
Finished Aug 27 01:18:45 PM UTC 24
Peak memory 289972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219237398 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.1219237398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.1998919573
Short name T724
Test name
Test status
Simulation time 44778500 ps
CPU time 47.87 seconds
Started Aug 27 01:17:54 PM UTC 24
Finished Aug 27 01:18:43 PM UTC 24
Peak memory 281584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1998919573 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw_evict_all_en.1998919573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.1524018859
Short name T403
Test name
Test status
Simulation time 924315200 ps
CPU time 73.63 seconds
Started Aug 27 01:18:32 PM UTC 24
Finished Aug 27 01:19:47 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1524018859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.1524018859
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.277901713
Short name T723
Test name
Test status
Simulation time 21802300 ps
CPU time 122.23 seconds
Started Aug 27 01:16:27 PM UTC 24
Finished Aug 27 01:18:31 PM UTC 24
Peak memory 287636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=277901713 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.277901713
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.2849522363
Short name T749
Test name
Test status
Simulation time 4876525700 ps
CPU time 222.76 seconds
Started Aug 27 01:16:46 PM UTC 24
Finished Aug 27 01:20:32 PM UTC 24
Peak memory 275572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2849522363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.2849522363
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1210019864
Short name T753
Test name
Test status
Simulation time 139659900 ps
CPU time 21.23 seconds
Started Aug 27 01:20:20 PM UTC 24
Finished Aug 27 01:20:43 PM UTC 24
Peak memory 269324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210019864 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.1210019864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.3412850474
Short name T84
Test name
Test status
Simulation time 14336800 ps
CPU time 32.43 seconds
Started Aug 27 01:20:16 PM UTC 24
Finished Aug 27 01:20:50 PM UTC 24
Peak memory 295116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412850474 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3412850474
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.3812606524
Short name T750
Test name
Test status
Simulation time 10799000 ps
CPU time 31.16 seconds
Started Aug 27 01:20:02 PM UTC 24
Finished Aug 27 01:20:34 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3812606524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_
ctrl_disable.3812606524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1495726273
Short name T759
Test name
Test status
Simulation time 10019293300 ps
CPU time 73.09 seconds
Started Aug 27 01:20:19 PM UTC 24
Finished Aug 27 01:21:34 PM UTC 24
Peak memory 302092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1495726273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.1495726273
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.1207532510
Short name T751
Test name
Test status
Simulation time 15641000 ps
CPU time 23.79 seconds
Started Aug 27 01:20:17 PM UTC 24
Finished Aug 27 01:20:42 PM UTC 24
Peak memory 269232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1207532510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
18.flash_ctrl_hw_read_seed_err.1207532510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.2161878489
Short name T206
Test name
Test status
Simulation time 160195791300 ps
CPU time 834.3 seconds
Started Aug 27 01:19:11 PM UTC 24
Finished Aug 27 01:33:15 PM UTC 24
Peak memory 275172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161878489
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_res
et.2161878489
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.2546222082
Short name T318
Test name
Test status
Simulation time 3360274800 ps
CPU time 117.65 seconds
Started Aug 27 01:19:07 PM UTC 24
Finished Aug 27 01:21:07 PM UTC 24
Peak memory 275340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546222082 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.2546222082
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.1577079635
Short name T350
Test name
Test status
Simulation time 743605400 ps
CPU time 155.48 seconds
Started Aug 27 01:19:28 PM UTC 24
Finished Aug 27 01:22:06 PM UTC 24
Peak memory 306428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577079635 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.1577079635
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1910234524
Short name T768
Test name
Test status
Simulation time 52998842300 ps
CPU time 177.7 seconds
Started Aug 27 01:19:36 PM UTC 24
Finished Aug 27 01:22:36 PM UTC 24
Peak memory 301988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1910234524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_intr_rd_slow_flash.1910234524
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.3328196410
Short name T752
Test name
Test status
Simulation time 1670366400 ps
CPU time 78.8 seconds
Started Aug 27 01:19:22 PM UTC 24
Finished Aug 27 01:20:42 PM UTC 24
Peak memory 275464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328196410 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.3328196410
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.48072482
Short name T754
Test name
Test status
Simulation time 25220000 ps
CPU time 25.97 seconds
Started Aug 27 01:20:16 PM UTC 24
Finished Aug 27 01:20:43 PM UTC 24
Peak memory 271364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=48072482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash
_ctrl_lcmgr_intg.48072482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.2089247946
Short name T952
Test name
Test status
Simulation time 27587129600 ps
CPU time 819.71 seconds
Started Aug 27 01:19:17 PM UTC 24
Finished Aug 27 01:33:05 PM UTC 24
Peak memory 285576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2089247946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.flash_ctrl_mp_regions.2089247946
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.2318889005
Short name T830
Test name
Test status
Simulation time 5099294500 ps
CPU time 450.61 seconds
Started Aug 27 01:19:06 PM UTC 24
Finished Aug 27 01:26:42 PM UTC 24
Peak memory 273224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318889005 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2318889005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.1267742444
Short name T741
Test name
Test status
Simulation time 175325600 ps
CPU time 23.78 seconds
Started Aug 27 01:19:40 PM UTC 24
Finished Aug 27 01:20:05 PM UTC 24
Peak memory 271228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267742444 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.1267742444
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.1720222603
Short name T987
Test name
Test status
Simulation time 312240600 ps
CPU time 918.6 seconds
Started Aug 27 01:19:03 PM UTC 24
Finished Aug 27 01:34:31 PM UTC 24
Peak memory 293780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1720222603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1720222603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.631282097
Short name T755
Test name
Test status
Simulation time 387681300 ps
CPU time 50.44 seconds
Started Aug 27 01:19:54 PM UTC 24
Finished Aug 27 01:20:46 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631282097 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.631282097
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.1185496442
Short name T757
Test name
Test status
Simulation time 673246700 ps
CPU time 116.92 seconds
Started Aug 27 01:19:25 PM UTC 24
Finished Aug 27 01:21:24 PM UTC 24
Peak memory 304048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1185496442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.1185496442
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.3797969782
Short name T815
Test name
Test status
Simulation time 13352609700 ps
CPU time 381.55 seconds
Started Aug 27 01:19:25 PM UTC 24
Finished Aug 27 01:25:51 PM UTC 24
Peak memory 324528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797969782 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.3797969782
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.2090738101
Short name T746
Test name
Test status
Simulation time 68904300 ps
CPU time 34.27 seconds
Started Aug 27 01:19:43 PM UTC 24
Finished Aug 27 01:20:19 PM UTC 24
Peak memory 287764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090738101 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.2090738101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.2862970911
Short name T747
Test name
Test status
Simulation time 71360700 ps
CPU time 34.52 seconds
Started Aug 27 01:19:48 PM UTC 24
Finished Aug 27 01:20:25 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2862970911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw_evict_all_en.2862970911
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.2270145256
Short name T758
Test name
Test status
Simulation time 489100600 ps
CPU time 82.7 seconds
Started Aug 27 01:20:06 PM UTC 24
Finished Aug 27 01:21:31 PM UTC 24
Peak memory 273168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270145256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.2270145256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.2662780368
Short name T765
Test name
Test status
Simulation time 22870100 ps
CPU time 211.09 seconds
Started Aug 27 01:18:53 PM UTC 24
Finished Aug 27 01:22:27 PM UTC 24
Peak memory 287632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662780368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.2662780368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.1499908679
Short name T770
Test name
Test status
Simulation time 4061731600 ps
CPU time 190.67 seconds
Started Aug 27 01:19:24 PM UTC 24
Finished Aug 27 01:22:38 PM UTC 24
Peak memory 275312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1499908679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.1499908679
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.3124116822
Short name T776
Test name
Test status
Simulation time 53737400 ps
CPU time 23.83 seconds
Started Aug 27 01:22:31 PM UTC 24
Finished Aug 27 01:22:56 PM UTC 24
Peak memory 275516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3124116822 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.3124116822
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.757895654
Short name T769
Test name
Test status
Simulation time 57598500 ps
CPU time 25.67 seconds
Started Aug 27 01:22:10 PM UTC 24
Finished Aug 27 01:22:37 PM UTC 24
Peak memory 295308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757895654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.757895654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.3575101398
Short name T388
Test name
Test status
Simulation time 22507400 ps
CPU time 35.73 seconds
Started Aug 27 01:21:53 PM UTC 24
Finished Aug 27 01:22:30 PM UTC 24
Peak memory 285880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3575101398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_
ctrl_disable.3575101398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3153542460
Short name T782
Test name
Test status
Simulation time 10083503800 ps
CPU time 68.49 seconds
Started Aug 27 01:22:27 PM UTC 24
Finished Aug 27 01:23:38 PM UTC 24
Peak memory 275468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3153542460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3153542460
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.657976638
Short name T773
Test name
Test status
Simulation time 26225000 ps
CPU time 21.96 seconds
Started Aug 27 01:22:25 PM UTC 24
Finished Aug 27 01:22:49 PM UTC 24
Peak memory 275520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=657976638 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
9.flash_ctrl_hw_read_seed_err.657976638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.566262730
Short name T1098
Test name
Test status
Simulation time 320284490600 ps
CPU time 1063.24 seconds
Started Aug 27 01:20:35 PM UTC 24
Finished Aug 27 01:38:31 PM UTC 24
Peak memory 275308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566262730 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_reset.566262730
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1297624833
Short name T789
Test name
Test status
Simulation time 5766846900 ps
CPU time 221.37 seconds
Started Aug 27 01:20:33 PM UTC 24
Finished Aug 27 01:24:17 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297624833 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.1297624833
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1274559527
Short name T801
Test name
Test status
Simulation time 6171399600 ps
CPU time 223.32 seconds
Started Aug 27 01:21:08 PM UTC 24
Finished Aug 27 01:24:55 PM UTC 24
Peak memory 302096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274559527 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.1274559527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1485686603
Short name T787
Test name
Test status
Simulation time 15217806000 ps
CPU time 156.87 seconds
Started Aug 27 01:21:26 PM UTC 24
Finished Aug 27 01:24:05 PM UTC 24
Peak memory 304304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1485686603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_intr_rd_slow_flash.1485686603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3715321300
Short name T767
Test name
Test status
Simulation time 1169592000 ps
CPU time 109.63 seconds
Started Aug 27 01:20:43 PM UTC 24
Finished Aug 27 01:22:35 PM UTC 24
Peak memory 271116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715321300 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3715321300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.1988988669
Short name T766
Test name
Test status
Simulation time 21170000 ps
CPU time 18.56 seconds
Started Aug 27 01:22:14 PM UTC 24
Finished Aug 27 01:22:34 PM UTC 24
Peak memory 275488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1988988669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.fla
sh_ctrl_lcmgr_intg.1988988669
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1813155821
Short name T834
Test name
Test status
Simulation time 4696968700 ps
CPU time 369.62 seconds
Started Aug 27 01:20:43 PM UTC 24
Finished Aug 27 01:26:58 PM UTC 24
Peak memory 283524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1813155821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.flash_ctrl_mp_regions.1813155821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.4122542641
Short name T799
Test name
Test status
Simulation time 447726600 ps
CPU time 244.5 seconds
Started Aug 27 01:20:43 PM UTC 24
Finished Aug 27 01:24:51 PM UTC 24
Peak memory 271400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122542641 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.4122542641
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.3689320604
Short name T825
Test name
Test status
Simulation time 2799673200 ps
CPU time 346.5 seconds
Started Aug 27 01:20:33 PM UTC 24
Finished Aug 27 01:26:24 PM UTC 24
Peak memory 273296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689320604 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.3689320604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.2017349254
Short name T761
Test name
Test status
Simulation time 35483700 ps
CPU time 24.43 seconds
Started Aug 27 01:21:26 PM UTC 24
Finished Aug 27 01:21:52 PM UTC 24
Peak memory 275244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017349254 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.2017349254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.237295785
Short name T1025
Test name
Test status
Simulation time 2302428700 ps
CPU time 911.52 seconds
Started Aug 27 01:20:33 PM UTC 24
Finished Aug 27 01:35:54 PM UTC 24
Peak memory 293776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237295785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.237295785
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2081668075
Short name T772
Test name
Test status
Simulation time 70426600 ps
CPU time 52.32 seconds
Started Aug 27 01:21:53 PM UTC 24
Finished Aug 27 01:22:46 PM UTC 24
Peak memory 283892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081668075 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.2081668075
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1621028226
Short name T778
Test name
Test status
Simulation time 11593445400 ps
CPU time 149.74 seconds
Started Aug 27 01:20:47 PM UTC 24
Finished Aug 27 01:23:19 PM UTC 24
Peak memory 291772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1621028226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.1621028226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.1416589622
Short name T869
Test name
Test status
Simulation time 19197537000 ps
CPU time 473.68 seconds
Started Aug 27 01:20:51 PM UTC 24
Finished Aug 27 01:28:50 PM UTC 24
Peak memory 322500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1416589622 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.1416589622
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.2703212837
Short name T764
Test name
Test status
Simulation time 56476600 ps
CPU time 50.44 seconds
Started Aug 27 01:21:32 PM UTC 24
Finished Aug 27 01:22:24 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703212837 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.2703212837
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.1564947566
Short name T763
Test name
Test status
Simulation time 43993200 ps
CPU time 36.5 seconds
Started Aug 27 01:21:35 PM UTC 24
Finished Aug 27 01:22:13 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1564947566 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw_evict_all_en.1564947566
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.492379230
Short name T407
Test name
Test status
Simulation time 1746317000 ps
CPU time 55.91 seconds
Started Aug 27 01:22:07 PM UTC 24
Finished Aug 27 01:23:04 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492379230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.492379230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.379648129
Short name T774
Test name
Test status
Simulation time 65985300 ps
CPU time 142.09 seconds
Started Aug 27 01:20:25 PM UTC 24
Finished Aug 27 01:22:50 PM UTC 24
Peak memory 287832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379648129 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.379648129
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.2342025894
Short name T786
Test name
Test status
Simulation time 2425303600 ps
CPU time 193.11 seconds
Started Aug 27 01:20:45 PM UTC 24
Finished Aug 27 01:24:01 PM UTC 24
Peak memory 271212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2342025894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.2342025894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.835330752
Short name T49
Test name
Test status
Simulation time 47565100 ps
CPU time 29.24 seconds
Started Aug 27 12:25:11 PM UTC 24
Finished Aug 27 12:25:41 PM UTC 24
Peak memory 275392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=835330752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disable
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.835330752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.718427423
Short name T309
Test name
Test status
Simulation time 39792900 ps
CPU time 25.32 seconds
Started Aug 27 12:25:41 PM UTC 24
Finished Aug 27 12:26:08 PM UTC 24
Peak memory 273288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718427423 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.718427423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.1617991526
Short name T6
Test name
Test status
Simulation time 27730200 ps
CPU time 31.28 seconds
Started Aug 27 12:24:59 PM UTC 24
Finished Aug 27 12:25:31 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617991526 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.1617991526
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.2117623661
Short name T455
Test name
Test status
Simulation time 1514809100 ps
CPU time 349.81 seconds
Started Aug 27 12:22:52 PM UTC 24
Finished Aug 27 12:28:46 PM UTC 24
Peak memory 29334712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2117623661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.flash_ctrl_derr_detect.2117623661
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.4023203320
Short name T164
Test name
Test status
Simulation time 11220605700 ps
CPU time 537.49 seconds
Started Aug 27 12:19:05 PM UTC 24
Finished Aug 27 12:28:09 PM UTC 24
Peak memory 275272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023203320 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.4023203320
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.1076499360
Short name T290
Test name
Test status
Simulation time 3546357400 ps
CPU time 3097.98 seconds
Started Aug 27 12:20:11 PM UTC 24
Finished Aug 27 01:12:20 PM UTC 24
Peak memory 275936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1076499360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.1076499360
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.3226982488
Short name T293
Test name
Test status
Simulation time 873681700 ps
CPU time 1264.53 seconds
Started Aug 27 12:20:04 PM UTC 24
Finished Aug 27 12:41:22 PM UTC 24
Peak memory 285524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226982488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.3226982488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.1125350936
Short name T52
Test name
Test status
Simulation time 1448259200 ps
CPU time 40.18 seconds
Started Aug 27 12:19:35 PM UTC 24
Finished Aug 27 12:20:17 PM UTC 24
Peak memory 273300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11
25350936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetc
h_code.1125350936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.3468178652
Short name T275
Test name
Test status
Simulation time 339511800 ps
CPU time 53.47 seconds
Started Aug 27 12:25:14 PM UTC 24
Finished Aug 27 12:26:09 PM UTC 24
Peak memory 273360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468178
652 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f
s_sup.3468178652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.1383525027
Short name T128
Test name
Test status
Simulation time 88284781700 ps
CPU time 2068.43 seconds
Started Aug 27 12:19:40 PM UTC 24
Finished Aug 27 12:54:31 PM UTC 24
Peak memory 277944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1383525027 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.1383525027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.1438415603
Short name T312
Test name
Test status
Simulation time 63837400 ps
CPU time 50.87 seconds
Started Aug 27 12:26:04 PM UTC 24
Finished Aug 27 12:26:57 PM UTC 24
Peak memory 285616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143841560
3 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ho
st_addr_infection.1438415603
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.732535418
Short name T234
Test name
Test status
Simulation time 235600800 ps
CPU time 158.51 seconds
Started Aug 27 12:18:40 PM UTC 24
Finished Aug 27 12:21:21 PM UTC 24
Peak memory 273488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=732535418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.732535418
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.4053483433
Short name T169
Test name
Test status
Simulation time 10035857300 ps
CPU time 62.42 seconds
Started Aug 27 12:26:01 PM UTC 24
Finished Aug 27 12:27:05 PM UTC 24
Peak memory 302088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4053483433 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.4053483433
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.1584696620
Short name T281
Test name
Test status
Simulation time 27028800 ps
CPU time 19.2 seconds
Started Aug 27 12:25:55 PM UTC 24
Finished Aug 27 12:26:15 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1584696620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_hw_read_seed_err.1584696620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1293868073
Short name T117
Test name
Test status
Simulation time 355446607000 ps
CPU time 1740.52 seconds
Started Aug 27 12:19:07 PM UTC 24
Finished Aug 27 12:48:26 PM UTC 24
Peak memory 278084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293868073
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.1293868073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.996223049
Short name T119
Test name
Test status
Simulation time 200213024700 ps
CPU time 838.89 seconds
Started Aug 27 12:19:07 PM UTC 24
Finished Aug 27 12:33:15 PM UTC 24
Peak memory 275180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996223049 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.996223049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.3298903101
Short name T106
Test name
Test status
Simulation time 3437639400 ps
CPU time 69.42 seconds
Started Aug 27 12:19:03 PM UTC 24
Finished Aug 27 12:20:14 PM UTC 24
Peak memory 273168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298903101 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.3298903101
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.4108280297
Short name T466
Test name
Test status
Simulation time 22665493000 ps
CPU time 550.49 seconds
Started Aug 27 12:22:57 PM UTC 24
Finished Aug 27 12:32:15 PM UTC 24
Peak memory 341184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4108280297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integr
ity.4108280297
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.3071327717
Short name T346
Test name
Test status
Simulation time 7086660200 ps
CPU time 260.84 seconds
Started Aug 27 12:23:13 PM UTC 24
Finished Aug 27 12:27:38 PM UTC 24
Peak memory 302068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3071327717 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.3071327717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.271256934
Short name T345
Test name
Test status
Simulation time 24290950200 ps
CPU time 222.26 seconds
Started Aug 27 12:23:35 PM UTC 24
Finished Aug 27 12:27:21 PM UTC 24
Peak memory 306096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=271256934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_intr_rd_slow_flash.271256934
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.2238899302
Short name T448
Test name
Test status
Simulation time 3531738200 ps
CPU time 74.59 seconds
Started Aug 27 12:23:15 PM UTC 24
Finished Aug 27 12:24:31 PM UTC 24
Peak memory 271408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238899302 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.2238899302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.1326621012
Short name T457
Test name
Test status
Simulation time 20557349200 ps
CPU time 303.29 seconds
Started Aug 27 12:23:56 PM UTC 24
Finished Aug 27 12:29:04 PM UTC 24
Peak memory 275636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326621012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.1326621012
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.3936849657
Short name T147
Test name
Test status
Simulation time 4032941200 ps
CPU time 91.29 seconds
Started Aug 27 12:20:12 PM UTC 24
Finished Aug 27 12:21:45 PM UTC 24
Peak memory 275468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3936849657 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.3936849657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.2869088772
Short name T174
Test name
Test status
Simulation time 15329200 ps
CPU time 29.18 seconds
Started Aug 27 12:25:53 PM UTC 24
Finished Aug 27 12:26:23 PM UTC 24
Peak memory 273416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2869088772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_lcmgr_intg.2869088772
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.4205250409
Short name T95
Test name
Test status
Simulation time 1648733600 ps
CPU time 138.56 seconds
Started Aug 27 12:20:15 PM UTC 24
Finished Aug 27 12:22:36 PM UTC 24
Peak memory 271068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205250409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.4205250409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.711991604
Short name T148
Test name
Test status
Simulation time 11727108500 ps
CPU time 317.54 seconds
Started Aug 27 12:19:35 PM UTC 24
Finished Aug 27 12:24:57 PM UTC 24
Peak memory 283528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=711991604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_mp_regions.711991604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.4009463926
Short name T203
Test name
Test status
Simulation time 1374116300 ps
CPU time 199.62 seconds
Started Aug 27 12:22:54 PM UTC 24
Finished Aug 27 12:26:17 PM UTC 24
Peak memory 292084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=4009463926 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_oversize_error.4009463926
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.4102897600
Short name T232
Test name
Test status
Simulation time 47292100 ps
CPU time 26.59 seconds
Started Aug 27 12:25:32 PM UTC 24
Finished Aug 27 12:26:00 PM UTC 24
Peak memory 275608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102897600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.4102897600
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.3306864513
Short name T197
Test name
Test status
Simulation time 40440600 ps
CPU time 230.08 seconds
Started Aug 27 12:19:03 PM UTC 24
Finished Aug 27 12:22:56 PM UTC 24
Peak memory 273488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306864513 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.3306864513
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.3806048388
Short name T447
Test name
Test status
Simulation time 37598200 ps
CPU time 23.63 seconds
Started Aug 27 12:24:04 PM UTC 24
Finished Aug 27 12:24:29 PM UTC 24
Peak memory 271212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806048388 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.3806048388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.3607798069
Short name T136
Test name
Test status
Simulation time 258768200 ps
CPU time 1286.71 seconds
Started Aug 27 12:18:34 PM UTC 24
Finished Aug 27 12:40:15 PM UTC 24
Peak memory 293776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3607798069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3607798069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.2652861886
Short name T235
Test name
Test status
Simulation time 2823209100 ps
CPU time 173.27 seconds
Started Aug 27 12:18:52 PM UTC 24
Finished Aug 27 12:21:48 PM UTC 24
Peak memory 273292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652861886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.2652861886
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.4081862486
Short name T198
Test name
Test status
Simulation time 135703300 ps
CPU time 45.98 seconds
Started Aug 27 12:22:26 PM UTC 24
Finished Aug 27 12:23:14 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4081862486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_read_word_sweep_derr.4081862486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.2315914606
Short name T194
Test name
Test status
Simulation time 133233100 ps
CPU time 38.15 seconds
Started Aug 27 12:21:46 PM UTC 24
Finished Aug 27 12:22:25 PM UTC 24
Peak memory 275456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315914606 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.2315914606
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.24767225
Short name T137
Test name
Test status
Simulation time 160158918000 ps
CPU time 871.9 seconds
Started Aug 27 12:25:43 PM UTC 24
Finished Aug 27 12:40:24 PM UTC 24
Peak memory 273104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=24767225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_rma_err.24767225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2949262604
Short name T195
Test name
Test status
Simulation time 519675000 ps
CPU time 116.08 seconds
Started Aug 27 12:20:43 PM UTC 24
Finished Aug 27 12:22:41 PM UTC 24
Peak memory 292044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2949262604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.2949262604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3424352438
Short name T446
Test name
Test status
Simulation time 10361954000 ps
CPU time 142.81 seconds
Started Aug 27 12:21:49 PM UTC 24
Finished Aug 27 12:24:14 PM UTC 24
Peak memory 306172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3424352438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash
_ctrl_ro_serr.3424352438
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.2931738200
Short name T227
Test name
Test status
Simulation time 3831997100 ps
CPU time 468.87 seconds
Started Aug 27 12:21:21 PM UTC 24
Finished Aug 27 12:29:16 PM UTC 24
Peak memory 324600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931738200 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.2931738200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.2884495485
Short name T450
Test name
Test status
Simulation time 2549825100 ps
CPU time 197.43 seconds
Started Aug 27 12:22:43 PM UTC 24
Finished Aug 27 12:26:03 PM UTC 24
Peak memory 296124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2884495485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rw_derr.2884495485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.1051895165
Short name T41
Test name
Test status
Simulation time 68348200 ps
CPU time 46.64 seconds
Started Aug 27 12:24:10 PM UTC 24
Finished Aug 27 12:24:58 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051895165 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.1051895165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.638756903
Short name T307
Test name
Test status
Simulation time 29368200 ps
CPU time 62.85 seconds
Started Aug 27 12:24:16 PM UTC 24
Finished Aug 27 12:25:20 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=638756903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctr
l_rw_evict_all_en.638756903
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.2842034267
Short name T449
Test name
Test status
Simulation time 1514515100 ps
CPU time 185.55 seconds
Started Aug 27 12:22:09 PM UTC 24
Finished Aug 27 12:25:17 PM UTC 24
Peak memory 306388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2842034267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.2842034267
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3314466954
Short name T43
Test name
Test status
Simulation time 5239151200 ps
CPU time 6311.15 seconds
Started Aug 27 12:24:32 PM UTC 24
Finished Aug 27 02:10:48 PM UTC 24
Peak memory 312564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314466954 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.3314466954
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.2458222992
Short name T207
Test name
Test status
Simulation time 2185241400 ps
CPU time 125.36 seconds
Started Aug 27 12:24:47 PM UTC 24
Finished Aug 27 12:26:55 PM UTC 24
Peak memory 273168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2458222992 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2458222992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.2076105137
Short name T382
Test name
Test status
Simulation time 1344603100 ps
CPU time 110.79 seconds
Started Aug 27 12:22:22 PM UTC 24
Finished Aug 27 12:24:15 PM UTC 24
Peak memory 275472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=207
6105137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ser
r_address.2076105137
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3475065548
Short name T199
Test name
Test status
Simulation time 1581345000 ps
CPU time 97.85 seconds
Started Aug 27 12:22:15 PM UTC 24
Finished Aug 27 12:23:55 PM UTC 24
Peak memory 275448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34
75065548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se
rr_counter.3475065548
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.2109554756
Short name T379
Test name
Test status
Simulation time 18939200 ps
CPU time 94.25 seconds
Started Aug 27 12:18:33 PM UTC 24
Finished Aug 27 12:20:09 PM UTC 24
Peak memory 287640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109554756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.2109554756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.3479937720
Short name T444
Test name
Test status
Simulation time 17780800 ps
CPU time 37.6 seconds
Started Aug 27 12:18:34 PM UTC 24
Finished Aug 27 12:19:13 PM UTC 24
Peak memory 271048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479937720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.3479937720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.3990874828
Short name T380
Test name
Test status
Simulation time 253716400 ps
CPU time 319.4 seconds
Started Aug 27 12:24:59 PM UTC 24
Finished Aug 27 12:30:22 PM UTC 24
Peak memory 291668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990874828 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.3990874828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.3440541980
Short name T445
Test name
Test status
Simulation time 19842100 ps
CPU time 54.14 seconds
Started Aug 27 12:18:38 PM UTC 24
Finished Aug 27 12:19:34 PM UTC 24
Peak memory 273104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3440541980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.3440541980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.372682497
Short name T381
Test name
Test status
Simulation time 7805030300 ps
CPU time 221.89 seconds
Started Aug 27 12:20:18 PM UTC 24
Finished Aug 27 12:24:04 PM UTC 24
Peak memory 275312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=372682497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.372682497
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.3459025085
Short name T781
Test name
Test status
Simulation time 98282600 ps
CPU time 29.06 seconds
Started Aug 27 01:23:05 PM UTC 24
Finished Aug 27 01:23:35 PM UTC 24
Peak memory 275664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459025085 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.3459025085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.2551028207
Short name T85
Test name
Test status
Simulation time 44519800 ps
CPU time 30.94 seconds
Started Aug 27 01:22:57 PM UTC 24
Finished Aug 27 01:23:29 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551028207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2551028207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.4018620917
Short name T780
Test name
Test status
Simulation time 33031000 ps
CPU time 35.4 seconds
Started Aug 27 01:22:50 PM UTC 24
Finished Aug 27 01:23:27 PM UTC 24
Peak memory 285884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4018620917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_
ctrl_disable.4018620917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.2690405080
Short name T804
Test name
Test status
Simulation time 11216016200 ps
CPU time 145.48 seconds
Started Aug 27 01:22:36 PM UTC 24
Finished Aug 27 01:25:04 PM UTC 24
Peak memory 273352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690405080 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.2690405080
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.2315332980
Short name T794
Test name
Test status
Simulation time 649037900 ps
CPU time 113.51 seconds
Started Aug 27 01:22:39 PM UTC 24
Finished Aug 27 01:24:34 PM UTC 24
Peak memory 304124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315332980 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.2315332980
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.996869991
Short name T808
Test name
Test status
Simulation time 5626177100 ps
CPU time 151.58 seconds
Started Aug 27 01:22:39 PM UTC 24
Finished Aug 27 01:25:13 PM UTC 24
Peak memory 304048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=996869991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 20.flash_ctrl_intr_rd_slow_flash.996869991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.2901849118
Short name T817
Test name
Test status
Simulation time 141375600 ps
CPU time 194.07 seconds
Started Aug 27 01:22:37 PM UTC 24
Finished Aug 27 01:25:54 PM UTC 24
Peak memory 271388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901849118 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.2901849118
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.1650570067
Short name T777
Test name
Test status
Simulation time 35067600 ps
CPU time 28.02 seconds
Started Aug 27 01:22:42 PM UTC 24
Finished Aug 27 01:23:11 PM UTC 24
Peak memory 275316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650570067 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.1650570067
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.3398892989
Short name T422
Test name
Test status
Simulation time 51206400 ps
CPU time 58.85 seconds
Started Aug 27 01:22:47 PM UTC 24
Finished Aug 27 01:23:48 PM UTC 24
Peak memory 283828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398892989 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.3398892989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.3657114117
Short name T783
Test name
Test status
Simulation time 83765200 ps
CPU time 48.13 seconds
Started Aug 27 01:22:49 PM UTC 24
Finished Aug 27 01:23:39 PM UTC 24
Peak memory 281584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3657114117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_c
trl_rw_evict_all_en.3657114117
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.3824712165
Short name T797
Test name
Test status
Simulation time 2830478700 ps
CPU time 105.8 seconds
Started Aug 27 01:22:56 PM UTC 24
Finished Aug 27 01:24:44 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824712165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.3824712165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.2042421848
Short name T788
Test name
Test status
Simulation time 29449300 ps
CPU time 94.03 seconds
Started Aug 27 01:22:35 PM UTC 24
Finished Aug 27 01:24:11 PM UTC 24
Peak memory 287892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042421848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2042421848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.1972234802
Short name T792
Test name
Test status
Simulation time 25307300 ps
CPU time 21.07 seconds
Started Aug 27 01:24:02 PM UTC 24
Finished Aug 27 01:24:25 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972234802 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.1972234802
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.1784899717
Short name T790
Test name
Test status
Simulation time 24694700 ps
CPU time 15.65 seconds
Started Aug 27 01:24:02 PM UTC 24
Finished Aug 27 01:24:19 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784899717 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1784899717
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.632606314
Short name T375
Test name
Test status
Simulation time 10926100 ps
CPU time 26.42 seconds
Started Aug 27 01:23:48 PM UTC 24
Finished Aug 27 01:24:16 PM UTC 24
Peak memory 285628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=632606314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_c
trl_disable.632606314
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.757006348
Short name T800
Test name
Test status
Simulation time 921075100 ps
CPU time 92.89 seconds
Started Aug 27 01:23:20 PM UTC 24
Finished Aug 27 01:24:55 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757006348 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.757006348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.4172191079
Short name T812
Test name
Test status
Simulation time 8001900300 ps
CPU time 118.6 seconds
Started Aug 27 01:23:28 PM UTC 24
Finished Aug 27 01:25:29 PM UTC 24
Peak memory 306164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172191079 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.4172191079
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1999534233
Short name T344
Test name
Test status
Simulation time 5848341300 ps
CPU time 147.69 seconds
Started Aug 27 01:23:30 PM UTC 24
Finished Aug 27 01:26:00 PM UTC 24
Peak memory 306132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1999534233 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 21.flash_ctrl_intr_rd_slow_flash.1999534233
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.3011592663
Short name T315
Test name
Test status
Simulation time 185535200 ps
CPU time 134.26 seconds
Started Aug 27 01:23:22 PM UTC 24
Finished Aug 27 01:25:39 PM UTC 24
Peak memory 271400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011592663 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.3011592663
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.1374404636
Short name T785
Test name
Test status
Simulation time 65031000 ps
CPU time 23.35 seconds
Started Aug 27 01:23:36 PM UTC 24
Finished Aug 27 01:24:01 PM UTC 24
Peak memory 271212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1374404636 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.1374404636
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.2036152791
Short name T796
Test name
Test status
Simulation time 36605000 ps
CPU time 62.88 seconds
Started Aug 27 01:23:39 PM UTC 24
Finished Aug 27 01:24:44 PM UTC 24
Peak memory 287760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2036152791 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.2036152791
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.313982751
Short name T793
Test name
Test status
Simulation time 26561400 ps
CPU time 46.81 seconds
Started Aug 27 01:23:40 PM UTC 24
Finished Aug 27 01:24:28 PM UTC 24
Peak memory 287756 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=313982751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ct
rl_rw_evict_all_en.313982751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.1705820558
Short name T818
Test name
Test status
Simulation time 34960900 ps
CPU time 162.59 seconds
Started Aug 27 01:23:12 PM UTC 24
Finished Aug 27 01:25:57 PM UTC 24
Peak memory 289684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705820558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.1705820558
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.40229784
Short name T807
Test name
Test status
Simulation time 37894400 ps
CPU time 23.05 seconds
Started Aug 27 01:24:46 PM UTC 24
Finished Aug 27 01:25:10 PM UTC 24
Peak memory 275648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40229784 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.40229784
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.3752417994
Short name T809
Test name
Test status
Simulation time 16109300 ps
CPU time 26.61 seconds
Started Aug 27 01:24:45 PM UTC 24
Finished Aug 27 01:25:13 PM UTC 24
Peak memory 295116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752417994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.3752417994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.2135793366
Short name T811
Test name
Test status
Simulation time 35086000 ps
CPU time 40.9 seconds
Started Aug 27 01:24:35 PM UTC 24
Finished Aug 27 01:25:18 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2135793366 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_
ctrl_disable.2135793366
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.1687098252
Short name T822
Test name
Test status
Simulation time 14427822000 ps
CPU time 124.78 seconds
Started Aug 27 01:24:12 PM UTC 24
Finished Aug 27 01:26:19 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687098252 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.1687098252
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.2008525988
Short name T848
Test name
Test status
Simulation time 2791025100 ps
CPU time 199.17 seconds
Started Aug 27 01:24:19 PM UTC 24
Finished Aug 27 01:27:41 PM UTC 24
Peak memory 293884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008525988 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.2008525988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1177297973
Short name T836
Test name
Test status
Simulation time 25792694700 ps
CPU time 157.06 seconds
Started Aug 27 01:24:20 PM UTC 24
Finished Aug 27 01:27:00 PM UTC 24
Peak memory 304276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1177297973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.flash_ctrl_intr_rd_slow_flash.1177297973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.2055361171
Short name T833
Test name
Test status
Simulation time 144141200 ps
CPU time 154.82 seconds
Started Aug 27 01:24:17 PM UTC 24
Finished Aug 27 01:26:55 PM UTC 24
Peak memory 271392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2055361171 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.2055361171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3855009882
Short name T798
Test name
Test status
Simulation time 20819700 ps
CPU time 23.89 seconds
Started Aug 27 01:24:23 PM UTC 24
Finished Aug 27 01:24:48 PM UTC 24
Peak memory 271208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855009882 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.3855009882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.2090482648
Short name T805
Test name
Test status
Simulation time 75119700 ps
CPU time 40.63 seconds
Started Aug 27 01:24:25 PM UTC 24
Finished Aug 27 01:25:07 PM UTC 24
Peak memory 287796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090482648 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.2090482648
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.82984455
Short name T806
Test name
Test status
Simulation time 253978400 ps
CPU time 37.53 seconds
Started Aug 27 01:24:29 PM UTC 24
Finished Aug 27 01:25:08 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=82984455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctr
l_rw_evict_all_en.82984455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.3469997936
Short name T409
Test name
Test status
Simulation time 2163308000 ps
CPU time 83.73 seconds
Started Aug 27 01:24:44 PM UTC 24
Finished Aug 27 01:26:09 PM UTC 24
Peak memory 275216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469997936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3469997936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.3513947894
Short name T827
Test name
Test status
Simulation time 45542600 ps
CPU time 138.42 seconds
Started Aug 27 01:24:06 PM UTC 24
Finished Aug 27 01:26:27 PM UTC 24
Peak memory 287892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513947894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.3513947894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.1022108654
Short name T814
Test name
Test status
Simulation time 31486900 ps
CPU time 28.62 seconds
Started Aug 27 01:25:14 PM UTC 24
Finished Aug 27 01:25:44 PM UTC 24
Peak memory 275600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022108654 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.1022108654
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.1827676001
Short name T813
Test name
Test status
Simulation time 105042900 ps
CPU time 23.98 seconds
Started Aug 27 01:25:14 PM UTC 24
Finished Aug 27 01:25:40 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827676001 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1827676001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.814482545
Short name T168
Test name
Test status
Simulation time 17718600 ps
CPU time 27.1 seconds
Started Aug 27 01:25:09 PM UTC 24
Finished Aug 27 01:25:37 PM UTC 24
Peak memory 285720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=814482545 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c
trl_disable.814482545
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3500674384
Short name T322
Test name
Test status
Simulation time 8207636900 ps
CPU time 135.72 seconds
Started Aug 27 01:24:52 PM UTC 24
Finished Aug 27 01:27:10 PM UTC 24
Peak memory 273160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500674384 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.3500674384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.3581328850
Short name T840
Test name
Test status
Simulation time 773525600 ps
CPU time 140.67 seconds
Started Aug 27 01:24:57 PM UTC 24
Finished Aug 27 01:27:20 PM UTC 24
Peak memory 302292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581328850 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.3581328850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3000771357
Short name T942
Test name
Test status
Simulation time 12820751500 ps
CPU time 455.17 seconds
Started Aug 27 01:25:03 PM UTC 24
Finished Aug 27 01:32:44 PM UTC 24
Peak memory 293992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3000771357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.flash_ctrl_intr_rd_slow_flash.3000771357
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.4241454953
Short name T179
Test name
Test status
Simulation time 50479100 ps
CPU time 171.38 seconds
Started Aug 27 01:24:56 PM UTC 24
Finished Aug 27 01:27:51 PM UTC 24
Peak memory 275372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241454953 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.4241454953
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.883030562
Short name T852
Test name
Test status
Simulation time 8764751400 ps
CPU time 169.24 seconds
Started Aug 27 01:25:04 PM UTC 24
Finished Aug 27 01:27:56 PM UTC 24
Peak memory 271280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883030562 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.883030562
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.1444569896
Short name T436
Test name
Test status
Simulation time 32576600 ps
CPU time 54.54 seconds
Started Aug 27 01:25:06 PM UTC 24
Finished Aug 27 01:26:02 PM UTC 24
Peak memory 281588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444569896 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.1444569896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.579394030
Short name T816
Test name
Test status
Simulation time 32555300 ps
CPU time 43.66 seconds
Started Aug 27 01:25:08 PM UTC 24
Finished Aug 27 01:25:53 PM UTC 24
Peak memory 287720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=579394030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ct
rl_rw_evict_all_en.579394030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.158236255
Short name T835
Test name
Test status
Simulation time 1664947200 ps
CPU time 104.79 seconds
Started Aug 27 01:25:11 PM UTC 24
Finished Aug 27 01:26:58 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=158236255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.158236255
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.3230009766
Short name T849
Test name
Test status
Simulation time 71801300 ps
CPU time 171.2 seconds
Started Aug 27 01:24:49 PM UTC 24
Finished Aug 27 01:27:43 PM UTC 24
Peak memory 289680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230009766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3230009766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.1786298312
Short name T821
Test name
Test status
Simulation time 19659600 ps
CPU time 22.91 seconds
Started Aug 27 01:25:54 PM UTC 24
Finished Aug 27 01:26:18 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786298312 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.1786298312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.2477547198
Short name T823
Test name
Test status
Simulation time 25943500 ps
CPU time 27.39 seconds
Started Aug 27 01:25:52 PM UTC 24
Finished Aug 27 01:26:21 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2477547198 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.2477547198
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.455618165
Short name T824
Test name
Test status
Simulation time 27995300 ps
CPU time 36.43 seconds
Started Aug 27 01:25:45 PM UTC 24
Finished Aug 27 01:26:23 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=455618165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c
trl_disable.455618165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.3771395731
Short name T861
Test name
Test status
Simulation time 42539046100 ps
CPU time 187.45 seconds
Started Aug 27 01:25:18 PM UTC 24
Finished Aug 27 01:28:28 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3771395731 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.3771395731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2821198295
Short name T853
Test name
Test status
Simulation time 5885490900 ps
CPU time 139.68 seconds
Started Aug 27 01:25:34 PM UTC 24
Finished Aug 27 01:27:57 PM UTC 24
Peak memory 304032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2821198295 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 24.flash_ctrl_intr_rd_slow_flash.2821198295
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.2352268173
Short name T865
Test name
Test status
Simulation time 42484800 ps
CPU time 199.96 seconds
Started Aug 27 01:25:19 PM UTC 24
Finished Aug 27 01:28:42 PM UTC 24
Peak memory 271400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352268173 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.2352268173
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.4093745374
Short name T819
Test name
Test status
Simulation time 69860400 ps
CPU time 23.73 seconds
Started Aug 27 01:25:38 PM UTC 24
Finished Aug 27 01:26:04 PM UTC 24
Peak memory 271228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093745374 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.4093745374
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.3782729836
Short name T438
Test name
Test status
Simulation time 40336100 ps
CPU time 43.99 seconds
Started Aug 27 01:25:39 PM UTC 24
Finished Aug 27 01:26:25 PM UTC 24
Peak memory 287988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782729836 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.3782729836
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.142164352
Short name T829
Test name
Test status
Simulation time 76443900 ps
CPU time 49.28 seconds
Started Aug 27 01:25:41 PM UTC 24
Finished Aug 27 01:26:31 PM UTC 24
Peak memory 287920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=142164352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ct
rl_rw_evict_all_en.142164352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.4264455015
Short name T826
Test name
Test status
Simulation time 18431300 ps
CPU time 67.4 seconds
Started Aug 27 01:25:15 PM UTC 24
Finished Aug 27 01:26:24 PM UTC 24
Peak memory 285832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264455015 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.4264455015
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.3500515754
Short name T832
Test name
Test status
Simulation time 129707800 ps
CPU time 28.29 seconds
Started Aug 27 01:26:23 PM UTC 24
Finished Aug 27 01:26:53 PM UTC 24
Peak memory 269328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500515754 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.3500515754
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.1484196742
Short name T831
Test name
Test status
Simulation time 38654400 ps
CPU time 22.8 seconds
Started Aug 27 01:26:22 PM UTC 24
Finished Aug 27 01:26:46 PM UTC 24
Peak memory 295116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1484196742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.1484196742
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.38324409
Short name T386
Test name
Test status
Simulation time 17098900 ps
CPU time 42.88 seconds
Started Aug 27 01:26:20 PM UTC 24
Finished Aug 27 01:27:04 PM UTC 24
Peak memory 285688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=38324409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ct
rl_disable.38324409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.3802377289
Short name T868
Test name
Test status
Simulation time 18683962700 ps
CPU time 167.96 seconds
Started Aug 27 01:25:58 PM UTC 24
Finished Aug 27 01:28:48 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802377289 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.3802377289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.2698412481
Short name T874
Test name
Test status
Simulation time 4767225700 ps
CPU time 180.79 seconds
Started Aug 27 01:26:03 PM UTC 24
Finished Aug 27 01:29:06 PM UTC 24
Peak memory 302292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698412481 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.2698412481
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.4221346551
Short name T904
Test name
Test status
Simulation time 22844438100 ps
CPU time 278.83 seconds
Started Aug 27 01:26:04 PM UTC 24
Finished Aug 27 01:30:46 PM UTC 24
Peak memory 302000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=4221346551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.flash_ctrl_intr_rd_slow_flash.4221346551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.2837375519
Short name T870
Test name
Test status
Simulation time 43013500 ps
CPU time 171.9 seconds
Started Aug 27 01:26:01 PM UTC 24
Finished Aug 27 01:28:55 PM UTC 24
Peak memory 271400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837375519 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.2837375519
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.595656915
Short name T828
Test name
Test status
Simulation time 22088100 ps
CPU time 15.92 seconds
Started Aug 27 01:26:10 PM UTC 24
Finished Aug 27 01:26:27 PM UTC 24
Peak memory 271432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595656915 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.595656915
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.2391025707
Short name T838
Test name
Test status
Simulation time 45329500 ps
CPU time 51 seconds
Started Aug 27 01:26:13 PM UTC 24
Finished Aug 27 01:27:06 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391025707 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.2391025707
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.3361674188
Short name T851
Test name
Test status
Simulation time 1337334300 ps
CPU time 86.92 seconds
Started Aug 27 01:26:21 PM UTC 24
Finished Aug 27 01:27:50 PM UTC 24
Peak memory 275216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361674188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3361674188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.3858545148
Short name T894
Test name
Test status
Simulation time 23513700 ps
CPU time 258.9 seconds
Started Aug 27 01:25:55 PM UTC 24
Finished Aug 27 01:30:18 PM UTC 24
Peak memory 289876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858545148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.3858545148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.4112498564
Short name T844
Test name
Test status
Simulation time 144321700 ps
CPU time 29.15 seconds
Started Aug 27 01:27:00 PM UTC 24
Finished Aug 27 01:27:31 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112498564 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.4112498564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.1611053820
Short name T842
Test name
Test status
Simulation time 15894300 ps
CPU time 27.06 seconds
Started Aug 27 01:27:00 PM UTC 24
Finished Aug 27 01:27:29 PM UTC 24
Peak memory 295376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611053820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1611053820
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.1795078759
Short name T847
Test name
Test status
Simulation time 16713600 ps
CPU time 41.11 seconds
Started Aug 27 01:26:54 PM UTC 24
Finished Aug 27 01:27:36 PM UTC 24
Peak memory 275708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1795078759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_
ctrl_disable.1795078759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.1404034736
Short name T839
Test name
Test status
Simulation time 948576200 ps
CPU time 51.5 seconds
Started Aug 27 01:26:26 PM UTC 24
Finished Aug 27 01:27:19 PM UTC 24
Peak memory 275468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404034736 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.1404034736
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.2444358598
Short name T889
Test name
Test status
Simulation time 3986939700 ps
CPU time 207.41 seconds
Started Aug 27 01:26:28 PM UTC 24
Finished Aug 27 01:29:58 PM UTC 24
Peak memory 294072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444358598 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.2444358598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3361880327
Short name T916
Test name
Test status
Simulation time 45170625300 ps
CPU time 297.43 seconds
Started Aug 27 01:26:28 PM UTC 24
Finished Aug 27 01:31:29 PM UTC 24
Peak memory 301992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3361880327 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.flash_ctrl_intr_rd_slow_flash.3361880327
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.198361534
Short name T866
Test name
Test status
Simulation time 38639000 ps
CPU time 136.27 seconds
Started Aug 27 01:26:26 PM UTC 24
Finished Aug 27 01:28:44 PM UTC 24
Peak memory 275636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198361534 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.198361534
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.4180819716
Short name T837
Test name
Test status
Simulation time 63613300 ps
CPU time 28.65 seconds
Started Aug 27 01:26:32 PM UTC 24
Finished Aug 27 01:27:02 PM UTC 24
Peak memory 275572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180819716 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.4180819716
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.258830128
Short name T846
Test name
Test status
Simulation time 53556300 ps
CPU time 52.31 seconds
Started Aug 27 01:26:42 PM UTC 24
Finished Aug 27 01:27:36 PM UTC 24
Peak memory 283828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258830128 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.258830128
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.2934869254
Short name T841
Test name
Test status
Simulation time 63198700 ps
CPU time 35.32 seconds
Started Aug 27 01:26:47 PM UTC 24
Finished Aug 27 01:27:24 PM UTC 24
Peak memory 285876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2934869254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c
trl_rw_evict_all_en.2934869254
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.4170811384
Short name T850
Test name
Test status
Simulation time 672997100 ps
CPU time 51.8 seconds
Started Aug 27 01:26:56 PM UTC 24
Finished Aug 27 01:27:50 PM UTC 24
Peak memory 275216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170811384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.4170811384
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.2311438211
Short name T888
Test name
Test status
Simulation time 2733335400 ps
CPU time 209.58 seconds
Started Aug 27 01:26:24 PM UTC 24
Finished Aug 27 01:29:57 PM UTC 24
Peak memory 291852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311438211 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2311438211
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.3319481249
Short name T855
Test name
Test status
Simulation time 48264600 ps
CPU time 23.95 seconds
Started Aug 27 01:27:32 PM UTC 24
Finished Aug 27 01:27:57 PM UTC 24
Peak memory 269304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319481249 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.3319481249
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.1563174352
Short name T854
Test name
Test status
Simulation time 34989000 ps
CPU time 24.84 seconds
Started Aug 27 01:27:31 PM UTC 24
Finished Aug 27 01:27:57 PM UTC 24
Peak memory 295376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563174352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.1563174352
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2633771676
Short name T377
Test name
Test status
Simulation time 10535600 ps
CPU time 35.58 seconds
Started Aug 27 01:27:20 PM UTC 24
Finished Aug 27 01:27:57 PM UTC 24
Peak memory 285916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2633771676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_
ctrl_disable.2633771676
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.1906631806
Short name T862
Test name
Test status
Simulation time 3282468000 ps
CPU time 85.56 seconds
Started Aug 27 01:27:01 PM UTC 24
Finished Aug 27 01:28:30 PM UTC 24
Peak memory 275404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906631806 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.1906631806
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.3187832955
Short name T877
Test name
Test status
Simulation time 2051908400 ps
CPU time 129.77 seconds
Started Aug 27 01:27:03 PM UTC 24
Finished Aug 27 01:29:16 PM UTC 24
Peak memory 302228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187832955 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.3187832955
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.3544299175
Short name T884
Test name
Test status
Simulation time 11330583100 ps
CPU time 157.06 seconds
Started Aug 27 01:27:05 PM UTC 24
Finished Aug 27 01:29:45 PM UTC 24
Peak memory 304076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3544299175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 27.flash_ctrl_intr_rd_slow_flash.3544299175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.3067345220
Short name T891
Test name
Test status
Simulation time 75349600 ps
CPU time 178.34 seconds
Started Aug 27 01:27:03 PM UTC 24
Finished Aug 27 01:30:05 PM UTC 24
Peak memory 271288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067345220 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.3067345220
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.2684596293
Short name T845
Test name
Test status
Simulation time 17908500 ps
CPU time 25.17 seconds
Started Aug 27 01:27:07 PM UTC 24
Finished Aug 27 01:27:33 PM UTC 24
Peak memory 271208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684596293 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.2684596293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.3959242753
Short name T858
Test name
Test status
Simulation time 70972200 ps
CPU time 53.81 seconds
Started Aug 27 01:27:19 PM UTC 24
Finished Aug 27 01:28:15 PM UTC 24
Peak memory 281584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3959242753 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c
trl_rw_evict_all_en.3959242753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.68165340
Short name T876
Test name
Test status
Simulation time 26568051500 ps
CPU time 107.92 seconds
Started Aug 27 01:27:25 PM UTC 24
Finished Aug 27 01:29:16 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68165340 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.68165340
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.4163311746
Short name T919
Test name
Test status
Simulation time 2783249800 ps
CPU time 266.54 seconds
Started Aug 27 01:27:01 PM UTC 24
Finished Aug 27 01:31:33 PM UTC 24
Peak memory 283540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163311746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.4163311746
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.862864706
Short name T860
Test name
Test status
Simulation time 37977900 ps
CPU time 28.48 seconds
Started Aug 27 01:27:58 PM UTC 24
Finished Aug 27 01:28:28 PM UTC 24
Peak memory 269328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862864706 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.862864706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.2694009844
Short name T859
Test name
Test status
Simulation time 17760700 ps
CPU time 26.43 seconds
Started Aug 27 01:27:58 PM UTC 24
Finished Aug 27 01:28:25 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694009844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.2694009844
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.3667749612
Short name T863
Test name
Test status
Simulation time 31333200 ps
CPU time 40.19 seconds
Started Aug 27 01:27:52 PM UTC 24
Finished Aug 27 01:28:34 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3667749612 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_
ctrl_disable.3667749612
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.2286944450
Short name T923
Test name
Test status
Simulation time 2921022800 ps
CPU time 259.63 seconds
Started Aug 27 01:27:34 PM UTC 24
Finished Aug 27 01:31:58 PM UTC 24
Peak memory 275404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2286944450 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.2286944450
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.3406087060
Short name T940
Test name
Test status
Simulation time 24846604800 ps
CPU time 294.7 seconds
Started Aug 27 01:27:42 PM UTC 24
Finished Aug 27 01:32:40 PM UTC 24
Peak memory 302184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3406087060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.flash_ctrl_intr_rd_slow_flash.3406087060
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.719886755
Short name T898
Test name
Test status
Simulation time 60481000 ps
CPU time 170.64 seconds
Started Aug 27 01:27:37 PM UTC 24
Finished Aug 27 01:30:31 PM UTC 24
Peak memory 271268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719886755 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.719886755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.1937614340
Short name T857
Test name
Test status
Simulation time 62009400 ps
CPU time 25.96 seconds
Started Aug 27 01:27:44 PM UTC 24
Finished Aug 27 01:28:11 PM UTC 24
Peak memory 271204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937614340 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.1937614340
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.1849269213
Short name T867
Test name
Test status
Simulation time 79039000 ps
CPU time 52.62 seconds
Started Aug 27 01:27:51 PM UTC 24
Finished Aug 27 01:28:45 PM UTC 24
Peak memory 285616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1849269213 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_c
trl_rw_evict_all_en.1849269213
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.61756983
Short name T391
Test name
Test status
Simulation time 3869429900 ps
CPU time 96.91 seconds
Started Aug 27 01:27:58 PM UTC 24
Finished Aug 27 01:29:37 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61756983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.61756983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.3436970041
Short name T903
Test name
Test status
Simulation time 69027000 ps
CPU time 183.58 seconds
Started Aug 27 01:27:33 PM UTC 24
Finished Aug 27 01:30:40 PM UTC 24
Peak memory 289672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436970041 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.3436970041
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.180373786
Short name T871
Test name
Test status
Simulation time 80135700 ps
CPU time 25.11 seconds
Started Aug 27 01:28:31 PM UTC 24
Finished Aug 27 01:28:57 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180373786 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.180373786
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.1167244479
Short name T872
Test name
Test status
Simulation time 14063200 ps
CPU time 27.89 seconds
Started Aug 27 01:28:30 PM UTC 24
Finished Aug 27 01:28:59 PM UTC 24
Peak memory 295116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167244479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1167244479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.3570384061
Short name T875
Test name
Test status
Simulation time 10532600 ps
CPU time 37.83 seconds
Started Aug 27 01:28:28 PM UTC 24
Finished Aug 27 01:29:08 PM UTC 24
Peak memory 284300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3570384061 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_
ctrl_disable.3570384061
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.2727576494
Short name T878
Test name
Test status
Simulation time 4609871100 ps
CPU time 78.82 seconds
Started Aug 27 01:27:59 PM UTC 24
Finished Aug 27 01:29:20 PM UTC 24
Peak memory 275400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727576494 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.2727576494
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.3346968454
Short name T901
Test name
Test status
Simulation time 3383678400 ps
CPU time 150.39 seconds
Started Aug 27 01:28:00 PM UTC 24
Finished Aug 27 01:30:33 PM UTC 24
Peak memory 293944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346968454 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.3346968454
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.3265297027
Short name T958
Test name
Test status
Simulation time 29279918300 ps
CPU time 306.59 seconds
Started Aug 27 01:28:10 PM UTC 24
Finished Aug 27 01:33:21 PM UTC 24
Peak memory 301988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3265297027 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.flash_ctrl_intr_rd_slow_flash.3265297027
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.2855672087
Short name T914
Test name
Test status
Simulation time 40120600 ps
CPU time 198.39 seconds
Started Aug 27 01:28:00 PM UTC 24
Finished Aug 27 01:31:22 PM UTC 24
Peak memory 271324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855672087 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.2855672087
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.3906879973
Short name T864
Test name
Test status
Simulation time 22492200 ps
CPU time 24.94 seconds
Started Aug 27 01:28:12 PM UTC 24
Finished Aug 27 01:28:38 PM UTC 24
Peak memory 271208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906879973 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.3906879973
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.3366501217
Short name T873
Test name
Test status
Simulation time 29008600 ps
CPU time 46.91 seconds
Started Aug 27 01:28:16 PM UTC 24
Finished Aug 27 01:29:04 PM UTC 24
Peak memory 285684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366501217 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.3366501217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.1219575000
Short name T879
Test name
Test status
Simulation time 36690000 ps
CPU time 52.19 seconds
Started Aug 27 01:28:26 PM UTC 24
Finished Aug 27 01:29:20 PM UTC 24
Peak memory 287924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1219575000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c
trl_rw_evict_all_en.1219575000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.3230940021
Short name T408
Test name
Test status
Simulation time 1316009200 ps
CPU time 92.86 seconds
Started Aug 27 01:28:28 PM UTC 24
Finished Aug 27 01:30:03 PM UTC 24
Peak memory 275412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230940021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3230940021
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.2990419501
Short name T887
Test name
Test status
Simulation time 329265100 ps
CPU time 114.35 seconds
Started Aug 27 01:27:58 PM UTC 24
Finished Aug 27 01:29:54 PM UTC 24
Peak memory 287636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990419501 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.2990419501
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.182008828
Short name T473
Test name
Test status
Simulation time 59644200 ps
CPU time 28.88 seconds
Started Aug 27 12:33:36 PM UTC 24
Finished Aug 27 12:34:07 PM UTC 24
Peak memory 275444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182008828 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.182008828
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.863390834
Short name T471
Test name
Test status
Simulation time 142157400 ps
CPU time 17.1 seconds
Started Aug 27 12:33:18 PM UTC 24
Finished Aug 27 12:33:36 PM UTC 24
Peak memory 273240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863390834 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.863390834
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.15408462
Short name T468
Test name
Test status
Simulation time 27020800 ps
CPU time 15.49 seconds
Started Aug 27 12:32:54 PM UTC 24
Finished Aug 27 12:33:11 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15408462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.15408462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.813547194
Short name T478
Test name
Test status
Simulation time 2899496400 ps
CPU time 262.86 seconds
Started Aug 27 12:30:43 PM UTC 24
Finished Aug 27 12:35:10 PM UTC 24
Peak memory 287736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=813547194 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 3.flash_ctrl_derr_detect.813547194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.1600306811
Short name T104
Test name
Test status
Simulation time 33253300 ps
CPU time 34.25 seconds
Started Aug 27 12:32:16 PM UTC 24
Finished Aug 27 12:32:51 PM UTC 24
Peak memory 285684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1600306811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_disable.1600306811
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.127844959
Short name T238
Test name
Test status
Simulation time 745343200 ps
CPU time 346.11 seconds
Started Aug 27 12:26:57 PM UTC 24
Finished Aug 27 12:32:47 PM UTC 24
Peak memory 275280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127844959 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.127844959
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1668430723
Short name T771
Test name
Test status
Simulation time 29220798200 ps
CPU time 3229 seconds
Started Aug 27 12:28:20 PM UTC 24
Finished Aug 27 01:22:41 PM UTC 24
Peak memory 276000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1668430723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1668430723
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.3958442098
Short name T502
Test name
Test status
Simulation time 572590300 ps
CPU time 963.82 seconds
Started Aug 27 12:28:10 PM UTC 24
Finished Aug 27 12:44:24 PM UTC 24
Peak memory 285524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958442098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.3958442098
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.2647434826
Short name T454
Test name
Test status
Simulation time 711596800 ps
CPU time 39.15 seconds
Started Aug 27 12:27:38 PM UTC 24
Finished Aug 27 12:28:19 PM UTC 24
Peak memory 273228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26
47434826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc
h_code.2647434826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.2381188342
Short name T1127
Test name
Test status
Simulation time 611397755700 ps
CPU time 4321.13 seconds
Started Aug 27 12:27:40 PM UTC 24
Finished Aug 27 01:40:26 PM UTC 24
Peak memory 278384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381188342 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.2381188342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.1173624188
Short name T453
Test name
Test status
Simulation time 49437200 ps
CPU time 101.14 seconds
Started Aug 27 12:26:25 PM UTC 24
Finished Aug 27 12:28:08 PM UTC 24
Peak memory 273296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173624188 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1173624188
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.1053014629
Short name T282
Test name
Test status
Simulation time 10032943900 ps
CPU time 63.65 seconds
Started Aug 27 12:33:34 PM UTC 24
Finished Aug 27 12:34:39 PM UTC 24
Peak memory 277512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1053014629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.1053014629
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3697710134
Short name T278
Test name
Test status
Simulation time 109017600 ps
CPU time 29.2 seconds
Started Aug 27 12:33:24 PM UTC 24
Finished Aug 27 12:33:55 PM UTC 24
Peak memory 275848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3697710134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_hw_read_seed_err.3697710134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.2474953378
Short name T139
Test name
Test status
Simulation time 80148548600 ps
CPU time 809.16 seconds
Started Aug 27 12:27:01 PM UTC 24
Finished Aug 27 12:40:39 PM UTC 24
Peak memory 275172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474953378
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.2474953378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.4109200693
Short name T456
Test name
Test status
Simulation time 9072353800 ps
CPU time 122.46 seconds
Started Aug 27 12:26:56 PM UTC 24
Finished Aug 27 12:29:01 PM UTC 24
Peak memory 273164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4109200693 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.4109200693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.3764409406
Short name T135
Test name
Test status
Simulation time 20877830000 ps
CPU time 539.49 seconds
Started Aug 27 12:31:08 PM UTC 24
Finished Aug 27 12:40:14 PM UTC 24
Peak memory 338940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3764409406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integr
ity.3764409406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.247516318
Short name T341
Test name
Test status
Simulation time 1574788600 ps
CPU time 175.5 seconds
Started Aug 27 12:31:12 PM UTC 24
Finished Aug 27 12:34:10 PM UTC 24
Peak memory 306168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247516318 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.247516318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.36383958
Short name T410
Test name
Test status
Simulation time 23346501200 ps
CPU time 192.61 seconds
Started Aug 27 12:31:22 PM UTC 24
Finished Aug 27 12:34:38 PM UTC 24
Peak memory 304068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=36383958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 3.flash_ctrl_intr_rd_slow_flash.36383958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.2246353107
Short name T467
Test name
Test status
Simulation time 3906977700 ps
CPU time 60.49 seconds
Started Aug 27 12:31:22 PM UTC 24
Finished Aug 27 12:32:24 PM UTC 24
Peak memory 275308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246353107 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.2246353107
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.474404991
Short name T483
Test name
Test status
Simulation time 40102069100 ps
CPU time 321.83 seconds
Started Aug 27 12:31:27 PM UTC 24
Finished Aug 27 12:36:54 PM UTC 24
Peak memory 275404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474404991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.474404991
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.626219395
Short name T460
Test name
Test status
Simulation time 1962328600 ps
CPU time 93.36 seconds
Started Aug 27 12:28:25 PM UTC 24
Finished Aug 27 12:30:00 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=626219395 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.626219395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.3226637368
Short name T472
Test name
Test status
Simulation time 72604000 ps
CPU time 23.24 seconds
Started Aug 27 12:33:19 PM UTC 24
Finished Aug 27 12:33:43 PM UTC 24
Peak memory 271368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3226637368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_lcmgr_intg.3226637368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.4210798394
Short name T162
Test name
Test status
Simulation time 2682887500 ps
CPU time 95.59 seconds
Started Aug 27 12:28:47 PM UTC 24
Finished Aug 27 12:30:25 PM UTC 24
Peak memory 271200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210798394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.4210798394
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.642672633
Short name T125
Test name
Test status
Simulation time 16947720700 ps
CPU time 760.99 seconds
Started Aug 27 12:27:21 PM UTC 24
Finished Aug 27 12:40:12 PM UTC 24
Peak memory 283528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=642672633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_mp_regions.642672633
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.990480496
Short name T75
Test name
Test status
Simulation time 42332100 ps
CPU time 212.45 seconds
Started Aug 27 12:27:06 PM UTC 24
Finished Aug 27 12:30:42 PM UTC 24
Peak memory 271740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990480496 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.990480496
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.828151630
Short name T476
Test name
Test status
Simulation time 1477484000 ps
CPU time 227.89 seconds
Started Aug 27 12:30:56 PM UTC 24
Finished Aug 27 12:34:47 PM UTC 24
Peak memory 304120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=828151630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_oversize_error.828151630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.2685161547
Short name T469
Test name
Test status
Simulation time 2798644400 ps
CPU time 395.5 seconds
Started Aug 27 12:26:36 PM UTC 24
Finished Aug 27 12:33:16 PM UTC 24
Peak memory 275344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685161547 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.2685161547
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.67389935
Short name T308
Test name
Test status
Simulation time 43838500 ps
CPU time 20.1 seconds
Started Aug 27 12:33:12 PM UTC 24
Finished Aug 27 12:33:33 PM UTC 24
Peak memory 273584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=67389935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.67389935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.3436320881
Short name T465
Test name
Test status
Simulation time 155759500 ps
CPU time 25.43 seconds
Started Aug 27 12:31:33 PM UTC 24
Finished Aug 27 12:32:00 PM UTC 24
Peak memory 271236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436320881 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.3436320881
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.236315493
Short name T529
Test name
Test status
Simulation time 376797800 ps
CPU time 1446 seconds
Started Aug 27 12:26:16 PM UTC 24
Finished Aug 27 12:50:37 PM UTC 24
Peak memory 298612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236315493 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.236315493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.423280033
Short name T237
Test name
Test status
Simulation time 2939997700 ps
CPU time 171.54 seconds
Started Aug 27 12:26:25 PM UTC 24
Finished Aug 27 12:29:19 PM UTC 24
Peak memory 273296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423280033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.423280033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.4284412887
Short name T416
Test name
Test status
Simulation time 66065400 ps
CPU time 37.58 seconds
Started Aug 27 12:32:14 PM UTC 24
Finished Aug 27 12:32:53 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4284412887 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.4284412887
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.706435776
Short name T462
Test name
Test status
Simulation time 18920300 ps
CPU time 42.06 seconds
Started Aug 27 12:30:23 PM UTC 24
Finished Aug 27 12:31:07 PM UTC 24
Peak memory 275632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=706435776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_read_word_sweep_derr.706435776
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.170714709
Short name T459
Test name
Test status
Simulation time 160927000 ps
CPU time 38.01 seconds
Started Aug 27 12:29:18 PM UTC 24
Finished Aug 27 12:29:57 PM UTC 24
Peak memory 275440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170714709 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.170714709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.3665240700
Short name T329
Test name
Test status
Simulation time 4352705700 ps
CPU time 138.89 seconds
Started Aug 27 12:29:05 PM UTC 24
Finished Aug 27 12:31:27 PM UTC 24
Peak memory 304188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3665240700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.3665240700
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.1267329704
Short name T470
Test name
Test status
Simulation time 1606540400 ps
CPU time 169.45 seconds
Started Aug 27 12:30:25 PM UTC 24
Finished Aug 27 12:33:18 PM UTC 24
Peak memory 291824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267329704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1267329704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.3887089134
Short name T225
Test name
Test status
Simulation time 453490400 ps
CPU time 119.84 seconds
Started Aug 27 12:29:20 PM UTC 24
Finished Aug 27 12:31:22 PM UTC 24
Peak memory 291840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3887089134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_ro_serr.3887089134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.2912051865
Short name T429
Test name
Test status
Simulation time 4000515900 ps
CPU time 639.05 seconds
Started Aug 27 12:29:16 PM UTC 24
Finished Aug 27 12:40:04 PM UTC 24
Peak memory 330696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912051865 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.2912051865
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.2796236026
Short name T474
Test name
Test status
Simulation time 1452639700 ps
CPU time 220.66 seconds
Started Aug 27 12:30:37 PM UTC 24
Finished Aug 27 12:34:21 PM UTC 24
Peak memory 292092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2796236026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_rw_derr.2796236026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.2738586652
Short name T222
Test name
Test status
Simulation time 45804300 ps
CPU time 36.87 seconds
Started Aug 27 12:31:34 PM UTC 24
Finished Aug 27 12:32:13 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738586652 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.2738586652
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.1803247711
Short name T424
Test name
Test status
Simulation time 45085600 ps
CPU time 51.75 seconds
Started Aug 27 12:32:01 PM UTC 24
Finished Aug 27 12:32:54 PM UTC 24
Peak memory 281520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1803247711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw_evict_all_en.1803247711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.3032799745
Short name T276
Test name
Test status
Simulation time 6486186700 ps
CPU time 237.57 seconds
Started Aug 27 12:29:47 PM UTC 24
Finished Aug 27 12:33:48 PM UTC 24
Peak memory 306176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3032799745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.3032799745
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.147174577
Short name T59
Test name
Test status
Simulation time 1028074300 ps
CPU time 6409.94 seconds
Started Aug 27 12:32:25 PM UTC 24
Finished Aug 27 02:20:19 PM UTC 24
Peak memory 312436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147174577 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.147174577
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.1506011386
Short name T208
Test name
Test status
Simulation time 1060976700 ps
CPU time 78.21 seconds
Started Aug 27 12:32:48 PM UTC 24
Finished Aug 27 12:34:08 PM UTC 24
Peak memory 275408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506011386 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1506011386
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.31233316
Short name T464
Test name
Test status
Simulation time 2280470400 ps
CPU time 89.72 seconds
Started Aug 27 12:30:01 PM UTC 24
Finished Aug 27 12:31:33 PM UTC 24
Peak memory 275456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=312
33316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_serr_
address.31233316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.14880146
Short name T463
Test name
Test status
Simulation time 2334099300 ps
CPU time 81.31 seconds
Started Aug 27 12:29:58 PM UTC 24
Finished Aug 27 12:31:21 PM UTC 24
Peak memory 285820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=14
880146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_serr
_counter.14880146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1100795640
Short name T458
Test name
Test status
Simulation time 219946500 ps
CPU time 182.35 seconds
Started Aug 27 12:26:10 PM UTC 24
Finished Aug 27 12:29:15 PM UTC 24
Peak memory 277396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100795640 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1100795640
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.809059675
Short name T452
Test name
Test status
Simulation time 16011800 ps
CPU time 55.26 seconds
Started Aug 27 12:26:10 PM UTC 24
Finished Aug 27 12:27:07 PM UTC 24
Peak memory 271044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809059675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.809059675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.4115347560
Short name T314
Test name
Test status
Simulation time 65151800 ps
CPU time 283.27 seconds
Started Aug 27 12:32:52 PM UTC 24
Finished Aug 27 12:37:39 PM UTC 24
Peak memory 279380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115347560 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.4115347560
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.3490622578
Short name T451
Test name
Test status
Simulation time 44134600 ps
CPU time 41.41 seconds
Started Aug 27 12:26:17 PM UTC 24
Finished Aug 27 12:27:00 PM UTC 24
Peak memory 271048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490622578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.3490622578
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.2193157807
Short name T384
Test name
Test status
Simulation time 6853136600 ps
CPU time 149.65 seconds
Started Aug 27 12:29:01 PM UTC 24
Finished Aug 27 12:31:33 PM UTC 24
Peak memory 271416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2193157807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.2193157807
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.3025648618
Short name T882
Test name
Test status
Simulation time 65932000 ps
CPU time 21.9 seconds
Started Aug 27 01:29:06 PM UTC 24
Finished Aug 27 01:29:29 PM UTC 24
Peak memory 269584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025648618 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.3025648618
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.2051186853
Short name T880
Test name
Test status
Simulation time 44727300 ps
CPU time 19.21 seconds
Started Aug 27 01:28:59 PM UTC 24
Finished Aug 27 01:29:20 PM UTC 24
Peak memory 295112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051186853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2051186853
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.2533974711
Short name T376
Test name
Test status
Simulation time 22178700 ps
CPU time 33.99 seconds
Started Aug 27 01:28:56 PM UTC 24
Finished Aug 27 01:29:31 PM UTC 24
Peak memory 285884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2533974711 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_
ctrl_disable.2533974711
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.3424381984
Short name T319
Test name
Test status
Simulation time 2646566500 ps
CPU time 45.82 seconds
Started Aug 27 01:28:39 PM UTC 24
Finished Aug 27 01:29:26 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3424381984 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.3424381984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.1457842708
Short name T930
Test name
Test status
Simulation time 2974824600 ps
CPU time 201.33 seconds
Started Aug 27 01:28:45 PM UTC 24
Finished Aug 27 01:32:10 PM UTC 24
Peak memory 302076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457842708 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.1457842708
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.629546138
Short name T934
Test name
Test status
Simulation time 16041133500 ps
CPU time 205.77 seconds
Started Aug 27 01:28:47 PM UTC 24
Finished Aug 27 01:32:16 PM UTC 24
Peak memory 304296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=629546138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 30.flash_ctrl_intr_rd_slow_flash.629546138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.1919320499
Short name T931
Test name
Test status
Simulation time 42710700 ps
CPU time 204.01 seconds
Started Aug 27 01:28:42 PM UTC 24
Finished Aug 27 01:32:10 PM UTC 24
Peak memory 271292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919320499 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.1919320499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.2029707710
Short name T883
Test name
Test status
Simulation time 96379800 ps
CPU time 39.29 seconds
Started Aug 27 01:28:51 PM UTC 24
Finished Aug 27 01:29:32 PM UTC 24
Peak memory 281844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2029707710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c
trl_rw_evict_all_en.2029707710
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.2965077026
Short name T404
Test name
Test status
Simulation time 3700573800 ps
CPU time 68.32 seconds
Started Aug 27 01:28:58 PM UTC 24
Finished Aug 27 01:30:08 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2965077026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.2965077026
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.1060312854
Short name T897
Test name
Test status
Simulation time 41779400 ps
CPU time 112.1 seconds
Started Aug 27 01:28:35 PM UTC 24
Finished Aug 27 01:30:29 PM UTC 24
Peak memory 277396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1060312854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.1060312854
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.160977510
Short name T885
Test name
Test status
Simulation time 45200700 ps
CPU time 20.09 seconds
Started Aug 27 01:29:32 PM UTC 24
Finished Aug 27 01:29:53 PM UTC 24
Peak memory 269564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160977510 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.160977510
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.958301594
Short name T890
Test name
Test status
Simulation time 50766500 ps
CPU time 28.57 seconds
Started Aug 27 01:29:30 PM UTC 24
Finished Aug 27 01:30:00 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958301594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.958301594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.217385744
Short name T929
Test name
Test status
Simulation time 4304673700 ps
CPU time 176.38 seconds
Started Aug 27 01:29:09 PM UTC 24
Finished Aug 27 01:32:08 PM UTC 24
Peak memory 271112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217385744 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.217385744
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.4251491138
Short name T947
Test name
Test status
Simulation time 3138928100 ps
CPU time 216.24 seconds
Started Aug 27 01:29:17 PM UTC 24
Finished Aug 27 01:32:57 PM UTC 24
Peak memory 302104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251491138 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.4251491138
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.1894907813
Short name T970
Test name
Test status
Simulation time 12435885300 ps
CPU time 265.65 seconds
Started Aug 27 01:29:21 PM UTC 24
Finished Aug 27 01:33:50 PM UTC 24
Peak memory 301496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1894907813 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 31.flash_ctrl_intr_rd_slow_flash.1894907813
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.1937216546
Short name T320
Test name
Test status
Simulation time 76326200 ps
CPU time 201.95 seconds
Started Aug 27 01:29:16 PM UTC 24
Finished Aug 27 01:32:41 PM UTC 24
Peak memory 271480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937216546 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.1937216546
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.3504321379
Short name T433
Test name
Test status
Simulation time 46578800 ps
CPU time 37.56 seconds
Started Aug 27 01:29:21 PM UTC 24
Finished Aug 27 01:29:59 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504321379 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.3504321379
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.2397491766
Short name T892
Test name
Test status
Simulation time 65696000 ps
CPU time 43.93 seconds
Started Aug 27 01:29:21 PM UTC 24
Finished Aug 27 01:30:06 PM UTC 24
Peak memory 285220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2397491766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c
trl_rw_evict_all_en.2397491766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.2070637556
Short name T397
Test name
Test status
Simulation time 2667164500 ps
CPU time 99.81 seconds
Started Aug 27 01:29:27 PM UTC 24
Finished Aug 27 01:31:09 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070637556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2070637556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.2547687332
Short name T921
Test name
Test status
Simulation time 172333400 ps
CPU time 151.45 seconds
Started Aug 27 01:29:08 PM UTC 24
Finished Aug 27 01:31:42 PM UTC 24
Peak memory 277384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547687332 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.2547687332
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.1283806309
Short name T896
Test name
Test status
Simulation time 40014500 ps
CPU time 26.63 seconds
Started Aug 27 01:30:00 PM UTC 24
Finished Aug 27 01:30:28 PM UTC 24
Peak memory 269300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283806309 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.1283806309
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.3788381428
Short name T895
Test name
Test status
Simulation time 19309500 ps
CPU time 18.69 seconds
Started Aug 27 01:29:59 PM UTC 24
Finished Aug 27 01:30:19 PM UTC 24
Peak memory 295312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3788381428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.3788381428
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.1081460649
Short name T900
Test name
Test status
Simulation time 752501700 ps
CPU time 52.97 seconds
Started Aug 27 01:29:37 PM UTC 24
Finished Aug 27 01:30:32 PM UTC 24
Peak memory 273160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1081460649 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.1081460649
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.2976452400
Short name T926
Test name
Test status
Simulation time 711722800 ps
CPU time 134.29 seconds
Started Aug 27 01:29:46 PM UTC 24
Finished Aug 27 01:32:03 PM UTC 24
Peak memory 293884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976452400 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.2976452400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1445528005
Short name T980
Test name
Test status
Simulation time 25166745400 ps
CPU time 262.96 seconds
Started Aug 27 01:29:52 PM UTC 24
Finished Aug 27 01:34:19 PM UTC 24
Peak memory 302036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1445528005 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 32.flash_ctrl_intr_rd_slow_flash.1445528005
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.1192394310
Short name T323
Test name
Test status
Simulation time 154245000 ps
CPU time 154.9 seconds
Started Aug 27 01:29:46 PM UTC 24
Finished Aug 27 01:32:23 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192394310 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.1192394310
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.2049051988
Short name T899
Test name
Test status
Simulation time 31223700 ps
CPU time 36.11 seconds
Started Aug 27 01:29:54 PM UTC 24
Finished Aug 27 01:30:32 PM UTC 24
Peak memory 281584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049051988 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.2049051988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.2738186025
Short name T902
Test name
Test status
Simulation time 81274700 ps
CPU time 37.11 seconds
Started Aug 27 01:29:56 PM UTC 24
Finished Aug 27 01:30:34 PM UTC 24
Peak memory 285712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2738186025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c
trl_rw_evict_all_en.2738186025
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.3418582478
Short name T910
Test name
Test status
Simulation time 826179800 ps
CPU time 68.02 seconds
Started Aug 27 01:29:58 PM UTC 24
Finished Aug 27 01:31:07 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3418582478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.3418582478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.3282856115
Short name T932
Test name
Test status
Simulation time 55471200 ps
CPU time 156.78 seconds
Started Aug 27 01:29:33 PM UTC 24
Finished Aug 27 01:32:13 PM UTC 24
Peak memory 287636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282856115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.3282856115
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.4130313705
Short name T905
Test name
Test status
Simulation time 32695700 ps
CPU time 15.18 seconds
Started Aug 27 01:30:30 PM UTC 24
Finished Aug 27 01:30:47 PM UTC 24
Peak memory 269520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130313705 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.4130313705
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.2780432146
Short name T906
Test name
Test status
Simulation time 39831700 ps
CPU time 21.2 seconds
Started Aug 27 01:30:29 PM UTC 24
Finished Aug 27 01:30:52 PM UTC 24
Peak memory 284940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780432146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.2780432146
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.3595143287
Short name T908
Test name
Test status
Simulation time 35792100 ps
CPU time 37.94 seconds
Started Aug 27 01:30:20 PM UTC 24
Finished Aug 27 01:30:59 PM UTC 24
Peak memory 285820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3595143287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_
ctrl_disable.3595143287
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.682130537
Short name T917
Test name
Test status
Simulation time 4785810600 ps
CPU time 84.66 seconds
Started Aug 27 01:30:04 PM UTC 24
Finished Aug 27 01:31:31 PM UTC 24
Peak memory 273164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682130537 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.682130537
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.70499904
Short name T984
Test name
Test status
Simulation time 20362116300 ps
CPU time 251 seconds
Started Aug 27 01:30:07 PM UTC 24
Finished Aug 27 01:34:22 PM UTC 24
Peak memory 293904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70499904 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.70499904
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.1401394626
Short name T1009
Test name
Test status
Simulation time 23794872200 ps
CPU time 313.78 seconds
Started Aug 27 01:30:09 PM UTC 24
Finished Aug 27 01:35:27 PM UTC 24
Peak memory 304048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1401394626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.flash_ctrl_intr_rd_slow_flash.1401394626
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.2307792819
Short name T943
Test name
Test status
Simulation time 38457300 ps
CPU time 156.49 seconds
Started Aug 27 01:30:06 PM UTC 24
Finished Aug 27 01:32:45 PM UTC 24
Peak memory 271388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307792819 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.2307792819
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.2308607868
Short name T909
Test name
Test status
Simulation time 167205100 ps
CPU time 39.88 seconds
Started Aug 27 01:30:19 PM UTC 24
Finished Aug 27 01:31:01 PM UTC 24
Peak memory 287988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308607868 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.2308607868
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.3600139088
Short name T907
Test name
Test status
Simulation time 27412800 ps
CPU time 33.26 seconds
Started Aug 27 01:30:20 PM UTC 24
Finished Aug 27 01:30:54 PM UTC 24
Peak memory 285704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3600139088 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c
trl_rw_evict_all_en.3600139088
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.4191040966
Short name T393
Test name
Test status
Simulation time 5549626400 ps
CPU time 100.16 seconds
Started Aug 27 01:30:23 PM UTC 24
Finished Aug 27 01:32:05 PM UTC 24
Peak memory 275276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191040966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.4191040966
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.2316107207
Short name T937
Test name
Test status
Simulation time 32258600 ps
CPU time 145.38 seconds
Started Aug 27 01:30:01 PM UTC 24
Finished Aug 27 01:32:29 PM UTC 24
Peak memory 287632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316107207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.2316107207
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.2380407706
Short name T911
Test name
Test status
Simulation time 28280500 ps
CPU time 18.86 seconds
Started Aug 27 01:31:00 PM UTC 24
Finished Aug 27 01:31:20 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380407706 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.2380407706
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.1181996758
Short name T915
Test name
Test status
Simulation time 65382900 ps
CPU time 31.24 seconds
Started Aug 27 01:30:55 PM UTC 24
Finished Aug 27 01:31:27 PM UTC 24
Peak memory 295312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181996758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.1181996758
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.3238138838
Short name T372
Test name
Test status
Simulation time 112065200 ps
CPU time 27.76 seconds
Started Aug 27 01:30:47 PM UTC 24
Finished Aug 27 01:31:16 PM UTC 24
Peak memory 275416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3238138838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_
ctrl_disable.3238138838
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.2131130002
Short name T922
Test name
Test status
Simulation time 17299358700 ps
CPU time 71.46 seconds
Started Aug 27 01:30:32 PM UTC 24
Finished Aug 27 01:31:46 PM UTC 24
Peak memory 275400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2131130002 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.2131130002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.3400378385
Short name T93
Test name
Test status
Simulation time 11578279100 ps
CPU time 217.61 seconds
Started Aug 27 01:30:35 PM UTC 24
Finished Aug 27 01:34:16 PM UTC 24
Peak memory 304264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400378385 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.3400378385
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3648422549
Short name T967
Test name
Test status
Simulation time 23108658500 ps
CPU time 186.89 seconds
Started Aug 27 01:30:35 PM UTC 24
Finished Aug 27 01:33:45 PM UTC 24
Peak memory 304048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3648422549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.flash_ctrl_intr_rd_slow_flash.3648422549
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.590699245
Short name T977
Test name
Test status
Simulation time 49697400 ps
CPU time 212.17 seconds
Started Aug 27 01:30:34 PM UTC 24
Finished Aug 27 01:34:09 PM UTC 24
Peak memory 275484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590699245 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.590699245
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.4280280368
Short name T920
Test name
Test status
Simulation time 72127800 ps
CPU time 55.6 seconds
Started Aug 27 01:30:40 PM UTC 24
Finished Aug 27 01:31:37 PM UTC 24
Peak memory 281588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280280368 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.4280280368
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.640002627
Short name T420
Test name
Test status
Simulation time 29854200 ps
CPU time 46.89 seconds
Started Aug 27 01:30:47 PM UTC 24
Finished Aug 27 01:31:36 PM UTC 24
Peak memory 281808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=640002627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ct
rl_rw_evict_all_en.640002627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.1717436002
Short name T941
Test name
Test status
Simulation time 7277970600 ps
CPU time 108.29 seconds
Started Aug 27 01:30:52 PM UTC 24
Finished Aug 27 01:32:43 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717436002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.1717436002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.2875248389
Short name T954
Test name
Test status
Simulation time 57668900 ps
CPU time 159.28 seconds
Started Aug 27 01:30:32 PM UTC 24
Finished Aug 27 01:33:14 PM UTC 24
Peak memory 289832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875248389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.2875248389
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.2662661689
Short name T924
Test name
Test status
Simulation time 106839700 ps
CPU time 25.14 seconds
Started Aug 27 01:31:32 PM UTC 24
Finished Aug 27 01:31:58 PM UTC 24
Peak memory 275444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662661689 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.2662661689
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.2712799507
Short name T925
Test name
Test status
Simulation time 52515400 ps
CPU time 26.9 seconds
Started Aug 27 01:31:31 PM UTC 24
Finished Aug 27 01:31:59 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2712799507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2712799507
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.4099712078
Short name T927
Test name
Test status
Simulation time 11683000 ps
CPU time 41.89 seconds
Started Aug 27 01:31:23 PM UTC 24
Finished Aug 27 01:32:07 PM UTC 24
Peak memory 275412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4099712078 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_
ctrl_disable.4099712078
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.1984913217
Short name T938
Test name
Test status
Simulation time 25458145900 ps
CPU time 82.24 seconds
Started Aug 27 01:31:08 PM UTC 24
Finished Aug 27 01:32:32 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984913217 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.1984913217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.2987760866
Short name T962
Test name
Test status
Simulation time 2759751500 ps
CPU time 135.71 seconds
Started Aug 27 01:31:17 PM UTC 24
Finished Aug 27 01:33:36 PM UTC 24
Peak memory 306168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987760866 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.2987760866
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1272246826
Short name T1056
Test name
Test status
Simulation time 64521676600 ps
CPU time 310.65 seconds
Started Aug 27 01:31:21 PM UTC 24
Finished Aug 27 01:36:35 PM UTC 24
Peak memory 301988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1272246826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.flash_ctrl_intr_rd_slow_flash.1272246826
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.1877069299
Short name T975
Test name
Test status
Simulation time 41733200 ps
CPU time 170.31 seconds
Started Aug 27 01:31:09 PM UTC 24
Finished Aug 27 01:34:02 PM UTC 24
Peak memory 275176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877069299 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.1877069299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.1159463289
Short name T933
Test name
Test status
Simulation time 27530400 ps
CPU time 51.02 seconds
Started Aug 27 01:31:22 PM UTC 24
Finished Aug 27 01:32:15 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159463289 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.1159463289
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.3174324177
Short name T928
Test name
Test status
Simulation time 27303500 ps
CPU time 43.85 seconds
Started Aug 27 01:31:22 PM UTC 24
Finished Aug 27 01:32:07 PM UTC 24
Peak memory 287664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3174324177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c
trl_rw_evict_all_en.3174324177
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.4255330292
Short name T394
Test name
Test status
Simulation time 1781252300 ps
CPU time 101.32 seconds
Started Aug 27 01:31:28 PM UTC 24
Finished Aug 27 01:33:12 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255330292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.4255330292
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.2917147373
Short name T976
Test name
Test status
Simulation time 157497300 ps
CPU time 181.25 seconds
Started Aug 27 01:31:02 PM UTC 24
Finished Aug 27 01:34:06 PM UTC 24
Peak memory 289800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2917147373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.2917147373
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.3863119992
Short name T935
Test name
Test status
Simulation time 148204300 ps
CPU time 19.16 seconds
Started Aug 27 01:32:08 PM UTC 24
Finished Aug 27 01:32:28 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863119992 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.3863119992
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.3459498091
Short name T936
Test name
Test status
Simulation time 15971900 ps
CPU time 21.6 seconds
Started Aug 27 01:32:06 PM UTC 24
Finished Aug 27 01:32:29 PM UTC 24
Peak memory 295376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459498091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.3459498091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.2241167243
Short name T939
Test name
Test status
Simulation time 10598100 ps
CPU time 35.17 seconds
Started Aug 27 01:32:00 PM UTC 24
Finished Aug 27 01:32:37 PM UTC 24
Peak memory 285688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2241167243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_
ctrl_disable.2241167243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.1246267380
Short name T949
Test name
Test status
Simulation time 4357306500 ps
CPU time 80.5 seconds
Started Aug 27 01:31:37 PM UTC 24
Finished Aug 27 01:32:59 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1246267380 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.1246267380
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.74681686
Short name T963
Test name
Test status
Simulation time 548012300 ps
CPU time 111.36 seconds
Started Aug 27 01:31:42 PM UTC 24
Finished Aug 27 01:33:36 PM UTC 24
Peak memory 306324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74681686 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.74681686
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.510189986
Short name T325
Test name
Test status
Simulation time 43141595400 ps
CPU time 176.01 seconds
Started Aug 27 01:31:47 PM UTC 24
Finished Aug 27 01:34:46 PM UTC 24
Peak memory 304068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=510189986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 36.flash_ctrl_intr_rd_slow_flash.510189986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.3319576266
Short name T994
Test name
Test status
Simulation time 39386200 ps
CPU time 185.39 seconds
Started Aug 27 01:31:38 PM UTC 24
Finished Aug 27 01:34:47 PM UTC 24
Peak memory 275492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319576266 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.3319576266
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.161745214
Short name T432
Test name
Test status
Simulation time 28629600 ps
CPU time 46.64 seconds
Started Aug 27 01:31:59 PM UTC 24
Finished Aug 27 01:32:48 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161745214 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.161745214
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.1983074983
Short name T944
Test name
Test status
Simulation time 58809200 ps
CPU time 48.02 seconds
Started Aug 27 01:31:59 PM UTC 24
Finished Aug 27 01:32:49 PM UTC 24
Peak memory 285640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1983074983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c
trl_rw_evict_all_en.1983074983
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.1334602984
Short name T969
Test name
Test status
Simulation time 1791239800 ps
CPU time 100.78 seconds
Started Aug 27 01:32:03 PM UTC 24
Finished Aug 27 01:33:47 PM UTC 24
Peak memory 275408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334602984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.1334602984
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.244164930
Short name T983
Test name
Test status
Simulation time 23065900 ps
CPU time 165.25 seconds
Started Aug 27 01:31:34 PM UTC 24
Finished Aug 27 01:34:22 PM UTC 24
Peak memory 289684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244164930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.244164930
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.1053628230
Short name T951
Test name
Test status
Simulation time 40456000 ps
CPU time 28.68 seconds
Started Aug 27 01:32:30 PM UTC 24
Finished Aug 27 01:33:00 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053628230 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.1053628230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.1126961279
Short name T945
Test name
Test status
Simulation time 42436200 ps
CPU time 21.31 seconds
Started Aug 27 01:32:29 PM UTC 24
Finished Aug 27 01:32:52 PM UTC 24
Peak memory 295312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1126961279 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1126961279
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.476371014
Short name T960
Test name
Test status
Simulation time 2669930700 ps
CPU time 79.57 seconds
Started Aug 27 01:32:09 PM UTC 24
Finished Aug 27 01:33:30 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=476371014 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.476371014
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.676200006
Short name T1017
Test name
Test status
Simulation time 6260859100 ps
CPU time 200.7 seconds
Started Aug 27 01:32:11 PM UTC 24
Finished Aug 27 01:35:35 PM UTC 24
Peak memory 293912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=676200006 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.676200006
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.2134500134
Short name T986
Test name
Test status
Simulation time 5601259600 ps
CPU time 130.57 seconds
Started Aug 27 01:32:14 PM UTC 24
Finished Aug 27 01:34:26 PM UTC 24
Peak memory 304084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2134500134 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.flash_ctrl_intr_rd_slow_flash.2134500134
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.1830099479
Short name T1002
Test name
Test status
Simulation time 36180100 ps
CPU time 175.85 seconds
Started Aug 27 01:32:11 PM UTC 24
Finished Aug 27 01:35:10 PM UTC 24
Peak memory 271396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830099479 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.1830099479
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.4277689970
Short name T946
Test name
Test status
Simulation time 28765200 ps
CPU time 35.78 seconds
Started Aug 27 01:32:16 PM UTC 24
Finished Aug 27 01:32:53 PM UTC 24
Peak memory 283636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277689970 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.4277689970
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.1225291073
Short name T948
Test name
Test status
Simulation time 29448400 ps
CPU time 39.67 seconds
Started Aug 27 01:32:17 PM UTC 24
Finished Aug 27 01:32:58 PM UTC 24
Peak memory 285708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1225291073 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_c
trl_rw_evict_all_en.1225291073
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.2527398285
Short name T399
Test name
Test status
Simulation time 1515292400 ps
CPU time 84.1 seconds
Started Aug 27 01:32:29 PM UTC 24
Finished Aug 27 01:33:55 PM UTC 24
Peak memory 275412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527398285 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2527398285
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.755485283
Short name T992
Test name
Test status
Simulation time 21881800 ps
CPU time 154.63 seconds
Started Aug 27 01:32:09 PM UTC 24
Finished Aug 27 01:34:46 PM UTC 24
Peak memory 289676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755485283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.755485283
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.437639693
Short name T956
Test name
Test status
Simulation time 24228100 ps
CPU time 20.82 seconds
Started Aug 27 01:32:54 PM UTC 24
Finished Aug 27 01:33:16 PM UTC 24
Peak memory 269328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437639693 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.437639693
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.2297444020
Short name T955
Test name
Test status
Simulation time 85530800 ps
CPU time 20.78 seconds
Started Aug 27 01:32:53 PM UTC 24
Finished Aug 27 01:33:15 PM UTC 24
Peak memory 284940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2297444020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2297444020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.3441494086
Short name T961
Test name
Test status
Simulation time 81981600 ps
CPU time 41.92 seconds
Started Aug 27 01:32:49 PM UTC 24
Finished Aug 27 01:33:32 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3441494086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_
ctrl_disable.3441494086
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.2740035722
Short name T1006
Test name
Test status
Simulation time 7713130200 ps
CPU time 155.47 seconds
Started Aug 27 01:32:38 PM UTC 24
Finished Aug 27 01:35:16 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740035722 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.2740035722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.1609168747
Short name T1037
Test name
Test status
Simulation time 2000557700 ps
CPU time 206.21 seconds
Started Aug 27 01:32:42 PM UTC 24
Finished Aug 27 01:36:11 PM UTC 24
Peak memory 302076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609168747 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.1609168747
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.463732159
Short name T94
Test name
Test status
Simulation time 12505706200 ps
CPU time 286.63 seconds
Started Aug 27 01:32:43 PM UTC 24
Finished Aug 27 01:37:34 PM UTC 24
Peak memory 306120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=463732159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 38.flash_ctrl_intr_rd_slow_flash.463732159
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.1268663801
Short name T1012
Test name
Test status
Simulation time 41983400 ps
CPU time 165.74 seconds
Started Aug 27 01:32:41 PM UTC 24
Finished Aug 27 01:35:30 PM UTC 24
Peak memory 271480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268663801 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.1268663801
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.4233342908
Short name T959
Test name
Test status
Simulation time 78286300 ps
CPU time 35.71 seconds
Started Aug 27 01:32:45 PM UTC 24
Finished Aug 27 01:33:23 PM UTC 24
Peak memory 283632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233342908 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.4233342908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.2059292453
Short name T957
Test name
Test status
Simulation time 29755800 ps
CPU time 33.53 seconds
Started Aug 27 01:32:46 PM UTC 24
Finished Aug 27 01:33:20 PM UTC 24
Peak memory 287924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2059292453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c
trl_rw_evict_all_en.2059292453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.2227135458
Short name T978
Test name
Test status
Simulation time 451065100 ps
CPU time 78.95 seconds
Started Aug 27 01:32:50 PM UTC 24
Finished Aug 27 01:34:11 PM UTC 24
Peak memory 275412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227135458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.2227135458
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.272608681
Short name T1000
Test name
Test status
Simulation time 61115400 ps
CPU time 148.18 seconds
Started Aug 27 01:32:33 PM UTC 24
Finished Aug 27 01:35:03 PM UTC 24
Peak memory 287640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272608681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.272608681
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.2187850658
Short name T964
Test name
Test status
Simulation time 70907600 ps
CPU time 21 seconds
Started Aug 27 01:33:16 PM UTC 24
Finished Aug 27 01:33:39 PM UTC 24
Peak memory 275644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187850658 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.2187850658
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.3831957951
Short name T968
Test name
Test status
Simulation time 16856300 ps
CPU time 29.33 seconds
Started Aug 27 01:33:15 PM UTC 24
Finished Aug 27 01:33:46 PM UTC 24
Peak memory 295116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831957951 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3831957951
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.2442335462
Short name T971
Test name
Test status
Simulation time 15087300 ps
CPU time 37.94 seconds
Started Aug 27 01:33:13 PM UTC 24
Finished Aug 27 01:33:53 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2442335462 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_
ctrl_disable.2442335462
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.1516351698
Short name T1011
Test name
Test status
Simulation time 17580294300 ps
CPU time 146.93 seconds
Started Aug 27 01:32:58 PM UTC 24
Finished Aug 27 01:35:28 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516351698 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.1516351698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.2256621476
Short name T1087
Test name
Test status
Simulation time 26654897500 ps
CPU time 272.07 seconds
Started Aug 27 01:33:01 PM UTC 24
Finished Aug 27 01:37:37 PM UTC 24
Peak memory 294076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256621476 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.2256621476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1126976901
Short name T1028
Test name
Test status
Simulation time 6031792200 ps
CPU time 172.65 seconds
Started Aug 27 01:33:02 PM UTC 24
Finished Aug 27 01:35:57 PM UTC 24
Peak memory 302064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1126976901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.flash_ctrl_intr_rd_slow_flash.1126976901
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.1170078597
Short name T1027
Test name
Test status
Simulation time 377457400 ps
CPU time 172.56 seconds
Started Aug 27 01:33:01 PM UTC 24
Finished Aug 27 01:35:56 PM UTC 24
Peak memory 271288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170078597 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.1170078597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.3298556630
Short name T965
Test name
Test status
Simulation time 71443400 ps
CPU time 37.45 seconds
Started Aug 27 01:33:04 PM UTC 24
Finished Aug 27 01:33:43 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298556630 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.3298556630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.3476797421
Short name T981
Test name
Test status
Simulation time 642346100 ps
CPU time 65.03 seconds
Started Aug 27 01:33:13 PM UTC 24
Finished Aug 27 01:34:20 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476797421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.3476797421
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.3460512664
Short name T997
Test name
Test status
Simulation time 50693000 ps
CPU time 116.1 seconds
Started Aug 27 01:32:57 PM UTC 24
Finished Aug 27 01:34:56 PM UTC 24
Peak memory 287816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460512664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.3460512664
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.4195972761
Short name T494
Test name
Test status
Simulation time 56569600 ps
CPU time 27.83 seconds
Started Aug 27 12:41:23 PM UTC 24
Finished Aug 27 12:41:52 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195972761 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.4195972761
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.2202058175
Short name T492
Test name
Test status
Simulation time 60790900 ps
CPU time 17.89 seconds
Started Aug 27 12:41:13 PM UTC 24
Finished Aug 27 12:41:32 PM UTC 24
Peak memory 275292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202058175 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.2202058175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.767837180
Short name T378
Test name
Test status
Simulation time 15478900 ps
CPU time 28.32 seconds
Started Aug 27 12:40:45 PM UTC 24
Finished Aug 27 12:41:15 PM UTC 24
Peak memory 295188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767837180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.767837180
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3504151643
Short name T499
Test name
Test status
Simulation time 4281499900 ps
CPU time 235.29 seconds
Started Aug 27 12:39:10 PM UTC 24
Finished Aug 27 12:43:09 PM UTC 24
Peak memory 291824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3504151643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 4.flash_ctrl_derr_detect.3504151643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.2075267347
Short name T187
Test name
Test status
Simulation time 81322100 ps
CPU time 45.86 seconds
Started Aug 27 12:40:25 PM UTC 24
Finished Aug 27 12:41:13 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2075267347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_disable.2075267347
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.2916443752
Short name T150
Test name
Test status
Simulation time 8179030000 ps
CPU time 441.48 seconds
Started Aug 27 12:34:19 PM UTC 24
Finished Aug 27 12:41:46 PM UTC 24
Peak memory 275468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916443752 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.2916443752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.4246281030
Short name T856
Test name
Test status
Simulation time 26061168800 ps
CPU time 3132.97 seconds
Started Aug 27 12:35:14 PM UTC 24
Finished Aug 27 01:27:59 PM UTC 24
Peak memory 276204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246281030 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.4246281030
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.3485601938
Short name T91
Test name
Test status
Simulation time 1135880100 ps
CPU time 2975.39 seconds
Started Aug 27 12:35:11 PM UTC 24
Finished Aug 27 01:25:17 PM UTC 24
Peak memory 276088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34
85601938 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_error_prog_type.3485601938
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.1841754520
Short name T551
Test name
Test status
Simulation time 2292101000 ps
CPU time 1211.32 seconds
Started Aug 27 12:35:14 PM UTC 24
Finished Aug 27 12:55:39 PM UTC 24
Peak memory 285712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841754520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1841754520
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.328749170
Short name T479
Test name
Test status
Simulation time 306631700 ps
CPU time 22.82 seconds
Started Aug 27 12:34:49 PM UTC 24
Finished Aug 27 12:35:13 PM UTC 24
Peak memory 275356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=32
8749170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetch
_code.328749170
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1505324239
Short name T495
Test name
Test status
Simulation time 318637600 ps
CPU time 57.92 seconds
Started Aug 27 12:41:01 PM UTC 24
Finished Aug 27 12:42:01 PM UTC 24
Peak memory 273616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505324
239 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_f
s_sup.1505324239
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.1114758485
Short name T132
Test name
Test status
Simulation time 364897161100 ps
CPU time 2212.36 seconds
Started Aug 27 12:34:54 PM UTC 24
Finished Aug 27 01:12:09 PM UTC 24
Peak memory 278072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114758485 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.1114758485
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1614245598
Short name T481
Test name
Test status
Simulation time 63568500 ps
CPU time 152.43 seconds
Started Aug 27 12:33:56 PM UTC 24
Finished Aug 27 12:36:31 PM UTC 24
Peak memory 275336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614245598 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1614245598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.1639285755
Short name T88
Test name
Test status
Simulation time 10014785900 ps
CPU time 235 seconds
Started Aug 27 12:41:21 PM UTC 24
Finished Aug 27 12:45:20 PM UTC 24
Peak memory 297944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1639285755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.1639285755
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.587314356
Short name T279
Test name
Test status
Simulation time 47696000 ps
CPU time 20.11 seconds
Started Aug 27 12:41:20 PM UTC 24
Finished Aug 27 12:41:42 PM UTC 24
Peak memory 269444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=587314356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4
.flash_ctrl_hw_read_seed_err.587314356
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.1818431642
Short name T190
Test name
Test status
Simulation time 40126869700 ps
CPU time 848.52 seconds
Started Aug 27 12:34:22 PM UTC 24
Finished Aug 27 12:48:40 PM UTC 24
Peak memory 275436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818431642
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.1818431642
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.2299539883
Short name T303
Test name
Test status
Simulation time 2009935100 ps
CPU time 60.14 seconds
Started Aug 27 12:34:11 PM UTC 24
Finished Aug 27 12:35:13 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2299539883 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.2299539883
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.1661162149
Short name T513
Test name
Test status
Simulation time 7757576500 ps
CPU time 486.53 seconds
Started Aug 27 12:39:18 PM UTC 24
Finished Aug 27 12:47:31 PM UTC 24
Peak memory 334848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1661162149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integr
ity.1661162149
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.1433131486
Short name T35
Test name
Test status
Simulation time 664307400 ps
CPU time 135.04 seconds
Started Aug 27 12:39:39 PM UTC 24
Finished Aug 27 12:41:57 PM UTC 24
Peak memory 302068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433131486 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.1433131486
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.1420903165
Short name T339
Test name
Test status
Simulation time 23713561400 ps
CPU time 279.62 seconds
Started Aug 27 12:39:50 PM UTC 24
Finished Aug 27 12:44:34 PM UTC 24
Peak memory 293800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1420903165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_intr_rd_slow_flash.1420903165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.145843643
Short name T141
Test name
Test status
Simulation time 7180442000 ps
CPU time 82.48 seconds
Started Aug 27 12:39:39 PM UTC 24
Finished Aug 27 12:41:04 PM UTC 24
Peak memory 271232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145843643 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.145843643
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.247161674
Short name T500
Test name
Test status
Simulation time 26433428600 ps
CPU time 222.41 seconds
Started Aug 27 12:40:04 PM UTC 24
Finished Aug 27 12:43:50 PM UTC 24
Peak memory 275376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=247161674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.247161674
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.157084898
Short name T286
Test name
Test status
Simulation time 49156900 ps
CPU time 26.99 seconds
Started Aug 27 12:41:15 PM UTC 24
Finished Aug 27 12:41:44 PM UTC 24
Peak memory 271364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=157084898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_lcmgr_intg.157084898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.3685557884
Short name T126
Test name
Test status
Simulation time 57569441500 ps
CPU time 396.1 seconds
Started Aug 27 12:34:40 PM UTC 24
Finished Aug 27 12:41:21 PM UTC 24
Peak memory 283528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3685557884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_mp_regions.3685557884
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.62804148
Short name T77
Test name
Test status
Simulation time 35747900 ps
CPU time 268.2 seconds
Started Aug 27 12:34:39 PM UTC 24
Finished Aug 27 12:39:12 PM UTC 24
Peak memory 271068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=62804148 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.62804148
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.3138066035
Short name T498
Test name
Test status
Simulation time 24174171800 ps
CPU time 227.14 seconds
Started Aug 27 12:39:12 PM UTC 24
Finished Aug 27 12:43:03 PM UTC 24
Peak memory 292020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3138066035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_oversize_error.3138066035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.3766390194
Short name T509
Test name
Test status
Simulation time 1396421100 ps
CPU time 735.31 seconds
Started Aug 27 12:34:09 PM UTC 24
Finished Aug 27 12:46:32 PM UTC 24
Peak memory 275344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766390194 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.3766390194
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.634211102
Short name T493
Test name
Test status
Simulation time 16390700 ps
CPU time 25.53 seconds
Started Aug 27 12:41:10 PM UTC 24
Finished Aug 27 12:41:37 PM UTC 24
Peak memory 275600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=634211102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.634211102
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.3107186598
Short name T138
Test name
Test status
Simulation time 32836700 ps
CPU time 18.74 seconds
Started Aug 27 12:40:15 PM UTC 24
Finished Aug 27 12:40:35 PM UTC 24
Peak memory 271412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107186598 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.3107186598
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.4053090623
Short name T550
Test name
Test status
Simulation time 82467800 ps
CPU time 1290.02 seconds
Started Aug 27 12:33:48 PM UTC 24
Finished Aug 27 12:55:33 PM UTC 24
Peak memory 293840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053090623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.4053090623
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.345562229
Short name T480
Test name
Test status
Simulation time 335972300 ps
CPU time 123.78 seconds
Started Aug 27 12:34:08 PM UTC 24
Finished Aug 27 12:36:14 PM UTC 24
Peak memory 273296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345562229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.345562229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.1423025388
Short name T161
Test name
Test status
Simulation time 67510100 ps
CPU time 61.91 seconds
Started Aug 27 12:40:16 PM UTC 24
Finished Aug 27 12:41:20 PM UTC 24
Peak memory 287988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423025388 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.1423025388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.2712737200
Short name T485
Test name
Test status
Simulation time 18282900 ps
CPU time 34 seconds
Started Aug 27 12:38:15 PM UTC 24
Finished Aug 27 12:38:50 PM UTC 24
Peak memory 275576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2712737200 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_read_word_sweep_derr.2712737200
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.2876988757
Short name T484
Test name
Test status
Simulation time 88508600 ps
CPU time 26.23 seconds
Started Aug 27 12:37:14 PM UTC 24
Finished Aug 27 12:37:41 PM UTC 24
Peak memory 275668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2876988757 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.2876988757
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.2660573631
Short name T487
Test name
Test status
Simulation time 515908600 ps
CPU time 140.05 seconds
Started Aug 27 12:36:55 PM UTC 24
Finished Aug 27 12:39:17 PM UTC 24
Peak memory 291792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2660573631 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.2660573631
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.3127098622
Short name T489
Test name
Test status
Simulation time 2715602000 ps
CPU time 150.19 seconds
Started Aug 27 12:38:37 PM UTC 24
Finished Aug 27 12:41:10 PM UTC 24
Peak memory 291832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127098622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.3127098622
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.222058261
Short name T140
Test name
Test status
Simulation time 1523044400 ps
CPU time 184.68 seconds
Started Aug 27 12:37:36 PM UTC 24
Finished Aug 27 12:40:44 PM UTC 24
Peak memory 291832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=222058261 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_
ctrl_ro_serr.222058261
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.11401398
Short name T217
Test name
Test status
Simulation time 2974842300 ps
CPU time 234.82 seconds
Started Aug 27 12:38:51 PM UTC 24
Finished Aug 27 12:42:49 PM UTC 24
Peak memory 300024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=11401398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/nu
ll -cm_name 4.flash_ctrl_rw_derr.11401398
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.322611290
Short name T142
Test name
Test status
Simulation time 67491700 ps
CPU time 52.83 seconds
Started Aug 27 12:40:15 PM UTC 24
Finished Aug 27 12:41:09 PM UTC 24
Peak memory 287728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322611290 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.322611290
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.2207524248
Short name T42
Test name
Test status
Simulation time 29707700 ps
CPU time 42.91 seconds
Started Aug 27 12:40:16 PM UTC 24
Finished Aug 27 12:41:01 PM UTC 24
Peak memory 285940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2207524248 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw_evict_all_en.2207524248
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.474065302
Short name T491
Test name
Test status
Simulation time 34083727500 ps
CPU time 226.63 seconds
Started Aug 27 12:37:40 PM UTC 24
Finished Aug 27 12:41:30 PM UTC 24
Peak memory 308224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=474065302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.474065302
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.1224593508
Short name T395
Test name
Test status
Simulation time 3255285500 ps
CPU time 76.16 seconds
Started Aug 27 12:40:40 PM UTC 24
Finished Aug 27 12:41:58 PM UTC 24
Peak memory 273168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224593508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1224593508
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.3593316144
Short name T486
Test name
Test status
Simulation time 2373248900 ps
CPU time 82.01 seconds
Started Aug 27 12:37:45 PM UTC 24
Finished Aug 27 12:39:09 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359
3316144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser
r_address.3593316144
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.1845898346
Short name T488
Test name
Test status
Simulation time 1542413600 ps
CPU time 113.11 seconds
Started Aug 27 12:37:42 PM UTC 24
Finished Aug 27 12:39:38 PM UTC 24
Peak memory 285712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18
45898346 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_se
rr_counter.1845898346
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.4212540153
Short name T482
Test name
Test status
Simulation time 49276500 ps
CPU time 176.05 seconds
Started Aug 27 12:33:37 PM UTC 24
Finished Aug 27 12:36:37 PM UTC 24
Peak memory 287640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4212540153 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.4212540153
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.435641165
Short name T475
Test name
Test status
Simulation time 19557200 ps
CPU time 53.21 seconds
Started Aug 27 12:33:44 PM UTC 24
Finished Aug 27 12:34:39 PM UTC 24
Peak memory 271048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435641165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.435641165
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.1431824178
Short name T950
Test name
Test status
Simulation time 1730321800 ps
CPU time 3104.03 seconds
Started Aug 27 12:40:42 PM UTC 24
Finished Aug 27 01:33:00 PM UTC 24
Peak memory 304144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431824178 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.1431824178
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.2342427482
Short name T477
Test name
Test status
Simulation time 23084400 ps
CPU time 56.53 seconds
Started Aug 27 12:33:55 PM UTC 24
Finished Aug 27 12:34:53 PM UTC 24
Peak memory 273104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342427482 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.2342427482
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.3500280656
Short name T974
Test name
Test status
Simulation time 48038700 ps
CPU time 27.92 seconds
Started Aug 27 01:33:33 PM UTC 24
Finished Aug 27 01:34:02 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500280656 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.3500280656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.1587032651
Short name T972
Test name
Test status
Simulation time 45469400 ps
CPU time 24.65 seconds
Started Aug 27 01:33:31 PM UTC 24
Finished Aug 27 01:33:58 PM UTC 24
Peak memory 284940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587032651 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.1587032651
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.3157721564
Short name T973
Test name
Test status
Simulation time 11829200 ps
CPU time 36.66 seconds
Started Aug 27 01:33:22 PM UTC 24
Finished Aug 27 01:34:00 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3157721564 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_
ctrl_disable.3157721564
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.3948780805
Short name T1067
Test name
Test status
Simulation time 3202972100 ps
CPU time 218.05 seconds
Started Aug 27 01:33:18 PM UTC 24
Finished Aug 27 01:36:59 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948780805 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.3948780805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.1109179293
Short name T1039
Test name
Test status
Simulation time 80995800 ps
CPU time 169.86 seconds
Started Aug 27 01:33:21 PM UTC 24
Finished Aug 27 01:36:13 PM UTC 24
Peak memory 271284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109179293 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.1109179293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.43661022
Short name T1057
Test name
Test status
Simulation time 232611500 ps
CPU time 198.2 seconds
Started Aug 27 01:33:17 PM UTC 24
Finished Aug 27 01:36:38 PM UTC 24
Peak memory 289680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43661022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.43661022
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.3178521800
Short name T966
Test name
Test status
Simulation time 24474500 ps
CPU time 23.24 seconds
Started Aug 27 01:33:47 PM UTC 24
Finished Aug 27 01:34:11 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178521800 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.3178521800
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.1623759304
Short name T979
Test name
Test status
Simulation time 13142700 ps
CPU time 27.05 seconds
Started Aug 27 01:33:47 PM UTC 24
Finished Aug 27 01:34:15 PM UTC 24
Peak memory 295176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623759304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.1623759304
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.2294327805
Short name T918
Test name
Test status
Simulation time 20993500 ps
CPU time 27.59 seconds
Started Aug 27 01:33:44 PM UTC 24
Finished Aug 27 01:34:13 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2294327805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_
ctrl_disable.2294327805
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.3752230464
Short name T1020
Test name
Test status
Simulation time 7060916900 ps
CPU time 118.44 seconds
Started Aug 27 01:33:37 PM UTC 24
Finished Aug 27 01:35:38 PM UTC 24
Peak memory 273356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752230464 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.3752230464
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.4096515466
Short name T1071
Test name
Test status
Simulation time 138201200 ps
CPU time 205.33 seconds
Started Aug 27 01:33:40 PM UTC 24
Finished Aug 27 01:37:09 PM UTC 24
Peak memory 271400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096515466 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.4096515466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.1759119797
Short name T400
Test name
Test status
Simulation time 2634396700 ps
CPU time 72.47 seconds
Started Aug 27 01:33:45 PM UTC 24
Finished Aug 27 01:35:00 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759119797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.1759119797
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.3926783487
Short name T1075
Test name
Test status
Simulation time 115009100 ps
CPU time 215.44 seconds
Started Aug 27 01:33:37 PM UTC 24
Finished Aug 27 01:37:15 PM UTC 24
Peak memory 289684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926783487 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3926783487
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.1124602662
Short name T982
Test name
Test status
Simulation time 116308900 ps
CPU time 17.67 seconds
Started Aug 27 01:34:03 PM UTC 24
Finished Aug 27 01:34:22 PM UTC 24
Peak memory 269324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124602662 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.1124602662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.221636139
Short name T985
Test name
Test status
Simulation time 48092600 ps
CPU time 22.51 seconds
Started Aug 27 01:34:01 PM UTC 24
Finished Aug 27 01:34:24 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221636139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.221636139
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.1964124226
Short name T374
Test name
Test status
Simulation time 11003200 ps
CPU time 26.22 seconds
Started Aug 27 01:33:56 PM UTC 24
Finished Aug 27 01:34:24 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1964124226 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_
ctrl_disable.1964124226
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.888209751
Short name T1018
Test name
Test status
Simulation time 12032447600 ps
CPU time 102.82 seconds
Started Aug 27 01:33:51 PM UTC 24
Finished Aug 27 01:35:36 PM UTC 24
Peak memory 273160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=888209751 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.888209751
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.2763295804
Short name T1064
Test name
Test status
Simulation time 148754400 ps
CPU time 177.72 seconds
Started Aug 27 01:33:53 PM UTC 24
Finished Aug 27 01:36:54 PM UTC 24
Peak memory 271736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763295804 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.2763295804
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.4224635967
Short name T1005
Test name
Test status
Simulation time 1275556900 ps
CPU time 73.19 seconds
Started Aug 27 01:33:58 PM UTC 24
Finished Aug 27 01:35:13 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224635967 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.4224635967
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.2940621488
Short name T1035
Test name
Test status
Simulation time 117208100 ps
CPU time 134.32 seconds
Started Aug 27 01:33:48 PM UTC 24
Finished Aug 27 01:36:04 PM UTC 24
Peak memory 287628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940621488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.2940621488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.2921921900
Short name T991
Test name
Test status
Simulation time 82166800 ps
CPU time 23.7 seconds
Started Aug 27 01:34:16 PM UTC 24
Finished Aug 27 01:34:41 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921921900 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.2921921900
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.82674864
Short name T989
Test name
Test status
Simulation time 15002100 ps
CPU time 22.02 seconds
Started Aug 27 01:34:14 PM UTC 24
Finished Aug 27 01:34:37 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82674864 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.82674864
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.200896587
Short name T996
Test name
Test status
Simulation time 12857400 ps
CPU time 39.73 seconds
Started Aug 27 01:34:11 PM UTC 24
Finished Aug 27 01:34:53 PM UTC 24
Peak memory 285628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=200896587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_c
trl_disable.200896587
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.4173217341
Short name T1003
Test name
Test status
Simulation time 1792392000 ps
CPU time 61.45 seconds
Started Aug 27 01:34:07 PM UTC 24
Finished Aug 27 01:35:10 PM UTC 24
Peak memory 275404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4173217341 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.4173217341
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.2062831335
Short name T1024
Test name
Test status
Simulation time 41312078500 ps
CPU time 95.99 seconds
Started Aug 27 01:34:12 PM UTC 24
Finished Aug 27 01:35:50 PM UTC 24
Peak memory 275408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062831335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.2062831335
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.68963000
Short name T1047
Test name
Test status
Simulation time 30294500 ps
CPU time 140.38 seconds
Started Aug 27 01:34:04 PM UTC 24
Finished Aug 27 01:36:27 PM UTC 24
Peak memory 287632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68963000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-s
im-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.68963000
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.1010990135
Short name T993
Test name
Test status
Simulation time 54413400 ps
CPU time 20.37 seconds
Started Aug 27 01:34:25 PM UTC 24
Finished Aug 27 01:34:46 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010990135 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.1010990135
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.3824391085
Short name T995
Test name
Test status
Simulation time 26340800 ps
CPU time 26.17 seconds
Started Aug 27 01:34:24 PM UTC 24
Finished Aug 27 01:34:51 PM UTC 24
Peak memory 295176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824391085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3824391085
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.3482678225
Short name T998
Test name
Test status
Simulation time 20530700 ps
CPU time 37.41 seconds
Started Aug 27 01:34:22 PM UTC 24
Finished Aug 27 01:35:01 PM UTC 24
Peak memory 275740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3482678225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_
ctrl_disable.3482678225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.2196728677
Short name T1014
Test name
Test status
Simulation time 2109840100 ps
CPU time 68.93 seconds
Started Aug 27 01:34:20 PM UTC 24
Finished Aug 27 01:35:31 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196728677 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.2196728677
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.546360585
Short name T1080
Test name
Test status
Simulation time 112355200 ps
CPU time 177.63 seconds
Started Aug 27 01:34:21 PM UTC 24
Finished Aug 27 01:37:22 PM UTC 24
Peak memory 271072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546360585 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.546360585
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.2551344997
Short name T1013
Test name
Test status
Simulation time 2370158700 ps
CPU time 65.83 seconds
Started Aug 27 01:34:22 PM UTC 24
Finished Aug 27 01:35:30 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551344997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.2551344997
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.4144199794
Short name T1083
Test name
Test status
Simulation time 101473900 ps
CPU time 189.07 seconds
Started Aug 27 01:34:17 PM UTC 24
Finished Aug 27 01:37:29 PM UTC 24
Peak memory 277396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144199794 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.4144199794
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.2393124174
Short name T1001
Test name
Test status
Simulation time 267120300 ps
CPU time 22.52 seconds
Started Aug 27 01:34:42 PM UTC 24
Finished Aug 27 01:35:06 PM UTC 24
Peak memory 269500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393124174 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.2393124174
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.4051588698
Short name T999
Test name
Test status
Simulation time 13177600 ps
CPU time 19.52 seconds
Started Aug 27 01:34:41 PM UTC 24
Finished Aug 27 01:35:02 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051588698 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.4051588698
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.234493691
Short name T1004
Test name
Test status
Simulation time 25862800 ps
CPU time 36.79 seconds
Started Aug 27 01:34:34 PM UTC 24
Finished Aug 27 01:35:13 PM UTC 24
Peak memory 285720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=234493691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_c
trl_disable.234493691
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.3220274092
Short name T1051
Test name
Test status
Simulation time 1955860300 ps
CPU time 122.98 seconds
Started Aug 27 01:34:27 PM UTC 24
Finished Aug 27 01:36:32 PM UTC 24
Peak memory 275468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220274092 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.3220274092
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.3693142316
Short name T1074
Test name
Test status
Simulation time 205738200 ps
CPU time 157.56 seconds
Started Aug 27 01:34:31 PM UTC 24
Finished Aug 27 01:37:11 PM UTC 24
Peak memory 271288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693142316 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.3693142316
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.113970024
Short name T1038
Test name
Test status
Simulation time 2195548600 ps
CPU time 91.79 seconds
Started Aug 27 01:34:38 PM UTC 24
Finished Aug 27 01:36:12 PM UTC 24
Peak memory 275212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113970024 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.113970024
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.1779019161
Short name T1019
Test name
Test status
Simulation time 33552700 ps
CPU time 69.65 seconds
Started Aug 27 01:34:25 PM UTC 24
Finished Aug 27 01:35:36 PM UTC 24
Peak memory 283540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779019161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.1779019161
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.3963352855
Short name T1007
Test name
Test status
Simulation time 281528500 ps
CPU time 18.96 seconds
Started Aug 27 01:34:57 PM UTC 24
Finished Aug 27 01:35:17 PM UTC 24
Peak memory 269324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963352855 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.3963352855
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.530779588
Short name T1010
Test name
Test status
Simulation time 13094700 ps
CPU time 32.07 seconds
Started Aug 27 01:34:54 PM UTC 24
Finished Aug 27 01:35:27 PM UTC 24
Peak memory 295176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530779588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.530779588
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.1680089561
Short name T1008
Test name
Test status
Simulation time 14047100 ps
CPU time 29.82 seconds
Started Aug 27 01:34:47 PM UTC 24
Finished Aug 27 01:35:19 PM UTC 24
Peak memory 285624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1680089561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_
ctrl_disable.1680089561
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.947241977
Short name T1089
Test name
Test status
Simulation time 9084778500 ps
CPU time 179.09 seconds
Started Aug 27 01:34:47 PM UTC 24
Finished Aug 27 01:37:49 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947241977 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.947241977
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1451649125
Short name T1088
Test name
Test status
Simulation time 80056200 ps
CPU time 177.12 seconds
Started Aug 27 01:34:47 PM UTC 24
Finished Aug 27 01:37:47 PM UTC 24
Peak memory 271548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1451649125 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.1451649125
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.2462573350
Short name T1032
Test name
Test status
Simulation time 3540700800 ps
CPU time 66.97 seconds
Started Aug 27 01:34:53 PM UTC 24
Finished Aug 27 01:36:02 PM UTC 24
Peak memory 275216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462573350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.2462573350
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.1866910091
Short name T1026
Test name
Test status
Simulation time 45761000 ps
CPU time 66.48 seconds
Started Aug 27 01:34:47 PM UTC 24
Finished Aug 27 01:35:56 PM UTC 24
Peak memory 285568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1866910091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1866910091
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.1732655142
Short name T1016
Test name
Test status
Simulation time 165197900 ps
CPU time 20.23 seconds
Started Aug 27 01:35:11 PM UTC 24
Finished Aug 27 01:35:32 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732655142 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.1732655142
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.123807939
Short name T1015
Test name
Test status
Simulation time 26941900 ps
CPU time 19.39 seconds
Started Aug 27 01:35:11 PM UTC 24
Finished Aug 27 01:35:31 PM UTC 24
Peak memory 295312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123807939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.123807939
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.299969635
Short name T1021
Test name
Test status
Simulation time 11468500 ps
CPU time 33.51 seconds
Started Aug 27 01:35:04 PM UTC 24
Finished Aug 27 01:35:39 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=299969635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_c
trl_disable.299969635
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.475959400
Short name T1104
Test name
Test status
Simulation time 3737135300 ps
CPU time 225.34 seconds
Started Aug 27 01:35:02 PM UTC 24
Finished Aug 27 01:38:51 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475959400 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.475959400
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.843339910
Short name T1091
Test name
Test status
Simulation time 136846400 ps
CPU time 173.5 seconds
Started Aug 27 01:35:02 PM UTC 24
Finished Aug 27 01:37:59 PM UTC 24
Peak memory 271392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843339910 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.843339910
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.3302279630
Short name T405
Test name
Test status
Simulation time 2538075400 ps
CPU time 81.61 seconds
Started Aug 27 01:35:07 PM UTC 24
Finished Aug 27 01:36:30 PM UTC 24
Peak memory 273172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3302279630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.3302279630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.3324252735
Short name T1033
Test name
Test status
Simulation time 70184300 ps
CPU time 62 seconds
Started Aug 27 01:35:00 PM UTC 24
Finished Aug 27 01:36:04 PM UTC 24
Peak memory 283540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324252735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3324252735
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.1351207766
Short name T1022
Test name
Test status
Simulation time 40834400 ps
CPU time 15.72 seconds
Started Aug 27 01:35:28 PM UTC 24
Finished Aug 27 01:35:45 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351207766 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.1351207766
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.2901596133
Short name T1023
Test name
Test status
Simulation time 85855000 ps
CPU time 21.02 seconds
Started Aug 27 01:35:28 PM UTC 24
Finished Aug 27 01:35:50 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901596133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2901596133
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.4159020909
Short name T1029
Test name
Test status
Simulation time 14237000 ps
CPU time 37.68 seconds
Started Aug 27 01:35:19 PM UTC 24
Finished Aug 27 01:35:58 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4159020909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_
ctrl_disable.4159020909
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.334901493
Short name T1078
Test name
Test status
Simulation time 1462636200 ps
CPU time 122.34 seconds
Started Aug 27 01:35:14 PM UTC 24
Finished Aug 27 01:37:19 PM UTC 24
Peak memory 271108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334901493 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.334901493
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.2625201272
Short name T1092
Test name
Test status
Simulation time 135968300 ps
CPU time 164.08 seconds
Started Aug 27 01:35:16 PM UTC 24
Finished Aug 27 01:38:03 PM UTC 24
Peak memory 271740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625201272 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.2625201272
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.1413425907
Short name T1045
Test name
Test status
Simulation time 2890655400 ps
CPU time 60.47 seconds
Started Aug 27 01:35:20 PM UTC 24
Finished Aug 27 01:36:22 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413425907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1413425907
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.575831799
Short name T1066
Test name
Test status
Simulation time 60230700 ps
CPU time 102.02 seconds
Started Aug 27 01:35:14 PM UTC 24
Finished Aug 27 01:36:58 PM UTC 24
Peak memory 287632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575831799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.575831799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.1311541359
Short name T1030
Test name
Test status
Simulation time 54235400 ps
CPU time 21.17 seconds
Started Aug 27 01:35:36 PM UTC 24
Finished Aug 27 01:35:59 PM UTC 24
Peak memory 269328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311541359 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.1311541359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.127787845
Short name T1036
Test name
Test status
Simulation time 41180200 ps
CPU time 32.48 seconds
Started Aug 27 01:35:33 PM UTC 24
Finished Aug 27 01:36:07 PM UTC 24
Peak memory 295176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127787845 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.127787845
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.1248778948
Short name T1041
Test name
Test status
Simulation time 23861800 ps
CPU time 42.08 seconds
Started Aug 27 01:35:32 PM UTC 24
Finished Aug 27 01:36:15 PM UTC 24
Peak memory 285692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1248778948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_
ctrl_disable.1248778948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.4243532269
Short name T1084
Test name
Test status
Simulation time 4916595700 ps
CPU time 119.86 seconds
Started Aug 27 01:35:31 PM UTC 24
Finished Aug 27 01:37:33 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4243532269 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.4243532269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2696095809
Short name T1090
Test name
Test status
Simulation time 233899500 ps
CPU time 140.53 seconds
Started Aug 27 01:35:31 PM UTC 24
Finished Aug 27 01:37:53 PM UTC 24
Peak memory 271400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696095809 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.2696095809
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.2983323559
Short name T1060
Test name
Test status
Simulation time 772901400 ps
CPU time 71.97 seconds
Started Aug 27 01:35:32 PM UTC 24
Finished Aug 27 01:36:46 PM UTC 24
Peak memory 275476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2983323559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.2983323559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.3308020733
Short name T1055
Test name
Test status
Simulation time 20257400 ps
CPU time 64.35 seconds
Started Aug 27 01:35:29 PM UTC 24
Finished Aug 27 01:36:35 PM UTC 24
Peak memory 285588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3308020733 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.3308020733
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.2198663300
Short name T507
Test name
Test status
Simulation time 56462200 ps
CPU time 23.72 seconds
Started Aug 27 12:45:13 PM UTC 24
Finished Aug 27 12:45:38 PM UTC 24
Peak memory 275452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198663300 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.2198663300
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.82367049
Short name T506
Test name
Test status
Simulation time 53698400 ps
CPU time 21.05 seconds
Started Aug 27 12:44:51 PM UTC 24
Finished Aug 27 12:45:13 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82367049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.82367049
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1530709615
Short name T102
Test name
Test status
Simulation time 15574300 ps
CPU time 36.72 seconds
Started Aug 27 12:44:34 PM UTC 24
Finished Aug 27 12:45:12 PM UTC 24
Peak memory 285684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1530709615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c
trl_disable.1530709615
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.3863326499
Short name T988
Test name
Test status
Simulation time 48650998200 ps
CPU time 3128.72 seconds
Started Aug 27 12:41:53 PM UTC 24
Finished Aug 27 01:34:34 PM UTC 24
Peak memory 273220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863326499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.3863326499
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.862313835
Short name T583
Test name
Test status
Simulation time 1181401400 ps
CPU time 1147.83 seconds
Started Aug 27 12:41:46 PM UTC 24
Finished Aug 27 01:01:06 PM UTC 24
Peak memory 285516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862313835 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/fl
ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.862313835
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.394662535
Short name T496
Test name
Test status
Simulation time 283156700 ps
CPU time 34.03 seconds
Started Aug 27 12:41:45 PM UTC 24
Finished Aug 27 12:42:20 PM UTC 24
Peak memory 275348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39
4662535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetch
_code.394662535
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.3300041511
Short name T89
Test name
Test status
Simulation time 10017010500 ps
CPU time 216.48 seconds
Started Aug 27 12:45:04 PM UTC 24
Finished Aug 27 12:48:44 PM UTC 24
Peak memory 312240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3300041511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.3300041511
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.1639095339
Short name T280
Test name
Test status
Simulation time 14949100 ps
CPU time 27.72 seconds
Started Aug 27 12:45:01 PM UTC 24
Finished Aug 27 12:45:30 PM UTC 24
Peak memory 275592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1639095339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_hw_read_seed_err.1639095339
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.3369270556
Short name T191
Test name
Test status
Simulation time 40125662700 ps
CPU time 751.81 seconds
Started Aug 27 12:41:38 PM UTC 24
Finished Aug 27 12:54:18 PM UTC 24
Peak memory 275436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369270556
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.3369270556
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.1603845753
Short name T497
Test name
Test status
Simulation time 4277120100 ps
CPU time 55.23 seconds
Started Aug 27 12:41:37 PM UTC 24
Finished Aug 27 12:42:34 PM UTC 24
Peak memory 271120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603845753 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.1603845753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.652806218
Short name T512
Test name
Test status
Simulation time 5525017200 ps
CPU time 202.13 seconds
Started Aug 27 12:43:51 PM UTC 24
Finished Aug 27 12:47:16 PM UTC 24
Peak memory 304056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=652806218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 5.flash_ctrl_intr_rd_slow_flash.652806218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.4146476264
Short name T505
Test name
Test status
Simulation time 2361397800 ps
CPU time 79.35 seconds
Started Aug 27 12:43:39 PM UTC 24
Finished Aug 27 12:45:00 PM UTC 24
Peak memory 271240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4146476264 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.4146476264
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.82136694
Short name T520
Test name
Test status
Simulation time 20866239800 ps
CPU time 336.9 seconds
Started Aug 27 12:43:58 PM UTC 24
Finished Aug 27 12:49:39 PM UTC 24
Peak memory 275376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=82136694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.82136694
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.1503034217
Short name T414
Test name
Test status
Simulation time 2990981700 ps
CPU time 97.06 seconds
Started Aug 27 12:41:58 PM UTC 24
Finished Aug 27 12:43:37 PM UTC 24
Peak memory 275204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503034217 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.1503034217
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1835538478
Short name T287
Test name
Test status
Simulation time 24286300 ps
CPU time 23.39 seconds
Started Aug 27 12:44:58 PM UTC 24
Finished Aug 27 12:45:22 PM UTC 24
Peak memory 275472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1835538478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_lcmgr_intg.1835538478
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.2210828449
Short name T127
Test name
Test status
Simulation time 27675141900 ps
CPU time 608.89 seconds
Started Aug 27 12:41:43 PM UTC 24
Finished Aug 27 12:51:59 PM UTC 24
Peak memory 283536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2210828449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_mp_regions.2210828449
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.3672841994
Short name T170
Test name
Test status
Simulation time 138392000 ps
CPU time 188.34 seconds
Started Aug 27 12:41:39 PM UTC 24
Finished Aug 27 12:44:50 PM UTC 24
Peak memory 271396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672841994 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.3672841994
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.1516516594
Short name T223
Test name
Test status
Simulation time 735994000 ps
CPU time 412.06 seconds
Started Aug 27 12:41:33 PM UTC 24
Finished Aug 27 12:48:30 PM UTC 24
Peak memory 275272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516516594 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.1516516594
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.3419865230
Short name T503
Test name
Test status
Simulation time 35767600 ps
CPU time 24.54 seconds
Started Aug 27 12:43:59 PM UTC 24
Finished Aug 27 12:44:25 PM UTC 24
Peak memory 271212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3419865230 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.3419865230
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.3141367066
Short name T131
Test name
Test status
Simulation time 6150273800 ps
CPU time 1601.92 seconds
Started Aug 27 12:41:31 PM UTC 24
Finished Aug 27 01:08:30 PM UTC 24
Peak memory 296080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141367066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3141367066
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.3824561795
Short name T437
Test name
Test status
Simulation time 153936900 ps
CPU time 58.87 seconds
Started Aug 27 12:44:26 PM UTC 24
Finished Aug 27 12:45:27 PM UTC 24
Peak memory 287924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3824561795 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.3824561795
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.231569827
Short name T501
Test name
Test status
Simulation time 5474623900 ps
CPU time 114.06 seconds
Started Aug 27 12:42:01 PM UTC 24
Finished Aug 27 12:43:58 PM UTC 24
Peak memory 308244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=231569827 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.231569827
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.1299298699
Short name T210
Test name
Test status
Simulation time 2572418100 ps
CPU time 180.72 seconds
Started Aug 27 12:43:04 PM UTC 24
Finished Aug 27 12:46:08 PM UTC 24
Peak memory 291960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299298699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.1299298699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.4051591359
Short name T504
Test name
Test status
Simulation time 1205401500 ps
CPU time 116.07 seconds
Started Aug 27 12:42:35 PM UTC 24
Finished Aug 27 12:44:33 PM UTC 24
Peak memory 306176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4051591359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_ro_serr.4051591359
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.1069464069
Short name T517
Test name
Test status
Simulation time 3265703300 ps
CPU time 408.91 seconds
Started Aug 27 12:42:21 PM UTC 24
Finished Aug 27 12:49:16 PM UTC 24
Peak memory 324544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069464069 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.1069464069
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.3419893378
Short name T226
Test name
Test status
Simulation time 2952015500 ps
CPU time 214.7 seconds
Started Aug 27 12:43:05 PM UTC 24
Finished Aug 27 12:46:43 PM UTC 24
Peak memory 295924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3419893378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.flash_ctrl_rw_derr.3419893378
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.706758218
Short name T439
Test name
Test status
Simulation time 44406100 ps
CPU time 44.2 seconds
Started Aug 27 12:44:11 PM UTC 24
Finished Aug 27 12:44:57 PM UTC 24
Peak memory 287792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706758218 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.706758218
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.3830785857
Short name T316
Test name
Test status
Simulation time 86293600 ps
CPU time 36.43 seconds
Started Aug 27 12:44:25 PM UTC 24
Finished Aug 27 12:45:03 PM UTC 24
Peak memory 281584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3830785857 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw_evict_all_en.3830785857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.572003762
Short name T510
Test name
Test status
Simulation time 2180905200 ps
CPU time 230.64 seconds
Started Aug 27 12:42:50 PM UTC 24
Finished Aug 27 12:46:44 PM UTC 24
Peak memory 291840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=572003762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.572003762
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.251101367
Short name T401
Test name
Test status
Simulation time 2081087600 ps
CPU time 95.08 seconds
Started Aug 27 12:44:34 PM UTC 24
Finished Aug 27 12:46:11 PM UTC 24
Peak memory 275220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251101367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.251101367
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.1161555780
Short name T508
Test name
Test status
Simulation time 37347800 ps
CPU time 280.67 seconds
Started Aug 27 12:41:23 PM UTC 24
Finished Aug 27 12:46:07 PM UTC 24
Peak memory 289676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161555780 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1161555780
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.3637994172
Short name T490
Test name
Test status
Simulation time 2334085400 ps
CPU time 116.81 seconds
Started Aug 27 12:41:58 PM UTC 24
Finished Aug 27 12:43:57 PM UTC 24
Peak memory 271216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3637994172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.3637994172
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.4140901793
Short name T1034
Test name
Test status
Simulation time 122085000 ps
CPU time 25.19 seconds
Started Aug 27 01:35:38 PM UTC 24
Finished Aug 27 01:36:04 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4140901793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.4140901793
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1983862423
Short name T1099
Test name
Test status
Simulation time 75294100 ps
CPU time 177.55 seconds
Started Aug 27 01:35:36 PM UTC 24
Finished Aug 27 01:38:37 PM UTC 24
Peak memory 271740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983862423 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.1983862423
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.1133637406
Short name T1031
Test name
Test status
Simulation time 35079400 ps
CPU time 19.84 seconds
Started Aug 27 01:35:40 PM UTC 24
Finished Aug 27 01:36:01 PM UTC 24
Peak memory 295176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133637406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.1133637406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.2818499001
Short name T1093
Test name
Test status
Simulation time 37385000 ps
CPU time 148.54 seconds
Started Aug 27 01:35:39 PM UTC 24
Finished Aug 27 01:38:10 PM UTC 24
Peak memory 271292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818499001 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.2818499001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.52444163
Short name T1040
Test name
Test status
Simulation time 13782100 ps
CPU time 21.44 seconds
Started Aug 27 01:35:51 PM UTC 24
Finished Aug 27 01:36:14 PM UTC 24
Peak memory 295188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=52444163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.52444163
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.2583379917
Short name T1106
Test name
Test status
Simulation time 44488400 ps
CPU time 197.09 seconds
Started Aug 27 01:35:46 PM UTC 24
Finished Aug 27 01:39:06 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583379917 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.2583379917
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.2356913607
Short name T1042
Test name
Test status
Simulation time 13763900 ps
CPU time 19.31 seconds
Started Aug 27 01:35:56 PM UTC 24
Finished Aug 27 01:36:16 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356913607 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2356913607
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.3918906175
Short name T1097
Test name
Test status
Simulation time 103689100 ps
CPU time 153.93 seconds
Started Aug 27 01:35:51 PM UTC 24
Finished Aug 27 01:38:28 PM UTC 24
Peak memory 275488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918906175 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.3918906175
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.1761968604
Short name T1044
Test name
Test status
Simulation time 13093000 ps
CPU time 22.83 seconds
Started Aug 27 01:35:57 PM UTC 24
Finished Aug 27 01:36:21 PM UTC 24
Peak memory 284936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761968604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1761968604
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3178152752
Short name T1095
Test name
Test status
Simulation time 47170600 ps
CPU time 142.17 seconds
Started Aug 27 01:35:57 PM UTC 24
Finished Aug 27 01:38:21 PM UTC 24
Peak memory 271288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178152752 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.3178152752
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.3912804571
Short name T1048
Test name
Test status
Simulation time 31798700 ps
CPU time 26.79 seconds
Started Aug 27 01:35:59 PM UTC 24
Finished Aug 27 01:36:27 PM UTC 24
Peak memory 284936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912804571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.3912804571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.4228864348
Short name T1094
Test name
Test status
Simulation time 44667600 ps
CPU time 134.41 seconds
Started Aug 27 01:35:58 PM UTC 24
Finished Aug 27 01:38:15 PM UTC 24
Peak memory 271392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228864348 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.4228864348
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.3937920010
Short name T1050
Test name
Test status
Simulation time 21778200 ps
CPU time 28.89 seconds
Started Aug 27 01:36:01 PM UTC 24
Finished Aug 27 01:36:32 PM UTC 24
Peak memory 284936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937920010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.3937920010
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.931867731
Short name T1103
Test name
Test status
Simulation time 38366100 ps
CPU time 162.72 seconds
Started Aug 27 01:36:00 PM UTC 24
Finished Aug 27 01:38:46 PM UTC 24
Peak memory 271284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=931867731 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.931867731
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.2780532620
Short name T1049
Test name
Test status
Simulation time 24595700 ps
CPU time 21.75 seconds
Started Aug 27 01:36:05 PM UTC 24
Finished Aug 27 01:36:28 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780532620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.2780532620
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.2984078627
Short name T1100
Test name
Test status
Simulation time 136384800 ps
CPU time 150.57 seconds
Started Aug 27 01:36:03 PM UTC 24
Finished Aug 27 01:38:37 PM UTC 24
Peak memory 275492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984078627 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.2984078627
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.2714698662
Short name T1046
Test name
Test status
Simulation time 27536000 ps
CPU time 16.6 seconds
Started Aug 27 01:36:06 PM UTC 24
Finished Aug 27 01:36:24 PM UTC 24
Peak memory 284940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2714698662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2714698662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3207804815
Short name T1102
Test name
Test status
Simulation time 75784300 ps
CPU time 157.37 seconds
Started Aug 27 01:36:05 PM UTC 24
Finished Aug 27 01:38:45 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207804815 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.3207804815
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.2069714940
Short name T1053
Test name
Test status
Simulation time 41691300 ps
CPU time 20.84 seconds
Started Aug 27 01:36:12 PM UTC 24
Finished Aug 27 01:36:34 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069714940 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2069714940
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.1168468722
Short name T1096
Test name
Test status
Simulation time 71890200 ps
CPU time 132.48 seconds
Started Aug 27 01:36:08 PM UTC 24
Finished Aug 27 01:38:23 PM UTC 24
Peak memory 271080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1168468722 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.1168468722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.3792269271
Short name T528
Test name
Test status
Simulation time 126882200 ps
CPU time 23.72 seconds
Started Aug 27 12:49:56 PM UTC 24
Finished Aug 27 12:50:21 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792269271 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.3792269271
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.2007395571
Short name T524
Test name
Test status
Simulation time 34979800 ps
CPU time 25.57 seconds
Started Aug 27 12:49:41 PM UTC 24
Finished Aug 27 12:50:07 PM UTC 24
Peak memory 295112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007395571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.2007395571
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.2612584656
Short name T188
Test name
Test status
Simulation time 11052700 ps
CPU time 29.39 seconds
Started Aug 27 12:49:35 PM UTC 24
Finished Aug 27 12:50:06 PM UTC 24
Peak memory 285724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2612584656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c
trl_disable.2612584656
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.3966285704
Short name T913
Test name
Test status
Simulation time 2864475100 ps
CPU time 2682.44 seconds
Started Aug 27 12:46:12 PM UTC 24
Finished Aug 27 01:31:21 PM UTC 24
Peak memory 275272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966285704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.3966285704
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.361197269
Short name T629
Test name
Test status
Simulation time 817088700 ps
CPU time 1204.13 seconds
Started Aug 27 12:46:10 PM UTC 24
Finished Aug 27 01:06:27 PM UTC 24
Peak memory 285520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361197269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/fl
ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.361197269
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2290116145
Short name T54
Test name
Test status
Simulation time 96535200 ps
CPU time 40.84 seconds
Started Aug 27 12:46:09 PM UTC 24
Finished Aug 27 12:46:51 PM UTC 24
Peak memory 275344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22
90116145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetc
h_code.2290116145
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.2751189229
Short name T283
Test name
Test status
Simulation time 10018888300 ps
CPU time 80.71 seconds
Started Aug 27 12:49:56 PM UTC 24
Finished Aug 27 12:51:18 PM UTC 24
Peak memory 296100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2751189229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.2751189229
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.1101520243
Short name T527
Test name
Test status
Simulation time 25563000 ps
CPU time 21.95 seconds
Started Aug 27 12:49:47 PM UTC 24
Finished Aug 27 12:50:10 PM UTC 24
Peak memory 269448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1101520243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_hw_read_seed_err.1101520243
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1135677001
Short name T185
Test name
Test status
Simulation time 160169796100 ps
CPU time 873.39 seconds
Started Aug 27 12:45:30 PM UTC 24
Finished Aug 27 01:00:14 PM UTC 24
Peak memory 275180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1135677001
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.1135677001
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.616978342
Short name T511
Test name
Test status
Simulation time 1462195300 ps
CPU time 87.36 seconds
Started Aug 27 12:45:27 PM UTC 24
Finished Aug 27 12:46:57 PM UTC 24
Peak memory 273164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616978342 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.616978342
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.4192455768
Short name T342
Test name
Test status
Simulation time 8097936100 ps
CPU time 192.41 seconds
Started Aug 27 12:48:13 PM UTC 24
Finished Aug 27 12:51:29 PM UTC 24
Peak memory 294168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192455768 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.4192455768
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3775736555
Short name T306
Test name
Test status
Simulation time 12242582100 ps
CPU time 158.89 seconds
Started Aug 27 12:48:32 PM UTC 24
Finished Aug 27 12:51:14 PM UTC 24
Peak memory 304044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3775736555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_intr_rd_slow_flash.3775736555
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.700083852
Short name T521
Test name
Test status
Simulation time 4627944200 ps
CPU time 86.69 seconds
Started Aug 27 12:48:27 PM UTC 24
Finished Aug 27 12:49:55 PM UTC 24
Peak memory 275572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700083852 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.700083852
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.2454617699
Short name T534
Test name
Test status
Simulation time 80106136700 ps
CPU time 228.54 seconds
Started Aug 27 12:48:41 PM UTC 24
Finished Aug 27 12:52:32 PM UTC 24
Peak memory 275388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454617699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.2454617699
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.310502406
Short name T415
Test name
Test status
Simulation time 2795073700 ps
CPU time 97.28 seconds
Started Aug 27 12:46:33 PM UTC 24
Finished Aug 27 12:48:13 PM UTC 24
Peak memory 271120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310502406 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.310502406
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.438177533
Short name T526
Test name
Test status
Simulation time 45045700 ps
CPU time 26.21 seconds
Started Aug 27 12:49:42 PM UTC 24
Finished Aug 27 12:50:09 PM UTC 24
Peak memory 275504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=438177533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_lcmgr_intg.438177533
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.418181850
Short name T151
Test name
Test status
Simulation time 12627139400 ps
CPU time 399.83 seconds
Started Aug 27 12:46:09 PM UTC 24
Finished Aug 27 12:52:54 PM UTC 24
Peak memory 283536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=418181850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_mp_regions.418181850
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3412505033
Short name T171
Test name
Test status
Simulation time 44973100 ps
CPU time 243.02 seconds
Started Aug 27 12:45:40 PM UTC 24
Finished Aug 27 12:49:46 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412505033 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.3412505033
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.1617853891
Short name T547
Test name
Test status
Simulation time 1137938400 ps
CPU time 585.6 seconds
Started Aug 27 12:45:23 PM UTC 24
Finished Aug 27 12:55:16 PM UTC 24
Peak memory 275264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617853891 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.1617853891
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.1755104089
Short name T516
Test name
Test status
Simulation time 164952100 ps
CPU time 28.19 seconds
Started Aug 27 12:48:45 PM UTC 24
Finished Aug 27 12:49:14 PM UTC 24
Peak memory 271216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755104089 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.1755104089
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.783102756
Short name T563
Test name
Test status
Simulation time 794369400 ps
CPU time 759.87 seconds
Started Aug 27 12:45:21 PM UTC 24
Finished Aug 27 12:58:10 PM UTC 24
Peak memory 291920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783102756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.783102756
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.1495758155
Short name T522
Test name
Test status
Simulation time 203870400 ps
CPU time 48.1 seconds
Started Aug 27 12:49:17 PM UTC 24
Finished Aug 27 12:50:07 PM UTC 24
Peak memory 287724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495758155 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.1495758155
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.1277939186
Short name T515
Test name
Test status
Simulation time 583022300 ps
CPU time 121.31 seconds
Started Aug 27 12:46:44 PM UTC 24
Finished Aug 27 12:48:48 PM UTC 24
Peak memory 304072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1277939186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.1277939186
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3134136312
Short name T221
Test name
Test status
Simulation time 3306761400 ps
CPU time 141.3 seconds
Started Aug 27 12:47:31 PM UTC 24
Finished Aug 27 12:49:55 PM UTC 24
Peak memory 291832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3134136312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3134136312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.2205537923
Short name T518
Test name
Test status
Simulation time 653476300 ps
CPU time 153.93 seconds
Started Aug 27 12:46:58 PM UTC 24
Finished Aug 27 12:49:34 PM UTC 24
Peak memory 292032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2205537923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_ro_serr.2205537923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.4290686857
Short name T543
Test name
Test status
Simulation time 15276582800 ps
CPU time 461.94 seconds
Started Aug 27 12:46:53 PM UTC 24
Finished Aug 27 12:54:41 PM UTC 24
Peak memory 320688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290686857 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.4290686857
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.608890931
Short name T536
Test name
Test status
Simulation time 1693305800 ps
CPU time 289.36 seconds
Started Aug 27 12:48:01 PM UTC 24
Finished Aug 27 12:52:55 PM UTC 24
Peak memory 295960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=608890931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 6.flash_ctrl_rw_derr.608890931
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.2355844551
Short name T430
Test name
Test status
Simulation time 53878900 ps
CPU time 50.64 seconds
Started Aug 27 12:48:49 PM UTC 24
Finished Aug 27 12:49:41 PM UTC 24
Peak memory 281584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355844551 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.2355844551
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.1484531840
Short name T525
Test name
Test status
Simulation time 31831700 ps
CPU time 51.01 seconds
Started Aug 27 12:49:15 PM UTC 24
Finished Aug 27 12:50:08 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1484531840 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct
rl_rw_evict_all_en.1484531840
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.67508225
Short name T523
Test name
Test status
Simulation time 1784966000 ps
CPU time 167.84 seconds
Started Aug 27 12:47:17 PM UTC 24
Finished Aug 27 12:50:07 PM UTC 24
Peak memory 306168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=67508225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.67508225
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.222134987
Short name T389
Test name
Test status
Simulation time 2148803600 ps
CPU time 65.77 seconds
Started Aug 27 12:49:40 PM UTC 24
Finished Aug 27 12:50:47 PM UTC 24
Peak memory 275480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222134987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.222134987
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.4269923488
Short name T514
Test name
Test status
Simulation time 52834700 ps
CPU time 163.14 seconds
Started Aug 27 12:45:14 PM UTC 24
Finished Aug 27 12:48:00 PM UTC 24
Peak memory 289688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269923488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.4269923488
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.879635035
Short name T530
Test name
Test status
Simulation time 5544120400 ps
CPU time 233.46 seconds
Started Aug 27 12:46:44 PM UTC 24
Finished Aug 27 12:50:41 PM UTC 24
Peak memory 275316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=879635035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.879635035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.446087258
Short name T1054
Test name
Test status
Simulation time 92569600 ps
CPU time 19.11 seconds
Started Aug 27 01:36:15 PM UTC 24
Finished Aug 27 01:36:35 PM UTC 24
Peak memory 295312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446087258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.446087258
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1677014094
Short name T1101
Test name
Test status
Simulation time 181388600 ps
CPU time 146.12 seconds
Started Aug 27 01:36:12 PM UTC 24
Finished Aug 27 01:38:41 PM UTC 24
Peak memory 271396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1677014094 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.1677014094
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.3135819675
Short name T1052
Test name
Test status
Simulation time 55078400 ps
CPU time 15.79 seconds
Started Aug 27 01:36:16 PM UTC 24
Finished Aug 27 01:36:33 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135819675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3135819675
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.3416077923
Short name T1111
Test name
Test status
Simulation time 38494000 ps
CPU time 179.86 seconds
Started Aug 27 01:36:15 PM UTC 24
Finished Aug 27 01:39:18 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416077923 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.3416077923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.3113370318
Short name T1059
Test name
Test status
Simulation time 15217600 ps
CPU time 22.99 seconds
Started Aug 27 01:36:21 PM UTC 24
Finished Aug 27 01:36:45 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113370318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3113370318
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.1885872894
Short name T1108
Test name
Test status
Simulation time 37131700 ps
CPU time 174.42 seconds
Started Aug 27 01:36:17 PM UTC 24
Finished Aug 27 01:39:14 PM UTC 24
Peak memory 271484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1885872894 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.1885872894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.2212390436
Short name T1058
Test name
Test status
Simulation time 14579300 ps
CPU time 20.01 seconds
Started Aug 27 01:36:22 PM UTC 24
Finished Aug 27 01:36:44 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2212390436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.2212390436
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2191252171
Short name T1107
Test name
Test status
Simulation time 142341500 ps
CPU time 167.22 seconds
Started Aug 27 01:36:22 PM UTC 24
Finished Aug 27 01:39:12 PM UTC 24
Peak memory 273584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191252171 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.2191252171
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.4002686668
Short name T1061
Test name
Test status
Simulation time 97856100 ps
CPU time 17.78 seconds
Started Aug 27 01:36:28 PM UTC 24
Finished Aug 27 01:36:47 PM UTC 24
Peak memory 295112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002686668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.4002686668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.2574358923
Short name T1105
Test name
Test status
Simulation time 140896500 ps
CPU time 156.85 seconds
Started Aug 27 01:36:25 PM UTC 24
Finished Aug 27 01:39:04 PM UTC 24
Peak memory 271480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574358923 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.2574358923
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.1306521734
Short name T1062
Test name
Test status
Simulation time 15892700 ps
CPU time 19.48 seconds
Started Aug 27 01:36:29 PM UTC 24
Finished Aug 27 01:36:50 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306521734 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.1306521734
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.2248862595
Short name T1115
Test name
Test status
Simulation time 43899700 ps
CPU time 188.08 seconds
Started Aug 27 01:36:28 PM UTC 24
Finished Aug 27 01:39:39 PM UTC 24
Peak memory 271288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248862595 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.2248862595
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.2751463685
Short name T1065
Test name
Test status
Simulation time 51919600 ps
CPU time 22.87 seconds
Started Aug 27 01:36:33 PM UTC 24
Finished Aug 27 01:36:58 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751463685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2751463685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1506319892
Short name T1122
Test name
Test status
Simulation time 37978100 ps
CPU time 212.6 seconds
Started Aug 27 01:36:31 PM UTC 24
Finished Aug 27 01:40:07 PM UTC 24
Peak memory 271548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506319892 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.1506319892
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.400916849
Short name T1063
Test name
Test status
Simulation time 119025100 ps
CPU time 16.82 seconds
Started Aug 27 01:36:34 PM UTC 24
Finished Aug 27 01:36:52 PM UTC 24
Peak memory 285068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400916849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.400916849
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.4123157851
Short name T1112
Test name
Test status
Simulation time 319818700 ps
CPU time 175.33 seconds
Started Aug 27 01:36:33 PM UTC 24
Finished Aug 27 01:39:32 PM UTC 24
Peak memory 275496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123157851 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.4123157851
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.1235309668
Short name T1068
Test name
Test status
Simulation time 22913800 ps
CPU time 22.46 seconds
Started Aug 27 01:36:36 PM UTC 24
Finished Aug 27 01:37:00 PM UTC 24
Peak memory 294964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235309668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.1235309668
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.44430408
Short name T1109
Test name
Test status
Simulation time 70199700 ps
CPU time 156.33 seconds
Started Aug 27 01:36:36 PM UTC 24
Finished Aug 27 01:39:15 PM UTC 24
Peak memory 275412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=44430408 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.44430408
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.2298811812
Short name T1070
Test name
Test status
Simulation time 22108100 ps
CPU time 24.36 seconds
Started Aug 27 01:36:37 PM UTC 24
Finished Aug 27 01:37:03 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298811812 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2298811812
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.2083497908
Short name T1116
Test name
Test status
Simulation time 339241600 ps
CPU time 183.73 seconds
Started Aug 27 01:36:36 PM UTC 24
Finished Aug 27 01:39:43 PM UTC 24
Peak memory 271288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083497908 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.2083497908
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1268089573
Short name T546
Test name
Test status
Simulation time 43461100 ps
CPU time 27.31 seconds
Started Aug 27 12:54:40 PM UTC 24
Finished Aug 27 12:55:08 PM UTC 24
Peak memory 269308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268089573 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1268089573
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.896687154
Short name T544
Test name
Test status
Simulation time 46509000 ps
CPU time 21.36 seconds
Started Aug 27 12:54:18 PM UTC 24
Finished Aug 27 12:54:41 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896687154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.896687154
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.198107105
Short name T189
Test name
Test status
Simulation time 29836700 ps
CPU time 36.78 seconds
Started Aug 27 12:54:06 PM UTC 24
Finished Aug 27 12:54:44 PM UTC 24
Peak memory 285628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=198107105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_disable.198107105
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.2875833035
Short name T1125
Test name
Test status
Simulation time 20751429300 ps
CPU time 2946.81 seconds
Started Aug 27 12:50:42 PM UTC 24
Finished Aug 27 01:40:18 PM UTC 24
Peak memory 275992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875833035 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.2875833035
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.2240336630
Short name T667
Test name
Test status
Simulation time 548660200 ps
CPU time 1228.34 seconds
Started Aug 27 12:50:38 PM UTC 24
Finished Aug 27 01:11:20 PM UTC 24
Peak memory 285780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240336630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.2240336630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.2986560593
Short name T55
Test name
Test status
Simulation time 686831100 ps
CPU time 37.34 seconds
Started Aug 27 12:50:22 PM UTC 24
Finished Aug 27 12:51:01 PM UTC 24
Peak memory 273300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29
86560593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc
h_code.2986560593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.2721152581
Short name T192
Test name
Test status
Simulation time 10012197800 ps
CPU time 179.61 seconds
Started Aug 27 12:54:40 PM UTC 24
Finished Aug 27 12:57:42 PM UTC 24
Peak memory 380136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2721152581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.2721152581
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1555386409
Short name T328
Test name
Test status
Simulation time 50894500 ps
CPU time 17.97 seconds
Started Aug 27 12:54:25 PM UTC 24
Finished Aug 27 12:54:44 PM UTC 24
Peak memory 271348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1555386409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_hw_read_seed_err.1555386409
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.1058248799
Short name T603
Test name
Test status
Simulation time 160157349300 ps
CPU time 836.46 seconds
Started Aug 27 12:50:08 PM UTC 24
Finished Aug 27 01:04:14 PM UTC 24
Peak memory 275364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058248799
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.1058248799
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.2706696593
Short name T533
Test name
Test status
Simulation time 2921272500 ps
CPU time 106.42 seconds
Started Aug 27 12:50:08 PM UTC 24
Finished Aug 27 12:51:57 PM UTC 24
Peak memory 275280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2706696593 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.2706696593
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.2193664777
Short name T347
Test name
Test status
Simulation time 25545418500 ps
CPU time 254.23 seconds
Started Aug 27 12:52:33 PM UTC 24
Finished Aug 27 12:56:51 PM UTC 24
Peak memory 302068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193664777 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.2193664777
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.2975167179
Short name T552
Test name
Test status
Simulation time 22705626300 ps
CPU time 177.87 seconds
Started Aug 27 12:52:55 PM UTC 24
Finished Aug 27 12:55:56 PM UTC 24
Peak memory 304300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2975167179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_intr_rd_slow_flash.2975167179
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.866360759
Short name T556
Test name
Test status
Simulation time 90746463800 ps
CPU time 241.54 seconds
Started Aug 27 12:52:56 PM UTC 24
Finished Aug 27 12:57:01 PM UTC 24
Peak memory 275580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=866360759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.866360759
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.3347721393
Short name T535
Test name
Test status
Simulation time 1364200700 ps
CPU time 117.44 seconds
Started Aug 27 12:50:48 PM UTC 24
Finished Aug 27 12:52:48 PM UTC 24
Peak memory 275408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347721393 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.3347721393
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.3140693748
Short name T545
Test name
Test status
Simulation time 21498500 ps
CPU time 25.02 seconds
Started Aug 27 12:54:23 PM UTC 24
Finished Aug 27 12:54:49 PM UTC 24
Peak memory 271568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3140693748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_lcmgr_intg.3140693748
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.1226691466
Short name T539
Test name
Test status
Simulation time 30704793900 ps
CPU time 238.59 seconds
Started Aug 27 12:50:11 PM UTC 24
Finished Aug 27 12:54:13 PM UTC 24
Peak memory 275340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1226691466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_mp_regions.1226691466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.3761110375
Short name T175
Test name
Test status
Simulation time 402454700 ps
CPU time 203.12 seconds
Started Aug 27 12:50:10 PM UTC 24
Finished Aug 27 12:53:37 PM UTC 24
Peak memory 271284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3761110375 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.3761110375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.2707831544
Short name T532
Test name
Test status
Simulation time 29380000 ps
CPU time 79.5 seconds
Started Aug 27 12:50:08 PM UTC 24
Finished Aug 27 12:51:30 PM UTC 24
Peak memory 275336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707831544 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.2707831544
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.2855487122
Short name T553
Test name
Test status
Simulation time 9275459400 ps
CPU time 193.82 seconds
Started Aug 27 12:53:05 PM UTC 24
Finished Aug 27 12:56:22 PM UTC 24
Peak memory 271244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855487122 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.2855487122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.1667781889
Short name T653
Test name
Test status
Simulation time 108368600 ps
CPU time 1152.74 seconds
Started Aug 27 12:50:08 PM UTC 24
Finished Aug 27 01:09:33 PM UTC 24
Peak memory 293776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667781889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.1667781889
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.2568754937
Short name T531
Test name
Test status
Simulation time 619654700 ps
CPU time 107.33 seconds
Started Aug 27 12:51:15 PM UTC 24
Finished Aug 27 12:53:04 PM UTC 24
Peak memory 291760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2568754937 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.2568754937
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.737787628
Short name T540
Test name
Test status
Simulation time 586238000 ps
CPU time 140.85 seconds
Started Aug 27 12:51:58 PM UTC 24
Finished Aug 27 12:54:22 PM UTC 24
Peak memory 292024 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737787628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.737787628
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1167037947
Short name T537
Test name
Test status
Simulation time 1791290800 ps
CPU time 138.67 seconds
Started Aug 27 12:51:30 PM UTC 24
Finished Aug 27 12:53:51 PM UTC 24
Peak memory 291864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1167037947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_ro_serr.1167037947
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.1464140559
Short name T575
Test name
Test status
Simulation time 3625409200 ps
CPU time 486.73 seconds
Started Aug 27 12:51:19 PM UTC 24
Finished Aug 27 12:59:32 PM UTC 24
Peak memory 336876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464140559 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.1464140559
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.1222044969
Short name T541
Test name
Test status
Simulation time 31470300 ps
CPU time 51.07 seconds
Started Aug 27 12:53:31 PM UTC 24
Finished Aug 27 12:54:24 PM UTC 24
Peak memory 287924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1222044969 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.1222044969
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.3111137455
Short name T434
Test name
Test status
Simulation time 30021500 ps
CPU time 52.2 seconds
Started Aug 27 12:53:37 PM UTC 24
Finished Aug 27 12:54:31 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3111137455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw_evict_all_en.3111137455
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.1556756611
Short name T548
Test name
Test status
Simulation time 1332481400 ps
CPU time 229.39 seconds
Started Aug 27 12:51:31 PM UTC 24
Finished Aug 27 12:55:24 PM UTC 24
Peak memory 291856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1556756611 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.1556756611
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2454092685
Short name T390
Test name
Test status
Simulation time 2111478500 ps
CPU time 102.51 seconds
Started Aug 27 12:54:14 PM UTC 24
Finished Aug 27 12:55:59 PM UTC 24
Peak memory 275208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454092685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2454092685
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2525020425
Short name T538
Test name
Test status
Simulation time 66431300 ps
CPU time 234.27 seconds
Started Aug 27 12:50:07 PM UTC 24
Finished Aug 27 12:54:05 PM UTC 24
Peak memory 289672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2525020425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2525020425
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.4261867737
Short name T542
Test name
Test status
Simulation time 2051525800 ps
CPU time 209.7 seconds
Started Aug 27 12:51:01 PM UTC 24
Finished Aug 27 12:54:35 PM UTC 24
Peak memory 275576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4261867737 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.4261867737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.2789015124
Short name T1069
Test name
Test status
Simulation time 15095800 ps
CPU time 20.55 seconds
Started Aug 27 01:36:40 PM UTC 24
Finished Aug 27 01:37:01 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789015124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2789015124
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.86027638
Short name T1110
Test name
Test status
Simulation time 139437400 ps
CPU time 155.46 seconds
Started Aug 27 01:36:38 PM UTC 24
Finished Aug 27 01:39:16 PM UTC 24
Peak memory 275488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86027638 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.86027638
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.1891199775
Short name T1073
Test name
Test status
Simulation time 23672200 ps
CPU time 22.02 seconds
Started Aug 27 01:36:46 PM UTC 24
Finished Aug 27 01:37:09 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891199775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1891199775
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.862641299
Short name T1118
Test name
Test status
Simulation time 40711000 ps
CPU time 182.49 seconds
Started Aug 27 01:36:45 PM UTC 24
Finished Aug 27 01:39:50 PM UTC 24
Peak memory 275892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862641299 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.862641299
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.3317513846
Short name T1072
Test name
Test status
Simulation time 94675000 ps
CPU time 19.38 seconds
Started Aug 27 01:36:48 PM UTC 24
Finished Aug 27 01:37:09 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3317513846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3317513846
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.4001017988
Short name T1113
Test name
Test status
Simulation time 43792100 ps
CPU time 166.58 seconds
Started Aug 27 01:36:47 PM UTC 24
Finished Aug 27 01:39:36 PM UTC 24
Peak memory 275640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001017988 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.4001017988
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.637842986
Short name T1076
Test name
Test status
Simulation time 16031600 ps
CPU time 22.99 seconds
Started Aug 27 01:36:52 PM UTC 24
Finished Aug 27 01:37:17 PM UTC 24
Peak memory 284940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637842986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.637842986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.761134002
Short name T1114
Test name
Test status
Simulation time 322807800 ps
CPU time 164.1 seconds
Started Aug 27 01:36:50 PM UTC 24
Finished Aug 27 01:39:37 PM UTC 24
Peak memory 271392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761134002 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.761134002
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.3827097395
Short name T1077
Test name
Test status
Simulation time 88558100 ps
CPU time 18.54 seconds
Started Aug 27 01:36:59 PM UTC 24
Finished Aug 27 01:37:18 PM UTC 24
Peak memory 295184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827097395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.3827097395
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.1959078127
Short name T1121
Test name
Test status
Simulation time 36015400 ps
CPU time 188.09 seconds
Started Aug 27 01:36:55 PM UTC 24
Finished Aug 27 01:40:06 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1959078127 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.1959078127
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.40546293
Short name T1079
Test name
Test status
Simulation time 14974900 ps
CPU time 17.87 seconds
Started Aug 27 01:37:00 PM UTC 24
Finished Aug 27 01:37:19 PM UTC 24
Peak memory 295048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40546293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.40546293
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.175062885
Short name T1117
Test name
Test status
Simulation time 40103100 ps
CPU time 161.55 seconds
Started Aug 27 01:37:00 PM UTC 24
Finished Aug 27 01:39:44 PM UTC 24
Peak memory 271272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175062885 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.175062885
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.3331335523
Short name T1081
Test name
Test status
Simulation time 45713700 ps
CPU time 18.89 seconds
Started Aug 27 01:37:02 PM UTC 24
Finished Aug 27 01:37:22 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331335523 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.3331335523
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.2043374404
Short name T1123
Test name
Test status
Simulation time 132037200 ps
CPU time 186.06 seconds
Started Aug 27 01:37:00 PM UTC 24
Finished Aug 27 01:40:09 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2043374404 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.2043374404
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.2701741532
Short name T1082
Test name
Test status
Simulation time 20764000 ps
CPU time 20.91 seconds
Started Aug 27 01:37:05 PM UTC 24
Finished Aug 27 01:37:27 PM UTC 24
Peak memory 295312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701741532 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2701741532
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2547650896
Short name T1120
Test name
Test status
Simulation time 37722900 ps
CPU time 175.15 seconds
Started Aug 27 01:37:03 PM UTC 24
Finished Aug 27 01:40:01 PM UTC 24
Peak memory 271288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2547650896 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.2547650896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.1038147602
Short name T1086
Test name
Test status
Simulation time 40966700 ps
CPU time 22.84 seconds
Started Aug 27 01:37:10 PM UTC 24
Finished Aug 27 01:37:34 PM UTC 24
Peak memory 295116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038147602 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1038147602
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.262254914
Short name T1124
Test name
Test status
Simulation time 77255800 ps
CPU time 181.04 seconds
Started Aug 27 01:37:10 PM UTC 24
Finished Aug 27 01:40:14 PM UTC 24
Peak memory 275640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=262254914 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.262254914
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2715673848
Short name T1085
Test name
Test status
Simulation time 39358300 ps
CPU time 19.51 seconds
Started Aug 27 01:37:12 PM UTC 24
Finished Aug 27 01:37:33 PM UTC 24
Peak memory 284936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715673848 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2715673848
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1948588215
Short name T1119
Test name
Test status
Simulation time 66914200 ps
CPU time 160.43 seconds
Started Aug 27 01:37:10 PM UTC 24
Finished Aug 27 01:39:53 PM UTC 24
Peak memory 275368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948588215 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.1948588215
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.902259312
Short name T569
Test name
Test status
Simulation time 107694100 ps
CPU time 23.85 seconds
Started Aug 27 12:58:07 PM UTC 24
Finished Aug 27 12:58:32 PM UTC 24
Peak memory 275724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902259312 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.902259312
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.1753967257
Short name T565
Test name
Test status
Simulation time 67083500 ps
CPU time 24.61 seconds
Started Aug 27 12:57:56 PM UTC 24
Finished Aug 27 12:58:22 PM UTC 24
Peak memory 295180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753967257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.1753967257
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3600801662
Short name T385
Test name
Test status
Simulation time 11456200 ps
CPU time 31.44 seconds
Started Aug 27 12:57:43 PM UTC 24
Finished Aug 27 12:58:16 PM UTC 24
Peak memory 275484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3600801662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_c
trl_disable.3600801662
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.4001697518
Short name T1128
Test name
Test status
Simulation time 69422356200 ps
CPU time 3172.49 seconds
Started Aug 27 12:55:17 PM UTC 24
Finished Aug 27 01:48:41 PM UTC 24
Peak memory 273216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001697518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.4001697518
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3244471575
Short name T687
Test name
Test status
Simulation time 1551414900 ps
CPU time 1130.57 seconds
Started Aug 27 12:55:10 PM UTC 24
Finished Aug 27 01:14:14 PM UTC 24
Peak memory 285784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3244471575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3244471575
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.541933197
Short name T549
Test name
Test status
Simulation time 347489600 ps
CPU time 27.99 seconds
Started Aug 27 12:55:02 PM UTC 24
Finished Aug 27 12:55:31 PM UTC 24
Peak memory 273308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54
1933197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch
_code.541933197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.3679951958
Short name T601
Test name
Test status
Simulation time 10011581700 ps
CPU time 339.35 seconds
Started Aug 27 12:58:06 PM UTC 24
Finished Aug 27 01:03:50 PM UTC 24
Peak memory 332724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3679951958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.3679951958
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.3856524007
Short name T570
Test name
Test status
Simulation time 50190300 ps
CPU time 27.29 seconds
Started Aug 27 12:58:06 PM UTC 24
Finished Aug 27 12:58:35 PM UTC 24
Peak memory 269704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3856524007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_hw_read_seed_err.3856524007
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2456851989
Short name T648
Test name
Test status
Simulation time 40123878100 ps
CPU time 833.27 seconds
Started Aug 27 12:54:44 PM UTC 24
Finished Aug 27 01:08:47 PM UTC 24
Peak memory 275364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456851989
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.2456851989
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1198219667
Short name T326
Test name
Test status
Simulation time 1412933200 ps
CPU time 123.68 seconds
Started Aug 27 12:54:42 PM UTC 24
Finished Aug 27 12:56:48 PM UTC 24
Peak memory 273164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198219667 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.1198219667
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.3022423466
Short name T343
Test name
Test status
Simulation time 1321486600 ps
CPU time 233.94 seconds
Started Aug 27 12:56:23 PM UTC 24
Finished Aug 27 01:00:20 PM UTC 24
Peak memory 294072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022423466 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.3022423466
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1767541968
Short name T577
Test name
Test status
Simulation time 22898389700 ps
CPU time 177.68 seconds
Started Aug 27 12:56:51 PM UTC 24
Finished Aug 27 12:59:52 PM UTC 24
Peak memory 304236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1767541968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_intr_rd_slow_flash.1767541968
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3459738753
Short name T567
Test name
Test status
Simulation time 3247297700 ps
CPU time 93.29 seconds
Started Aug 27 12:56:49 PM UTC 24
Finished Aug 27 12:58:25 PM UTC 24
Peak memory 275308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459738753 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.3459738753
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.370060948
Short name T588
Test name
Test status
Simulation time 41009074300 ps
CPU time 290.78 seconds
Started Aug 27 12:56:52 PM UTC 24
Finished Aug 27 01:01:47 PM UTC 24
Peak memory 275572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=370060948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.370060948
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.2875232205
Short name T554
Test name
Test status
Simulation time 973838400 ps
CPU time 78.38 seconds
Started Aug 27 12:55:30 PM UTC 24
Finished Aug 27 12:56:50 PM UTC 24
Peak memory 273352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875232205 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2875232205
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.2780336986
Short name T566
Test name
Test status
Simulation time 214356800 ps
CPU time 25.19 seconds
Started Aug 27 12:57:57 PM UTC 24
Finished Aug 27 12:58:24 PM UTC 24
Peak memory 275492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2780336986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_lcmgr_intg.2780336986
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.3231516935
Short name T560
Test name
Test status
Simulation time 12752756200 ps
CPU time 191.74 seconds
Started Aug 27 12:54:49 PM UTC 24
Finished Aug 27 12:58:04 PM UTC 24
Peak memory 275332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3231516935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_mp_regions.3231516935
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.4158062841
Short name T182
Test name
Test status
Simulation time 80353400 ps
CPU time 188.48 seconds
Started Aug 27 12:54:45 PM UTC 24
Finished Aug 27 12:57:57 PM UTC 24
Peak memory 275172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4158062841 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.4158062841
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.88754286
Short name T581
Test name
Test status
Simulation time 61338500 ps
CPU time 362.12 seconds
Started Aug 27 12:54:41 PM UTC 24
Finished Aug 27 01:00:48 PM UTC 24
Peak memory 275272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88754286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.88754286
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.1237479453
Short name T557
Test name
Test status
Simulation time 100762100 ps
CPU time 28.33 seconds
Started Aug 27 12:56:55 PM UTC 24
Finished Aug 27 12:57:26 PM UTC 24
Peak memory 271244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1237479453 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.1237479453
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.2537606515
Short name T613
Test name
Test status
Simulation time 395086800 ps
CPU time 606.2 seconds
Started Aug 27 12:54:40 PM UTC 24
Finished Aug 27 01:04:53 PM UTC 24
Peak memory 291920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537606515 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2537606515
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.519771150
Short name T564
Test name
Test status
Simulation time 134425000 ps
CPU time 39.8 seconds
Started Aug 27 12:57:41 PM UTC 24
Finished Aug 27 12:58:22 PM UTC 24
Peak memory 287988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519771150 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.519771150
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.853413591
Short name T559
Test name
Test status
Simulation time 548430700 ps
CPU time 140.97 seconds
Started Aug 27 12:55:32 PM UTC 24
Finished Aug 27 12:57:56 PM UTC 24
Peak memory 304124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=853413591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.853413591
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.1072236898
Short name T571
Test name
Test status
Simulation time 688727300 ps
CPU time 178.08 seconds
Started Aug 27 12:55:57 PM UTC 24
Finished Aug 27 12:58:58 PM UTC 24
Peak memory 291856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072236898 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.1072236898
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.740198361
Short name T558
Test name
Test status
Simulation time 588891600 ps
CPU time 130.48 seconds
Started Aug 27 12:55:39 PM UTC 24
Finished Aug 27 12:57:52 PM UTC 24
Peak memory 291836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=740198361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_
ctrl_ro_serr.740198361
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.49816131
Short name T440
Test name
Test status
Simulation time 3606949500 ps
CPU time 436.21 seconds
Started Aug 27 12:55:34 PM UTC 24
Finished Aug 27 01:02:56 PM UTC 24
Peak memory 324764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49816131 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.49816131
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1157172570
Short name T576
Test name
Test status
Simulation time 4104263800 ps
CPU time 219.66 seconds
Started Aug 27 12:56:00 PM UTC 24
Finished Aug 27 12:59:43 PM UTC 24
Peak memory 302092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1157172570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.flash_ctrl_rw_derr.1157172570
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.4131335657
Short name T561
Test name
Test status
Simulation time 103886300 ps
CPU time 61.91 seconds
Started Aug 27 12:57:02 PM UTC 24
Finished Aug 27 12:58:05 PM UTC 24
Peak memory 287760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131335657 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.4131335657
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.2686526821
Short name T425
Test name
Test status
Simulation time 39211700 ps
CPU time 41.55 seconds
Started Aug 27 12:57:27 PM UTC 24
Finished Aug 27 12:58:10 PM UTC 24
Peak memory 287764 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2686526821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw_evict_all_en.2686526821
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.4186836918
Short name T584
Test name
Test status
Simulation time 20912016700 ps
CPU time 334.7 seconds
Started Aug 27 12:55:40 PM UTC 24
Finished Aug 27 01:01:20 PM UTC 24
Peak memory 306364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4186836918 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.4186836918
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.3338709044
Short name T572
Test name
Test status
Simulation time 1321209600 ps
CPU time 66.44 seconds
Started Aug 27 12:57:53 PM UTC 24
Finished Aug 27 12:59:01 PM UTC 24
Peak memory 275344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338709044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3338709044
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.2955120720
Short name T555
Test name
Test status
Simulation time 33142200 ps
CPU time 132.87 seconds
Started Aug 27 12:54:40 PM UTC 24
Finished Aug 27 12:56:55 PM UTC 24
Peak memory 287632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955120720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2955120720
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.436687020
Short name T568
Test name
Test status
Simulation time 7351676300 ps
CPU time 173.42 seconds
Started Aug 27 12:55:30 PM UTC 24
Finished Aug 27 12:58:26 PM UTC 24
Peak memory 271216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=436687020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.436687020
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.3511413476
Short name T593
Test name
Test status
Simulation time 31852200 ps
CPU time 21.59 seconds
Started Aug 27 01:01:42 PM UTC 24
Finished Aug 27 01:02:05 PM UTC 24
Peak memory 275644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3511413476 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.3511413476
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.576663863
Short name T589
Test name
Test status
Simulation time 59500000 ps
CPU time 26.05 seconds
Started Aug 27 01:01:20 PM UTC 24
Finished Aug 27 01:01:48 PM UTC 24
Peak memory 295120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576663863 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.576663863
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2125455256
Short name T103
Test name
Test status
Simulation time 16103300 ps
CPU time 33.34 seconds
Started Aug 27 01:01:07 PM UTC 24
Finished Aug 27 01:01:42 PM UTC 24
Peak memory 285880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2125455256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c
trl_disable.2125455256
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.916250847
Short name T1129
Test name
Test status
Simulation time 7461602000 ps
CPU time 3020.51 seconds
Started Aug 27 12:58:33 PM UTC 24
Finished Aug 27 01:49:25 PM UTC 24
Peak memory 273356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916250847 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.916250847
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.2463237722
Short name T748
Test name
Test status
Simulation time 1273392800 ps
CPU time 1309.39 seconds
Started Aug 27 12:58:27 PM UTC 24
Finished Aug 27 01:20:31 PM UTC 24
Peak memory 283468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463237722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2463237722
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1971662122
Short name T573
Test name
Test status
Simulation time 613496400 ps
CPU time 33.84 seconds
Started Aug 27 12:58:26 PM UTC 24
Finished Aug 27 12:59:01 PM UTC 24
Peak memory 275348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19
71662122 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc
h_code.1971662122
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3900957527
Short name T611
Test name
Test status
Simulation time 10014363400 ps
CPU time 186.84 seconds
Started Aug 27 01:01:40 PM UTC 24
Finished Aug 27 01:04:50 PM UTC 24
Peak memory 371944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3900957527 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3900957527
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.3359753630
Short name T590
Test name
Test status
Simulation time 26164700 ps
CPU time 19.11 seconds
Started Aug 27 01:01:38 PM UTC 24
Finished Aug 27 01:01:58 PM UTC 24
Peak memory 271344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3359753630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
9.flash_ctrl_hw_read_seed_err.3359753630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.4172610053
Short name T204
Test name
Test status
Simulation time 130168372200 ps
CPU time 806.41 seconds
Started Aug 27 12:58:23 PM UTC 24
Finished Aug 27 01:11:59 PM UTC 24
Peak memory 275180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172610053
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.4172610053
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.4074695936
Short name T578
Test name
Test status
Simulation time 810871200 ps
CPU time 103.77 seconds
Started Aug 27 12:58:17 PM UTC 24
Finished Aug 27 01:00:02 PM UTC 24
Peak memory 275280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4074695936 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.4074695936
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.1952374737
Short name T340
Test name
Test status
Simulation time 1386163000 ps
CPU time 202.86 seconds
Started Aug 27 01:00:06 PM UTC 24
Finished Aug 27 01:03:33 PM UTC 24
Peak memory 304152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952374737 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.1952374737
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.2860060597
Short name T598
Test name
Test status
Simulation time 5820725200 ps
CPU time 177.87 seconds
Started Aug 27 01:00:21 PM UTC 24
Finished Aug 27 01:03:22 PM UTC 24
Peak memory 304048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2860060597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_intr_rd_slow_flash.2860060597
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.1983521216
Short name T585
Test name
Test status
Simulation time 4931048000 ps
CPU time 78.67 seconds
Started Aug 27 01:00:15 PM UTC 24
Finished Aug 27 01:01:35 PM UTC 24
Peak memory 271224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983521216 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.1983521216
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.3374181653
Short name T615
Test name
Test status
Simulation time 137156847100 ps
CPU time 288.45 seconds
Started Aug 27 01:00:30 PM UTC 24
Finished Aug 27 01:05:23 PM UTC 24
Peak memory 275380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374181653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.3374181653
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2375763790
Short name T580
Test name
Test status
Simulation time 1463329400 ps
CPU time 118.26 seconds
Started Aug 27 12:58:35 PM UTC 24
Finished Aug 27 01:00:36 PM UTC 24
Peak memory 271112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375763790 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2375763790
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.2876450168
Short name T592
Test name
Test status
Simulation time 15623700 ps
CPU time 24.48 seconds
Started Aug 27 01:01:36 PM UTC 24
Finished Aug 27 01:02:03 PM UTC 24
Peak memory 275472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2876450168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_lcmgr_intg.2876450168
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1062868490
Short name T579
Test name
Test status
Simulation time 3533240000 ps
CPU time 121.09 seconds
Started Aug 27 12:58:25 PM UTC 24
Finished Aug 27 01:00:28 PM UTC 24
Peak memory 275344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1062868490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_mp_regions.1062868490
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.2273292670
Short name T177
Test name
Test status
Simulation time 38765000 ps
CPU time 235.29 seconds
Started Aug 27 12:58:23 PM UTC 24
Finished Aug 27 01:02:22 PM UTC 24
Peak memory 271544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2273292670 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.2273292670
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.620899451
Short name T600
Test name
Test status
Simulation time 74062200 ps
CPU time 322.68 seconds
Started Aug 27 12:58:10 PM UTC 24
Finished Aug 27 01:03:37 PM UTC 24
Peak memory 275464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620899451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.620899451
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.2649916718
Short name T310
Test name
Test status
Simulation time 27902400 ps
CPU time 28.73 seconds
Started Aug 27 01:00:36 PM UTC 24
Finished Aug 27 01:01:07 PM UTC 24
Peak memory 271224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649916718 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.2649916718
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.651970592
Short name T740
Test name
Test status
Simulation time 9132389700 ps
CPU time 1288.9 seconds
Started Aug 27 12:58:10 PM UTC 24
Finished Aug 27 01:19:53 PM UTC 24
Peak memory 295828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651970592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.651970592
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.1059551882
Short name T417
Test name
Test status
Simulation time 230126100 ps
CPU time 49.86 seconds
Started Aug 27 01:00:55 PM UTC 24
Finished Aug 27 01:01:46 PM UTC 24
Peak memory 287732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059551882 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.1059551882
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.2218493375
Short name T582
Test name
Test status
Simulation time 1124620900 ps
CPU time 110.35 seconds
Started Aug 27 12:59:02 PM UTC 24
Finished Aug 27 01:00:54 PM UTC 24
Peak memory 304124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2218493375 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.2218493375
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2444962741
Short name T591
Test name
Test status
Simulation time 515781200 ps
CPU time 136.11 seconds
Started Aug 27 12:59:43 PM UTC 24
Finished Aug 27 01:02:02 PM UTC 24
Peak memory 291856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444962741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2444962741
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.1358656709
Short name T586
Test name
Test status
Simulation time 1224064600 ps
CPU time 142.15 seconds
Started Aug 27 12:59:12 PM UTC 24
Finished Aug 27 01:01:37 PM UTC 24
Peak memory 292060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1358656709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_ro_serr.1358656709
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.1327665732
Short name T638
Test name
Test status
Simulation time 8847494300 ps
CPU time 539.92 seconds
Started Aug 27 12:59:02 PM UTC 24
Finished Aug 27 01:08:08 PM UTC 24
Peak memory 320504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327665732 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.1327665732
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.2119234440
Short name T596
Test name
Test status
Simulation time 1296929600 ps
CPU time 179.52 seconds
Started Aug 27 12:59:52 PM UTC 24
Finished Aug 27 01:02:55 PM UTC 24
Peak memory 291836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2119234440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 9.flash_ctrl_rw_derr.2119234440
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.383262952
Short name T419
Test name
Test status
Simulation time 55413200 ps
CPU time 48.53 seconds
Started Aug 27 01:00:49 PM UTC 24
Finished Aug 27 01:01:39 PM UTC 24
Peak memory 285904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383262952 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.383262952
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.3530229388
Short name T587
Test name
Test status
Simulation time 38175800 ps
CPU time 49.75 seconds
Started Aug 27 01:00:50 PM UTC 24
Finished Aug 27 01:01:41 PM UTC 24
Peak memory 281584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3530229388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw_evict_all_en.3530229388
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.4192746894
Short name T594
Test name
Test status
Simulation time 2249558100 ps
CPU time 162.71 seconds
Started Aug 27 12:59:33 PM UTC 24
Finished Aug 27 01:02:18 PM UTC 24
Peak memory 306192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4192746894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.4192746894
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3995285896
Short name T595
Test name
Test status
Simulation time 1468326500 ps
CPU time 96.21 seconds
Started Aug 27 01:01:08 PM UTC 24
Finished Aug 27 01:02:46 PM UTC 24
Peak memory 275216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995285896 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.3995285896
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.3944174630
Short name T574
Test name
Test status
Simulation time 25565800 ps
CPU time 60.82 seconds
Started Aug 27 12:58:08 PM UTC 24
Finished Aug 27 12:59:11 PM UTC 24
Peak memory 283544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944174630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.3944174630
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.4022864197
Short name T597
Test name
Test status
Simulation time 2384899500 ps
CPU time 244.48 seconds
Started Aug 27 12:58:59 PM UTC 24
Finished Aug 27 01:03:07 PM UTC 24
Peak memory 271440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4022864197 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.4022864197
Directory /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest
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