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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.28 95.73 93.98 98.31 92.52 98.25 96.99 98.21


Total test records in report: 1267
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html

T660 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.32209439 Aug 27 01:09:47 PM UTC 24 Aug 27 01:10:11 PM UTC 24 15452100 ps
T661 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.4212956462 Aug 27 01:09:31 PM UTC 24 Aug 27 01:10:17 PM UTC 24 26902000 ps
T662 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.2932269408 Aug 27 01:09:26 PM UTC 24 Aug 27 01:10:20 PM UTC 24 245045300 ps
T153 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.125017343 Aug 27 01:08:43 PM UTC 24 Aug 27 01:10:24 PM UTC 24 2100549700 ps
T431 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.2719253042 Aug 27 01:09:26 PM UTC 24 Aug 27 01:10:25 PM UTC 24 247322000 ps
T663 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.4121143483 Aug 27 01:10:05 PM UTC 24 Aug 27 01:10:33 PM UTC 24 129784000 ps
T664 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.2208730768 Aug 27 01:08:26 PM UTC 24 Aug 27 01:10:41 PM UTC 24 20625900 ps
T665 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.2058357576 Aug 27 01:09:34 PM UTC 24 Aug 27 01:10:43 PM UTC 24 1730539400 ps
T79 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.1280306403 Aug 27 01:08:35 PM UTC 24 Aug 27 01:11:11 PM UTC 24 123756900 ps
T666 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.3388809616 Aug 27 01:09:02 PM UTC 24 Aug 27 01:11:20 PM UTC 24 15003232100 ps
T667 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.2240336630 Aug 27 12:50:38 PM UTC 24 Aug 27 01:11:20 PM UTC 24 548660200 ps
T668 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.1112548494 Aug 27 01:04:18 PM UTC 24 Aug 27 01:11:35 PM UTC 24 167445100 ps
T669 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.3901572588 Aug 27 01:10:06 PM UTC 24 Aug 27 01:11:38 PM UTC 24 42022100 ps
T670 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2909293137 Aug 27 01:09:53 PM UTC 24 Aug 27 01:11:42 PM UTC 24 10034060300 ps
T671 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.2927280441 Aug 27 01:11:22 PM UTC 24 Aug 27 01:11:46 PM UTC 24 71359100 ps
T672 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.4249925645 Aug 27 01:08:44 PM UTC 24 Aug 27 01:11:58 PM UTC 24 25246162400 ps
T204 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.4172610053 Aug 27 12:58:23 PM UTC 24 Aug 27 01:11:59 PM UTC 24 130168372200 ps
T132 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.1114758485 Aug 27 12:34:54 PM UTC 24 Aug 27 01:12:09 PM UTC 24 364897161100 ps
T290 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.1076499360 Aug 27 12:20:11 PM UTC 24 Aug 27 01:12:20 PM UTC 24 3546357400 ps
T673 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.3075010495 Aug 27 01:11:37 PM UTC 24 Aug 27 01:12:21 PM UTC 24 108204300 ps
T674 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.689422226 Aug 27 01:10:25 PM UTC 24 Aug 27 01:12:24 PM UTC 24 3111670600 ps
T675 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.4229768358 Aug 27 01:11:39 PM UTC 24 Aug 27 01:12:28 PM UTC 24 240376900 ps
T676 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.1096985575 Aug 27 01:12:00 PM UTC 24 Aug 27 01:12:28 PM UTC 24 32051600 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.4185304269 Aug 27 01:10:12 PM UTC 24 Aug 27 01:12:31 PM UTC 24 3662237200 ps
T105 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.152872342 Aug 27 01:11:47 PM UTC 24 Aug 27 01:12:32 PM UTC 24 16065000 ps
T677 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.1006144318 Aug 27 01:12:18 PM UTC 24 Aug 27 01:12:35 PM UTC 24 15615100 ps
T224 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.4239761590 Aug 27 01:11:43 PM UTC 24 Aug 27 01:12:38 PM UTC 24 74755500 ps
T678 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.2822335076 Aug 27 01:08:09 PM UTC 24 Aug 27 01:12:47 PM UTC 24 10012444100 ps
T679 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.516200001 Aug 27 01:12:25 PM UTC 24 Aug 27 01:12:48 PM UTC 24 85214900 ps
T680 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.754665056 Aug 27 01:12:21 PM UTC 24 Aug 27 01:12:49 PM UTC 24 47145800 ps
T681 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.514977776 Aug 27 01:10:42 PM UTC 24 Aug 27 01:12:52 PM UTC 24 2255572300 ps
T682 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.244521540 Aug 27 01:10:34 PM UTC 24 Aug 27 01:12:55 PM UTC 24 7027682200 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.2209500729 Aug 27 01:08:50 PM UTC 24 Aug 27 01:13:13 PM UTC 24 1589776900 ps
T348 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.4184412214 Aug 27 01:11:12 PM UTC 24 Aug 27 01:13:16 PM UTC 24 1735879800 ps
T284 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.2327336001 Aug 27 01:12:22 PM UTC 24 Aug 27 01:13:19 PM UTC 24 10032191100 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.909069065 Aug 27 01:11:58 PM UTC 24 Aug 27 01:13:21 PM UTC 24 16161967200 ps
T683 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.1117554763 Aug 27 01:13:20 PM UTC 24 Aug 27 01:13:45 PM UTC 24 152158700 ps
T684 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.1475629699 Aug 27 01:04:45 PM UTC 24 Aug 27 01:13:45 PM UTC 24 8030759400 ps
T685 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.3475497243 Aug 27 01:06:27 PM UTC 24 Aug 27 01:13:49 PM UTC 24 7107475300 ps
T686 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.1766365482 Aug 27 01:10:21 PM UTC 24 Aug 27 01:14:01 PM UTC 24 36217700 ps
T154 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.965718218 Aug 27 12:14:32 PM UTC 24 Aug 27 01:14:02 PM UTC 24 325734948300 ps
T687 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3244471575 Aug 27 12:55:10 PM UTC 24 Aug 27 01:14:14 PM UTC 24 1551414900 ps
T427 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.6090079 Aug 27 01:13:22 PM UTC 24 Aug 27 01:14:14 PM UTC 24 39582300 ps
T688 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.2364119263 Aug 27 01:12:49 PM UTC 24 Aug 27 01:14:17 PM UTC 24 4442337900 ps
T689 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.2726710194 Aug 27 01:12:53 PM UTC 24 Aug 27 01:14:25 PM UTC 24 1943178700 ps
T690 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.2789496535 Aug 27 01:14:10 PM UTC 24 Aug 27 01:14:27 PM UTC 24 21290900 ps
T133 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.2667375691 Aug 27 01:06:14 PM UTC 24 Aug 27 01:14:30 PM UTC 24 34512069900 ps
T691 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.3188917073 Aug 27 01:13:46 PM UTC 24 Aug 27 01:14:30 PM UTC 24 37746200 ps
T692 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.4242161920 Aug 27 01:13:46 PM UTC 24 Aug 27 01:14:32 PM UTC 24 135293200 ps
T693 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.1313614732 Aug 27 01:13:51 PM UTC 24 Aug 27 01:14:33 PM UTC 24 25544500 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.305597906 Aug 27 01:12:33 PM UTC 24 Aug 27 01:14:33 PM UTC 24 1104760500 ps
T694 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.1112665053 Aug 27 01:14:15 PM UTC 24 Aug 27 01:14:34 PM UTC 24 47921900 ps
T695 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.3458658415 Aug 27 01:14:15 PM UTC 24 Aug 27 01:14:38 PM UTC 24 42915900 ps
T696 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.35224417 Aug 27 01:11:21 PM UTC 24 Aug 27 01:14:42 PM UTC 24 32326180900 ps
T697 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.3602800344 Aug 27 01:14:26 PM UTC 24 Aug 27 01:14:49 PM UTC 24 31440800 ps
T698 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.2248011743 Aug 27 01:14:02 PM UTC 24 Aug 27 01:15:11 PM UTC 24 1389967000 ps
T699 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.1278353591 Aug 27 01:10:24 PM UTC 24 Aug 27 01:15:17 PM UTC 24 12842288100 ps
T700 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.3640078107 Aug 27 01:14:32 PM UTC 24 Aug 27 01:15:43 PM UTC 24 1994723400 ps
T701 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3483755105 Aug 27 01:14:18 PM UTC 24 Aug 27 01:15:48 PM UTC 24 10048352000 ps
T702 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.1579255793 Aug 27 01:12:29 PM UTC 24 Aug 27 01:15:50 PM UTC 24 24302300 ps
T703 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3136849355 Aug 27 01:13:17 PM UTC 24 Aug 27 01:15:56 PM UTC 24 11708238300 ps
T704 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.1938871767 Aug 27 01:12:31 PM UTC 24 Aug 27 01:15:59 PM UTC 24 112331700 ps
T705 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.3107442551 Aug 27 01:01:59 PM UTC 24 Aug 27 01:16:04 PM UTC 24 160170561400 ps
T706 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.2329903882 Aug 27 01:14:39 PM UTC 24 Aug 27 01:16:04 PM UTC 24 2931617100 ps
T178 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.2177424351 Aug 27 01:12:39 PM UTC 24 Aug 27 01:16:07 PM UTC 24 85963600 ps
T707 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.3509135990 Aug 27 01:13:14 PM UTC 24 Aug 27 01:16:08 PM UTC 24 1281053300 ps
T708 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.236815388 Aug 27 01:12:50 PM UTC 24 Aug 27 01:16:10 PM UTC 24 2210743700 ps
T709 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.3770014304 Aug 27 01:15:49 PM UTC 24 Aug 27 01:16:16 PM UTC 24 21242800 ps
T710 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.549459636 Aug 27 01:08:49 PM UTC 24 Aug 27 01:16:26 PM UTC 24 38311390700 ps
T711 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.517844993 Aug 27 01:16:09 PM UTC 24 Aug 27 01:16:29 PM UTC 24 45201000 ps
T428 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.3946353551 Aug 27 01:15:51 PM UTC 24 Aug 27 01:16:31 PM UTC 24 85432800 ps
T712 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.922336059 Aug 27 01:14:32 PM UTC 24 Aug 27 01:16:32 PM UTC 24 109478000 ps
T713 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.242333758 Aug 27 01:16:09 PM UTC 24 Aug 27 01:16:33 PM UTC 24 24363300 ps
T714 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.54994305 Aug 27 01:16:05 PM UTC 24 Aug 27 01:16:34 PM UTC 24 12106000 ps
T715 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.3230112491 Aug 27 01:16:17 PM UTC 24 Aug 27 01:16:37 PM UTC 24 88365900 ps
T716 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.2930527825 Aug 27 01:16:11 PM UTC 24 Aug 27 01:16:37 PM UTC 24 26881300 ps
T717 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.3325111183 Aug 27 01:16:00 PM UTC 24 Aug 27 01:16:44 PM UTC 24 254825500 ps
T718 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.166694352 Aug 27 01:14:50 PM UTC 24 Aug 27 01:16:58 PM UTC 24 4914069800 ps
T719 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.1585170280 Aug 27 01:14:43 PM UTC 24 Aug 27 01:17:07 PM UTC 24 11737477600 ps
T220 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.3829876164 Aug 27 12:34:40 PM UTC 24 Aug 27 01:17:26 PM UTC 24 358562982300 ps
T180 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.878847215 Aug 27 01:14:35 PM UTC 24 Aug 27 01:17:44 PM UTC 24 360772500 ps
T720 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.1357849889 Aug 27 01:06:09 PM UTC 24 Aug 27 01:17:50 PM UTC 24 9187105800 ps
T412 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.822719608 Aug 27 01:16:39 PM UTC 24 Aug 27 01:17:53 PM UTC 24 6074250800 ps
T721 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3244480111 Aug 27 01:16:05 PM UTC 24 Aug 27 01:18:14 PM UTC 24 2433272000 ps
T722 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.1565474522 Aug 27 01:12:29 PM UTC 24 Aug 27 01:18:15 PM UTC 24 181313500 ps
T723 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.277901713 Aug 27 01:16:27 PM UTC 24 Aug 27 01:18:31 PM UTC 24 21802300 ps
T724 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.1998919573 Aug 27 01:17:54 PM UTC 24 Aug 27 01:18:43 PM UTC 24 44778500 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.1219237398 Aug 27 01:17:51 PM UTC 24 Aug 27 01:18:45 PM UTC 24 63570500 ps
T176 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.2959807968 Aug 27 01:06:11 PM UTC 24 Aug 27 01:18:46 PM UTC 24 80141227400 ps
T725 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.751860074 Aug 27 01:16:51 PM UTC 24 Aug 27 01:18:46 PM UTC 24 616894100 ps
T726 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.748918425 Aug 27 01:18:15 PM UTC 24 Aug 27 01:18:47 PM UTC 24 35878500 ps
T285 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.2191683002 Aug 27 01:16:17 PM UTC 24 Aug 27 01:18:52 PM UTC 24 10012163000 ps
T727 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.1048189071 Aug 27 01:16:33 PM UTC 24 Aug 27 01:19:01 PM UTC 24 1977557000 ps
T728 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.2280647037 Aug 27 01:18:47 PM UTC 24 Aug 27 01:19:05 PM UTC 24 29031400 ps
T729 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.3240924884 Aug 27 01:18:45 PM UTC 24 Aug 27 01:19:06 PM UTC 24 28473400 ps
T730 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.2807357546 Aug 27 01:18:46 PM UTC 24 Aug 27 01:19:11 PM UTC 24 26474000 ps
T731 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.1424195103 Aug 27 01:18:47 PM UTC 24 Aug 27 01:19:13 PM UTC 24 91198500 ps
T732 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.3951789423 Aug 27 01:15:19 PM UTC 24 Aug 27 01:19:16 PM UTC 24 1933161400 ps
T733 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.3819438696 Aug 27 01:15:44 PM UTC 24 Aug 27 01:19:21 PM UTC 24 39125084300 ps
T734 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.3468797958 Aug 27 01:17:07 PM UTC 24 Aug 27 01:19:23 PM UTC 24 1319916900 ps
T735 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.2922754908 Aug 27 01:04:22 PM UTC 24 Aug 27 01:19:24 PM UTC 24 40129092600 ps
T736 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.1006327118 Aug 27 01:18:15 PM UTC 24 Aug 27 01:19:25 PM UTC 24 90355600 ps
T134 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.560056992 Aug 27 01:12:48 PM UTC 24 Aug 27 01:19:27 PM UTC 24 24236637300 ps
T737 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.3598044528 Aug 27 01:14:28 PM UTC 24 Aug 27 01:19:35 PM UTC 24 45816500 ps
T738 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.3647350415 Aug 27 01:10:44 PM UTC 24 Aug 27 01:19:39 PM UTC 24 4469521300 ps
T739 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.1334109244 Aug 27 01:18:47 PM UTC 24 Aug 27 01:19:42 PM UTC 24 10060781900 ps
T403 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.1524018859 Aug 27 01:18:32 PM UTC 24 Aug 27 01:19:47 PM UTC 24 924315200 ps
T740 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.651970592 Aug 27 12:58:10 PM UTC 24 Aug 27 01:19:53 PM UTC 24 9132389700 ps
T741 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.1267742444 Aug 27 01:19:40 PM UTC 24 Aug 27 01:20:05 PM UTC 24 175325600 ps
T742 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.548958619 Aug 27 01:14:35 PM UTC 24 Aug 27 01:20:14 PM UTC 24 21056039200 ps
T743 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.1321584405 Aug 27 01:17:45 PM UTC 24 Aug 27 01:20:15 PM UTC 24 8078017900 ps
T744 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.2869985120 Aug 27 01:10:12 PM UTC 24 Aug 27 01:20:15 PM UTC 24 4059343800 ps
T745 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.738330312 Aug 27 01:08:27 PM UTC 24 Aug 27 01:20:18 PM UTC 24 2954183400 ps
T746 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.2090738101 Aug 27 01:19:43 PM UTC 24 Aug 27 01:20:19 PM UTC 24 68904300 ps
T747 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.2862970911 Aug 27 01:19:48 PM UTC 24 Aug 27 01:20:25 PM UTC 24 71360700 ps
T748 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.2463237722 Aug 27 12:58:27 PM UTC 24 Aug 27 01:20:31 PM UTC 24 1273392800 ps
T181 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.2985300818 Aug 27 01:16:35 PM UTC 24 Aug 27 01:20:32 PM UTC 24 70092100 ps
T749 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.2849522363 Aug 27 01:16:46 PM UTC 24 Aug 27 01:20:32 PM UTC 24 4876525700 ps
T750 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.3812606524 Aug 27 01:20:02 PM UTC 24 Aug 27 01:20:34 PM UTC 24 10799000 ps
T751 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.1207532510 Aug 27 01:20:17 PM UTC 24 Aug 27 01:20:42 PM UTC 24 15641000 ps
T752 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.3328196410 Aug 27 01:19:22 PM UTC 24 Aug 27 01:20:42 PM UTC 24 1670366400 ps
T753 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1210019864 Aug 27 01:20:20 PM UTC 24 Aug 27 01:20:43 PM UTC 24 139659900 ps
T754 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.48072482 Aug 27 01:20:16 PM UTC 24 Aug 27 01:20:43 PM UTC 24 25220000 ps
T755 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.631282097 Aug 27 01:19:54 PM UTC 24 Aug 27 01:20:46 PM UTC 24 387681300 ps
T84 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.3412850474 Aug 27 01:20:16 PM UTC 24 Aug 27 01:20:50 PM UTC 24 14336800 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.2546222082 Aug 27 01:19:07 PM UTC 24 Aug 27 01:21:07 PM UTC 24 3360274800 ps
T756 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.1337545126 Aug 27 01:16:39 PM UTC 24 Aug 27 01:21:24 PM UTC 24 13843786100 ps
T757 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.1185496442 Aug 27 01:19:25 PM UTC 24 Aug 27 01:21:24 PM UTC 24 673246700 ps
T758 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.2270145256 Aug 27 01:20:06 PM UTC 24 Aug 27 01:21:31 PM UTC 24 489100600 ps
T759 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.1495726273 Aug 27 01:20:19 PM UTC 24 Aug 27 01:21:34 PM UTC 24 10019293300 ps
T760 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.699057282 Aug 27 01:12:56 PM UTC 24 Aug 27 01:21:51 PM UTC 24 3838812500 ps
T761 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.2017349254 Aug 27 01:21:26 PM UTC 24 Aug 27 01:21:52 PM UTC 24 35483700 ps
T350 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.1577079635 Aug 27 01:19:28 PM UTC 24 Aug 27 01:22:06 PM UTC 24 743605400 ps
T762 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.293681727 Aug 27 01:19:13 PM UTC 24 Aug 27 01:22:09 PM UTC 24 88139000 ps
T763 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.1564947566 Aug 27 01:21:35 PM UTC 24 Aug 27 01:22:13 PM UTC 24 43993200 ps
T764 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.2703212837 Aug 27 01:21:32 PM UTC 24 Aug 27 01:22:24 PM UTC 24 56476600 ps
T765 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.2662780368 Aug 27 01:18:53 PM UTC 24 Aug 27 01:22:27 PM UTC 24 22870100 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.3575101398 Aug 27 01:21:53 PM UTC 24 Aug 27 01:22:30 PM UTC 24 22507400 ps
T766 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.1988988669 Aug 27 01:22:14 PM UTC 24 Aug 27 01:22:34 PM UTC 24 21170000 ps
T767 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3715321300 Aug 27 01:20:43 PM UTC 24 Aug 27 01:22:35 PM UTC 24 1169592000 ps
T768 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1910234524 Aug 27 01:19:36 PM UTC 24 Aug 27 01:22:36 PM UTC 24 52998842300 ps
T769 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.757895654 Aug 27 01:22:10 PM UTC 24 Aug 27 01:22:37 PM UTC 24 57598500 ps
T770 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.1499908679 Aug 27 01:19:24 PM UTC 24 Aug 27 01:22:38 PM UTC 24 4061731600 ps
T771 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1668430723 Aug 27 12:28:20 PM UTC 24 Aug 27 01:22:41 PM UTC 24 29220798200 ps
T772 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.2081668075 Aug 27 01:21:53 PM UTC 24 Aug 27 01:22:46 PM UTC 24 70426600 ps
T773 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.657976638 Aug 27 01:22:25 PM UTC 24 Aug 27 01:22:49 PM UTC 24 26225000 ps
T774 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.379648129 Aug 27 01:20:25 PM UTC 24 Aug 27 01:22:50 PM UTC 24 65985300 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3500674384 Aug 27 01:24:52 PM UTC 24 Aug 27 01:27:10 PM UTC 24 8207636900 ps
T775 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.1724898074 Aug 27 01:08:31 PM UTC 24 Aug 27 01:22:55 PM UTC 24 40125465000 ps
T776 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.3124116822 Aug 27 01:22:31 PM UTC 24 Aug 27 01:22:56 PM UTC 24 53737400 ps
T407 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.492379230 Aug 27 01:22:07 PM UTC 24 Aug 27 01:23:04 PM UTC 24 1746317000 ps
T777 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.1650570067 Aug 27 01:22:42 PM UTC 24 Aug 27 01:23:11 PM UTC 24 35067600 ps
T778 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1621028226 Aug 27 01:20:47 PM UTC 24 Aug 27 01:23:19 PM UTC 24 11593445400 ps
T779 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.1016159733 Aug 27 01:16:32 PM UTC 24 Aug 27 01:23:21 PM UTC 24 615029300 ps
T780 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.4018620917 Aug 27 01:22:50 PM UTC 24 Aug 27 01:23:27 PM UTC 24 33031000 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.2551028207 Aug 27 01:22:57 PM UTC 24 Aug 27 01:23:29 PM UTC 24 44519800 ps
T781 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.3459025085 Aug 27 01:23:05 PM UTC 24 Aug 27 01:23:35 PM UTC 24 98282600 ps
T782 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3153542460 Aug 27 01:22:27 PM UTC 24 Aug 27 01:23:38 PM UTC 24 10083503800 ps
T783 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.3657114117 Aug 27 01:22:49 PM UTC 24 Aug 27 01:23:39 PM UTC 24 83765200 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.3398892989 Aug 27 01:22:47 PM UTC 24 Aug 27 01:23:48 PM UTC 24 51206400 ps
T784 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.941405976 Aug 27 01:16:59 PM UTC 24 Aug 27 01:23:56 PM UTC 24 6266238700 ps
T785 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.1374404636 Aug 27 01:23:36 PM UTC 24 Aug 27 01:24:01 PM UTC 24 65031000 ps
T786 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.2342025894 Aug 27 01:20:45 PM UTC 24 Aug 27 01:24:01 PM UTC 24 2425303600 ps
T787 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.1485686603 Aug 27 01:21:26 PM UTC 24 Aug 27 01:24:05 PM UTC 24 15217806000 ps
T788 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.2042421848 Aug 27 01:22:35 PM UTC 24 Aug 27 01:24:11 PM UTC 24 29449300 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.632606314 Aug 27 01:23:48 PM UTC 24 Aug 27 01:24:16 PM UTC 24 10926100 ps
T789 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1297624833 Aug 27 01:20:33 PM UTC 24 Aug 27 01:24:17 PM UTC 24 5766846900 ps
T790 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.1784899717 Aug 27 01:24:02 PM UTC 24 Aug 27 01:24:19 PM UTC 24 24694700 ps
T791 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.1732765868 Aug 27 01:15:12 PM UTC 24 Aug 27 01:24:22 PM UTC 24 3861746300 ps
T792 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.1972234802 Aug 27 01:24:02 PM UTC 24 Aug 27 01:24:25 PM UTC 24 25307300 ps
T793 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.313982751 Aug 27 01:23:40 PM UTC 24 Aug 27 01:24:28 PM UTC 24 26561400 ps
T794 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.2315332980 Aug 27 01:22:39 PM UTC 24 Aug 27 01:24:34 PM UTC 24 649037900 ps
T795 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1290396164 Aug 27 01:04:16 PM UTC 24 Aug 27 01:24:43 PM UTC 24 840618100 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.2036152791 Aug 27 01:23:39 PM UTC 24 Aug 27 01:24:44 PM UTC 24 36605000 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.3824712165 Aug 27 01:22:56 PM UTC 24 Aug 27 01:24:44 PM UTC 24 2830478700 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.3855009882 Aug 27 01:24:23 PM UTC 24 Aug 27 01:24:48 PM UTC 24 20819700 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.4122542641 Aug 27 01:20:43 PM UTC 24 Aug 27 01:24:51 PM UTC 24 447726600 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.757006348 Aug 27 01:23:20 PM UTC 24 Aug 27 01:24:55 PM UTC 24 921075100 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.1274559527 Aug 27 01:21:08 PM UTC 24 Aug 27 01:24:55 PM UTC 24 6171399600 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.4045488939 Aug 27 01:08:42 PM UTC 24 Aug 27 01:25:02 PM UTC 24 31307198200 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.491268411 Aug 27 01:10:07 PM UTC 24 Aug 27 01:25:03 PM UTC 24 592698100 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.2690405080 Aug 27 01:22:36 PM UTC 24 Aug 27 01:25:04 PM UTC 24 11216016200 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.2090482648 Aug 27 01:24:25 PM UTC 24 Aug 27 01:25:07 PM UTC 24 75119700 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.82984455 Aug 27 01:24:29 PM UTC 24 Aug 27 01:25:08 PM UTC 24 253978400 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.40229784 Aug 27 01:24:46 PM UTC 24 Aug 27 01:25:10 PM UTC 24 37894400 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.996869991 Aug 27 01:22:39 PM UTC 24 Aug 27 01:25:13 PM UTC 24 5626177100 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.3752417994 Aug 27 01:24:45 PM UTC 24 Aug 27 01:25:13 PM UTC 24 16109300 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.3096861071 Aug 27 01:10:18 PM UTC 24 Aug 27 01:25:15 PM UTC 24 40127277400 ps
T91 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.3485601938 Aug 27 12:35:11 PM UTC 24 Aug 27 01:25:17 PM UTC 24 1135880100 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.2135793366 Aug 27 01:24:35 PM UTC 24 Aug 27 01:25:18 PM UTC 24 35086000 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.4172191079 Aug 27 01:23:28 PM UTC 24 Aug 27 01:25:29 PM UTC 24 8001900300 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.3119937914 Aug 27 01:23:57 PM UTC 24 Aug 27 01:25:33 PM UTC 24 2365460800 ps
T168 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.814482545 Aug 27 01:25:09 PM UTC 24 Aug 27 01:25:37 PM UTC 24 17718600 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.3011592663 Aug 27 01:23:22 PM UTC 24 Aug 27 01:25:39 PM UTC 24 185535200 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.1827676001 Aug 27 01:25:14 PM UTC 24 Aug 27 01:25:40 PM UTC 24 105042900 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.1022108654 Aug 27 01:25:14 PM UTC 24 Aug 27 01:25:44 PM UTC 24 31486900 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1018256452 Aug 27 01:17:27 PM UTC 24 Aug 27 01:25:51 PM UTC 24 240037999700 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.3797969782 Aug 27 01:19:25 PM UTC 24 Aug 27 01:25:51 PM UTC 24 13352609700 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.579394030 Aug 27 01:25:08 PM UTC 24 Aug 27 01:25:53 PM UTC 24 32555300 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.2901849118 Aug 27 01:22:37 PM UTC 24 Aug 27 01:25:54 PM UTC 24 141375600 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.1705820558 Aug 27 01:23:12 PM UTC 24 Aug 27 01:25:57 PM UTC 24 34960900 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.1999534233 Aug 27 01:23:30 PM UTC 24 Aug 27 01:26:00 PM UTC 24 5848341300 ps
T436 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.1444569896 Aug 27 01:25:06 PM UTC 24 Aug 27 01:26:02 PM UTC 24 32576600 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.4093745374 Aug 27 01:25:38 PM UTC 24 Aug 27 01:26:04 PM UTC 24 69860400 ps
T409 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.3469997936 Aug 27 01:24:44 PM UTC 24 Aug 27 01:26:09 PM UTC 24 2163308000 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.2729815685 Aug 27 01:06:09 PM UTC 24 Aug 27 01:26:12 PM UTC 24 852518900 ps
T205 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.704797959 Aug 27 01:12:36 PM UTC 24 Aug 27 01:26:13 PM UTC 24 80143510700 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.1786298312 Aug 27 01:25:54 PM UTC 24 Aug 27 01:26:18 PM UTC 24 19659600 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.1687098252 Aug 27 01:24:12 PM UTC 24 Aug 27 01:26:19 PM UTC 24 14427822000 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.2477547198 Aug 27 01:25:52 PM UTC 24 Aug 27 01:26:21 PM UTC 24 25943500 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.455618165 Aug 27 01:25:45 PM UTC 24 Aug 27 01:26:23 PM UTC 24 27995300 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.3689320604 Aug 27 01:20:33 PM UTC 24 Aug 27 01:26:24 PM UTC 24 2799673200 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.4264455015 Aug 27 01:25:15 PM UTC 24 Aug 27 01:26:24 PM UTC 24 18431300 ps
T438 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.3782729836 Aug 27 01:25:39 PM UTC 24 Aug 27 01:26:25 PM UTC 24 40336100 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.3513947894 Aug 27 01:24:06 PM UTC 24 Aug 27 01:26:27 PM UTC 24 45542600 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.595656915 Aug 27 01:26:10 PM UTC 24 Aug 27 01:26:27 PM UTC 24 22088100 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.142164352 Aug 27 01:25:41 PM UTC 24 Aug 27 01:26:31 PM UTC 24 76443900 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.2318889005 Aug 27 01:19:06 PM UTC 24 Aug 27 01:26:42 PM UTC 24 5099294500 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.1484196742 Aug 27 01:26:22 PM UTC 24 Aug 27 01:26:46 PM UTC 24 38654400 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.3500515754 Aug 27 01:26:23 PM UTC 24 Aug 27 01:26:53 PM UTC 24 129707800 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.2055361171 Aug 27 01:24:17 PM UTC 24 Aug 27 01:26:55 PM UTC 24 144141200 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1813155821 Aug 27 01:20:43 PM UTC 24 Aug 27 01:26:58 PM UTC 24 4696968700 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.158236255 Aug 27 01:25:11 PM UTC 24 Aug 27 01:26:58 PM UTC 24 1664947200 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.1177297973 Aug 27 01:24:20 PM UTC 24 Aug 27 01:27:00 PM UTC 24 25792694700 ps
T406 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.3046514905 Aug 27 01:25:52 PM UTC 24 Aug 27 01:27:00 PM UTC 24 443044400 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.4180819716 Aug 27 01:26:32 PM UTC 24 Aug 27 01:27:02 PM UTC 24 63613300 ps
T426 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.1411275930 Aug 27 01:26:14 PM UTC 24 Aug 27 01:27:03 PM UTC 24 25851900 ps
T386 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.38324409 Aug 27 01:26:20 PM UTC 24 Aug 27 01:27:04 PM UTC 24 17098900 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.2391025707 Aug 27 01:26:13 PM UTC 24 Aug 27 01:27:06 PM UTC 24 45329500 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.1404034736 Aug 27 01:26:26 PM UTC 24 Aug 27 01:27:19 PM UTC 24 948576200 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.3581328850 Aug 27 01:24:57 PM UTC 24 Aug 27 01:27:20 PM UTC 24 773525600 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.2934869254 Aug 27 01:26:47 PM UTC 24 Aug 27 01:27:24 PM UTC 24 63198700 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.1611053820 Aug 27 01:27:00 PM UTC 24 Aug 27 01:27:29 PM UTC 24 15894300 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3749274673 Aug 27 01:08:26 PM UTC 24 Aug 27 01:27:31 PM UTC 24 780363300 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.4112498564 Aug 27 01:27:00 PM UTC 24 Aug 27 01:27:31 PM UTC 24 144321700 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.2684596293 Aug 27 01:27:07 PM UTC 24 Aug 27 01:27:33 PM UTC 24 17908500 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.258830128 Aug 27 01:26:42 PM UTC 24 Aug 27 01:27:36 PM UTC 24 53556300 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.1795078759 Aug 27 01:26:54 PM UTC 24 Aug 27 01:27:36 PM UTC 24 16713600 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.2008525988 Aug 27 01:24:19 PM UTC 24 Aug 27 01:27:41 PM UTC 24 2791025100 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.3230009766 Aug 27 01:24:49 PM UTC 24 Aug 27 01:27:43 PM UTC 24 71801300 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.4170811384 Aug 27 01:26:56 PM UTC 24 Aug 27 01:27:50 PM UTC 24 672997100 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.3361674188 Aug 27 01:26:21 PM UTC 24 Aug 27 01:27:50 PM UTC 24 1337334300 ps
T179 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.4241454953 Aug 27 01:24:56 PM UTC 24 Aug 27 01:27:51 PM UTC 24 50479100 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.883030562 Aug 27 01:25:04 PM UTC 24 Aug 27 01:27:56 PM UTC 24 8764751400 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2821198295 Aug 27 01:25:34 PM UTC 24 Aug 27 01:27:57 PM UTC 24 5885490900 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.1563174352 Aug 27 01:27:31 PM UTC 24 Aug 27 01:27:57 PM UTC 24 34989000 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.3319481249 Aug 27 01:27:32 PM UTC 24 Aug 27 01:27:57 PM UTC 24 48264600 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2633771676 Aug 27 01:27:20 PM UTC 24 Aug 27 01:27:57 PM UTC 24 10535600 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.4246281030 Aug 27 12:35:14 PM UTC 24 Aug 27 01:27:59 PM UTC 24 26061168800 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.1937614340 Aug 27 01:27:44 PM UTC 24 Aug 27 01:28:11 PM UTC 24 62009400 ps
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