| T1084 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.4243532269 |
|
|
Aug 27 01:35:31 PM UTC 24 |
Aug 27 01:37:33 PM UTC 24 |
4916595700 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2715673848 |
|
|
Aug 27 01:37:12 PM UTC 24 |
Aug 27 01:37:33 PM UTC 24 |
39358300 ps |
| T94 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.463732159 |
|
|
Aug 27 01:32:43 PM UTC 24 |
Aug 27 01:37:34 PM UTC 24 |
12505706200 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.1038147602 |
|
|
Aug 27 01:37:10 PM UTC 24 |
Aug 27 01:37:34 PM UTC 24 |
40966700 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.2256621476 |
|
|
Aug 27 01:33:01 PM UTC 24 |
Aug 27 01:37:37 PM UTC 24 |
26654897500 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1451649125 |
|
|
Aug 27 01:34:47 PM UTC 24 |
Aug 27 01:37:47 PM UTC 24 |
80056200 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.947241977 |
|
|
Aug 27 01:34:47 PM UTC 24 |
Aug 27 01:37:49 PM UTC 24 |
9084778500 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2696095809 |
|
|
Aug 27 01:35:31 PM UTC 24 |
Aug 27 01:37:53 PM UTC 24 |
233899500 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.843339910 |
|
|
Aug 27 01:35:02 PM UTC 24 |
Aug 27 01:37:59 PM UTC 24 |
136846400 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.2625201272 |
|
|
Aug 27 01:35:16 PM UTC 24 |
Aug 27 01:38:03 PM UTC 24 |
135968300 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.2818499001 |
|
|
Aug 27 01:35:39 PM UTC 24 |
Aug 27 01:38:10 PM UTC 24 |
37385000 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.4228864348 |
|
|
Aug 27 01:35:58 PM UTC 24 |
Aug 27 01:38:15 PM UTC 24 |
44667600 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3178152752 |
|
|
Aug 27 01:35:57 PM UTC 24 |
Aug 27 01:38:21 PM UTC 24 |
47170600 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.1168468722 |
|
|
Aug 27 01:36:08 PM UTC 24 |
Aug 27 01:38:23 PM UTC 24 |
71890200 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.3918906175 |
|
|
Aug 27 01:35:51 PM UTC 24 |
Aug 27 01:38:28 PM UTC 24 |
103689100 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.566262730 |
|
|
Aug 27 01:20:35 PM UTC 24 |
Aug 27 01:38:31 PM UTC 24 |
320284490600 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.1983862423 |
|
|
Aug 27 01:35:36 PM UTC 24 |
Aug 27 01:38:37 PM UTC 24 |
75294100 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.2984078627 |
|
|
Aug 27 01:36:03 PM UTC 24 |
Aug 27 01:38:37 PM UTC 24 |
136384800 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1677014094 |
|
|
Aug 27 01:36:12 PM UTC 24 |
Aug 27 01:38:41 PM UTC 24 |
181388600 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3207804815 |
|
|
Aug 27 01:36:05 PM UTC 24 |
Aug 27 01:38:45 PM UTC 24 |
75784300 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.931867731 |
|
|
Aug 27 01:36:00 PM UTC 24 |
Aug 27 01:38:46 PM UTC 24 |
38366100 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.475959400 |
|
|
Aug 27 01:35:02 PM UTC 24 |
Aug 27 01:38:51 PM UTC 24 |
3737135300 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.2574358923 |
|
|
Aug 27 01:36:25 PM UTC 24 |
Aug 27 01:39:04 PM UTC 24 |
140896500 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.2583379917 |
|
|
Aug 27 01:35:46 PM UTC 24 |
Aug 27 01:39:06 PM UTC 24 |
44488400 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.2191252171 |
|
|
Aug 27 01:36:22 PM UTC 24 |
Aug 27 01:39:12 PM UTC 24 |
142341500 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.1885872894 |
|
|
Aug 27 01:36:17 PM UTC 24 |
Aug 27 01:39:14 PM UTC 24 |
37131700 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.44430408 |
|
|
Aug 27 01:36:36 PM UTC 24 |
Aug 27 01:39:15 PM UTC 24 |
70199700 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.86027638 |
|
|
Aug 27 01:36:38 PM UTC 24 |
Aug 27 01:39:16 PM UTC 24 |
139437400 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.3416077923 |
|
|
Aug 27 01:36:15 PM UTC 24 |
Aug 27 01:39:18 PM UTC 24 |
38494000 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.4123157851 |
|
|
Aug 27 01:36:33 PM UTC 24 |
Aug 27 01:39:32 PM UTC 24 |
319818700 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.4001017988 |
|
|
Aug 27 01:36:47 PM UTC 24 |
Aug 27 01:39:36 PM UTC 24 |
43792100 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.761134002 |
|
|
Aug 27 01:36:50 PM UTC 24 |
Aug 27 01:39:37 PM UTC 24 |
322807800 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.2248862595 |
|
|
Aug 27 01:36:28 PM UTC 24 |
Aug 27 01:39:39 PM UTC 24 |
43899700 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.2083497908 |
|
|
Aug 27 01:36:36 PM UTC 24 |
Aug 27 01:39:43 PM UTC 24 |
339241600 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.175062885 |
|
|
Aug 27 01:37:00 PM UTC 24 |
Aug 27 01:39:44 PM UTC 24 |
40103100 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.862641299 |
|
|
Aug 27 01:36:45 PM UTC 24 |
Aug 27 01:39:50 PM UTC 24 |
40711000 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1948588215 |
|
|
Aug 27 01:37:10 PM UTC 24 |
Aug 27 01:39:53 PM UTC 24 |
66914200 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.2547650896 |
|
|
Aug 27 01:37:03 PM UTC 24 |
Aug 27 01:40:01 PM UTC 24 |
37722900 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.1959078127 |
|
|
Aug 27 01:36:55 PM UTC 24 |
Aug 27 01:40:06 PM UTC 24 |
36015400 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1506319892 |
|
|
Aug 27 01:36:31 PM UTC 24 |
Aug 27 01:40:07 PM UTC 24 |
37978100 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.2043374404 |
|
|
Aug 27 01:37:00 PM UTC 24 |
Aug 27 01:40:09 PM UTC 24 |
132037200 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.262254914 |
|
|
Aug 27 01:37:10 PM UTC 24 |
Aug 27 01:40:14 PM UTC 24 |
77255800 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.2875833035 |
|
|
Aug 27 12:50:42 PM UTC 24 |
Aug 27 01:40:18 PM UTC 24 |
20751429300 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.2822759045 |
|
|
Aug 27 01:14:32 PM UTC 24 |
Aug 27 01:40:21 PM UTC 24 |
804568700 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.2381188342 |
|
|
Aug 27 12:27:40 PM UTC 24 |
Aug 27 01:40:26 PM UTC 24 |
611397755700 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.4001697518 |
|
|
Aug 27 12:55:17 PM UTC 24 |
Aug 27 01:48:41 PM UTC 24 |
69422356200 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.916250847 |
|
|
Aug 27 12:58:33 PM UTC 24 |
Aug 27 01:49:25 PM UTC 24 |
7461602000 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.3941506247 |
|
|
Aug 27 12:12:32 PM UTC 24 |
Aug 27 02:01:23 PM UTC 24 |
25660402200 ps |
| T43 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3314466954 |
|
|
Aug 27 12:24:32 PM UTC 24 |
Aug 27 02:10:48 PM UTC 24 |
5239151200 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.3653068161 |
|
|
Aug 27 12:17:30 PM UTC 24 |
Aug 27 02:18:40 PM UTC 24 |
3785417500 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.147174577 |
|
|
Aug 27 12:32:25 PM UTC 24 |
Aug 27 02:20:19 PM UTC 24 |
1028074300 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3437555487 |
|
|
Aug 27 12:40:36 PM UTC 24 |
Aug 27 02:27:31 PM UTC 24 |
4423667100 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.2359466832 |
|
|
Aug 27 06:30:16 PM UTC 24 |
Aug 27 06:30:40 PM UTC 24 |
94720100 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.3651190339 |
|
|
Aug 27 06:30:19 PM UTC 24 |
Aug 27 06:30:41 PM UTC 24 |
44674500 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3567943302 |
|
|
Aug 27 06:30:15 PM UTC 24 |
Aug 27 06:30:45 PM UTC 24 |
18667000 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.1972645175 |
|
|
Aug 27 06:30:12 PM UTC 24 |
Aug 27 06:30:46 PM UTC 24 |
39382200 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.1618511354 |
|
|
Aug 27 06:30:17 PM UTC 24 |
Aug 27 06:30:48 PM UTC 24 |
20098800 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1293809802 |
|
|
Aug 27 06:30:23 PM UTC 24 |
Aug 27 06:30:53 PM UTC 24 |
142943100 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2278673260 |
|
|
Aug 27 06:30:30 PM UTC 24 |
Aug 27 06:31:05 PM UTC 24 |
118546100 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2999258868 |
|
|
Aug 27 06:30:41 PM UTC 24 |
Aug 27 06:31:14 PM UTC 24 |
260611900 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.3860288909 |
|
|
Aug 27 06:30:45 PM UTC 24 |
Aug 27 06:31:18 PM UTC 24 |
190128200 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.459323535 |
|
|
Aug 27 06:30:51 PM UTC 24 |
Aug 27 06:31:21 PM UTC 24 |
12598200 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.3509375 |
|
|
Aug 27 06:30:47 PM UTC 24 |
Aug 27 06:31:23 PM UTC 24 |
106471700 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.1529129485 |
|
|
Aug 27 06:30:54 PM UTC 24 |
Aug 27 06:31:23 PM UTC 24 |
21427900 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.3406557272 |
|
|
Aug 27 06:31:07 PM UTC 24 |
Aug 27 06:31:26 PM UTC 24 |
63960300 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3955958535 |
|
|
Aug 27 06:30:59 PM UTC 24 |
Aug 27 06:31:29 PM UTC 24 |
17457100 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.2641385854 |
|
|
Aug 27 06:31:07 PM UTC 24 |
Aug 27 06:31:29 PM UTC 24 |
13985800 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.1193451185 |
|
|
Aug 27 06:31:15 PM UTC 24 |
Aug 27 06:31:36 PM UTC 24 |
471956400 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.1194589661 |
|
|
Aug 27 06:30:41 PM UTC 24 |
Aug 27 06:31:39 PM UTC 24 |
2645046400 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.808928888 |
|
|
Aug 27 06:31:19 PM UTC 24 |
Aug 27 06:31:40 PM UTC 24 |
34414600 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2102854409 |
|
|
Aug 27 06:31:16 PM UTC 24 |
Aug 27 06:31:44 PM UTC 24 |
194906200 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.3806399314 |
|
|
Aug 27 06:30:26 PM UTC 24 |
Aug 27 06:31:45 PM UTC 24 |
168778700 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.3738532326 |
|
|
Aug 27 06:31:24 PM UTC 24 |
Aug 27 06:31:48 PM UTC 24 |
41682300 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.2098792802 |
|
|
Aug 27 06:31:18 PM UTC 24 |
Aug 27 06:31:50 PM UTC 24 |
101735700 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.3001269038 |
|
|
Aug 27 06:31:24 PM UTC 24 |
Aug 27 06:31:51 PM UTC 24 |
16335600 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.1819367083 |
|
|
Aug 27 06:31:28 PM UTC 24 |
Aug 27 06:31:51 PM UTC 24 |
106201200 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.3432408951 |
|
|
Aug 27 06:31:24 PM UTC 24 |
Aug 27 06:31:51 PM UTC 24 |
31315100 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.3223892218 |
|
|
Aug 27 06:31:22 PM UTC 24 |
Aug 27 06:31:55 PM UTC 24 |
12728800 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.3496102790 |
|
|
Aug 27 06:31:22 PM UTC 24 |
Aug 27 06:31:55 PM UTC 24 |
193787200 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2573734381 |
|
|
Aug 27 06:31:36 PM UTC 24 |
Aug 27 06:32:00 PM UTC 24 |
187154700 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.858868744 |
|
|
Aug 27 06:30:32 PM UTC 24 |
Aug 27 06:32:04 PM UTC 24 |
2623519300 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2245337571 |
|
|
Aug 27 06:31:41 PM UTC 24 |
Aug 27 06:32:06 PM UTC 24 |
112681600 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.560462633 |
|
|
Aug 27 06:31:47 PM UTC 24 |
Aug 27 06:32:08 PM UTC 24 |
20120200 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.488483405 |
|
|
Aug 27 06:31:28 PM UTC 24 |
Aug 27 06:32:08 PM UTC 24 |
336568600 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.2336118143 |
|
|
Aug 27 06:31:49 PM UTC 24 |
Aug 27 06:32:09 PM UTC 24 |
27819700 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.4128774724 |
|
|
Aug 27 06:31:40 PM UTC 24 |
Aug 27 06:32:12 PM UTC 24 |
73802700 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.1574770724 |
|
|
Aug 27 06:31:52 PM UTC 24 |
Aug 27 06:32:15 PM UTC 24 |
17809700 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.243588097 |
|
|
Aug 27 06:31:52 PM UTC 24 |
Aug 27 06:32:15 PM UTC 24 |
50476800 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1756148951 |
|
|
Aug 27 06:31:47 PM UTC 24 |
Aug 27 06:32:17 PM UTC 24 |
11557800 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.1969183631 |
|
|
Aug 27 06:31:16 PM UTC 24 |
Aug 27 06:32:18 PM UTC 24 |
2605319300 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2448242303 |
|
|
Aug 27 06:31:10 PM UTC 24 |
Aug 27 06:32:18 PM UTC 24 |
221418400 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.3990485878 |
|
|
Aug 27 06:31:52 PM UTC 24 |
Aug 27 06:32:20 PM UTC 24 |
64894400 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.74439858 |
|
|
Aug 27 06:32:00 PM UTC 24 |
Aug 27 06:32:24 PM UTC 24 |
61424800 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.4141109892 |
|
|
Aug 27 06:31:30 PM UTC 24 |
Aug 27 06:32:25 PM UTC 24 |
293591900 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.2413161201 |
|
|
Aug 27 06:32:05 PM UTC 24 |
Aug 27 06:32:27 PM UTC 24 |
11291700 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1646935521 |
|
|
Aug 27 06:32:07 PM UTC 24 |
Aug 27 06:32:29 PM UTC 24 |
15066800 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1023019082 |
|
|
Aug 27 06:31:30 PM UTC 24 |
Aug 27 06:32:30 PM UTC 24 |
646763800 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.132142917 |
|
|
Aug 27 06:31:57 PM UTC 24 |
Aug 27 06:32:32 PM UTC 24 |
24409900 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.766832577 |
|
|
Aug 27 06:31:52 PM UTC 24 |
Aug 27 06:32:32 PM UTC 24 |
34481200 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1831831299 |
|
|
Aug 27 06:32:09 PM UTC 24 |
Aug 27 06:32:34 PM UTC 24 |
27700700 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2315047689 |
|
|
Aug 27 06:32:09 PM UTC 24 |
Aug 27 06:32:36 PM UTC 24 |
29091300 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.360638522 |
|
|
Aug 27 06:32:10 PM UTC 24 |
Aug 27 06:32:37 PM UTC 24 |
62273800 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.2948785514 |
|
|
Aug 27 06:32:20 PM UTC 24 |
Aug 27 06:32:39 PM UTC 24 |
303453800 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.3437171045 |
|
|
Aug 27 06:31:57 PM UTC 24 |
Aug 27 06:32:39 PM UTC 24 |
156579200 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.799108834 |
|
|
Aug 27 06:32:16 PM UTC 24 |
Aug 27 06:32:40 PM UTC 24 |
52968200 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.2914662764 |
|
|
Aug 27 06:32:21 PM UTC 24 |
Aug 27 06:32:41 PM UTC 24 |
13977700 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.161991684 |
|
|
Aug 27 06:32:24 PM UTC 24 |
Aug 27 06:32:47 PM UTC 24 |
18362400 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.3544866760 |
|
|
Aug 27 06:32:18 PM UTC 24 |
Aug 27 06:32:47 PM UTC 24 |
126255400 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2959855018 |
|
|
Aug 27 06:32:33 PM UTC 24 |
Aug 27 06:32:51 PM UTC 24 |
47842500 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.1832812653 |
|
|
Aug 27 06:32:25 PM UTC 24 |
Aug 27 06:32:55 PM UTC 24 |
106323000 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1305387153 |
|
|
Aug 27 06:32:20 PM UTC 24 |
Aug 27 06:32:56 PM UTC 24 |
125944100 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4072300928 |
|
|
Aug 27 06:32:29 PM UTC 24 |
Aug 27 06:32:58 PM UTC 24 |
28511300 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1793012426 |
|
|
Aug 27 06:32:37 PM UTC 24 |
Aug 27 06:32:59 PM UTC 24 |
57564300 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.126691100 |
|
|
Aug 27 06:32:28 PM UTC 24 |
Aug 27 06:33:01 PM UTC 24 |
19097600 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.2024151238 |
|
|
Aug 27 06:32:35 PM UTC 24 |
Aug 27 06:33:03 PM UTC 24 |
24973300 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.3211519861 |
|
|
Aug 27 06:32:41 PM UTC 24 |
Aug 27 06:33:04 PM UTC 24 |
30185500 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.2249799870 |
|
|
Aug 27 06:32:36 PM UTC 24 |
Aug 27 06:33:04 PM UTC 24 |
77955100 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.1208701206 |
|
|
Aug 27 06:32:40 PM UTC 24 |
Aug 27 06:33:06 PM UTC 24 |
24887100 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.2095583823 |
|
|
Aug 27 06:31:16 PM UTC 24 |
Aug 27 06:33:06 PM UTC 24 |
13093548700 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.696646811 |
|
|
Aug 27 06:32:48 PM UTC 24 |
Aug 27 06:33:07 PM UTC 24 |
41665000 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.886850546 |
|
|
Aug 27 06:32:48 PM UTC 24 |
Aug 27 06:33:07 PM UTC 24 |
12486700 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1929369696 |
|
|
Aug 27 06:32:40 PM UTC 24 |
Aug 27 06:33:07 PM UTC 24 |
114954600 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3484059487 |
|
|
Aug 27 06:32:31 PM UTC 24 |
Aug 27 06:33:08 PM UTC 24 |
110738500 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.2995060703 |
|
|
Aug 27 06:32:52 PM UTC 24 |
Aug 27 06:33:12 PM UTC 24 |
15502700 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2154680907 |
|
|
Aug 27 06:32:56 PM UTC 24 |
Aug 27 06:33:18 PM UTC 24 |
75175500 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.2688613905 |
|
|
Aug 27 06:33:01 PM UTC 24 |
Aug 27 06:33:23 PM UTC 24 |
14009800 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.54416014 |
|
|
Aug 27 06:32:55 PM UTC 24 |
Aug 27 06:33:21 PM UTC 24 |
90618700 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.903338047 |
|
|
Aug 27 06:32:28 PM UTC 24 |
Aug 27 06:33:23 PM UTC 24 |
62652400 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.1931575229 |
|
|
Aug 27 06:33:04 PM UTC 24 |
Aug 27 06:33:23 PM UTC 24 |
21338800 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3557636101 |
|
|
Aug 27 06:32:17 PM UTC 24 |
Aug 27 06:33:23 PM UTC 24 |
6262642200 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.276009411 |
|
|
Aug 27 06:31:55 PM UTC 24 |
Aug 27 06:33:25 PM UTC 24 |
20421735200 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1150206018 |
|
|
Aug 27 06:33:04 PM UTC 24 |
Aug 27 06:33:26 PM UTC 24 |
59163700 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2508012251 |
|
|
Aug 27 06:32:59 PM UTC 24 |
Aug 27 06:33:28 PM UTC 24 |
61343700 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.2456106567 |
|
|
Aug 27 06:33:07 PM UTC 24 |
Aug 27 06:33:30 PM UTC 24 |
11467300 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.250274750 |
|
|
Aug 27 06:33:06 PM UTC 24 |
Aug 27 06:33:31 PM UTC 24 |
82723200 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.1027263252 |
|
|
Aug 27 06:33:07 PM UTC 24 |
Aug 27 06:33:33 PM UTC 24 |
126902000 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3249162277 |
|
|
Aug 27 06:32:57 PM UTC 24 |
Aug 27 06:33:33 PM UTC 24 |
100323400 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.691708872 |
|
|
Aug 27 06:33:08 PM UTC 24 |
Aug 27 06:33:34 PM UTC 24 |
30667100 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.1947965560 |
|
|
Aug 27 06:33:07 PM UTC 24 |
Aug 27 06:33:35 PM UTC 24 |
26681800 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1963490977 |
|
|
Aug 27 06:33:03 PM UTC 24 |
Aug 27 06:33:36 PM UTC 24 |
26170100 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.957132267 |
|
|
Aug 27 06:33:09 PM UTC 24 |
Aug 27 06:33:37 PM UTC 24 |
31366000 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1798131321 |
|
|
Aug 27 06:33:14 PM UTC 24 |
Aug 27 06:33:38 PM UTC 24 |
321325100 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.3562200435 |
|
|
Aug 27 06:33:21 PM UTC 24 |
Aug 27 06:33:43 PM UTC 24 |
13378400 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.3249859249 |
|
|
Aug 27 06:33:24 PM UTC 24 |
Aug 27 06:33:44 PM UTC 24 |
16824500 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.3137001470 |
|
|
Aug 27 06:32:12 PM UTC 24 |
Aug 27 06:33:45 PM UTC 24 |
24979500 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3316690298 |
|
|
Aug 27 06:33:25 PM UTC 24 |
Aug 27 06:33:47 PM UTC 24 |
129588100 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.343747470 |
|
|
Aug 27 06:33:24 PM UTC 24 |
Aug 27 06:33:48 PM UTC 24 |
113904400 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1783898467 |
|
|
Aug 27 06:33:14 PM UTC 24 |
Aug 27 06:33:49 PM UTC 24 |
92876400 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1689034986 |
|
|
Aug 27 06:33:19 PM UTC 24 |
Aug 27 06:33:51 PM UTC 24 |
32850100 ps |
| T301 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.3990182628 |
|
|
Aug 27 06:33:04 PM UTC 24 |
Aug 27 06:33:52 PM UTC 24 |
215460300 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.1764342783 |
|
|
Aug 27 06:33:34 PM UTC 24 |
Aug 27 06:33:52 PM UTC 24 |
16871900 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2361208444 |
|
|
Aug 27 06:33:24 PM UTC 24 |
Aug 27 06:33:53 PM UTC 24 |
14076600 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3057002531 |
|
|
Aug 27 06:33:36 PM UTC 24 |
Aug 27 06:33:53 PM UTC 24 |
810662300 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1189626524 |
|
|
Aug 27 06:31:53 PM UTC 24 |
Aug 27 06:33:54 PM UTC 24 |
14424164700 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1345678637 |
|
|
Aug 27 06:33:26 PM UTC 24 |
Aug 27 06:33:55 PM UTC 24 |
140159700 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.2659976712 |
|
|
Aug 27 06:33:39 PM UTC 24 |
Aug 27 06:33:55 PM UTC 24 |
35271300 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3598594160 |
|
|
Aug 27 06:33:34 PM UTC 24 |
Aug 27 06:33:57 PM UTC 24 |
71149300 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.224816200 |
|
|
Aug 27 06:33:32 PM UTC 24 |
Aug 27 06:33:58 PM UTC 24 |
34138800 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.213598165 |
|
|
Aug 27 06:33:28 PM UTC 24 |
Aug 27 06:34:01 PM UTC 24 |
422433600 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.2463007649 |
|
|
Aug 27 06:33:37 PM UTC 24 |
Aug 27 06:34:02 PM UTC 24 |
122799600 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.685721447 |
|
|
Aug 27 06:33:45 PM UTC 24 |
Aug 27 06:34:05 PM UTC 24 |
27815900 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.3550291351 |
|
|
Aug 27 06:32:16 PM UTC 24 |
Aug 27 06:34:06 PM UTC 24 |
14694118200 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3972664659 |
|
|
Aug 27 06:33:31 PM UTC 24 |
Aug 27 06:34:06 PM UTC 24 |
30389600 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.687379653 |
|
|
Aug 27 06:33:53 PM UTC 24 |
Aug 27 06:34:10 PM UTC 24 |
14574000 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1144726203 |
|
|
Aug 27 06:33:44 PM UTC 24 |
Aug 27 06:34:12 PM UTC 24 |
19623300 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.1093465307 |
|
|
Aug 27 06:33:48 PM UTC 24 |
Aug 27 06:34:12 PM UTC 24 |
188000400 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.4053674042 |
|
|
Aug 27 06:33:53 PM UTC 24 |
Aug 27 06:34:12 PM UTC 24 |
14546300 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1603581747 |
|
|
Aug 27 06:33:57 PM UTC 24 |
Aug 27 06:34:15 PM UTC 24 |
30965000 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3925221265 |
|
|
Aug 27 06:33:46 PM UTC 24 |
Aug 27 06:34:18 PM UTC 24 |
101144700 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.3706987728 |
|
|
Aug 27 06:33:52 PM UTC 24 |
Aug 27 06:34:18 PM UTC 24 |
12462700 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.904737406 |
|
|
Aug 27 06:33:48 PM UTC 24 |
Aug 27 06:34:18 PM UTC 24 |
260094200 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2797292874 |
|
|
Aug 27 06:33:57 PM UTC 24 |
Aug 27 06:34:19 PM UTC 24 |
120927400 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.1097271657 |
|
|
Aug 27 06:33:57 PM UTC 24 |
Aug 27 06:34:19 PM UTC 24 |
13079900 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1161641418 |
|
|
Aug 27 06:33:49 PM UTC 24 |
Aug 27 06:34:19 PM UTC 24 |
67533100 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.698715246 |
|
|
Aug 27 06:33:54 PM UTC 24 |
Aug 27 06:34:20 PM UTC 24 |
222695200 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.3588568921 |
|
|
Aug 27 06:33:54 PM UTC 24 |
Aug 27 06:34:21 PM UTC 24 |
28397000 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.139305491 |
|
|
Aug 27 06:33:58 PM UTC 24 |
Aug 27 06:34:25 PM UTC 24 |
12250100 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3502172055 |
|
|
Aug 27 06:33:35 PM UTC 24 |
Aug 27 06:34:27 PM UTC 24 |
340423700 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3173572061 |
|
|
Aug 27 06:34:01 PM UTC 24 |
Aug 27 06:34:27 PM UTC 24 |
54558700 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3752356570 |
|
|
Aug 27 06:34:02 PM UTC 24 |
Aug 27 06:34:27 PM UTC 24 |
95141600 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.108818680 |
|
|
Aug 27 06:34:01 PM UTC 24 |
Aug 27 06:34:27 PM UTC 24 |
101774000 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1146871929 |
|
|
Aug 27 06:34:01 PM UTC 24 |
Aug 27 06:34:28 PM UTC 24 |
18986400 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.3866134971 |
|
|
Aug 27 06:34:04 PM UTC 24 |
Aug 27 06:34:29 PM UTC 24 |
140210600 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.886716032 |
|
|
Aug 27 06:34:06 PM UTC 24 |
Aug 27 06:34:29 PM UTC 24 |
15005100 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1175199913 |
|
|
Aug 27 06:34:06 PM UTC 24 |
Aug 27 06:34:33 PM UTC 24 |
16408700 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.836049546 |
|
|
Aug 27 06:34:07 PM UTC 24 |
Aug 27 06:34:33 PM UTC 24 |
77388500 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.1660661846 |
|
|
Aug 27 06:34:14 PM UTC 24 |
Aug 27 06:34:36 PM UTC 24 |
31707200 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.3686664878 |
|
|
Aug 27 06:34:17 PM UTC 24 |
Aug 27 06:34:36 PM UTC 24 |
93941800 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1604105088 |
|
|
Aug 27 06:34:14 PM UTC 24 |
Aug 27 06:34:37 PM UTC 24 |
35705400 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2286562149 |
|
|
Aug 27 06:34:10 PM UTC 24 |
Aug 27 06:34:38 PM UTC 24 |
107932800 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2669676007 |
|
|
Aug 27 06:34:14 PM UTC 24 |
Aug 27 06:34:39 PM UTC 24 |
202614100 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3026893665 |
|
|
Aug 27 06:34:19 PM UTC 24 |
Aug 27 06:34:41 PM UTC 24 |
161794700 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.634024319 |
|
|
Aug 27 06:34:21 PM UTC 24 |
Aug 27 06:34:42 PM UTC 24 |
14337700 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.4240827483 |
|
|
Aug 27 06:34:19 PM UTC 24 |
Aug 27 06:34:43 PM UTC 24 |
136178100 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.4034800182 |
|
|
Aug 27 06:34:22 PM UTC 24 |
Aug 27 06:34:43 PM UTC 24 |
15743600 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1051686694 |
|
|
Aug 27 06:34:21 PM UTC 24 |
Aug 27 06:34:43 PM UTC 24 |
45017800 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1908796656 |
|
|
Aug 27 06:34:14 PM UTC 24 |
Aug 27 06:34:44 PM UTC 24 |
12229000 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3577901618 |
|
|
Aug 27 06:34:19 PM UTC 24 |
Aug 27 06:34:45 PM UTC 24 |
67001300 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.1508033129 |
|
|
Aug 27 06:34:25 PM UTC 24 |
Aug 27 06:34:46 PM UTC 24 |
330272000 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3391518127 |
|
|
Aug 27 06:34:25 PM UTC 24 |
Aug 27 06:34:48 PM UTC 24 |
32481900 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2882124520 |
|
|
Aug 27 06:34:19 PM UTC 24 |
Aug 27 06:34:49 PM UTC 24 |
78170400 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.2287136695 |
|
|
Aug 27 06:34:30 PM UTC 24 |
Aug 27 06:34:49 PM UTC 24 |
24089100 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3226003464 |
|
|
Aug 27 06:34:29 PM UTC 24 |
Aug 27 06:34:50 PM UTC 24 |
13375600 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.4146388900 |
|
|
Aug 27 06:34:34 PM UTC 24 |
Aug 27 06:34:52 PM UTC 24 |
181223600 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.1022117185 |
|
|
Aug 27 06:34:29 PM UTC 24 |
Aug 27 06:34:53 PM UTC 24 |
139968200 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1392485794 |
|
|
Aug 27 06:34:12 PM UTC 24 |
Aug 27 06:34:54 PM UTC 24 |
117367000 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.332507218 |
|
|
Aug 27 06:34:27 PM UTC 24 |
Aug 27 06:34:54 PM UTC 24 |
54254600 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1582656151 |
|
|
Aug 27 06:34:30 PM UTC 24 |
Aug 27 06:34:55 PM UTC 24 |
30493100 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.1936563280 |
|
|
Aug 27 06:34:34 PM UTC 24 |
Aug 27 06:34:56 PM UTC 24 |
77351300 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.4010809160 |
|
|
Aug 27 06:34:40 PM UTC 24 |
Aug 27 06:34:58 PM UTC 24 |
56757200 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.3891802664 |
|
|
Aug 27 06:34:26 PM UTC 24 |
Aug 27 06:34:59 PM UTC 24 |
55609500 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.3443953449 |
|
|
Aug 27 06:34:37 PM UTC 24 |
Aug 27 06:35:00 PM UTC 24 |
58843300 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.999098990 |
|
|
Aug 27 06:34:45 PM UTC 24 |
Aug 27 06:35:02 PM UTC 24 |
24426400 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.4175751106 |
|
|
Aug 27 06:34:30 PM UTC 24 |
Aug 27 06:35:03 PM UTC 24 |
218675300 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1983725452 |
|
|
Aug 27 06:34:45 PM UTC 24 |
Aug 27 06:35:03 PM UTC 24 |
15126400 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1944051303 |
|
|
Aug 27 06:34:41 PM UTC 24 |
Aug 27 06:35:04 PM UTC 24 |
106702300 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.514892912 |
|
|
Aug 27 06:34:45 PM UTC 24 |
Aug 27 06:35:05 PM UTC 24 |
15374000 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.2212354222 |
|
|
Aug 27 06:34:38 PM UTC 24 |
Aug 27 06:35:06 PM UTC 24 |
63848300 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.3472775336 |
|
|
Aug 27 06:34:45 PM UTC 24 |
Aug 27 06:35:08 PM UTC 24 |
42112000 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2006021692 |
|
|
Aug 27 06:34:43 PM UTC 24 |
Aug 27 06:35:09 PM UTC 24 |
383544300 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1421616620 |
|
|
Aug 27 06:34:42 PM UTC 24 |
Aug 27 06:35:09 PM UTC 24 |
166214600 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.4013190507 |
|
|
Aug 27 06:34:50 PM UTC 24 |
Aug 27 06:35:09 PM UTC 24 |
24803300 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.2918679988 |
|
|
Aug 27 06:34:50 PM UTC 24 |
Aug 27 06:35:12 PM UTC 24 |
18773400 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.891427553 |
|
|
Aug 27 06:34:48 PM UTC 24 |
Aug 27 06:35:12 PM UTC 24 |
17363100 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.939267138 |
|
|
Aug 27 06:34:54 PM UTC 24 |
Aug 27 06:35:12 PM UTC 24 |
59608400 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.266674792 |
|
|
Aug 27 06:34:46 PM UTC 24 |
Aug 27 06:35:12 PM UTC 24 |
17952700 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2240171766 |
|
|
Aug 27 06:34:56 PM UTC 24 |
Aug 27 06:35:13 PM UTC 24 |
20616300 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.3327674527 |
|
|
Aug 27 06:34:55 PM UTC 24 |
Aug 27 06:35:13 PM UTC 24 |
16568500 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1058118720 |
|
|
Aug 27 06:34:55 PM UTC 24 |
Aug 27 06:35:13 PM UTC 24 |
98929300 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.1541779674 |
|
|
Aug 27 06:34:51 PM UTC 24 |
Aug 27 06:35:14 PM UTC 24 |
47864000 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.456570593 |
|
|
Aug 27 06:34:53 PM UTC 24 |
Aug 27 06:35:16 PM UTC 24 |
21595400 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.1016849775 |
|
|
Aug 27 06:34:58 PM UTC 24 |
Aug 27 06:35:17 PM UTC 24 |
51426900 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.1680410497 |
|
|
Aug 27 06:34:48 PM UTC 24 |
Aug 27 06:35:18 PM UTC 24 |
36011300 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.4132242166 |
|
|
Aug 27 06:34:57 PM UTC 24 |
Aug 27 06:35:19 PM UTC 24 |
14498500 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.649693542 |
|
|
Aug 27 06:34:50 PM UTC 24 |
Aug 27 06:35:20 PM UTC 24 |
37043300 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.1248976961 |
|
|
Aug 27 06:35:04 PM UTC 24 |
Aug 27 06:35:24 PM UTC 24 |
28595500 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2566716645 |
|
|
Aug 27 06:35:00 PM UTC 24 |
Aug 27 06:35:24 PM UTC 24 |
17635300 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.151356341 |
|
|
Aug 27 06:35:05 PM UTC 24 |
Aug 27 06:35:24 PM UTC 24 |
52888200 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2775168995 |
|
|
Aug 27 06:35:04 PM UTC 24 |
Aug 27 06:35:24 PM UTC 24 |
56302400 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.1300965522 |
|
|
Aug 27 06:35:02 PM UTC 24 |
Aug 27 06:35:26 PM UTC 24 |
17693100 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1012780596 |
|
|
Aug 27 06:35:08 PM UTC 24 |
Aug 27 06:35:26 PM UTC 24 |
57324200 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.73964714 |
|
|
Aug 27 06:35:08 PM UTC 24 |
Aug 27 06:35:26 PM UTC 24 |
17848600 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.3931787799 |
|
|
Aug 27 06:35:10 PM UTC 24 |
Aug 27 06:35:28 PM UTC 24 |
79631400 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.1700107250 |
|
|
Aug 27 06:35:03 PM UTC 24 |
Aug 27 06:35:28 PM UTC 24 |
48162800 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.2028848483 |
|
|
Aug 27 06:35:06 PM UTC 24 |
Aug 27 06:35:29 PM UTC 24 |
44261300 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.2478116025 |
|
|
Aug 27 06:35:10 PM UTC 24 |
Aug 27 06:35:31 PM UTC 24 |
41742100 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2141441305 |
|
|
Aug 27 06:35:09 PM UTC 24 |
Aug 27 06:35:33 PM UTC 24 |
17561400 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.2332851713 |
|
|
Aug 27 06:31:19 PM UTC 24 |
Aug 27 06:41:25 PM UTC 24 |
1548895700 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.3201126518 |
|
|
Aug 27 06:33:00 PM UTC 24 |
Aug 27 06:41:34 PM UTC 24 |
343775700 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_26/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.4221565724 |
|
|
Aug 27 06:30:50 PM UTC 24 |
Aug 27 06:41:39 PM UTC 24 |
877442900 ps |