Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
98.94 99.31 95.82 100.00 99.56 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
80.00 80.00 gen_generic.u_impl_generic


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_chk 100.00 100.00 100.00 100.00
u_csr0_regwen 100.00 100.00 100.00 100.00
u_csr10 100.00 100.00 100.00 100.00
u_csr11 100.00 100.00 100.00 100.00
u_csr12 100.00 100.00 100.00 100.00
u_csr13_field0 100.00 100.00 100.00 100.00
u_csr13_field1 100.00 100.00 100.00 100.00
u_csr14_field0 100.00 100.00 100.00 100.00
u_csr14_field1 100.00 100.00 100.00 100.00
u_csr15_field0 100.00 100.00 100.00 100.00
u_csr15_field1 100.00 100.00 100.00 100.00
u_csr16_field0 100.00 100.00 100.00 100.00
u_csr16_field1 100.00 100.00 100.00 100.00
u_csr17_field0 100.00 100.00 100.00 100.00
u_csr17_field1 100.00 100.00 100.00 100.00
u_csr18 100.00 100.00 100.00 100.00
u_csr19 100.00 100.00 100.00 100.00
u_csr1_field0 100.00 100.00 100.00 100.00
u_csr1_field1 100.00 100.00 100.00 100.00
u_csr20_field0 88.89 100.00 66.67 100.00
u_csr20_field1 88.89 100.00 66.67 100.00
u_csr20_field2 55.19 55.56 50.00 60.00
u_csr2_field0 88.89 100.00 66.67 100.00
u_csr2_field1 88.89 100.00 66.67 100.00
u_csr2_field2 88.89 100.00 66.67 100.00
u_csr2_field3 96.30 100.00 88.89 100.00
u_csr2_field4 88.89 100.00 66.67 100.00
u_csr2_field5 88.89 100.00 66.67 100.00
u_csr2_field6 88.89 100.00 66.67 100.00
u_csr2_field7 96.30 100.00 88.89 100.00
u_csr3_field0 100.00 100.00 100.00 100.00
u_csr3_field1 100.00 100.00 100.00 100.00
u_csr3_field2 100.00 100.00 100.00 100.00
u_csr3_field3 100.00 100.00 100.00 100.00
u_csr3_field4 100.00 100.00 100.00 100.00
u_csr3_field5 100.00 100.00 100.00 100.00
u_csr3_field6 100.00 100.00 100.00 100.00
u_csr3_field7 100.00 100.00 100.00 100.00
u_csr3_field8 100.00 100.00 100.00 100.00
u_csr3_field9 100.00 100.00 100.00 100.00
u_csr4_field0 100.00 100.00 100.00 100.00
u_csr4_field1 100.00 100.00 100.00 100.00
u_csr4_field2 100.00 100.00 100.00 100.00
u_csr4_field3 100.00 100.00 100.00 100.00
u_csr5_field0 100.00 100.00 100.00 100.00
u_csr5_field1 100.00 100.00 100.00 100.00
u_csr5_field2 100.00 100.00 100.00 100.00
u_csr5_field3 100.00 100.00 100.00 100.00
u_csr5_field4 100.00 100.00 100.00 100.00
u_csr6_field0 100.00 100.00 100.00 100.00
u_csr6_field1 100.00 100.00 100.00 100.00
u_csr6_field2 100.00 100.00 100.00 100.00
u_csr6_field3 100.00 100.00 100.00 100.00
u_csr6_field4 100.00 100.00 100.00 100.00
u_csr6_field5 100.00 100.00 100.00 100.00
u_csr6_field6 100.00 100.00 100.00 100.00
u_csr6_field7 100.00 100.00 100.00 100.00
u_csr6_field8 100.00 100.00 100.00 100.00
u_csr7_field0 100.00 100.00 100.00 100.00
u_csr7_field1 100.00 100.00 100.00 100.00
u_csr8 100.00 100.00 100.00 100.00
u_csr9 100.00 100.00 100.00 100.00
u_prim_reg_we_check 100.00 100.00 100.00
u_reg_if 98.67 97.14 97.53 100.00 100.00
u_rsp_intg_gen 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_prim_reg_top
Line No.TotalCoveredPercent
TOTAL219219100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
CONT_ASSIGN11811100.00
CONT_ASSIGN11911100.00
CONT_ASSIGN29911100.00
CONT_ASSIGN57611100.00
CONT_ASSIGN85111100.00
CONT_ASSIGN96411100.00
CONT_ASSIGN110411100.00
CONT_ASSIGN135211100.00
CONT_ASSIGN141111100.00
CONT_ASSIGN144211100.00
CONT_ASSIGN147311100.00
CONT_ASSIGN150411100.00
CONT_ASSIGN153511100.00
CONT_ASSIGN156611100.00
CONT_ASSIGN162511100.00
CONT_ASSIGN168411100.00
CONT_ASSIGN174311100.00
CONT_ASSIGN180211100.00
CONT_ASSIGN186111100.00
CONT_ASSIGN189211100.00
ALWAYS20062222100.00
CONT_ASSIGN203011100.00
ALWAYS203411100.00
CONT_ASSIGN205911100.00
CONT_ASSIGN206111100.00
CONT_ASSIGN206211100.00
CONT_ASSIGN206411100.00
CONT_ASSIGN206611100.00
CONT_ASSIGN206711100.00
CONT_ASSIGN206911100.00
CONT_ASSIGN207111100.00
CONT_ASSIGN207311100.00
CONT_ASSIGN207511100.00
CONT_ASSIGN207711100.00
CONT_ASSIGN207911100.00
CONT_ASSIGN208111100.00
CONT_ASSIGN208311100.00
CONT_ASSIGN208411100.00
CONT_ASSIGN208611100.00
CONT_ASSIGN208811100.00
CONT_ASSIGN209011100.00
CONT_ASSIGN209211100.00
CONT_ASSIGN209411100.00
CONT_ASSIGN209611100.00
CONT_ASSIGN209811100.00
CONT_ASSIGN210011100.00
CONT_ASSIGN210211100.00
CONT_ASSIGN210411100.00
CONT_ASSIGN210511100.00
CONT_ASSIGN210711100.00
CONT_ASSIGN210911100.00
CONT_ASSIGN211111100.00
CONT_ASSIGN211311100.00
CONT_ASSIGN211411100.00
CONT_ASSIGN211611100.00
CONT_ASSIGN211811100.00
CONT_ASSIGN212011100.00
CONT_ASSIGN212211100.00
CONT_ASSIGN212411100.00
CONT_ASSIGN212511100.00
CONT_ASSIGN212711100.00
CONT_ASSIGN212911100.00
CONT_ASSIGN213111100.00
CONT_ASSIGN213311100.00
CONT_ASSIGN213511100.00
CONT_ASSIGN213711100.00
CONT_ASSIGN213911100.00
CONT_ASSIGN214111100.00
CONT_ASSIGN214311100.00
CONT_ASSIGN214411100.00
CONT_ASSIGN214611100.00
CONT_ASSIGN214811100.00
CONT_ASSIGN214911100.00
CONT_ASSIGN215111100.00
CONT_ASSIGN215211100.00
CONT_ASSIGN215411100.00
CONT_ASSIGN215511100.00
CONT_ASSIGN215711100.00
CONT_ASSIGN215811100.00
CONT_ASSIGN216011100.00
CONT_ASSIGN216111100.00
CONT_ASSIGN216311100.00
CONT_ASSIGN216411100.00
CONT_ASSIGN216611100.00
CONT_ASSIGN216811100.00
CONT_ASSIGN216911100.00
CONT_ASSIGN217111100.00
CONT_ASSIGN217311100.00
CONT_ASSIGN217411100.00
CONT_ASSIGN217611100.00
CONT_ASSIGN217811100.00
CONT_ASSIGN217911100.00
CONT_ASSIGN218111100.00
CONT_ASSIGN218311100.00
CONT_ASSIGN218411100.00
CONT_ASSIGN218611100.00
CONT_ASSIGN218811100.00
CONT_ASSIGN218911100.00
CONT_ASSIGN219111100.00
CONT_ASSIGN219211100.00
CONT_ASSIGN219411100.00
CONT_ASSIGN219511100.00
CONT_ASSIGN219711100.00
CONT_ASSIGN219911100.00
ALWAYS22032222100.00
ALWAYS22296363100.00
CONT_ASSIGN236600
CONT_ASSIGN237411100.00
CONT_ASSIGN237511100.00

Click here to see the source line report.

Cond Coverage for Module : flash_ctrl_prim_reg_top
TotalCoveredPercent
Conditions287287100.00
Logical287287100.00
Non-Logical00
Event00

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT111,T112,T113
11CoveredT111,T67,T112

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT16,T43,T44
10CoveredT266,T267,T268

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT16,T43,T44
010CoveredT266,T267,T268
100CoveredT16,T43,T44

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT266,T267,T268
010CoveredT111,T112,T69
100CoveredT111,T112,T113

 LINE       299
 EXPRESSION (csr1_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       576
 EXPRESSION (csr3_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       851
 EXPRESSION (csr4_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T271
11CoveredT67,T69,T115

 LINE       964
 EXPRESSION (csr5_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1104
 EXPRESSION (csr6_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1352
 EXPRESSION (csr7_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1411
 EXPRESSION (csr8_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1442
 EXPRESSION (csr9_we & csr0_regwen_qs)
             ---1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T271
11CoveredT67,T69,T115

 LINE       1473
 EXPRESSION (csr10_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT115,T257,T270
11CoveredT67,T69,T257

 LINE       1504
 EXPRESSION (csr11_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1535
 EXPRESSION (csr12_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T271
11CoveredT67,T69,T115

 LINE       1566
 EXPRESSION (csr13_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT69,T257,T270
11CoveredT67,T115,T257

 LINE       1625
 EXPRESSION (csr14_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1684
 EXPRESSION (csr15_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T271
11CoveredT67,T69,T115

 LINE       1743
 EXPRESSION (csr16_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1802
 EXPRESSION (csr17_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1861
 EXPRESSION (csr18_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT257,T270,T259
11CoveredT67,T69,T115

 LINE       1892
 EXPRESSION (csr19_we & csr0_regwen_qs)
             ----1---   -------2------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT69,T257,T270
11CoveredT67,T115,T270

 LINE       2007
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR0_REGWEN_OFFSET)
            -------------------------------1-------------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT50,T93,T195

 LINE       2008
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR1_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT54,T50,T321

 LINE       2009
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR2_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT50,T263,T321

 LINE       2010
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR3_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT24,T242,T50

 LINE       2011
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR4_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT94,T50,T290

 LINE       2012
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR5_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT66,T50,T97

 LINE       2013
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR6_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T4,T8
1CoveredT7,T9,T54

 LINE       2014
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR7_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT50,T149,T195

 LINE       2015
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR8_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT8,T50,T5

 LINE       2016
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR9_OFFSET)
            ----------------------------1---------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT8,T54,T50

 LINE       2017
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR10_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT54,T39,T50

 LINE       2018
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR11_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT59,T109,T242

 LINE       2019
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR12_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT50,T85,T321

 LINE       2020
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR13_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T8
1CoveredT4,T64,T92

 LINE       2021
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR14_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT119,T50,T177

 LINE       2022
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR15_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT50,T176,T321

 LINE       2023
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR16_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT66,T50,T151

 LINE       2024
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR17_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT50,T321,T118

 LINE       2025
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR18_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT50,T93,T195

 LINE       2026
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR19_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT110,T109,T50

 LINE       2027
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR20_OFFSET)
            ----------------------------1----------------------------
-1-StatusTests
0CoveredT17,T7,T4
1CoveredT50,T320,T321

 LINE       2030
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT111,T67,T112

 LINE       2030
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT111,T67,T112
10CoveredT111,T67,T112

 LINE       2034
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be)))))))
-1--2-StatusTests
01CoveredT7,T4,T8
10CoveredT111,T67,T112
11CoveredT111,T112,T69

 LINE       2034
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))))
Sensitive Expression == 1StatusTests
ALL ZEROSCoveredT17,T8,T54
21 (addr_hit[20] & ((|(4'...CoveredT50,T320,T321
20 (addr_hit[19] & ((|(4'...CoveredT110,T50,T195
19 (addr_hit[18] & ((|(4'...CoveredT50,T321,T322
18 (addr_hit[17] & ((|(4'...CoveredT50,T321,T118
17 (addr_hit[16] & ((|(4'...CoveredT66,T50,T151
16 (addr_hit[15] & ((|(4'...CoveredT50,T176,T321
15 (addr_hit[14] & ((|(4'...CoveredT119,T50,T177
14 (addr_hit[13] & ((|(4'...CoveredT4,T64,T92
13 (addr_hit[12] & ((|(4'...CoveredT50,T85,T321
12 (addr_hit[11] & ((|(4'...CoveredT59,T109,T242
11 (addr_hit[10] & ((|(4'...CoveredT54,T39,T50
10 (addr_hit[9] & ((|(4'b...CoveredT8,T54,T50
9 (addr_hit[8] & ((|(4'b...CoveredT8,T50,T5
8 (addr_hit[7] & ((|(4'b...CoveredT50,T149,T195
7 (addr_hit[6] & ((|(4'b...CoveredT7,T9,T54
6 (addr_hit[5] & ((|(4'b...CoveredT66,T50,T161
5 (addr_hit[4] & ((|(4'b...CoveredT94,T50,T290
4 (addr_hit[3] & ((|(4'b...CoveredT24,T242,T50
3 (addr_hit[2] & ((|(4'b...CoveredT50,T321,T322
2 (addr_hit[1] & ((|(4'b...CoveredT50,T321,T168
1 (addr_hit[0] & ((|(4'b...CoveredT50,T195,T167

 LINE       2034
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT7,T8,T54
10CoveredT50,T93,T263
11CoveredT50,T195,T167

 LINE       2034
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT54,T321,T322
11CoveredT50,T321,T168

 LINE       2034
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------
-1--2-StatusTests
01CoveredT7,T8,T54
10CoveredT50,T263,T321
11CoveredT50,T321,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT321,T323,T324
11CoveredT24,T242,T50

 LINE       2034
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT321,T322,T188
11CoveredT94,T50,T290

 LINE       2034
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT97,T321,T323
11CoveredT66,T50,T161

 LINE       2034
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T4,T8
10CoveredT325,T111,T67
11CoveredT7,T9,T54

 LINE       2034
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT50,T321,T296
11CoveredT50,T149,T195

 LINE       2034
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT57,T326,T327
11CoveredT8,T50,T5

 LINE       2034
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT50,T322,T325
11CoveredT8,T54,T50

 LINE       2034
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT300,T328,T111
11CoveredT54,T39,T50

 LINE       2034
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT50,T321,T322
11CoveredT59,T109,T242

 LINE       2034
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT50,T321,T322
11CoveredT50,T85,T321

 LINE       2034
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T8
10CoveredT321,T322,T197
11CoveredT4,T64,T92

 LINE       2034
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT50,T195,T321
11CoveredT119,T50,T177

 LINE       2034
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT50,T321,T42
11CoveredT50,T176,T321

 LINE       2034
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT321,T325,T323
11CoveredT66,T50,T151

 LINE       2034
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------
-1--2-StatusTests
01CoveredT17,T7,T4
10CoveredT50,T321,T325
11CoveredT50,T321,T118

 LINE       2034
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT7,T8,T54
10CoveredT50,T93,T195
11CoveredT50,T321,T322

 LINE       2034
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT7,T8,T54
10CoveredT109,T50,T263
11CoveredT110,T50,T195

 LINE       2034
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------
-1--2-StatusTests
01CoveredT7,T8,T54
10CoveredT50,T321,T322
11CoveredT50,T320,T321

 LINE       2059
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT50,T93,T195
110CoveredT111,T112,T69
111CoveredT67,T69,T115

 LINE       2062
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT54,T110,T50
110CoveredT111,T112,T113
111CoveredT67,T69,T115

 LINE       2067
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT50,T320,T263
110CoveredT111,T112,T247
111CoveredT67,T69,T115

 LINE       2084
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT8,T24,T242
110CoveredT111,T112,T113
111CoveredT67,T69,T115

 LINE       2105
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT94,T50,T97
110CoveredT111,T113,T237
111CoveredT67,T69,T115

 LINE       2114
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT74,T66,T50
110CoveredT113,T247,T114
111CoveredT67,T69,T115

 LINE       2125
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT7,T4,T9
110CoveredT113,T247,T114
111CoveredT67,T69,T115

 LINE       2144
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT50,T149,T195
110CoveredT111,T112,T247
111CoveredT67,T69,T115

 LINE       2149
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT8,T119,T50
110CoveredT111,T112,T237
111CoveredT67,T69,T115

 LINE       2152
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT8,T54,T50
110CoveredT111,T112,T114
111CoveredT67,T69,T115

 LINE       2155
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT54,T39,T109
110CoveredT112,T113,T247
111CoveredT67,T69,T115

 LINE       2158
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT59,T39,T109
110CoveredT111,T112,T113
111CoveredT67,T69,T115

 LINE       2161
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT17,T50,T85
110CoveredT111,T112,T237
111CoveredT67,T69,T115

 LINE       2164
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT4,T64,T92
110CoveredT112,T113,T247
111CoveredT67,T69,T115

 LINE       2169
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT119,T50,T177
110CoveredT111,T112,T69
111CoveredT67,T69,T115

 LINE       2174
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT50,T176,T321
110CoveredT112,T69,T113
111CoveredT67,T69,T115

 LINE       2179
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT66,T50,T53
110CoveredT112,T237,T247
111CoveredT67,T69,T115

 LINE       2184
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT50,T321,T118
110CoveredT111,T112,T114
111CoveredT67,T69,T115

 LINE       2189
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT54,T50,T93
110CoveredT112,T69,T113
111CoveredT67,T69,T115

 LINE       2192
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT110,T109,T66
110CoveredT112,T247,T250
111CoveredT67,T69,T115

 LINE       2195
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------
-1--2--3-StatusTests
011CoveredT67,T69,T115
101CoveredT9,T242,T50
110CoveredT112,T69,T113
111CoveredT67,T69,T115

Branch Coverage for Module : flash_ctrl_prim_reg_top
Line No.TotalCoveredPercent
Branches 27 27 100.00
TERNARY 2030 2 2 100.00
IF 68 3 3 100.00
CASE 2230 22 22 100.00


2030 assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T111,T67,T112
0 Covered T1,T2,T3


68 if (!rst_ni) begin -1- 69 err_q <= '0; ==> 70 end else if (intg_err || reg_we_err) begin -2- 71 err_q <= 1'b1; ==> 72 end MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T16,T43,T44
0 0 Covered T1,T2,T3


2230 unique case (1'b1) -1- 2231 addr_hit[0]: begin 2232 reg_rdata_next[0] = csr0_regwen_qs; ==> 2233 end 2234 2235 addr_hit[1]: begin 2236 reg_rdata_next[7:0] = csr1_field0_qs; ==> 2237 reg_rdata_next[12:8] = csr1_field1_qs; 2238 end 2239 2240 addr_hit[2]: begin 2241 reg_rdata_next[0] = csr2_field0_qs; ==> 2242 reg_rdata_next[1] = csr2_field1_qs; 2243 reg_rdata_next[2] = csr2_field2_qs; 2244 reg_rdata_next[3] = csr2_field3_qs; 2245 reg_rdata_next[4] = csr2_field4_qs; 2246 reg_rdata_next[5] = csr2_field5_qs; 2247 reg_rdata_next[6] = csr2_field6_qs; 2248 reg_rdata_next[7] = csr2_field7_qs; 2249 end 2250 2251 addr_hit[3]: begin 2252 reg_rdata_next[3:0] = csr3_field0_qs; ==> 2253 reg_rdata_next[7:4] = csr3_field1_qs; 2254 reg_rdata_next[10:8] = csr3_field2_qs; 2255 reg_rdata_next[13:11] = csr3_field3_qs; 2256 reg_rdata_next[16:14] = csr3_field4_qs; 2257 reg_rdata_next[19:17] = csr3_field5_qs; 2258 reg_rdata_next[20] = csr3_field6_qs; 2259 reg_rdata_next[23:21] = csr3_field7_qs; 2260 reg_rdata_next[25:24] = csr3_field8_qs; 2261 reg_rdata_next[27:26] = csr3_field9_qs; 2262 end 2263 2264 addr_hit[4]: begin 2265 reg_rdata_next[2:0] = csr4_field0_qs; ==> 2266 reg_rdata_next[5:3] = csr4_field1_qs; 2267 reg_rdata_next[8:6] = csr4_field2_qs; 2268 reg_rdata_next[11:9] = csr4_field3_qs; 2269 end 2270 2271 addr_hit[5]: begin 2272 reg_rdata_next[2:0] = csr5_field0_qs; ==> 2273 reg_rdata_next[4:3] = csr5_field1_qs; 2274 reg_rdata_next[13:5] = csr5_field2_qs; 2275 reg_rdata_next[18:14] = csr5_field3_qs; 2276 reg_rdata_next[22:19] = csr5_field4_qs; 2277 end 2278 2279 addr_hit[6]: begin 2280 reg_rdata_next[2:0] = csr6_field0_qs; ==> 2281 reg_rdata_next[5:3] = csr6_field1_qs; 2282 reg_rdata_next[13:6] = csr6_field2_qs; 2283 reg_rdata_next[16:14] = csr6_field3_qs; 2284 reg_rdata_next[18:17] = csr6_field4_qs; 2285 reg_rdata_next[20:19] = csr6_field5_qs; 2286 reg_rdata_next[22:21] = csr6_field6_qs; 2287 reg_rdata_next[23] = csr6_field7_qs; 2288 reg_rdata_next[24] = csr6_field8_qs; 2289 end 2290 2291 addr_hit[7]: begin 2292 reg_rdata_next[7:0] = csr7_field0_qs; ==> 2293 reg_rdata_next[16:8] = csr7_field1_qs; 2294 end 2295 2296 addr_hit[8]: begin 2297 reg_rdata_next[31:0] = csr8_qs; ==> 2298 end 2299 2300 addr_hit[9]: begin 2301 reg_rdata_next[31:0] = csr9_qs; ==> 2302 end 2303 2304 addr_hit[10]: begin 2305 reg_rdata_next[31:0] = csr10_qs; ==> 2306 end 2307 2308 addr_hit[11]: begin 2309 reg_rdata_next[31:0] = csr11_qs; ==> 2310 end 2311 2312 addr_hit[12]: begin 2313 reg_rdata_next[9:0] = csr12_qs; ==> 2314 end 2315 2316 addr_hit[13]: begin 2317 reg_rdata_next[19:0] = csr13_field0_qs; ==> 2318 reg_rdata_next[20] = csr13_field1_qs; 2319 end 2320 2321 addr_hit[14]: begin 2322 reg_rdata_next[7:0] = csr14_field0_qs; ==> 2323 reg_rdata_next[8] = csr14_field1_qs; 2324 end 2325 2326 addr_hit[15]: begin 2327 reg_rdata_next[7:0] = csr15_field0_qs; ==> 2328 reg_rdata_next[8] = csr15_field1_qs; 2329 end 2330 2331 addr_hit[16]: begin 2332 reg_rdata_next[7:0] = csr16_field0_qs; ==> 2333 reg_rdata_next[8] = csr16_field1_qs; 2334 end 2335 2336 addr_hit[17]: begin 2337 reg_rdata_next[7:0] = csr17_field0_qs; ==> 2338 reg_rdata_next[8] = csr17_field1_qs; 2339 end 2340 2341 addr_hit[18]: begin 2342 reg_rdata_next[0] = csr18_qs; ==> 2343 end 2344 2345 addr_hit[19]: begin 2346 reg_rdata_next[0] = csr19_qs; ==> 2347 end 2348 2349 addr_hit[20]: begin 2350 reg_rdata_next[0] = csr20_field0_qs; ==> 2351 reg_rdata_next[1] = csr20_field1_qs; 2352 reg_rdata_next[2] = csr20_field2_qs; 2353 end 2354 2355 default: begin 2356 reg_rdata_next = '1; ==>

Branches:
-1-StatusTests
addr_hit[0] Covered T1,T2,T3
addr_hit[1] Covered T1,T2,T3
addr_hit[2] Covered T1,T2,T3
addr_hit[3] Covered T1,T2,T3
addr_hit[4] Covered T1,T2,T3
addr_hit[5] Covered T1,T2,T3
addr_hit[6] Covered T1,T2,T3
addr_hit[7] Covered T1,T2,T3
addr_hit[8] Covered T1,T2,T3
addr_hit[9] Covered T1,T2,T3
addr_hit[10] Covered T1,T2,T3
addr_hit[11] Covered T1,T2,T3
addr_hit[12] Covered T1,T2,T3
addr_hit[13] Covered T1,T2,T3
addr_hit[14] Covered T1,T2,T3
addr_hit[15] Covered T1,T2,T3
addr_hit[16] Covered T1,T2,T3
addr_hit[17] Covered T1,T2,T3
addr_hit[18] Covered T1,T2,T3
addr_hit[19] Covered T1,T2,T3
addr_hit[20] Covered T1,T2,T3
default Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl_prim_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 390820040 61556 0 0
reAfterRv 390820040 61556 0 0
rePulse 390820040 41941 0 0
wePulse 390820040 19615 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 390820040 61556 0 0
T67 2638 130 0 0
T69 5248 83 0 0
T111 5530 21 0 0
T112 5852 40 0 0
T113 3049 109 0 0
T115 2381 42 0 0
T237 3144 10 0 0
T257 5135 134 0 0
T259 3722 53 0 0
T270 63238 5376 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 390820040 61556 0 0
T67 2638 130 0 0
T69 5248 83 0 0
T111 5530 21 0 0
T112 5852 40 0 0
T113 3049 109 0 0
T115 2381 42 0 0
T237 3144 10 0 0
T257 5135 134 0 0
T259 3722 53 0 0
T270 63238 5376 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 390820040 41941 0 0
T67 2638 88 0 0
T69 5248 57 0 0
T111 5530 3 0 0
T112 5852 4 0 0
T113 3049 67 0 0
T115 2381 21 0 0
T237 3144 3 0 0
T257 5135 92 0 0
T259 3722 32 0 0
T270 63238 2688 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 390820040 19615 0 0
T67 2638 42 0 0
T69 5248 26 0 0
T111 5530 18 0 0
T112 5852 36 0 0
T113 3049 42 0 0
T115 2381 21 0 0
T237 3144 7 0 0
T257 5135 42 0 0
T259 3722 21 0 0
T270 63238 2688 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%