Module Definition
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Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_plain_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.43 100.00 89.74 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_plain_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.69 100.00 98.46 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_plain_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
97.38 100.00 89.52 100.00 100.00 u_rd


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_plain_enc

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.38 100.00 96.92 100.00 100.00 100.00 gen_prog_data.u_prog


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_secded_hamming_72_64_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 72'(data_i); Tests: T1 T2 T3  14 1/1 data_o[64] = ^(data_o & 72'h00AB55555556AAAD5B); Tests: T1 T2 T3  15 1/1 data_o[65] = ^(data_o & 72'h00CD9999999B33366D); Tests: T1 T2 T3  16 1/1 data_o[66] = ^(data_o & 72'h00F1E1E1E1E3C3C78E); Tests: T1 T2 T3  17 1/1 data_o[67] = ^(data_o & 72'h0001FE01FE03FC07F0); Tests: T1 T2 T3  18 1/1 data_o[68] = ^(data_o & 72'h0001FFFE0003FFF800); Tests: T1 T2 T3  19 1/1 data_o[69] = ^(data_o & 72'h0001FFFFFFFC000000); Tests: T1 T2 T3  20 1/1 data_o[70] = ^(data_o & 72'h00FE00000000000000); Tests: T1 T2 T3  21 1/1 data_o[71] = ^(data_o & 72'h7FFFFFFFFFFFFFFFFF); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_plain_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 72'(data_i); Tests: T1 T2 T3  14 1/1 data_o[64] = ^(data_o & 72'h00AB55555556AAAD5B); Tests: T1 T2 T3  15 1/1 data_o[65] = ^(data_o & 72'h00CD9999999B33366D); Tests: T1 T2 T3  16 1/1 data_o[66] = ^(data_o & 72'h00F1E1E1E1E3C3C78E); Tests: T1 T2 T3  17 1/1 data_o[67] = ^(data_o & 72'h0001FE01FE03FC07F0); Tests: T1 T2 T3  18 1/1 data_o[68] = ^(data_o & 72'h0001FFFE0003FFF800); Tests: T1 T2 T3  19 1/1 data_o[69] = ^(data_o & 72'h0001FFFFFFFC000000); Tests: T1 T2 T3  20 1/1 data_o[70] = ^(data_o & 72'h00FE00000000000000); Tests: T1 T2 T3  21 1/1 data_o[71] = ^(data_o & 72'h7FFFFFFFFFFFFFFFFF); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog.u_plain_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 72'(data_i); Tests: T1 T2 T3  14 1/1 data_o[64] = ^(data_o & 72'h00AB55555556AAAD5B); Tests: T1 T2 T3  15 1/1 data_o[65] = ^(data_o & 72'h00CD9999999B33366D); Tests: T1 T2 T3  16 1/1 data_o[66] = ^(data_o & 72'h00F1E1E1E1E3C3C78E); Tests: T1 T2 T3  17 1/1 data_o[67] = ^(data_o & 72'h0001FE01FE03FC07F0); Tests: T1 T2 T3  18 1/1 data_o[68] = ^(data_o & 72'h0001FFFE0003FFF800); Tests: T1 T2 T3  19 1/1 data_o[69] = ^(data_o & 72'h0001FFFFFFFC000000); Tests: T1 T2 T3  20 1/1 data_o[70] = ^(data_o & 72'h00FE00000000000000); Tests: T1 T2 T3  21 1/1 data_o[71] = ^(data_o & 72'h7FFFFFFFFFFFFFFFFF); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_plain_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 72'(data_i); Tests: T1 T2 T3  14 1/1 data_o[64] = ^(data_o & 72'h00AB55555556AAAD5B); Tests: T1 T2 T3  15 1/1 data_o[65] = ^(data_o & 72'h00CD9999999B33366D); Tests: T1 T2 T3  16 1/1 data_o[66] = ^(data_o & 72'h00F1E1E1E1E3C3C78E); Tests: T1 T2 T3  17 1/1 data_o[67] = ^(data_o & 72'h0001FE01FE03FC07F0); Tests: T1 T2 T3  18 1/1 data_o[68] = ^(data_o & 72'h0001FFFE0003FFF800); Tests: T1 T2 T3  19 1/1 data_o[69] = ^(data_o & 72'h0001FFFFFFFC000000); Tests: T1 T2 T3  20 1/1 data_o[70] = ^(data_o & 72'h00FE00000000000000); Tests: T1 T2 T3  21 1/1 data_o[71] = ^(data_o & 72'h7FFFFFFFFFFFFFFFFF); Tests: T1 T2 T3 
Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_plain_enc
Line No.TotalCoveredPercent
TOTAL99100.00
ALWAYS1399100.00

12 always_comb begin : p_encode 13 1/1 data_o = 72'(data_i); Tests: T1 T2 T3  14 1/1 data_o[64] = ^(data_o & 72'h00AB55555556AAAD5B); Tests: T1 T2 T3  15 1/1 data_o[65] = ^(data_o & 72'h00CD9999999B33366D); Tests: T1 T2 T3  16 1/1 data_o[66] = ^(data_o & 72'h00F1E1E1E1E3C3C78E); Tests: T1 T2 T3  17 1/1 data_o[67] = ^(data_o & 72'h0001FE01FE03FC07F0); Tests: T1 T2 T3  18 1/1 data_o[68] = ^(data_o & 72'h0001FFFE0003FFF800); Tests: T1 T2 T3  19 1/1 data_o[69] = ^(data_o & 72'h0001FFFFFFFC000000); Tests: T1 T2 T3  20 1/1 data_o[70] = ^(data_o & 72'h00FE00000000000000); Tests: T1 T2 T3  21 1/1 data_o[71] = ^(data_o & 72'h7FFFFFFFFFFFFFFFFF); Tests: T1 T2 T3 
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