Unified Coverage Report :: Module :: flash_phy_prog

Module : flash_phy_prog

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog	99.38	100.00	96.92		100.00	100.00	100.00
tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog	99.69	100.00	98.46		100.00	100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.38	100.00	96.92		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.65	100.00	96.92	95.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.74	100.00	85.85		100.00	97.83	100.00	gen_flash_cores[1].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	97.50	100.00		95.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.69	100.00	98.46		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.74	100.00	98.46	100.00	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.87	100.00	94.34		100.00	100.00	100.00	gen_flash_cores[0].u_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_data_intg_chk	100.00	100.00		100.00
u_enc	100.00	100.00
u_plain_enc	100.00	100.00
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

110                       // selects empty data or real data
111        1/1            assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
           Tests:       T1 T2 T3 
112                     
113                       logic data_intg_ok;
114                       logic data_err;
115                     
116                       // use the tlul integrity module directly for bus integrity
117                       // SEC_CM: MEM.BUS.INTEGRITY
118                       tlul_data_integ_dec u_data_intg_chk (
119                         .data_intg_i(data_i),
120                         .data_err_o(data_err)
121                       );
122        1/1            assign data_intg_ok = ~data_err;
           Tests:       T1 T2 T3 
123                     
124                       logic data_invalid_q, data_invalid_d;
125                       // hold on integrity failure indication until reset
126        1/1            assign data_invalid_d = data_invalid_q |
           Tests:       T1 T2 T3 
127                                               (pack_valid & ~data_intg_ok);
128                     
129                       always_ff @(posedge clk_i or negedge rst_ni) begin
130        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
131        1/1                data_invalid_q <= '0;
           Tests:       T1 T2 T3 
132                         end else begin
133        1/1                data_invalid_q <= data_invalid_d;
           Tests:       T1 T2 T3 
134                         end
135                       end
136                     
137                       // indication to upper layer presence of error
138        1/1            assign intg_err_o = data_invalid_q;
           Tests:       T1 T2 T3 
139                     
140                       // if integrity failure is seen, fake communication with flash
141                       // and simply terminate
142                       logic ack, done;
143        1/1            assign ack = ack_i | data_invalid_q;
           Tests:       T1 T2 T3 
144        1/1            assign done = done_i | data_invalid_q;
           Tests:       T1 T2 T3 
145                     
146                       // next idx will be aligned
147        1/1            assign idx_sub_one = idx - 1'b1;
           Tests:       T1 T2 T3 
148        1/1            assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
           Tests:       T1 T2 T3 
149                     
150                       always_ff @(posedge clk_i or negedge rst_ni) begin
151        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
152        1/1                idx <= '0;
           Tests:       T1 T2 T3 
153        1/1              end else if (pack_valid && idx == MaxIdx) begin
           Tests:       T1 T2 T3 
154                           // when a flash word is packed full, return index to 0
155        1/1                idx <= '0;
           Tests:       T1 T12 T20 
156        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
157                           // increment otherwise
158        1/1                idx <= idx + 1'b1;
           Tests:       T1 T12 T20 
159                         end
                        MISSING_ELSE
160                       end
161                     
162                     
163                       // SEC_CM: PHY_PROG.FSM.SPARSE
164        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
164.1                   `ifdef SIMULATION                                   
164.2                       prim_sparse_fsm_flop #(                           
164.3                         .StateEnumT(state_e),                            
164.4                         .Width($bits(state_e)),                          
164.5                         .ResetValue($bits(state_e)'(StIdle)),          
164.6                         .EnableAlertTriggerSVA(1), 
164.7                         .CustomForceName("state_q")          
164.8                       ) u_state_regs (                                        
164.9                         .clk_i   ( clk_i   ),                           
164.10                        .rst_ni  ( rst_ni ),                           
164.11                        .state_i ( state_d     ),                           
164.12                        .state_o (         )                            
164.13                      );                                                
164.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
164.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
164.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
164.17                      end else begin                                    
164.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
164.19                      end                                               
164.20                    end  
164.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
164.22                      else begin                                                                           
164.23                        `ifdef UVM                                                                               
164.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
164.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv", 164, "", 1);                                
164.26                  `else                                                                                    
164.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
164.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
164.29                  `endif                                                              
164.30                      end 
164.31                    `else                                               
164.32                      prim_sparse_fsm_flop #(                           
164.33                        .StateEnumT(state_e),                            
164.34                        .Width($bits(state_e)),                          
164.35                        .ResetValue($bits(state_e)'(StIdle)),          
164.36                        .EnableAlertTriggerSVA(1)  
164.37                      ) u_state_regs (                                        
164.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
164.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
164.40                        .state_i ( state_d     ),                           
164.41                        .state_o ( state_q     )                            
164.42                      );                                                
164.43                    `endif165                     
166                       // If the first beat of an incoming transaction is not aligned to word boundary (for example
167                       // if each flash word is 4 bus words wide, and the first word to program starts at index 1),
168                       // the fsm pre-packs the flash word with empty words until the supplied index.
169                       // Once at the index, real data supplied from the flash controller is packed until the last
170                       // beat of data.  At the last beat of data, if it is not also aligned (index 3 in this example),
171                       // more empty words are packed at the end to fill out the word.
172                       //
173                       always_comb begin
174        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
175                     
176        1/1              pack_valid = 1'b0;
           Tests:       T1 T2 T3 
177        1/1              data_sel = Filler;
           Tests:       T1 T2 T3 
178        1/1              plain_ecc_en = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              req_o = 1'b0;
           Tests:       T1 T2 T3 
180        1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
181        1/1              last_o = 1'b0;
           Tests:       T1 T2 T3 
182        1/1              calc_req_o = 1'b0;
           Tests:       T1 T2 T3 
183        1/1              scramble_req_o = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           StIdle: begin
188                             // if first beat of a transaction is not aligned, prepack with empty bits
189        1/1                  if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
           Tests:       T1 T2 T3 
190                               // only disable during idle state to ensure program is able to gracefully complete
191                               // this is important as we do not want to accidentally disturb any electrical procedure
192                               // internal to the flash macro
193        1/1                    state_d = StDisabled;
           Tests:       T7 T8 T9 
194        1/1                  end else if (req_i && |sel_i) begin
           Tests:       T1 T2 T3 
195        1/1                    state_d = StPrePack;
           Tests:       T10 T59 T46 
196        1/1                  end else if (req_i) begin
           Tests:       T1 T2 T3 
197        1/1                    state_d = StPackData;
           Tests:       T1 T12 T20 
198                             end
                        MISSING_ELSE
199                           end
200                     
201                           StPrePack: begin
202                             // pack until currently supplied data
203        1/1                  pack_valid = (idx < sel_i);
           Tests:       T10 T59 T46 
204        1/1                  if (idx == align_next) begin
           Tests:       T10 T59 T46 
205        1/1                    state_d = StPackData;
           Tests:       T10 T59 T46 
206                             end
                        MISSING_ELSE
207                           end
208                     
209                           StPackData: begin
210        1/1                  pack_valid = req_i;
           Tests:       T1 T12 T20 
211        1/1                  data_sel = Actual;
           Tests:       T1 T12 T20 
212                     
213        1/1                  if (req_i && idx == MaxIdx) begin
           Tests:       T1 T12 T20 
214                               // last beat of a flash word
215        1/1                    state_d = StCalcPlainEcc;
           Tests:       T1 T12 T20 
216        1/1                  end else if (req_i && last_i) begin
           Tests:       T1 T12 T20 
217                               // last beat is not aligned with the last entry of flash word
218        1/1                    state_d = StPostPack;
           Tests:       T10 T59 T46 
219        1/1                  end else if (req_i) begin
           Tests:       T1 T12 T20 
220        1/1                    ack_o = 1'b1;
           Tests:       T1 T12 T20 
221                             end
                        MISSING_ELSE
222                           end
223                     
224                           StPostPack: begin
225                             // supply filler data
226        1/1                  pack_valid = 1'b1;
           Tests:       T10 T59 T46 
227        1/1                  data_sel = Filler;
           Tests:       T10 T59 T46 
228                     
229                             // finish packing remaining entries
230        1/1                  if (idx == MaxIdx) begin
           Tests:       T10 T59 T46 
231        1/1                    state_d = StCalcPlainEcc;
           Tests:       T10 T59 T46 
232                             end
                        MISSING_ELSE
233                           end
234                     
235                           StCalcPlainEcc: begin
236        1/1                  plain_ecc_en = 1'b1;
           Tests:       T1 T12 T20 
237        1/1                  state_d = scramble_i ? StCalcMask : StReqFlash;
           Tests:       T1 T12 T20 
238                           end
239                     
240                           StCalcMask: begin
241        1/1                  calc_req_o = 1'b1;
           Tests:       T13 T14 T8 
242                     
243        1/1                  if (calc_ack_i) begin
           Tests:       T13 T14 T8 
244        1/1                    state_d = StScrambleData;
           Tests:       T13 T14 T8 
245                             end
                        MISSING_ELSE
246                           end
247                     
248                           StScrambleData: begin
249        1/1                  scramble_req_o = 1'b1;
           Tests:       T13 T14 T8 
250                     
251        1/1                  if (scramble_ack_i) begin
           Tests:       T13 T14 T8 
252        1/1                    state_d = StCalcEcc;
           Tests:       T13 T14 T8 
253                             end
                        MISSING_ELSE
254                           end
255                     
256                           StCalcEcc: begin
257        1/1                  state_d = StReqFlash;
           Tests:       T13 T14 T8 
258                           end
259                     
260                           StReqFlash: begin
261                             // only request flash if data integrity was valid
262        1/1                  req_o = ~data_invalid_q;
           Tests:       T1 T12 T20 
263        1/1                  last_o = last_i;
           Tests:       T1 T12 T20 
264                     
265                             // if this is the last beat of the program burst
266                             //   - wait for done
267                             // if this is NOT the last beat
268                             //   - ack the upstream request and accept more beats
269        1/1                  if (last_i) begin
           Tests:       T1 T12 T20 
270        1/1                    state_d = ack ? StWaitFlash : StReqFlash;
           Tests:       T1 T12 T20 
271                             end else begin
272        1/1                    ack_o = ack;
           Tests:       T1 T12 T14 
273        1/1                    state_d = ack ? StIdle : StReqFlash;
           Tests:       T1 T12 T14 
274                             end
275                           end
276                     
277                           StWaitFlash: begin
278        1/1                  if (done) begin
           Tests:       T1 T12 T20 
279        1/1                    ack_o = 1'b1;
           Tests:       T1 T12 T20 
280        1/1                    state_d = StIdle;
           Tests:       T1 T12 T20 
281                             end
                        MISSING_ELSE
282                           end
283                     
284                           StDisabled: begin
285        1/1                  state_d = StDisabled;
           Tests:       T7 T8 T9 
286                           end
287                     
288                           default: begin
289                             fsm_err_o = 1'b1;
290                           end
291                     
292                         endcase // unique case (state_q)
293                     
294                       end
295                     
296                       logic [DataWidth-1:0] mask_q;
297                     
298                       always_ff @(posedge clk_i or negedge rst_ni) begin
299        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
300        1/1                packed_data <= '0;
           Tests:       T1 T2 T3 
301        1/1                mask_q <= '0;
           Tests:       T1 T2 T3 
302        1/1              end else if (req_o && ack) begin
           Tests:       T1 T2 T3 
303        1/1                packed_data <= '0;
           Tests:       T1 T12 T20 
304        1/1              end else if (calc_req_o && calc_ack_i) begin
           Tests:       T1 T2 T3 
305        1/1                packed_data <= packed_data ^ mask_i;
           Tests:       T13 T14 T8 
306        1/1                mask_q <= mask_i;
           Tests:       T13 T14 T8 
307        1/1              end else if (scramble_req_o && scramble_ack_i) begin
           Tests:       T1 T2 T3 
308        1/1                packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
           Tests:       T13 T14 T8 
309        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
310        1/1                packed_data[idx] <= pack_data;
           Tests:       T1 T12 T20 
311                         end
                        MISSING_ELSE
312                       end
313                     
314        1/1            assign block_data_o = packed_data;
           Tests:       T1 T2 T3 
315                     
316                       // ECC handling
317                       localparam int PlainDataEccWidth = DataWidth + 8;
318                     
319                       logic [FullDataWidth-1:0] ecc_data;
320                       logic [PlainDataEccWidth-1:0] plain_data_w_ecc;
321                       logic [PlainIntgWidth-1:0] plain_data_ecc;
322                       always_ff @(posedge clk_i or negedge rst_ni) begin
323        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
324        1/1                plain_data_ecc <= '1;
           Tests:       T1 T2 T3 
325        1/1              end else if (plain_ecc_en) begin
           Tests:       T1 T2 T3 
326        1/1                plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
           Tests:       T1 T12 T20 
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       logic [PlainDataWidth-1:0] ecc_data_in;
331        1/1            assign ecc_data_in = {plain_data_ecc, packed_data};
           Tests:       T1 T2 T3 
332                     
333                       // reliability ECC calculation
334                       prim_secded_hamming_76_68_enc u_enc (
335                         .data_i(ecc_data_in),
336                         .data_o(ecc_data)
337                       );
338                     
339                       // integrity ECC calculation
340                       // This instance can technically be merged with the instance above, but is
341                       // kept separate for the sake of convenience
342                       // The plain data ecc is calculated continuously from packed data (which changes
343                       // from packed data to masked/scrambled data based on software configuration).
344                       // The actual plain data ECC is explicitly captured during this process when
345                       // it is required.
346                       prim_secded_hamming_72_64_enc u_plain_enc (
347                         .data_i(packed_data),
348                         .data_o(plain_data_w_ecc)
349                       );
350                     
351                       logic unused_data;
352        1/1            assign unused_data = |plain_data_w_ecc;
           Tests:       T1 T2 T3 
353                     
354                       // pad the remaining bits with '1' if ecc is not used.
355        1/1            assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
           Tests:       T1 T2 T3 
356                     
357                       /////////////////////////////////
358                       // Assertions
359                       /////////////////////////////////
360                     
361                     `ifdef INC_ASSERT
362                       logic txn_done;
363                       logic [15:0] done_cnt_d, done_cnt_q;
364                     
365        1/1            assign txn_done = req_i && ack_o && last_i;
           Tests:       T1 T2 T3 
366        1/1            assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
           Tests:       T1 T2 T3 
367                     
368                       always_ff @(posedge clk_i or negedge rst_ni) begin
369        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
370        1/1                done_cnt_q <= '0;
           Tests:       T1 T2 T3 
371                         end else begin
372        1/1                done_cnt_q <= done_cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Module : flash_phy_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T20

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T20

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T21,T263
1	0	Covered	T8,T21,T263

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T20
1	1	Covered	T8,T21,T263

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T21,T263
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T21,T263
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T20

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T12,T20
1	Covered	T59,T46,T80

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T20
1	0	Covered	T1,T12,T20
1	1	Covered	T1,T12,T20

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T20

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T20
1	1	Covered	T59,T46,T264

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T11
1	Covered	T10,T59,T46

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T20
1	0	Covered	T1,T12,T20
1	1	Covered	T1,T12,T20

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T12,T20
1	Covered	T1,T12,T20

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T20
1	0	Covered	T1,T12,T20
1	1	Covered	T59,T46,T80

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10,T11
1	Covered	T59,T46,T80

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T12,T20
1	Covered	T13,T14,T8

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T12,T14
1	Covered	T1,T12,T20

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T12,T8
1	Covered	T1,T12,T14

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T12,T14
1	1	Covered	T1,T12,T20

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T8
1	1	Covered	T13,T14,T8

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T8
1	1	Covered	T13,T14,T8

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T12,T20
1	1	0	Covered	T1,T12,T20
1	1	1	Covered	T1,T12,T20

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T20

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Module : flash_phy_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T13,T14,T8
StCalcMask	237	Covered	T13,T14,T8
StCalcPlainEcc	215	Covered	T1,T12,T20
StDisabled	193	Covered	T7,T8,T9
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T12,T20
StPostPack	218	Covered	T59,T46,T80
StPrePack	195	Covered	T59,T46,T264
StReqFlash	237	Covered	T1,T12,T20
StScrambleData	244	Covered	T13,T14,T8
StWaitFlash	270	Covered	T1,T12,T20

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T13,T14,T8
StCalcMask->StScrambleData	244	Covered	T13,T14,T8
StCalcPlainEcc->StCalcMask	237	Covered	T13,T14,T8
StCalcPlainEcc->StReqFlash	237	Covered	T1,T12,T20
StIdle->StDisabled	193	Covered	T7,T8,T9
StIdle->StPackData	197	Covered	T1,T12,T20
StIdle->StPrePack	195	Covered	T59,T46,T264
StPackData->StCalcPlainEcc	215	Covered	T1,T12,T20
StPackData->StPostPack	218	Covered	T59,T46,T80
StPostPack->StCalcPlainEcc	231	Covered	T59,T46,T80
StPrePack->StPackData	205	Covered	T59,T46,T264
StReqFlash->StIdle	273	Covered	T1,T12,T14
StReqFlash->StWaitFlash	270	Covered	T1,T12,T20
StScrambleData->StCalcEcc	252	Covered	T13,T14,T8
StWaitFlash->StIdle	280	Covered	T1,T12,T20

---

Branch Coverage for Module : flash_phy_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

111          assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T20
0	Covered	T1,T2,T3

148          assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T12,T20
0	Covered	T1,T2,T3

355          assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
                                   -1-  
                                   ==>  
                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

366          assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
                                          -1-          -2-   
                                          ==>          ==>   
                                                       ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T12,T20
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

130            if (!rst_ni) begin
               -1-  
131              data_invalid_q <= '0;
                 ==>
132            end else begin
133              data_invalid_q <= data_invalid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

151            if (!rst_ni) begin
               -1-  
152              idx <= '0;
                 ==>
153            end else if (pack_valid && idx == MaxIdx) begin
                        -2-  
154              // when a flash word is packed full, return index to 0
155              idx <= '0;
                 ==>
156            end else if (pack_valid) begin
                        -3-  
157              // increment otherwise
158              idx <= idx + 1'b1;
                 ==>
159            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T12,T20
0	0	1	Covered	T1,T12,T20
0	0	0	Covered	T1,T2,T3

164          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              StIdle: begin
188                // if first beat of a transaction is not aligned, prepack with empty bits
189                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -2-  
190                  // only disable during idle state to ensure program is able to gracefully complete
191                  // this is important as we do not want to accidentally disturb any electrical procedure
192                  // internal to the flash macro
193                  state_d = StDisabled;
                     ==>
194                end else if (req_i && |sel_i) begin
                            -3-  
195                  state_d = StPrePack;
                     ==>
196                end else if (req_i) begin
                            -4-  
197                  state_d = StPackData;
                     ==>
198                end
                   MISSING_ELSE
                   ==>
199              end
200        
201              StPrePack: begin
202                // pack until currently supplied data
203                pack_valid = (idx < sel_i);
204                if (idx == align_next) begin
                   -5-  
205                  state_d = StPackData;
                     ==>
206                end
                   MISSING_ELSE
                   ==>
207              end
208        
209              StPackData: begin
210                pack_valid = req_i;
211                data_sel = Actual;
212        
213                if (req_i && idx == MaxIdx) begin
                   -6-  
214                  // last beat of a flash word
215                  state_d = StCalcPlainEcc;
                     ==>
216                end else if (req_i && last_i) begin
                            -7-  
217                  // last beat is not aligned with the last entry of flash word
218                  state_d = StPostPack;
                     ==>
219                end else if (req_i) begin
                            -8-  
220                  ack_o = 1'b1;
                     ==>
221                end
                   MISSING_ELSE
                   ==>
222              end
223        
224              StPostPack: begin
225                // supply filler data
226                pack_valid = 1'b1;
227                data_sel = Filler;
228        
229                // finish packing remaining entries
230                if (idx == MaxIdx) begin
                   -9-  
231                  state_d = StCalcPlainEcc;
                     ==>
232                end
                   MISSING_ELSE
                   ==>
233              end
234        
235              StCalcPlainEcc: begin
236                plain_ecc_en = 1'b1;
237                state_d = scramble_i ? StCalcMask : StReqFlash;
                                        -10-  
                                        ==>  
                                        ==>  
238              end
239        
240              StCalcMask: begin
241                calc_req_o = 1'b1;
242        
243                if (calc_ack_i) begin
                   -11-  
244                  state_d = StScrambleData;
                     ==>
245                end
                   MISSING_ELSE
                   ==>
246              end
247        
248              StScrambleData: begin
249                scramble_req_o = 1'b1;
250        
251                if (scramble_ack_i) begin
                   -12-  
252                  state_d = StCalcEcc;
                     ==>
253                end
                   MISSING_ELSE
                   ==>
254              end
255        
256              StCalcEcc: begin
257                state_d = StReqFlash;
                   ==>
258              end
259        
260              StReqFlash: begin
261                // only request flash if data integrity was valid
262                req_o = ~data_invalid_q;
263                last_o = last_i;
264        
265                // if this is the last beat of the program burst
266                //   - wait for done
267                // if this is NOT the last beat
268                //   - ack the upstream request and accept more beats
269                if (last_i) begin
                   -13-  
270                  state_d = ack ? StWaitFlash : StReqFlash;
                                   -14-  
                                   ==>  
                                   ==>  
271                end else begin
272                  ack_o = ack;
273                  state_d = ack ? StIdle : StReqFlash;
                                   -15-  
                                   ==>  
                                   ==>  
274                end
275              end
276        
277              StWaitFlash: begin
278                if (done) begin
                   -16-  
279                  ack_o = 1'b1;
                     ==>
280                  state_d = StIdle;
281                end
                   MISSING_ELSE
                   ==>
282              end
283        
284              StDisabled: begin
285                state_d = StDisabled;
                   ==>
286              end
287        
288              default: begin
289                fsm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T59,T46
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T20
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T59,T46
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T12,T20
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T59,T46
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T12,T20
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T12,T20
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T10,T59,T46
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T11
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T14,T8
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T12,T20
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T13,T14,T8
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T13,T14,T8
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T14,T8
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T13,T14,T8
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T8
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T12,T20
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T12,T14
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T12,T14
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T12,T8
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T12,T20
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T12,T20
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T16

299            if (!rst_ni) begin
               -1-  
300              packed_data <= '0;
                 ==>
301              mask_q <= '0;
302            end else if (req_o && ack) begin
                        -2-  
303              packed_data <= '0;
                 ==>
304            end else if (calc_req_o && calc_ack_i) begin
                        -3-  
305              packed_data <= packed_data ^ mask_i;
                 ==>
306              mask_q <= mask_i;
307            end else if (scramble_req_o && scramble_ack_i) begin
                        -4-  
308              packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
                 ==>
309            end else if (pack_valid) begin
                        -5-  
310              packed_data[idx] <= pack_data;
                 ==>
311            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T12,T20
0	0	1	-	-	Covered	T13,T14,T8
0	0	0	1	-	Covered	T13,T14,T8
0	0	0	0	1	Covered	T1,T12,T20
0	0	0	0	0	Covered	T1,T2,T3

323            if (!rst_ni) begin
               -1-  
324              plain_data_ecc <= '1;
                 ==>
325            end else if (plain_ecc_en) begin
                        -2-  
326              plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T12,T20
0	0	Covered	T1,T2,T3

369            if (!rst_ni) begin
               -1-  
370              done_cnt_q <= '0;
                 ==>
371            end else begin
372              done_cnt_q <= done_cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_phy_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	776511532	2427809	0	0
PostPackRule_A	776511532	1734	0	0
PrePackRule_A	776511532	1205	0	0
WidthCheck_A	2114	2114	0	0
u_state_regs_A	776511532	774831282	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	2427809	0	0
T1	3906	13	0	0
T2	10848	0	0	0
T3	1224	0	0	0
T4	1780	0	0	0
T7	1944	0	0	0
T8	4134	0	0	0
T9	976	1	0	0
T12	4004	1	0	0
T13	2705	1	0	0
T14	144394	108	0	0
T15	29510	6	0	0
T17	1544	0	0	0
T18	1950	0	0	0
T19	2303	0	0	0
T20	2946	1	0	0
T23	7299	0	0	0
T27	0	1384	0	0
T39	0	272	0	0
T40	0	46	0	0
T46	0	30	0	0
T51	0	100	0	0
T59	0	4	0	0
T64	0	1	0	0
T80	0	1	0	0
T98	0	346	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	1734	0	0
T24	1472	0	0	0
T25	0	2	0	0
T30	371652	0	0	0
T31	0	9	0	0
T39	63721	0	0	0
T40	32297	0	0	0
T41	55208	0	0	0
T46	165218	28	0	0
T47	111904	0	0	0
T55	53090	0	0	0
T59	3485	3	0	0
T65	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T80	4234	1	0	0
T92	0	32	0	0
T93	0	34	0	0
T94	1788	0	0	0
T109	2660	0	0	0
T110	1127	0	0	0
T126	1266	0	0	0
T150	0	7	0	0
T231	0	4	0	0
T251	1902	0	0	0
T264	1801	1	0	0
T265	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	1205	0	0
T24	1472	0	0	0
T25	0	1	0	0
T30	371652	0	0	0
T31	0	10	0	0
T39	63721	0	0	0
T40	32297	0	0	0
T41	55208	0	0	0
T46	165218	23	0	0
T47	111904	0	0	0
T55	53090	0	0	0
T59	3485	4	0	0
T65	0	2	0	0
T74	0	1	0	0
T75	0	3	0	0
T80	4234	0	0	0
T92	0	29	0	0
T93	0	27	0	0
T94	1788	0	0	0
T109	2660	0	0	0
T110	1127	0	0	0
T126	1266	0	0	0
T150	0	9	0	0
T231	0	2	0	0
T251	1902	0	0	0
T264	1801	1	0	0
T265	0	2	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2114	2114	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T7	2	2	0	0
T12	2	2	0	0
T17	2	2	0	0
T18	2	2	0	0
T19	2	2	0	0
T20	2	2	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	776511532	774831282	0	0
T1	7812	7706	0	0
T2	21696	21556	0	0
T3	2448	2334	0	0
T4	1780	1680	0	0
T7	1944	1844	0	0
T12	4004	3888	0	0
T17	3088	2978	0	0
T18	3900	3732	0	0
T19	4606	4422	0	0
T20	2946	2676	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

110                       // selects empty data or real data
111        1/1            assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
           Tests:       T1 T2 T3 
112                     
113                       logic data_intg_ok;
114                       logic data_err;
115                     
116                       // use the tlul integrity module directly for bus integrity
117                       // SEC_CM: MEM.BUS.INTEGRITY
118                       tlul_data_integ_dec u_data_intg_chk (
119                         .data_intg_i(data_i),
120                         .data_err_o(data_err)
121                       );
122        1/1            assign data_intg_ok = ~data_err;
           Tests:       T1 T2 T3 
123                     
124                       logic data_invalid_q, data_invalid_d;
125                       // hold on integrity failure indication until reset
126        1/1            assign data_invalid_d = data_invalid_q |
           Tests:       T1 T2 T3 
127                                               (pack_valid & ~data_intg_ok);
128                     
129                       always_ff @(posedge clk_i or negedge rst_ni) begin
130        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
131        1/1                data_invalid_q <= '0;
           Tests:       T1 T2 T3 
132                         end else begin
133        1/1                data_invalid_q <= data_invalid_d;
           Tests:       T1 T2 T3 
134                         end
135                       end
136                     
137                       // indication to upper layer presence of error
138        1/1            assign intg_err_o = data_invalid_q;
           Tests:       T1 T2 T3 
139                     
140                       // if integrity failure is seen, fake communication with flash
141                       // and simply terminate
142                       logic ack, done;
143        1/1            assign ack = ack_i | data_invalid_q;
           Tests:       T1 T2 T3 
144        1/1            assign done = done_i | data_invalid_q;
           Tests:       T1 T2 T3 
145                     
146                       // next idx will be aligned
147        1/1            assign idx_sub_one = idx - 1'b1;
           Tests:       T1 T2 T3 
148        1/1            assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
           Tests:       T1 T2 T3 
149                     
150                       always_ff @(posedge clk_i or negedge rst_ni) begin
151        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
152        1/1                idx <= '0;
           Tests:       T1 T2 T3 
153        1/1              end else if (pack_valid && idx == MaxIdx) begin
           Tests:       T1 T2 T3 
154                           // when a flash word is packed full, return index to 0
155        1/1                idx <= '0;
           Tests:       T1 T8 T9 
156        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
157                           // increment otherwise
158        1/1                idx <= idx + 1'b1;
           Tests:       T1 T8 T9 
159                         end
                        MISSING_ELSE
160                       end
161                     
162                     
163                       // SEC_CM: PHY_PROG.FSM.SPARSE
164        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
164.1                   `ifdef SIMULATION                                   
164.2                       prim_sparse_fsm_flop #(                           
164.3                         .StateEnumT(state_e),                            
164.4                         .Width($bits(state_e)),                          
164.5                         .ResetValue($bits(state_e)'(StIdle)),          
164.6                         .EnableAlertTriggerSVA(1), 
164.7                         .CustomForceName("state_q")          
164.8                       ) u_state_regs (                                        
164.9                         .clk_i   ( clk_i   ),                           
164.10                        .rst_ni  ( rst_ni ),                           
164.11                        .state_i ( state_d     ),                           
164.12                        .state_o (         )                            
164.13                      );                                                
164.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
164.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
164.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
164.17                      end else begin                                    
164.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
164.19                      end                                               
164.20                    end  
164.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
164.22                      else begin                                                                           
164.23                        `ifdef UVM                                                                               
164.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
164.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv", 164, "", 1);                                
164.26                  `else                                                                                    
164.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
164.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
164.29                  `endif                                                              
164.30                      end 
164.31                    `else                                               
164.32                      prim_sparse_fsm_flop #(                           
164.33                        .StateEnumT(state_e),                            
164.34                        .Width($bits(state_e)),                          
164.35                        .ResetValue($bits(state_e)'(StIdle)),          
164.36                        .EnableAlertTriggerSVA(1)  
164.37                      ) u_state_regs (                                        
164.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
164.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
164.40                        .state_i ( state_d     ),                           
164.41                        .state_o ( state_q     )                            
164.42                      );                                                
164.43                    `endif165                     
166                       // If the first beat of an incoming transaction is not aligned to word boundary (for example
167                       // if each flash word is 4 bus words wide, and the first word to program starts at index 1),
168                       // the fsm pre-packs the flash word with empty words until the supplied index.
169                       // Once at the index, real data supplied from the flash controller is packed until the last
170                       // beat of data.  At the last beat of data, if it is not also aligned (index 3 in this example),
171                       // more empty words are packed at the end to fill out the word.
172                       //
173                       always_comb begin
174        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
175                     
176        1/1              pack_valid = 1'b0;
           Tests:       T1 T2 T3 
177        1/1              data_sel = Filler;
           Tests:       T1 T2 T3 
178        1/1              plain_ecc_en = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              req_o = 1'b0;
           Tests:       T1 T2 T3 
180        1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
181        1/1              last_o = 1'b0;
           Tests:       T1 T2 T3 
182        1/1              calc_req_o = 1'b0;
           Tests:       T1 T2 T3 
183        1/1              scramble_req_o = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           StIdle: begin
188                             // if first beat of a transaction is not aligned, prepack with empty bits
189        1/1                  if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
           Tests:       T1 T2 T3 
190                               // only disable during idle state to ensure program is able to gracefully complete
191                               // this is important as we do not want to accidentally disturb any electrical procedure
192                               // internal to the flash macro
193        1/1                    state_d = StDisabled;
           Tests:       T7 T8 T9 
194        1/1                  end else if (req_i && |sel_i) begin
           Tests:       T1 T2 T3 
195        1/1                    state_d = StPrePack;
           Tests:       T10 T59 T46 
196        1/1                  end else if (req_i) begin
           Tests:       T1 T2 T3 
197        1/1                    state_d = StPackData;
           Tests:       T1 T8 T9 
198                             end
                        MISSING_ELSE
199                           end
200                     
201                           StPrePack: begin
202                             // pack until currently supplied data
203        1/1                  pack_valid = (idx < sel_i);
           Tests:       T10 T59 T46 
204        1/1                  if (idx == align_next) begin
           Tests:       T10 T59 T46 
205        1/1                    state_d = StPackData;
           Tests:       T10 T59 T46 
206                             end
                        MISSING_ELSE
207                           end
208                     
209                           StPackData: begin
210        1/1                  pack_valid = req_i;
           Tests:       T1 T8 T9 
211        1/1                  data_sel = Actual;
           Tests:       T1 T8 T9 
212                     
213        1/1                  if (req_i && idx == MaxIdx) begin
           Tests:       T1 T8 T9 
214                               // last beat of a flash word
215        1/1                    state_d = StCalcPlainEcc;
           Tests:       T1 T8 T9 
216        1/1                  end else if (req_i && last_i) begin
           Tests:       T1 T8 T9 
217                               // last beat is not aligned with the last entry of flash word
218        1/1                    state_d = StPostPack;
           Tests:       T10 T59 T46 
219        1/1                  end else if (req_i) begin
           Tests:       T1 T8 T9 
220        1/1                    ack_o = 1'b1;
           Tests:       T1 T8 T9 
221                             end
                        MISSING_ELSE
222                           end
223                     
224                           StPostPack: begin
225                             // supply filler data
226        1/1                  pack_valid = 1'b1;
           Tests:       T10 T59 T46 
227        1/1                  data_sel = Filler;
           Tests:       T10 T59 T46 
228                     
229                             // finish packing remaining entries
230        1/1                  if (idx == MaxIdx) begin
           Tests:       T10 T59 T46 
231        1/1                    state_d = StCalcPlainEcc;
           Tests:       T10 T59 T46 
232                             end
                        MISSING_ELSE
233                           end
234                     
235                           StCalcPlainEcc: begin
236        1/1                  plain_ecc_en = 1'b1;
           Tests:       T1 T8 T9 
237        1/1                  state_d = scramble_i ? StCalcMask : StReqFlash;
           Tests:       T1 T8 T9 
238                           end
239                     
240                           StCalcMask: begin
241        1/1                  calc_req_o = 1'b1;
           Tests:       T8 T9 T27 
242                     
243        1/1                  if (calc_ack_i) begin
           Tests:       T8 T9 T27 
244        1/1                    state_d = StScrambleData;
           Tests:       T8 T9 T27 
245                             end
                        MISSING_ELSE
246                           end
247                     
248                           StScrambleData: begin
249        1/1                  scramble_req_o = 1'b1;
           Tests:       T8 T9 T27 
250                     
251        1/1                  if (scramble_ack_i) begin
           Tests:       T8 T9 T27 
252        1/1                    state_d = StCalcEcc;
           Tests:       T8 T9 T27 
253                             end
                        MISSING_ELSE
254                           end
255                     
256                           StCalcEcc: begin
257        1/1                  state_d = StReqFlash;
           Tests:       T8 T9 T27 
258                           end
259                     
260                           StReqFlash: begin
261                             // only request flash if data integrity was valid
262        1/1                  req_o = ~data_invalid_q;
           Tests:       T1 T8 T9 
263        1/1                  last_o = last_i;
           Tests:       T1 T8 T9 
264                     
265                             // if this is the last beat of the program burst
266                             //   - wait for done
267                             // if this is NOT the last beat
268                             //   - ack the upstream request and accept more beats
269        1/1                  if (last_i) begin
           Tests:       T1 T8 T9 
270        1/1                    state_d = ack ? StWaitFlash : StReqFlash;
           Tests:       T1 T9 T51 
271                             end else begin
272        1/1                    ack_o = ack;
           Tests:       T1 T8 T51 
273        1/1                    state_d = ack ? StIdle : StReqFlash;
           Tests:       T1 T8 T51 
274                             end
275                           end
276                     
277                           StWaitFlash: begin
278        1/1                  if (done) begin
           Tests:       T1 T9 T51 
279        1/1                    ack_o = 1'b1;
           Tests:       T1 T9 T51 
280        1/1                    state_d = StIdle;
           Tests:       T1 T9 T51 
281                             end
                        MISSING_ELSE
282                           end
283                     
284                           StDisabled: begin
285        1/1                  state_d = StDisabled;
           Tests:       T7 T8 T9 
286                           end
287                     
288                           default: begin
289                             fsm_err_o = 1'b1;
290                           end
291                     
292                         endcase // unique case (state_q)
293                     
294                       end
295                     
296                       logic [DataWidth-1:0] mask_q;
297                     
298                       always_ff @(posedge clk_i or negedge rst_ni) begin
299        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
300        1/1                packed_data <= '0;
           Tests:       T1 T2 T3 
301        1/1                mask_q <= '0;
           Tests:       T1 T2 T3 
302        1/1              end else if (req_o && ack) begin
           Tests:       T1 T2 T3 
303        1/1                packed_data <= '0;
           Tests:       T1 T9 T51 
304        1/1              end else if (calc_req_o && calc_ack_i) begin
           Tests:       T1 T2 T3 
305        1/1                packed_data <= packed_data ^ mask_i;
           Tests:       T8 T9 T27 
306        1/1                mask_q <= mask_i;
           Tests:       T8 T9 T27 
307        1/1              end else if (scramble_req_o && scramble_ack_i) begin
           Tests:       T1 T2 T3 
308        1/1                packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
           Tests:       T8 T9 T27 
309        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
310        1/1                packed_data[idx] <= pack_data;
           Tests:       T1 T8 T9 
311                         end
                        MISSING_ELSE
312                       end
313                     
314        1/1            assign block_data_o = packed_data;
           Tests:       T1 T2 T3 
315                     
316                       // ECC handling
317                       localparam int PlainDataEccWidth = DataWidth + 8;
318                     
319                       logic [FullDataWidth-1:0] ecc_data;
320                       logic [PlainDataEccWidth-1:0] plain_data_w_ecc;
321                       logic [PlainIntgWidth-1:0] plain_data_ecc;
322                       always_ff @(posedge clk_i or negedge rst_ni) begin
323        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
324        1/1                plain_data_ecc <= '1;
           Tests:       T1 T2 T3 
325        1/1              end else if (plain_ecc_en) begin
           Tests:       T1 T2 T3 
326        1/1                plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
           Tests:       T1 T8 T9 
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       logic [PlainDataWidth-1:0] ecc_data_in;
331        1/1            assign ecc_data_in = {plain_data_ecc, packed_data};
           Tests:       T1 T2 T3 
332                     
333                       // reliability ECC calculation
334                       prim_secded_hamming_76_68_enc u_enc (
335                         .data_i(ecc_data_in),
336                         .data_o(ecc_data)
337                       );
338                     
339                       // integrity ECC calculation
340                       // This instance can technically be merged with the instance above, but is
341                       // kept separate for the sake of convenience
342                       // The plain data ecc is calculated continuously from packed data (which changes
343                       // from packed data to masked/scrambled data based on software configuration).
344                       // The actual plain data ECC is explicitly captured during this process when
345                       // it is required.
346                       prim_secded_hamming_72_64_enc u_plain_enc (
347                         .data_i(packed_data),
348                         .data_o(plain_data_w_ecc)
349                       );
350                     
351                       logic unused_data;
352        1/1            assign unused_data = |plain_data_w_ecc;
           Tests:       T1 T2 T3 
353                     
354                       // pad the remaining bits with '1' if ecc is not used.
355        1/1            assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
           Tests:       T1 T2 T3 
356                     
357                       /////////////////////////////////
358                       // Assertions
359                       /////////////////////////////////
360                     
361                     `ifdef INC_ASSERT
362                       logic txn_done;
363                       logic [15:0] done_cnt_d, done_cnt_q;
364                     
365        1/1            assign txn_done = req_i && ack_o && last_i;
           Tests:       T1 T2 T3 
366        1/1            assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
           Tests:       T1 T2 T3 
367                     
368                       always_ff @(posedge clk_i or negedge rst_ni) begin
369        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
370        1/1                done_cnt_q <= '0;
           Tests:       T1 T2 T3 
371                         end else begin
372        1/1                done_cnt_q <= done_cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	63	96.92
Logical	65	63	96.92
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T21,T263
1	0	Covered	T8,T21,T263

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T9,T51
1	1	Covered	T8,T21,T263

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Not Covered
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T21,T263
1	0	Covered	T1,T2,T18

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T1,T8,T9
1	Covered	T59,T46,T80

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T8,T9

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T8,T9
1	1	Covered	T59,T46,T74

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10
1	Covered	T10,T59,T46

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9
1	1	Covered	T1,T8,T9

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T8,T9
1	Covered	T1,T8,T9

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T1,T8,T9
1	1	Covered	T59,T46,T80

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10
1	Covered	T59,T46,T80

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T1,T51,T27
1	Covered	T8,T9,T27

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T51,T27
1	Covered	T1,T9,T51

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T1,T51,T27
1	Covered	T1,T8,T51

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T51,T27
1	1	Covered	T1,T9,T51

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T20,T23,T13
1	0	Covered	T8,T9,T27
1	1	Covered	T8,T9,T27

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T20,T23,T13
1	0	Covered	T8,T9,T27
1	1	Covered	T8,T9,T27

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T1,T8,T9
1	1	0	Covered	T1,T8,T9
1	1	1	Covered	T1,T9,T51

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T9,T51

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T2,T18,T20

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T8,T9,T27
StCalcMask	237	Covered	T8,T9,T27
StCalcPlainEcc	215	Covered	T1,T8,T9
StDisabled	193	Covered	T7,T8,T9
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T1,T8,T9
StPostPack	218	Covered	T59,T46,T80
StPrePack	195	Covered	T59,T46,T74
StReqFlash	237	Covered	T1,T8,T9
StScrambleData	244	Covered	T8,T9,T27
StWaitFlash	270	Covered	T1,T9,T51

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T8,T9,T27
StCalcMask->StScrambleData	244	Covered	T8,T9,T27
StCalcPlainEcc->StCalcMask	237	Covered	T8,T9,T27
StCalcPlainEcc->StReqFlash	237	Covered	T1,T51,T27
StIdle->StDisabled	193	Covered	T7,T8,T9
StIdle->StPackData	197	Covered	T1,T8,T9
StIdle->StPrePack	195	Covered	T59,T46,T74
StPackData->StCalcPlainEcc	215	Covered	T1,T8,T9
StPackData->StPostPack	218	Covered	T59,T46,T80
StPostPack->StCalcPlainEcc	231	Covered	T59,T46,T80
StPrePack->StPackData	205	Covered	T59,T46,T74
StReqFlash->StIdle	273	Covered	T1,T8,T51
StReqFlash->StWaitFlash	270	Covered	T1,T9,T51
StScrambleData->StCalcEcc	252	Covered	T8,T9,T27
StWaitFlash->StIdle	280	Covered	T1,T9,T51

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

111          assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

148          assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T1,T2,T3

355          assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
                                   -1-  
                                   ==>  
                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

366          assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
                                          -1-          -2-   
                                          ==>          ==>   
                                                       ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T9,T51
0	1	Covered	T2,T18,T20
0	0	Covered	T1,T2,T3

130            if (!rst_ni) begin
               -1-  
131              data_invalid_q <= '0;
                 ==>
132            end else begin
133              data_invalid_q <= data_invalid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

151            if (!rst_ni) begin
               -1-  
152              idx <= '0;
                 ==>
153            end else if (pack_valid && idx == MaxIdx) begin
                        -2-  
154              // when a flash word is packed full, return index to 0
155              idx <= '0;
                 ==>
156            end else if (pack_valid) begin
                        -3-  
157              // increment otherwise
158              idx <= idx + 1'b1;
                 ==>
159            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T1,T8,T9
0	0	1	Covered	T1,T8,T9
0	0	0	Covered	T1,T2,T3

164          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              StIdle: begin
188                // if first beat of a transaction is not aligned, prepack with empty bits
189                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -2-  
190                  // only disable during idle state to ensure program is able to gracefully complete
191                  // this is important as we do not want to accidentally disturb any electrical procedure
192                  // internal to the flash macro
193                  state_d = StDisabled;
                     ==>
194                end else if (req_i && |sel_i) begin
                            -3-  
195                  state_d = StPrePack;
                     ==>
196                end else if (req_i) begin
                            -4-  
197                  state_d = StPackData;
                     ==>
198                end
                   MISSING_ELSE
                   ==>
199              end
200        
201              StPrePack: begin
202                // pack until currently supplied data
203                pack_valid = (idx < sel_i);
204                if (idx == align_next) begin
                   -5-  
205                  state_d = StPackData;
                     ==>
206                end
                   MISSING_ELSE
                   ==>
207              end
208        
209              StPackData: begin
210                pack_valid = req_i;
211                data_sel = Actual;
212        
213                if (req_i && idx == MaxIdx) begin
                   -6-  
214                  // last beat of a flash word
215                  state_d = StCalcPlainEcc;
                     ==>
216                end else if (req_i && last_i) begin
                            -7-  
217                  // last beat is not aligned with the last entry of flash word
218                  state_d = StPostPack;
                     ==>
219                end else if (req_i) begin
                            -8-  
220                  ack_o = 1'b1;
                     ==>
221                end
                   MISSING_ELSE
                   ==>
222              end
223        
224              StPostPack: begin
225                // supply filler data
226                pack_valid = 1'b1;
227                data_sel = Filler;
228        
229                // finish packing remaining entries
230                if (idx == MaxIdx) begin
                   -9-  
231                  state_d = StCalcPlainEcc;
                     ==>
232                end
                   MISSING_ELSE
                   ==>
233              end
234        
235              StCalcPlainEcc: begin
236                plain_ecc_en = 1'b1;
237                state_d = scramble_i ? StCalcMask : StReqFlash;
                                        -10-  
                                        ==>  
                                        ==>  
238              end
239        
240              StCalcMask: begin
241                calc_req_o = 1'b1;
242        
243                if (calc_ack_i) begin
                   -11-  
244                  state_d = StScrambleData;
                     ==>
245                end
                   MISSING_ELSE
                   ==>
246              end
247        
248              StScrambleData: begin
249                scramble_req_o = 1'b1;
250        
251                if (scramble_ack_i) begin
                   -12-  
252                  state_d = StCalcEcc;
                     ==>
253                end
                   MISSING_ELSE
                   ==>
254              end
255        
256              StCalcEcc: begin
257                state_d = StReqFlash;
                   ==>
258              end
259        
260              StReqFlash: begin
261                // only request flash if data integrity was valid
262                req_o = ~data_invalid_q;
263                last_o = last_i;
264        
265                // if this is the last beat of the program burst
266                //   - wait for done
267                // if this is NOT the last beat
268                //   - ack the upstream request and accept more beats
269                if (last_i) begin
                   -13-  
270                  state_d = ack ? StWaitFlash : StReqFlash;
                                   -14-  
                                   ==>  
                                   ==>  
271                end else begin
272                  ack_o = ack;
273                  state_d = ack ? StIdle : StReqFlash;
                                   -15-  
                                   ==>  
                                   ==>  
274                end
275              end
276        
277              StWaitFlash: begin
278                if (done) begin
                   -16-  
279                  ack_o = 1'b1;
                     ==>
280                  state_d = StIdle;
281                end
                   MISSING_ELSE
                   ==>
282              end
283        
284              StDisabled: begin
285                state_d = StDisabled;
                   ==>
286              end
287        
288              default: begin
289                fsm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T59,T46
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T9
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T59,T46
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T1,T8,T9
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T59,T46
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T1,T8,T9
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T1,T8,T9
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T10,T59,T46
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T8,T9,T27
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T1,T51,T27
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T8,T9,T27
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T8,T9,T27
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T8,T9,T27
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T8,T9,T27
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T8,T9,T27
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T1,T9,T51
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T1,T51,T27
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T1,T8,T51
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T1,T51,T27
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T1,T9,T51
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T9,T51
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T16,T43

299            if (!rst_ni) begin
               -1-  
300              packed_data <= '0;
                 ==>
301              mask_q <= '0;
302            end else if (req_o && ack) begin
                        -2-  
303              packed_data <= '0;
                 ==>
304            end else if (calc_req_o && calc_ack_i) begin
                        -3-  
305              packed_data <= packed_data ^ mask_i;
                 ==>
306              mask_q <= mask_i;
307            end else if (scramble_req_o && scramble_ack_i) begin
                        -4-  
308              packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
                 ==>
309            end else if (pack_valid) begin
                        -5-  
310              packed_data[idx] <= pack_data;
                 ==>
311            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T1,T9,T51
0	0	1	-	-	Covered	T8,T9,T27
0	0	0	1	-	Covered	T8,T9,T27
0	0	0	0	1	Covered	T1,T8,T9
0	0	0	0	0	Covered	T1,T2,T3

323            if (!rst_ni) begin
               -1-  
324              plain_data_ecc <= '1;
                 ==>
325            end else if (plain_ecc_en) begin
                        -2-  
326              plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T1,T8,T9
0	0	Covered	T1,T2,T3

369            if (!rst_ni) begin
               -1-  
370              done_cnt_q <= '0;
                 ==>
371            end else begin
372              done_cnt_q <= done_cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	388255766	1200980	0	0
PostPackRule_A	388255766	841	0	0
PrePackRule_A	388255766	596	0	0
WidthCheck_A	1057	1057	0	0
u_state_regs_A	388255766	387415641	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	1200980	0	0
T1	3906	13	0	0
T2	10848	0	0	0
T3	1224	0	0	0
T4	890	0	0	0
T7	972	0	0	0
T9	0	1	0	0
T12	2002	0	0	0
T17	1544	0	0	0
T18	1950	0	0	0
T19	2303	0	0	0
T20	1473	0	0	0
T27	0	822	0	0
T39	0	113	0	0
T40	0	46	0	0
T46	0	30	0	0
T51	0	54	0	0
T59	0	4	0	0
T80	0	1	0	0
T98	0	166	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	841	0	0
T30	185826	0	0	0
T31	0	2	0	0
T39	63721	0	0	0
T40	32297	0	0	0
T46	82609	16	0	0
T47	55952	0	0	0
T59	3485	3	0	0
T65	0	2	0	0
T74	0	2	0	0
T80	2117	1	0	0
T92	0	14	0	0
T93	0	17	0	0
T94	1788	0	0	0
T110	1127	0	0	0
T126	1266	0	0	0
T150	0	4	0	0
T231	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	596	0	0
T30	185826	0	0	0
T31	0	3	0	0
T39	63721	0	0	0
T40	32297	0	0	0
T46	82609	11	0	0
T47	55952	0	0	0
T59	3485	4	0	0
T65	0	2	0	0
T74	0	1	0	0
T75	0	1	0	0
T80	2117	0	0	0
T92	0	13	0	0
T93	0	16	0	0
T94	1788	0	0	0
T110	1127	0	0	0
T126	1266	0	0	0
T150	0	6	0	0
T265	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	387415641	0	0
T1	3906	3853	0	0
T2	10848	10778	0	0
T3	1224	1167	0	0
T4	890	840	0	0
T7	972	922	0	0
T12	2002	1944	0	0
T17	1544	1489	0	0
T18	1950	1866	0	0
T19	2303	2211	0	0
T20	1473	1338	0	0

Line Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
TOTAL		96	96	100.00
CONT_ASSIGN	111	1	1	100.00
CONT_ASSIGN	122	1	1	100.00
CONT_ASSIGN	126	1	1	100.00
ALWAYS	130	3	3	100.00
CONT_ASSIGN	138	1	1	100.00
CONT_ASSIGN	143	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	147	1	1	100.00
CONT_ASSIGN	148	1	1	100.00
ALWAYS	151	6	6	100.00
ALWAYS	164	3	3	100.00
ALWAYS	174	51	51	100.00
ALWAYS	299	12	12	100.00
CONT_ASSIGN	314	1	1	100.00
ALWAYS	323	4	4	100.00
CONT_ASSIGN	331	1	1	100.00
CONT_ASSIGN	352	1	1	100.00
CONT_ASSIGN	355	1	1	100.00
CONT_ASSIGN	365	1	1	100.00
CONT_ASSIGN	366	1	1	100.00
ALWAYS	369	3	3	100.00

110                       // selects empty data or real data
111        1/1            assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
           Tests:       T1 T2 T3 
112                     
113                       logic data_intg_ok;
114                       logic data_err;
115                     
116                       // use the tlul integrity module directly for bus integrity
117                       // SEC_CM: MEM.BUS.INTEGRITY
118                       tlul_data_integ_dec u_data_intg_chk (
119                         .data_intg_i(data_i),
120                         .data_err_o(data_err)
121                       );
122        1/1            assign data_intg_ok = ~data_err;
           Tests:       T1 T2 T3 
123                     
124                       logic data_invalid_q, data_invalid_d;
125                       // hold on integrity failure indication until reset
126        1/1            assign data_invalid_d = data_invalid_q |
           Tests:       T1 T2 T3 
127                                               (pack_valid & ~data_intg_ok);
128                     
129                       always_ff @(posedge clk_i or negedge rst_ni) begin
130        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
131        1/1                data_invalid_q <= '0;
           Tests:       T1 T2 T3 
132                         end else begin
133        1/1                data_invalid_q <= data_invalid_d;
           Tests:       T1 T2 T3 
134                         end
135                       end
136                     
137                       // indication to upper layer presence of error
138        1/1            assign intg_err_o = data_invalid_q;
           Tests:       T1 T2 T3 
139                     
140                       // if integrity failure is seen, fake communication with flash
141                       // and simply terminate
142                       logic ack, done;
143        1/1            assign ack = ack_i | data_invalid_q;
           Tests:       T1 T2 T3 
144        1/1            assign done = done_i | data_invalid_q;
           Tests:       T1 T2 T3 
145                     
146                       // next idx will be aligned
147        1/1            assign idx_sub_one = idx - 1'b1;
           Tests:       T1 T2 T3 
148        1/1            assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
           Tests:       T1 T2 T3 
149                     
150                       always_ff @(posedge clk_i or negedge rst_ni) begin
151        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
152        1/1                idx <= '0;
           Tests:       T1 T2 T3 
153        1/1              end else if (pack_valid && idx == MaxIdx) begin
           Tests:       T1 T2 T3 
154                           // when a flash word is packed full, return index to 0
155        1/1                idx <= '0;
           Tests:       T12 T20 T13 
156        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
157                           // increment otherwise
158        1/1                idx <= idx + 1'b1;
           Tests:       T12 T20 T13 
159                         end
                        MISSING_ELSE
160                       end
161                     
162                     
163                       // SEC_CM: PHY_PROG.FSM.SPARSE
164        3/3            `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
           Tests:       T1 T2 T3  | T1 T2 T3  | T1 T2 T3 
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle):
164.1                   `ifdef SIMULATION                                   
164.2                       prim_sparse_fsm_flop #(                           
164.3                         .StateEnumT(state_e),                            
164.4                         .Width($bits(state_e)),                          
164.5                         .ResetValue($bits(state_e)'(StIdle)),          
164.6                         .EnableAlertTriggerSVA(1), 
164.7                         .CustomForceName("state_q")          
164.8                       ) u_state_regs (                                        
164.9                         .clk_i   ( clk_i   ),                           
164.10                        .rst_ni  ( rst_ni ),                           
164.11                        .state_i ( state_d     ),                           
164.12                        .state_o (         )                            
164.13                      );                                                
164.14                      always_ff @(posedge clk_i or negedge rst_ni) begin 
164.15     1/1              if (!rst_ni) begin                               
           Tests:       T1 T2 T3 
164.16     1/1                state_q <= StIdle;                                
           Tests:       T1 T2 T3 
164.17                      end else begin                                    
164.18     1/1                state_q <= state_d;                                     
           Tests:       T1 T2 T3 
164.19                      end                                               
164.20                    end  
164.21                      u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o))       
164.22                      else begin                                                                           
164.23                        `ifdef UVM                                                                               
164.24                    uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 
164.25                                              "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_phy_prog.sv", 164, "", 1);                                
164.26                  `else                                                                                    
164.27                    $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__,         
164.28                           `PRIM_STRINGIFY(u_state_regs_A));                                                       
164.29                  `endif                                                              
164.30                      end 
164.31                    `else                                               
164.32                      prim_sparse_fsm_flop #(                           
164.33                        .StateEnumT(state_e),                            
164.34                        .Width($bits(state_e)),                          
164.35                        .ResetValue($bits(state_e)'(StIdle)),          
164.36                        .EnableAlertTriggerSVA(1)  
164.37                      ) u_state_regs (                                        
164.38                        .clk_i   ( `PRIM_FLOP_CLK   ),                           
164.39                        .rst_ni  ( `PRIM_FLOP_RST ),                           
164.40                        .state_i ( state_d     ),                           
164.41                        .state_o ( state_q     )                            
164.42                      );                                                
164.43                    `endif165                     
166                       // If the first beat of an incoming transaction is not aligned to word boundary (for example
167                       // if each flash word is 4 bus words wide, and the first word to program starts at index 1),
168                       // the fsm pre-packs the flash word with empty words until the supplied index.
169                       // Once at the index, real data supplied from the flash controller is packed until the last
170                       // beat of data.  At the last beat of data, if it is not also aligned (index 3 in this example),
171                       // more empty words are packed at the end to fill out the word.
172                       //
173                       always_comb begin
174        1/1              state_d = state_q;
           Tests:       T1 T2 T3 
175                     
176        1/1              pack_valid = 1'b0;
           Tests:       T1 T2 T3 
177        1/1              data_sel = Filler;
           Tests:       T1 T2 T3 
178        1/1              plain_ecc_en = 1'b0;
           Tests:       T1 T2 T3 
179        1/1              req_o = 1'b0;
           Tests:       T1 T2 T3 
180        1/1              ack_o = 1'b0;
           Tests:       T1 T2 T3 
181        1/1              last_o = 1'b0;
           Tests:       T1 T2 T3 
182        1/1              calc_req_o = 1'b0;
           Tests:       T1 T2 T3 
183        1/1              scramble_req_o = 1'b0;
           Tests:       T1 T2 T3 
184        1/1              fsm_err_o = 1'b0;
           Tests:       T1 T2 T3 
185                     
186        1/1              unique case (state_q)
           Tests:       T1 T2 T3 
187                           StIdle: begin
188                             // if first beat of a transaction is not aligned, prepack with empty bits
189        1/1                  if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
           Tests:       T1 T2 T3 
190                               // only disable during idle state to ensure program is able to gracefully complete
191                               // this is important as we do not want to accidentally disturb any electrical procedure
192                               // internal to the flash macro
193        1/1                    state_d = StDisabled;
           Tests:       T7 T8 T9 
194        1/1                  end else if (req_i && |sel_i) begin
           Tests:       T1 T2 T3 
195        1/1                    state_d = StPrePack;
           Tests:       T10 T46 T264 
196        1/1                  end else if (req_i) begin
           Tests:       T1 T2 T3 
197        1/1                    state_d = StPackData;
           Tests:       T12 T20 T13 
198                             end
                        MISSING_ELSE
199                           end
200                     
201                           StPrePack: begin
202                             // pack until currently supplied data
203        1/1                  pack_valid = (idx < sel_i);
           Tests:       T10 T46 T264 
204        1/1                  if (idx == align_next) begin
           Tests:       T10 T46 T264 
205        1/1                    state_d = StPackData;
           Tests:       T10 T46 T264 
206                             end
                        MISSING_ELSE
207                           end
208                     
209                           StPackData: begin
210        1/1                  pack_valid = req_i;
           Tests:       T12 T20 T13 
211        1/1                  data_sel = Actual;
           Tests:       T12 T20 T13 
212                     
213        1/1                  if (req_i && idx == MaxIdx) begin
           Tests:       T12 T20 T13 
214                               // last beat of a flash word
215        1/1                    state_d = StCalcPlainEcc;
           Tests:       T12 T20 T13 
216        1/1                  end else if (req_i && last_i) begin
           Tests:       T12 T20 T13 
217                               // last beat is not aligned with the last entry of flash word
218        1/1                    state_d = StPostPack;
           Tests:       T10 T46 T264 
219        1/1                  end else if (req_i) begin
           Tests:       T12 T20 T13 
220        1/1                    ack_o = 1'b1;
           Tests:       T12 T20 T13 
221                             end
                        MISSING_ELSE
222                           end
223                     
224                           StPostPack: begin
225                             // supply filler data
226        1/1                  pack_valid = 1'b1;
           Tests:       T10 T46 T264 
227        1/1                  data_sel = Filler;
           Tests:       T10 T46 T264 
228                     
229                             // finish packing remaining entries
230        1/1                  if (idx == MaxIdx) begin
           Tests:       T10 T46 T264 
231        1/1                    state_d = StCalcPlainEcc;
           Tests:       T10 T46 T264 
232                             end
                        MISSING_ELSE
233                           end
234                     
235                           StCalcPlainEcc: begin
236        1/1                  plain_ecc_en = 1'b1;
           Tests:       T12 T20 T13 
237        1/1                  state_d = scramble_i ? StCalcMask : StReqFlash;
           Tests:       T12 T20 T13 
238                           end
239                     
240                           StCalcMask: begin
241        1/1                  calc_req_o = 1'b1;
           Tests:       T13 T14 T8 
242                     
243        1/1                  if (calc_ack_i) begin
           Tests:       T13 T14 T8 
244        1/1                    state_d = StScrambleData;
           Tests:       T13 T14 T8 
245                             end
                        MISSING_ELSE
246                           end
247                     
248                           StScrambleData: begin
249        1/1                  scramble_req_o = 1'b1;
           Tests:       T13 T14 T8 
250                     
251        1/1                  if (scramble_ack_i) begin
           Tests:       T13 T14 T8 
252        1/1                    state_d = StCalcEcc;
           Tests:       T13 T14 T8 
253                             end
                        MISSING_ELSE
254                           end
255                     
256                           StCalcEcc: begin
257        1/1                  state_d = StReqFlash;
           Tests:       T13 T14 T8 
258                           end
259                     
260                           StReqFlash: begin
261                             // only request flash if data integrity was valid
262        1/1                  req_o = ~data_invalid_q;
           Tests:       T12 T20 T13 
263        1/1                  last_o = last_i;
           Tests:       T12 T20 T13 
264                     
265                             // if this is the last beat of the program burst
266                             //   - wait for done
267                             // if this is NOT the last beat
268                             //   - ack the upstream request and accept more beats
269        1/1                  if (last_i) begin
           Tests:       T12 T20 T13 
270        1/1                    state_d = ack ? StWaitFlash : StReqFlash;
           Tests:       T12 T20 T13 
271                             end else begin
272        1/1                    ack_o = ack;
           Tests:       T12 T14 T8 
273        1/1                    state_d = ack ? StIdle : StReqFlash;
           Tests:       T12 T14 T8 
274                             end
275                           end
276                     
277                           StWaitFlash: begin
278        1/1                  if (done) begin
           Tests:       T12 T20 T13 
279        1/1                    ack_o = 1'b1;
           Tests:       T12 T20 T13 
280        1/1                    state_d = StIdle;
           Tests:       T12 T20 T13 
281                             end
                        MISSING_ELSE
282                           end
283                     
284                           StDisabled: begin
285        1/1                  state_d = StDisabled;
           Tests:       T7 T8 T9 
286                           end
287                     
288                           default: begin
289                             fsm_err_o = 1'b1;
290                           end
291                     
292                         endcase // unique case (state_q)
293                     
294                       end
295                     
296                       logic [DataWidth-1:0] mask_q;
297                     
298                       always_ff @(posedge clk_i or negedge rst_ni) begin
299        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
300        1/1                packed_data <= '0;
           Tests:       T1 T2 T3 
301        1/1                mask_q <= '0;
           Tests:       T1 T2 T3 
302        1/1              end else if (req_o && ack) begin
           Tests:       T1 T2 T3 
303        1/1                packed_data <= '0;
           Tests:       T12 T20 T13 
304        1/1              end else if (calc_req_o && calc_ack_i) begin
           Tests:       T1 T2 T3 
305        1/1                packed_data <= packed_data ^ mask_i;
           Tests:       T13 T14 T8 
306        1/1                mask_q <= mask_i;
           Tests:       T13 T14 T8 
307        1/1              end else if (scramble_req_o && scramble_ack_i) begin
           Tests:       T1 T2 T3 
308        1/1                packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
           Tests:       T13 T14 T8 
309        1/1              end else if (pack_valid) begin
           Tests:       T1 T2 T3 
310        1/1                packed_data[idx] <= pack_data;
           Tests:       T12 T20 T13 
311                         end
                        MISSING_ELSE
312                       end
313                     
314        1/1            assign block_data_o = packed_data;
           Tests:       T1 T2 T3 
315                     
316                       // ECC handling
317                       localparam int PlainDataEccWidth = DataWidth + 8;
318                     
319                       logic [FullDataWidth-1:0] ecc_data;
320                       logic [PlainDataEccWidth-1:0] plain_data_w_ecc;
321                       logic [PlainIntgWidth-1:0] plain_data_ecc;
322                       always_ff @(posedge clk_i or negedge rst_ni) begin
323        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
324        1/1                plain_data_ecc <= '1;
           Tests:       T1 T2 T3 
325        1/1              end else if (plain_ecc_en) begin
           Tests:       T1 T2 T3 
326        1/1                plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
           Tests:       T12 T20 T13 
327                         end
                        MISSING_ELSE
328                       end
329                     
330                       logic [PlainDataWidth-1:0] ecc_data_in;
331        1/1            assign ecc_data_in = {plain_data_ecc, packed_data};
           Tests:       T1 T2 T3 
332                     
333                       // reliability ECC calculation
334                       prim_secded_hamming_76_68_enc u_enc (
335                         .data_i(ecc_data_in),
336                         .data_o(ecc_data)
337                       );
338                     
339                       // integrity ECC calculation
340                       // This instance can technically be merged with the instance above, but is
341                       // kept separate for the sake of convenience
342                       // The plain data ecc is calculated continuously from packed data (which changes
343                       // from packed data to masked/scrambled data based on software configuration).
344                       // The actual plain data ECC is explicitly captured during this process when
345                       // it is required.
346                       prim_secded_hamming_72_64_enc u_plain_enc (
347                         .data_i(packed_data),
348                         .data_o(plain_data_w_ecc)
349                       );
350                     
351                       logic unused_data;
352        1/1            assign unused_data = |plain_data_w_ecc;
           Tests:       T1 T2 T3 
353                     
354                       // pad the remaining bits with '1' if ecc is not used.
355        1/1            assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
           Tests:       T1 T2 T3 
356                     
357                       /////////////////////////////////
358                       // Assertions
359                       /////////////////////////////////
360                     
361                     `ifdef INC_ASSERT
362                       logic txn_done;
363                       logic [15:0] done_cnt_d, done_cnt_q;
364                     
365        1/1            assign txn_done = req_i && ack_o && last_i;
           Tests:       T1 T2 T3 
366        1/1            assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
           Tests:       T1 T2 T3 
367                     
368                       always_ff @(posedge clk_i or negedge rst_ni) begin
369        1/1              if (!rst_ni) begin
           Tests:       T1 T2 T3 
370        1/1                done_cnt_q <= '0;
           Tests:       T1 T2 T3 
371                         end else begin
372        1/1                done_cnt_q <= done_cnt_d;
           Tests:       T1 T2 T3 

---

Cond Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Covered	Percent
Conditions	65	64	98.46
Logical	65	64	98.46
Non-Logical	0	0
Event	0	0

 LINE       111
 EXPRESSION ((data_sel == Actual) ? data_i[(flash_phy_pkg::BusWidth - 1):0] : ({flash_phy_pkg::BusWidth {1'b1}}))
             ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T20,T13

 LINE       111
 SUB-EXPRESSION (data_sel == Actual)
                ----------1---------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T20,T13

 LINE       126
 EXPRESSION (data_invalid_q | (pack_valid & ((~data_intg_ok))))
             -------1------   ----------------2---------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T21,T263
1	0	Covered	T8,T21,T263

 LINE       126
 SUB-EXPRESSION (pack_valid & ((~data_intg_ok)))
                 -----1----   --------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T13
1	1	Covered	T8,T21,T263

 LINE       143
 EXPRESSION (ack_i | data_invalid_q)
             --1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T21,T263
1	0	Covered	T1,T2,T3

 LINE       144
 EXPRESSION (done_i | data_invalid_q)
             ---1--   -------2------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T8,T21,T263
1	0	Covered	T1,T2,T3

 LINE       148
 EXPRESSION ((idx > '0) ? (idx_sub_one == sel_i) : 1'b0)
             -----1----

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T20,T13

 LINE       148
 SUB-EXPRESSION (idx_sub_one == sel_i)
                -----------1----------

-1-	Status	Tests
0	Covered	T12,T20,T13
1	Covered	T46,T264,T31

 LINE       153
 EXPRESSION (pack_valid && (idx == MaxIdx))
             -----1----    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T13
1	0	Covered	T12,T20,T13
1	1	Covered	T12,T20,T13

 LINE       153
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T20,T13

 LINE       194
 EXPRESSION (req_i && ((|sel_i)))
             --1--    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T20,T13
1	1	Covered	T46,T264,T31

 LINE       204
 EXPRESSION (idx == align_next)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T11
1	Covered	T10,T46,T264

 LINE       213
 EXPRESSION (req_i && (idx == MaxIdx))
             --1--    -------2-------

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T13
1	0	Covered	T12,T20,T13
1	1	Covered	T12,T20,T13

 LINE       213
 SUB-EXPRESSION (idx == MaxIdx)
                -------1-------

-1-	Status	Tests
0	Covered	T12,T20,T13
1	Covered	T12,T20,T13

 LINE       216
 EXPRESSION (req_i && last_i)
             --1--    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T12,T20,T13
1	0	Covered	T12,T20,T13
1	1	Covered	T46,T264,T31

 LINE       230
 EXPRESSION (idx == MaxIdx)
            -------1-------

-1-	Status	Tests
0	Covered	T10,T11
1	Covered	T46,T264,T31

 LINE       237
 EXPRESSION (scramble_i ? StCalcMask : StReqFlash)
             -----1----

-1-	Status	Tests
0	Covered	T12,T20,T51
1	Covered	T13,T14,T8

 LINE       270
 EXPRESSION (ack ? StWaitFlash : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T12,T14,T51
1	Covered	T12,T20,T13

 LINE       273
 EXPRESSION (ack ? StIdle : StReqFlash)
             -1-

-1-	Status	Tests
0	Covered	T12,T8,T51
1	Covered	T12,T14,T8

 LINE       302
 EXPRESSION (req_o && ack)
             --1--    -2-

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T12,T14,T8
1	1	Covered	T12,T20,T13

 LINE       304
 EXPRESSION (calc_req_o && calc_ack_i)
             -----1----    -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T8
1	1	Covered	T13,T14,T8

 LINE       307
 EXPRESSION (scramble_req_o && scramble_ack_i)
             -------1------    -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T13,T14,T8
1	1	Covered	T13,T14,T8

 LINE       355
 EXPRESSION (ecc_i ? ecc_data : ({{flash_phy_pkg::EccWidth {1'b1}}, ecc_data_in}))
             --1--

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

 LINE       365
 EXPRESSION (req_i && ack_o && last_i)
             --1--    --2--    ---3--

-1-	-2-	-3-	Status	Tests
0	1	1	Not Covered
1	0	1	Covered	T12,T20,T13
1	1	0	Covered	T12,T20,T13
1	1	1	Covered	T12,T20,T13

 LINE       366
 EXPRESSION (txn_done ? '0 : (done ? ((done_cnt_q + 16'b1)) : done_cnt_q))
             ----1---

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T20,T13

 LINE       366
 SUB-EXPRESSION (done ? ((done_cnt_q + 16'b1)) : done_cnt_q)
                 --1-

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T2,T3

---

FSM Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

Summary for FSM :: state_q

	Total	Covered	Percent
States	11	11	100.00	(Not included in score)
Transitions	15	15	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
StCalcEcc	252	Covered	T13,T14,T8
StCalcMask	237	Covered	T13,T14,T8
StCalcPlainEcc	215	Covered	T12,T20,T13
StDisabled	193	Covered	T7,T8,T9
StIdle	273	Covered	T1,T2,T3
StPackData	197	Covered	T12,T20,T13
StPostPack	218	Covered	T46,T264,T31
StPrePack	195	Covered	T46,T264,T31
StReqFlash	237	Covered	T12,T20,T13
StScrambleData	244	Covered	T13,T14,T8
StWaitFlash	270	Covered	T12,T20,T13

transitions	Line No.	Covered	Tests
StCalcEcc->StReqFlash	257	Covered	T13,T14,T8
StCalcMask->StScrambleData	244	Covered	T13,T14,T8
StCalcPlainEcc->StCalcMask	237	Covered	T13,T14,T8
StCalcPlainEcc->StReqFlash	237	Covered	T12,T20,T51
StIdle->StDisabled	193	Covered	T7,T8,T9
StIdle->StPackData	197	Covered	T12,T20,T13
StIdle->StPrePack	195	Covered	T46,T264,T31
StPackData->StCalcPlainEcc	215	Covered	T12,T20,T13
StPackData->StPostPack	218	Covered	T46,T264,T31
StPostPack->StCalcPlainEcc	231	Covered	T46,T264,T31
StPrePack->StPackData	205	Covered	T46,T264,T31
StReqFlash->StIdle	273	Covered	T12,T14,T8
StReqFlash->StWaitFlash	270	Covered	T12,T20,T13
StScrambleData->StCalcEcc	252	Covered	T13,T14,T8
StWaitFlash->StIdle	280	Covered	T12,T20,T13

---

Branch Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Line No.	Total	Covered	Percent
Branches		55	55	100.00
TERNARY	111	2	2	100.00
TERNARY	148	2	2	100.00
TERNARY	355	2	2	100.00
TERNARY	366	3	3	100.00
IF	130	2	2	100.00
IF	151	4	4	100.00
IF	164	2	2	100.00
CASE	186	27	27	100.00
IF	299	6	6	100.00
IF	323	3	3	100.00
IF	369	2	2	100.00

111          assign pack_data  = (data_sel == Actual) ? data_i[BusWidth-1:0] : {BusWidth{1'b1}};
                                                      -1-  
                                                      ==>  
                                                      ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T20,T13
0	Covered	T1,T2,T3

148          assign align_next = (idx > '0) ? (idx_sub_one == sel_i) : 1'b0;
                                            -1-  
                                            ==>  
                                            ==>  

Branches:

-1-	Status	Tests
1	Covered	T12,T20,T13
0	Covered	T1,T2,T3

355          assign data_o = ecc_i ? ecc_data : {{EccWidth{1'b1}}, ecc_data_in};
                                   -1-  
                                   ==>  
                                   ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

366          assign done_cnt_d = txn_done ? '0 : (done ? done_cnt_q + 16'h1 : done_cnt_q);
                                          -1-          -2-   
                                          ==>          ==>   
                                                       ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T12,T20,T13
0	1	Covered	T1,T2,T3
0	0	Covered	T1,T2,T3

130            if (!rst_ni) begin
               -1-  
131              data_invalid_q <= '0;
                 ==>
132            end else begin
133              data_invalid_q <= data_invalid_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

151            if (!rst_ni) begin
               -1-  
152              idx <= '0;
                 ==>
153            end else if (pack_valid && idx == MaxIdx) begin
                        -2-  
154              // when a flash word is packed full, return index to 0
155              idx <= '0;
                 ==>
156            end else if (pack_valid) begin
                        -3-  
157              // increment otherwise
158              idx <= idx + 1'b1;
                 ==>
159            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T12,T20,T13
0	0	1	Covered	T12,T20,T13
0	0	0	Covered	T1,T2,T3

164          `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, state_e, StIdle)
             -1-                                                                      
             ==>                                                                      
             ==>                                                                      

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

186            unique case (state_q)
                      -1-  
187              StIdle: begin
188                // if first beat of a transaction is not aligned, prepack with empty bits
189                if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin
                   -2-  
190                  // only disable during idle state to ensure program is able to gracefully complete
191                  // this is important as we do not want to accidentally disturb any electrical procedure
192                  // internal to the flash macro
193                  state_d = StDisabled;
                     ==>
194                end else if (req_i && |sel_i) begin
                            -3-  
195                  state_d = StPrePack;
                     ==>
196                end else if (req_i) begin
                            -4-  
197                  state_d = StPackData;
                     ==>
198                end
                   MISSING_ELSE
                   ==>
199              end
200        
201              StPrePack: begin
202                // pack until currently supplied data
203                pack_valid = (idx < sel_i);
204                if (idx == align_next) begin
                   -5-  
205                  state_d = StPackData;
                     ==>
206                end
                   MISSING_ELSE
                   ==>
207              end
208        
209              StPackData: begin
210                pack_valid = req_i;
211                data_sel = Actual;
212        
213                if (req_i && idx == MaxIdx) begin
                   -6-  
214                  // last beat of a flash word
215                  state_d = StCalcPlainEcc;
                     ==>
216                end else if (req_i && last_i) begin
                            -7-  
217                  // last beat is not aligned with the last entry of flash word
218                  state_d = StPostPack;
                     ==>
219                end else if (req_i) begin
                            -8-  
220                  ack_o = 1'b1;
                     ==>
221                end
                   MISSING_ELSE
                   ==>
222              end
223        
224              StPostPack: begin
225                // supply filler data
226                pack_valid = 1'b1;
227                data_sel = Filler;
228        
229                // finish packing remaining entries
230                if (idx == MaxIdx) begin
                   -9-  
231                  state_d = StCalcPlainEcc;
                     ==>
232                end
                   MISSING_ELSE
                   ==>
233              end
234        
235              StCalcPlainEcc: begin
236                plain_ecc_en = 1'b1;
237                state_d = scramble_i ? StCalcMask : StReqFlash;
                                        -10-  
                                        ==>  
                                        ==>  
238              end
239        
240              StCalcMask: begin
241                calc_req_o = 1'b1;
242        
243                if (calc_ack_i) begin
                   -11-  
244                  state_d = StScrambleData;
                     ==>
245                end
                   MISSING_ELSE
                   ==>
246              end
247        
248              StScrambleData: begin
249                scramble_req_o = 1'b1;
250        
251                if (scramble_ack_i) begin
                   -12-  
252                  state_d = StCalcEcc;
                     ==>
253                end
                   MISSING_ELSE
                   ==>
254              end
255        
256              StCalcEcc: begin
257                state_d = StReqFlash;
                   ==>
258              end
259        
260              StReqFlash: begin
261                // only request flash if data integrity was valid
262                req_o = ~data_invalid_q;
263                last_o = last_i;
264        
265                // if this is the last beat of the program burst
266                //   - wait for done
267                // if this is NOT the last beat
268                //   - ack the upstream request and accept more beats
269                if (last_i) begin
                   -13-  
270                  state_d = ack ? StWaitFlash : StReqFlash;
                                   -14-  
                                   ==>  
                                   ==>  
271                end else begin
272                  ack_o = ack;
273                  state_d = ack ? StIdle : StReqFlash;
                                   -15-  
                                   ==>  
                                   ==>  
274                end
275              end
276        
277              StWaitFlash: begin
278                if (done) begin
                   -16-  
279                  ack_o = 1'b1;
                     ==>
280                  state_d = StIdle;
281                end
                   MISSING_ELSE
                   ==>
282              end
283        
284              StDisabled: begin
285                state_d = StDisabled;
                   ==>
286              end
287        
288              default: begin
289                fsm_err_o = 1'b1;
                   ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	-15-	-16-	Status	Tests
StIdle	1	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
StIdle	0	1	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T46,T264
StIdle	0	0	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T12,T20,T13
StIdle	0	0	0	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
StPrePack	-	-	-	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T46,T264
StPrePack	-	-	-	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11
StPackData	-	-	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T20,T13
StPackData	-	-	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T46,T264
StPackData	-	-	-	-	0	0	1	-	-	-	-	-	-	-	-	Covered	T12,T20,T13
StPackData	-	-	-	-	0	0	0	-	-	-	-	-	-	-	-	Covered	T12,T20,T13
StPostPack	-	-	-	-	-	-	-	1	-	-	-	-	-	-	-	Covered	T10,T46,T264
StPostPack	-	-	-	-	-	-	-	0	-	-	-	-	-	-	-	Covered	T10,T11
StCalcPlainEcc	-	-	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T13,T14,T8
StCalcPlainEcc	-	-	-	-	-	-	-	-	0	-	-	-	-	-	-	Covered	T12,T20,T51
StCalcMask	-	-	-	-	-	-	-	-	-	1	-	-	-	-	-	Covered	T13,T14,T8
StCalcMask	-	-	-	-	-	-	-	-	-	0	-	-	-	-	-	Covered	T13,T14,T8
StScrambleData	-	-	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T13,T14,T8
StScrambleData	-	-	-	-	-	-	-	-	-	-	0	-	-	-	-	Covered	T13,T14,T8
StCalcEcc	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T13,T14,T8
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	1	-	-	Covered	T12,T20,T13
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	1	0	-	-	Covered	T12,T14,T51
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	1	-	Covered	T12,T14,T8
StReqFlash	-	-	-	-	-	-	-	-	-	-	-	0	-	0	-	Covered	T12,T8,T51
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T20,T13
StWaitFlash	-	-	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T12,T20,T13
StDisabled	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T11,T16

299            if (!rst_ni) begin
               -1-  
300              packed_data <= '0;
                 ==>
301              mask_q <= '0;
302            end else if (req_o && ack) begin
                        -2-  
303              packed_data <= '0;
                 ==>
304            end else if (calc_req_o && calc_ack_i) begin
                        -3-  
305              packed_data <= packed_data ^ mask_i;
                 ==>
306              mask_q <= mask_i;
307            end else if (scramble_req_o && scramble_ack_i) begin
                        -4-  
308              packed_data <= scrambled_data_i[DataWidth-1:0] ^ mask_q;
                 ==>
309            end else if (pack_valid) begin
                        -5-  
310              packed_data[idx] <= pack_data;
                 ==>
311            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	-3-	-4-	-5-	Status	Tests
1	-	-	-	-	Covered	T1,T2,T3
0	1	-	-	-	Covered	T12,T20,T13
0	0	1	-	-	Covered	T13,T14,T8
0	0	0	1	-	Covered	T13,T14,T8
0	0	0	0	1	Covered	T12,T20,T13
0	0	0	0	0	Covered	T1,T2,T3

323            if (!rst_ni) begin
               -1-  
324              plain_data_ecc <= '1;
                 ==>
325            end else if (plain_ecc_en) begin
                        -2-  
326              plain_data_ecc <= plain_data_w_ecc[DataWidth +: PlainIntgWidth];
                 ==>
327            end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T12,T20,T13
0	0	Covered	T1,T2,T3

369            if (!rst_ni) begin
               -1-  
370              done_cnt_q <= '0;
                 ==>
371            end else begin
372              done_cnt_q <= done_cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.u_eflash.gen_flash_cores[0].u_core.gen_prog_data.u_prog

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
OneDonePerTxn_A	388255766	1226829	0	0
PostPackRule_A	388255766	893	0	0
PrePackRule_A	388255766	609	0	0
WidthCheck_A	1057	1057	0	0
u_state_regs_A	388255766	387415641	0	0

OneDonePerTxn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	1226829	0	0
T4	890	0	0	0
T7	972	0	0	0
T8	4134	0	0	0
T9	976	0	0	0
T12	2002	1	0	0
T13	2705	1	0	0
T14	144394	108	0	0
T15	29510	6	0	0
T20	1473	1	0	0
T23	7299	0	0	0
T27	0	562	0	0
T39	0	159	0	0
T51	0	46	0	0
T64	0	1	0	0
T98	0	180	0	0

PostPackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	893	0	0
T24	1472	0	0	0
T25	0	2	0	0
T30	185826	0	0	0
T31	0	7	0	0
T41	55208	0	0	0
T46	82609	12	0	0
T47	55952	0	0	0
T55	53090	0	0	0
T75	0	2	0	0
T80	2117	0	0	0
T92	0	18	0	0
T93	0	17	0	0
T109	2660	0	0	0
T150	0	3	0	0
T231	0	3	0	0
T251	1902	0	0	0
T264	1801	1	0	0
T265	0	1	0	0

PrePackRule_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	609	0	0
T24	1472	0	0	0
T25	0	1	0	0
T30	185826	0	0	0
T31	0	7	0	0
T41	55208	0	0	0
T46	82609	12	0	0
T47	55952	0	0	0
T55	53090	0	0	0
T75	0	2	0	0
T80	2117	0	0	0
T92	0	16	0	0
T93	0	11	0	0
T109	2660	0	0	0
T150	0	3	0	0
T231	0	2	0	0
T251	1902	0	0	0
T264	1801	1	0	0
T265	0	1	0	0

WidthCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1057	1057	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T7	1	1	0	0
T12	1	1	0	0
T17	1	1	0	0
T18	1	1	0	0
T19	1	1	0	0
T20	1	1	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	388255766	387415641	0	0
T1	3906	3853	0	0
T2	10848	10778	0	0
T3	1224	1167	0	0
T4	890	840	0	0
T7	972	922	0	0
T12	2002	1944	0	0
T17	1544	1489	0	0
T18	1950	1866	0	0
T19	2303	2211	0	0
T20	1473	1338	0	0