Unified Coverage Report :: Module :: flash_ctrl_core_reg

Module : flash_ctrl_core_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.88	100.00	99.51			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_28/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_reg_0.1/rtl/flash_ctrl_core_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_reg_core	99.88	100.00	99.51			100.00	100.00

Module Instance : tb.dut.u_reg_core

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.88	100.00	99.51			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.31	99.00	98.62	100.00		98.92	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.69	97.12	93.60	98.44		100.00	84.29	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_addr	100.00	100.00	100.00			100.00
u_alert_test_fatal_err	100.00	100.00
u_alert_test_fatal_prim_flash_alert	100.00	100.00
u_alert_test_fatal_std_err	100.00	100.00
u_alert_test_recov_err	100.00	100.00
u_alert_test_recov_prim_flash_alert	100.00	100.00
u_bank0_info0_page_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_ecc_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_erase_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_he_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_prog_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_rd_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_2_scramble_en_2	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_ecc_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_erase_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_he_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_prog_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_rd_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_3_scramble_en_3	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_ecc_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_erase_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_he_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_prog_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_rd_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_4_scramble_en_4	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_ecc_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_erase_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_he_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_prog_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_rd_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_5_scramble_en_5	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_ecc_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_erase_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_he_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_prog_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_rd_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_6_scramble_en_6	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_ecc_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_erase_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_he_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_prog_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_rd_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_7_scramble_en_7	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_ecc_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_erase_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_he_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_prog_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_rd_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_8_scramble_en_8	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_ecc_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_erase_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_he_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_prog_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_rd_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_page_cfg_9_scramble_en_9	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_0	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_1	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_2	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_3	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_4	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_5	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_6	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_7	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_8	100.00	100.00	100.00			100.00
u_bank0_info0_regwen_9	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_ecc_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_erase_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_he_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_prog_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_rd_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_page_cfg_scramble_en_0	100.00	100.00	100.00			100.00
u_bank0_info1_regwen	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_page_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_bank0_info2_regwen_0	100.00	100.00	100.00			100.00
u_bank0_info2_regwen_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_ecc_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_erase_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_he_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_prog_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_rd_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_2_scramble_en_2	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_ecc_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_erase_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_he_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_prog_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_rd_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_3_scramble_en_3	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_ecc_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_erase_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_he_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_prog_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_rd_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_4_scramble_en_4	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_ecc_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_erase_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_he_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_prog_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_rd_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_5_scramble_en_5	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_ecc_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_erase_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_he_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_prog_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_rd_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_6_scramble_en_6	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_ecc_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_erase_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_he_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_prog_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_rd_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_7_scramble_en_7	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_ecc_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_erase_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_he_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_prog_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_rd_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_8_scramble_en_8	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_ecc_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_erase_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_he_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_prog_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_rd_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_page_cfg_9_scramble_en_9	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_0	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_1	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_2	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_3	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_4	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_5	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_6	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_7	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_8	100.00	100.00	100.00			100.00
u_bank1_info0_regwen_9	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_ecc_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_erase_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_he_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_prog_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_rd_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_page_cfg_scramble_en_0	100.00	100.00	100.00			100.00
u_bank1_info1_regwen	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_page_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_bank1_info2_regwen_0	100.00	100.00	100.00			100.00
u_bank1_info2_regwen_1	100.00	100.00	100.00			100.00
u_bank_cfg_regwen	100.00	100.00	100.00			100.00
u_chk	100.00	100.00		100.00			100.00
u_control_erase_sel	100.00	100.00	100.00			100.00
u_control_info_sel	100.00	100.00	100.00			100.00
u_control_num	100.00	100.00	100.00			100.00
u_control_op	100.00	100.00	100.00			100.00
u_control_partition_sel	100.00	100.00	100.00			100.00
u_control_prog_sel	100.00	100.00	100.00			100.00
u_control_start	100.00	100.00	100.00			100.00
u_ctrl_regwen	100.00	100.00
u_curr_fifo_lvl_prog	100.00	100.00
u_curr_fifo_lvl_rd	100.00	100.00
u_debug_state	100.00	100.00
u_default_region_ecc_en	100.00	100.00	100.00			100.00
u_default_region_erase_en	100.00	100.00	100.00			100.00
u_default_region_he_en	100.00	100.00	100.00			100.00
u_default_region_prog_en	100.00	100.00	100.00			100.00
u_default_region_rd_en	100.00	100.00	100.00			100.00
u_default_region_scramble_en	100.00	100.00	100.00			100.00
u_dis	100.00	100.00	100.00			100.00
u_ecc_single_err_addr_0	100.00	100.00	100.00			100.00
u_ecc_single_err_addr_1	100.00	100.00	100.00			100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_0	100.00	100.00	100.00			100.00
u_ecc_single_err_cnt_ecc_single_err_cnt_1	100.00	100.00	100.00			100.00
u_erase_suspend	100.00	100.00	100.00			100.00
u_err_addr	100.00	100.00	100.00			100.00
u_err_code_macro_err	88.89	100.00	66.67			100.00
u_err_code_mp_err	100.00	100.00	100.00			100.00
u_err_code_op_err	100.00	100.00	100.00			100.00
u_err_code_prog_err	100.00	100.00	100.00			100.00
u_err_code_prog_type_err	100.00	100.00	100.00			100.00
u_err_code_prog_win_err	100.00	100.00	100.00			100.00
u_err_code_rd_err	100.00	100.00	100.00			100.00
u_err_code_update_err	88.89	100.00	66.67			100.00
u_exec	100.00	100.00	100.00			100.00
u_fault_status_arb_err	96.30	88.89	100.00			100.00
u_fault_status_host_gnt_err	96.30	88.89	100.00			100.00
u_fault_status_mp_err	96.30	88.89	100.00			100.00
u_fault_status_op_err	96.30	88.89	100.00			100.00
u_fault_status_phy_relbl_err	97.22	100.00	91.67			100.00
u_fault_status_phy_storage_err	97.22	100.00	91.67			100.00
u_fault_status_prog_err	96.30	88.89	100.00			100.00
u_fault_status_prog_type_err	96.30	88.89	100.00			100.00
u_fault_status_prog_win_err	96.30	88.89	100.00			100.00
u_fault_status_rd_err	96.30	88.89	100.00			100.00
u_fault_status_seed_err	96.30	88.89	100.00			100.00
u_fault_status_spurious_ack	96.30	88.89	100.00			100.00
u_fifo_lvl_prog	100.00	100.00	100.00			100.00
u_fifo_lvl_rd	100.00	100.00	100.00			100.00
u_fifo_rst	100.00	100.00	100.00			100.00
u_hw_info_cfg_override_ecc_dis	100.00	100.00	100.00			100.00
u_hw_info_cfg_override_scramble_dis	100.00	100.00	100.00			100.00
u_init	100.00	100.00	100.00			100.00
u_intr_enable_corr_err	100.00	100.00	100.00			100.00
u_intr_enable_op_done	100.00	100.00	100.00			100.00
u_intr_enable_prog_empty	100.00	100.00	100.00			100.00
u_intr_enable_prog_lvl	100.00	100.00	100.00			100.00
u_intr_enable_rd_full	100.00	100.00	100.00			100.00
u_intr_enable_rd_lvl	100.00	100.00	100.00			100.00
u_intr_state_corr_err	100.00	100.00	100.00			100.00
u_intr_state_op_done	100.00	100.00	100.00			100.00
u_intr_state_prog_empty	62.59	77.78	50.00			60.00
u_intr_state_prog_lvl	62.59	77.78	50.00			60.00
u_intr_state_rd_full	62.59	77.78	50.00			60.00
u_intr_state_rd_lvl	62.59	77.78	50.00			60.00
u_intr_test_corr_err	100.00	100.00
u_intr_test_op_done	100.00	100.00
u_intr_test_prog_empty	100.00	100.00
u_intr_test_prog_lvl	100.00	100.00
u_intr_test_rd_full	100.00	100.00
u_intr_test_rd_lvl	100.00	100.00
u_mp_bank_cfg_shadowed_erase_en_0	96.88	100.00	87.50			100.00	100.00
u_mp_bank_cfg_shadowed_erase_en_1	96.88	100.00	87.50			100.00	100.00
u_mp_region_0_base_0	100.00	100.00	100.00			100.00
u_mp_region_0_size_0	100.00	100.00	100.00			100.00
u_mp_region_1_base_1	100.00	100.00	100.00			100.00
u_mp_region_1_size_1	100.00	100.00	100.00			100.00
u_mp_region_2_base_2	100.00	100.00	100.00			100.00
u_mp_region_2_size_2	100.00	100.00	100.00			100.00
u_mp_region_3_base_3	100.00	100.00	100.00			100.00
u_mp_region_3_size_3	100.00	100.00	100.00			100.00
u_mp_region_4_base_4	100.00	100.00	100.00			100.00
u_mp_region_4_size_4	100.00	100.00	100.00			100.00
u_mp_region_5_base_5	100.00	100.00	100.00			100.00
u_mp_region_5_size_5	100.00	100.00	100.00			100.00
u_mp_region_6_base_6	100.00	100.00	100.00			100.00
u_mp_region_6_size_6	100.00	100.00	100.00			100.00
u_mp_region_7_base_7	100.00	100.00	100.00			100.00
u_mp_region_7_size_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_ecc_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_erase_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_he_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_prog_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_rd_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_0_scramble_en_0	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_ecc_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_erase_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_he_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_prog_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_rd_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_1_scramble_en_1	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_ecc_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_erase_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_he_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_prog_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_rd_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_2_scramble_en_2	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_ecc_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_erase_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_he_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_prog_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_rd_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_3_scramble_en_3	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_ecc_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_erase_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_he_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_prog_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_rd_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_4_scramble_en_4	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_ecc_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_erase_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_he_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_prog_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_rd_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_5_scramble_en_5	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_ecc_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_erase_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_he_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_prog_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_rd_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_6_scramble_en_6	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_ecc_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_erase_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_he_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_prog_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_rd_en_7	100.00	100.00	100.00			100.00
u_mp_region_cfg_7_scramble_en_7	100.00	100.00	100.00			100.00
u_op_status_done	100.00	100.00	100.00			100.00
u_op_status_err	100.00	100.00	100.00			100.00
u_phy_alert_cfg_alert_ack	65.34	88.89	50.00			57.14
u_phy_alert_cfg_alert_trig	65.34	88.89	50.00			57.14
u_phy_status_init_wip	62.59	77.78	50.00			60.00
u_phy_status_prog_normal_avail	58.89	66.67	50.00			60.00
u_phy_status_prog_repair_avail	58.89	66.67	50.00			60.00
u_prim_reg_we_check	100.00	100.00		100.00
u_prog_type_en_normal	100.00	100.00	100.00			100.00
u_prog_type_en_repair	100.00	100.00	100.00			100.00
u_reg_if	98.49	98.72	95.24			100.00	100.00
u_region_cfg_regwen_0	100.00	100.00	100.00			100.00
u_region_cfg_regwen_1	100.00	100.00	100.00			100.00
u_region_cfg_regwen_2	100.00	100.00	100.00			100.00
u_region_cfg_regwen_3	100.00	100.00	100.00			100.00
u_region_cfg_regwen_4	100.00	100.00	100.00			100.00
u_region_cfg_regwen_5	100.00	100.00	100.00			100.00
u_region_cfg_regwen_6	100.00	100.00	100.00			100.00
u_region_cfg_regwen_7	100.00	100.00	100.00			100.00
u_rsp_intg_gen	100.00	100.00					100.00
u_scratch	100.00	100.00	100.00			100.00
u_socket	94.37	96.05	89.53			91.89	100.00
u_status_init_wip	62.59	77.78	50.00			60.00
u_status_initialized	62.59	77.78	50.00			60.00
u_status_prog_empty	100.00	100.00	100.00			100.00
u_status_prog_full	100.00	100.00	100.00			100.00
u_status_rd_empty	100.00	100.00	100.00			100.00
u_status_rd_full	100.00	100.00	100.00			100.00
u_std_fault_status_arb_fsm_err	96.30	88.89	100.00			100.00
u_std_fault_status_ctrl_cnt_err	96.30	88.89	100.00			100.00
u_std_fault_status_fifo_err	96.30	88.89	100.00			100.00
u_std_fault_status_lcmgr_err	96.30	88.89	100.00			100.00
u_std_fault_status_lcmgr_intg_err	96.30	88.89	100.00			100.00
u_std_fault_status_phy_fsm_err	96.30	88.89	100.00			100.00
u_std_fault_status_prog_intg_err	96.30	88.89	100.00			100.00
u_std_fault_status_reg_intg_err	96.30	88.89	100.00			100.00
u_std_fault_status_storage_err	62.59	77.78	50.00			60.00

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
TOTAL		1155	1155	100.00
ALWAYS	77	4	4	100.00
CONT_ASSIGN	86	1	1	100.00
CONT_ASSIGN	104	1	1	100.00
CONT_ASSIGN	105	1	1	100.00
CONT_ASSIGN	107	1	1	100.00
CONT_ASSIGN	108	1	1	100.00
CONT_ASSIGN	109	1	1	100.00
CONT_ASSIGN	110	1	1	100.00
ALWAYS	136	3	3	100.00
CONT_ASSIGN	174	1	1	100.00
CONT_ASSIGN	175	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1367	1	1	100.00
CONT_ASSIGN	1383	1	1	100.00
CONT_ASSIGN	1399	1	1	100.00
CONT_ASSIGN	1415	1	1	100.00
CONT_ASSIGN	1431	1	1	100.00
CONT_ASSIGN	1447	1	1	100.00
CONT_ASSIGN	1453	1	1	100.00
CONT_ASSIGN	1468	1	1	100.00
CONT_ASSIGN	1484	1	1	100.00
CONT_ASSIGN	1500	1	1	100.00
CONT_ASSIGN	1516	1	1	100.00
CONT_ASSIGN	1532	1	1	100.00
CONT_ASSIGN	1638	1	1	100.00
CONT_ASSIGN	1832	1	1	100.00
CONT_ASSIGN	1863	1	1	100.00
CONT_ASSIGN	2183	1	1	100.00
CONT_ASSIGN	2378	1	1	100.00
CONT_ASSIGN	2573	1	1	100.00
CONT_ASSIGN	2768	1	1	100.00
CONT_ASSIGN	2963	1	1	100.00
CONT_ASSIGN	3158	1	1	100.00
CONT_ASSIGN	3353	1	1	100.00
CONT_ASSIGN	3548	1	1	100.00
CONT_ASSIGN	3743	1	1	100.00
CONT_ASSIGN	3803	1	1	100.00
CONT_ASSIGN	3863	1	1	100.00
CONT_ASSIGN	3923	1	1	100.00
CONT_ASSIGN	3983	1	1	100.00
CONT_ASSIGN	4043	1	1	100.00
CONT_ASSIGN	4103	1	1	100.00
CONT_ASSIGN	4163	1	1	100.00
CONT_ASSIGN	4677	1	1	100.00
CONT_ASSIGN	4872	1	1	100.00
CONT_ASSIGN	5067	1	1	100.00
CONT_ASSIGN	5262	1	1	100.00
CONT_ASSIGN	5457	1	1	100.00
CONT_ASSIGN	5652	1	1	100.00
CONT_ASSIGN	5847	1	1	100.00
CONT_ASSIGN	6042	1	1	100.00
CONT_ASSIGN	6237	1	1	100.00
CONT_ASSIGN	6432	1	1	100.00
CONT_ASSIGN	6656	1	1	100.00
CONT_ASSIGN	6909	1	1	100.00
CONT_ASSIGN	7104	1	1	100.00
CONT_ASSIGN	7589	1	1	100.00
CONT_ASSIGN	7784	1	1	100.00
CONT_ASSIGN	7979	1	1	100.00
CONT_ASSIGN	8174	1	1	100.00
CONT_ASSIGN	8369	1	1	100.00
CONT_ASSIGN	8564	1	1	100.00
CONT_ASSIGN	8759	1	1	100.00
CONT_ASSIGN	8954	1	1	100.00
CONT_ASSIGN	9149	1	1	100.00
CONT_ASSIGN	9344	1	1	100.00
CONT_ASSIGN	9568	1	1	100.00
CONT_ASSIGN	9821	1	1	100.00
CONT_ASSIGN	10016	1	1	100.00
CONT_ASSIGN	10295	1	1	100.00
ALWAYS	11823	109	109	100.00
CONT_ASSIGN	11934	1	1	100.00
ALWAYS	11938	1	1	100.00
CONT_ASSIGN	12050	1	1	100.00
CONT_ASSIGN	12052	1	1	100.00
CONT_ASSIGN	12054	1	1	100.00
CONT_ASSIGN	12055	1	1	100.00
CONT_ASSIGN	12057	1	1	100.00
CONT_ASSIGN	12059	1	1	100.00
CONT_ASSIGN	12061	1	1	100.00
CONT_ASSIGN	12063	1	1	100.00
CONT_ASSIGN	12065	1	1	100.00
CONT_ASSIGN	12067	1	1	100.00
CONT_ASSIGN	12068	1	1	100.00
CONT_ASSIGN	12070	1	1	100.00
CONT_ASSIGN	12072	1	1	100.00
CONT_ASSIGN	12074	1	1	100.00
CONT_ASSIGN	12076	1	1	100.00
CONT_ASSIGN	12078	1	1	100.00
CONT_ASSIGN	12080	1	1	100.00
CONT_ASSIGN	12081	1	1	100.00
CONT_ASSIGN	12083	1	1	100.00
CONT_ASSIGN	12085	1	1	100.00
CONT_ASSIGN	12087	1	1	100.00
CONT_ASSIGN	12089	1	1	100.00
CONT_ASSIGN	12091	1	1	100.00
CONT_ASSIGN	12092	1	1	100.00
CONT_ASSIGN	12094	1	1	100.00
CONT_ASSIGN	12095	1	1	100.00
CONT_ASSIGN	12097	1	1	100.00
CONT_ASSIGN	12098	1	1	100.00
CONT_ASSIGN	12100	1	1	100.00
CONT_ASSIGN	12101	1	1	100.00
CONT_ASSIGN	12102	1	1	100.00
CONT_ASSIGN	12104	1	1	100.00
CONT_ASSIGN	12106	1	1	100.00
CONT_ASSIGN	12108	1	1	100.00
CONT_ASSIGN	12110	1	1	100.00
CONT_ASSIGN	12112	1	1	100.00
CONT_ASSIGN	12114	1	1	100.00
CONT_ASSIGN	12116	1	1	100.00
CONT_ASSIGN	12117	1	1	100.00
CONT_ASSIGN	12119	1	1	100.00
CONT_ASSIGN	12120	1	1	100.00
CONT_ASSIGN	12122	1	1	100.00
CONT_ASSIGN	12124	1	1	100.00
CONT_ASSIGN	12125	1	1	100.00
CONT_ASSIGN	12127	1	1	100.00
CONT_ASSIGN	12128	1	1	100.00
CONT_ASSIGN	12130	1	1	100.00
CONT_ASSIGN	12131	1	1	100.00
CONT_ASSIGN	12133	1	1	100.00
CONT_ASSIGN	12134	1	1	100.00
CONT_ASSIGN	12136	1	1	100.00
CONT_ASSIGN	12137	1	1	100.00
CONT_ASSIGN	12139	1	1	100.00
CONT_ASSIGN	12140	1	1	100.00
CONT_ASSIGN	12142	1	1	100.00
CONT_ASSIGN	12143	1	1	100.00
CONT_ASSIGN	12145	1	1	100.00
CONT_ASSIGN	12146	1	1	100.00
CONT_ASSIGN	12148	1	1	100.00
CONT_ASSIGN	12149	1	1	100.00
CONT_ASSIGN	12151	1	1	100.00
CONT_ASSIGN	12152	1	1	100.00
CONT_ASSIGN	12154	1	1	100.00
CONT_ASSIGN	12156	1	1	100.00
CONT_ASSIGN	12158	1	1	100.00
CONT_ASSIGN	12160	1	1	100.00
CONT_ASSIGN	12162	1	1	100.00
CONT_ASSIGN	12164	1	1	100.00
CONT_ASSIGN	12166	1	1	100.00
CONT_ASSIGN	12167	1	1	100.00
CONT_ASSIGN	12169	1	1	100.00
CONT_ASSIGN	12171	1	1	100.00
CONT_ASSIGN	12173	1	1	100.00
CONT_ASSIGN	12175	1	1	100.00
CONT_ASSIGN	12177	1	1	100.00
CONT_ASSIGN	12179	1	1	100.00
CONT_ASSIGN	12181	1	1	100.00
CONT_ASSIGN	12182	1	1	100.00
CONT_ASSIGN	12184	1	1	100.00
CONT_ASSIGN	12186	1	1	100.00
CONT_ASSIGN	12188	1	1	100.00
CONT_ASSIGN	12190	1	1	100.00
CONT_ASSIGN	12192	1	1	100.00
CONT_ASSIGN	12194	1	1	100.00
CONT_ASSIGN	12196	1	1	100.00
CONT_ASSIGN	12197	1	1	100.00
CONT_ASSIGN	12199	1	1	100.00
CONT_ASSIGN	12201	1	1	100.00
CONT_ASSIGN	12203	1	1	100.00
CONT_ASSIGN	12205	1	1	100.00
CONT_ASSIGN	12207	1	1	100.00
CONT_ASSIGN	12209	1	1	100.00
CONT_ASSIGN	12211	1	1	100.00
CONT_ASSIGN	12212	1	1	100.00
CONT_ASSIGN	12214	1	1	100.00
CONT_ASSIGN	12216	1	1	100.00
CONT_ASSIGN	12218	1	1	100.00
CONT_ASSIGN	12220	1	1	100.00
CONT_ASSIGN	12222	1	1	100.00
CONT_ASSIGN	12224	1	1	100.00
CONT_ASSIGN	12226	1	1	100.00
CONT_ASSIGN	12227	1	1	100.00
CONT_ASSIGN	12229	1	1	100.00
CONT_ASSIGN	12231	1	1	100.00
CONT_ASSIGN	12233	1	1	100.00
CONT_ASSIGN	12235	1	1	100.00
CONT_ASSIGN	12237	1	1	100.00
CONT_ASSIGN	12239	1	1	100.00
CONT_ASSIGN	12241	1	1	100.00
CONT_ASSIGN	12242	1	1	100.00
CONT_ASSIGN	12244	1	1	100.00
CONT_ASSIGN	12246	1	1	100.00
CONT_ASSIGN	12248	1	1	100.00
CONT_ASSIGN	12250	1	1	100.00
CONT_ASSIGN	12252	1	1	100.00
CONT_ASSIGN	12254	1	1	100.00
CONT_ASSIGN	12256	1	1	100.00
CONT_ASSIGN	12257	1	1	100.00
CONT_ASSIGN	12259	1	1	100.00
CONT_ASSIGN	12261	1	1	100.00
CONT_ASSIGN	12263	1	1	100.00
CONT_ASSIGN	12265	1	1	100.00
CONT_ASSIGN	12267	1	1	100.00
CONT_ASSIGN	12269	1	1	100.00
CONT_ASSIGN	12271	1	1	100.00
CONT_ASSIGN	12272	1	1	100.00
CONT_ASSIGN	12274	1	1	100.00
CONT_ASSIGN	12276	1	1	100.00
CONT_ASSIGN	12277	1	1	100.00
CONT_ASSIGN	12279	1	1	100.00
CONT_ASSIGN	12281	1	1	100.00
CONT_ASSIGN	12282	1	1	100.00
CONT_ASSIGN	12284	1	1	100.00
CONT_ASSIGN	12286	1	1	100.00
CONT_ASSIGN	12287	1	1	100.00
CONT_ASSIGN	12289	1	1	100.00
CONT_ASSIGN	12291	1	1	100.00
CONT_ASSIGN	12292	1	1	100.00
CONT_ASSIGN	12294	1	1	100.00
CONT_ASSIGN	12296	1	1	100.00
CONT_ASSIGN	12297	1	1	100.00
CONT_ASSIGN	12299	1	1	100.00
CONT_ASSIGN	12301	1	1	100.00
CONT_ASSIGN	12302	1	1	100.00
CONT_ASSIGN	12304	1	1	100.00
CONT_ASSIGN	12306	1	1	100.00
CONT_ASSIGN	12307	1	1	100.00
CONT_ASSIGN	12309	1	1	100.00
CONT_ASSIGN	12311	1	1	100.00
CONT_ASSIGN	12312	1	1	100.00
CONT_ASSIGN	12314	1	1	100.00
CONT_ASSIGN	12316	1	1	100.00
CONT_ASSIGN	12318	1	1	100.00
CONT_ASSIGN	12320	1	1	100.00
CONT_ASSIGN	12322	1	1	100.00
CONT_ASSIGN	12324	1	1	100.00
CONT_ASSIGN	12325	1	1	100.00
CONT_ASSIGN	12327	1	1	100.00
CONT_ASSIGN	12328	1	1	100.00
CONT_ASSIGN	12330	1	1	100.00
CONT_ASSIGN	12331	1	1	100.00
CONT_ASSIGN	12333	1	1	100.00
CONT_ASSIGN	12334	1	1	100.00
CONT_ASSIGN	12336	1	1	100.00
CONT_ASSIGN	12337	1	1	100.00
CONT_ASSIGN	12339	1	1	100.00
CONT_ASSIGN	12340	1	1	100.00
CONT_ASSIGN	12342	1	1	100.00
CONT_ASSIGN	12343	1	1	100.00
CONT_ASSIGN	12345	1	1	100.00
CONT_ASSIGN	12346	1	1	100.00
CONT_ASSIGN	12348	1	1	100.00
CONT_ASSIGN	12349	1	1	100.00
CONT_ASSIGN	12351	1	1	100.00
CONT_ASSIGN	12352	1	1	100.00
CONT_ASSIGN	12354	1	1	100.00
CONT_ASSIGN	12355	1	1	100.00
CONT_ASSIGN	12357	1	1	100.00
CONT_ASSIGN	12359	1	1	100.00
CONT_ASSIGN	12361	1	1	100.00
CONT_ASSIGN	12363	1	1	100.00
CONT_ASSIGN	12365	1	1	100.00
CONT_ASSIGN	12367	1	1	100.00
CONT_ASSIGN	12369	1	1	100.00
CONT_ASSIGN	12370	1	1	100.00
CONT_ASSIGN	12372	1	1	100.00
CONT_ASSIGN	12374	1	1	100.00
CONT_ASSIGN	12376	1	1	100.00
CONT_ASSIGN	12378	1	1	100.00
CONT_ASSIGN	12380	1	1	100.00
CONT_ASSIGN	12382	1	1	100.00
CONT_ASSIGN	12384	1	1	100.00
CONT_ASSIGN	12385	1	1	100.00
CONT_ASSIGN	12387	1	1	100.00
CONT_ASSIGN	12389	1	1	100.00
CONT_ASSIGN	12391	1	1	100.00
CONT_ASSIGN	12393	1	1	100.00
CONT_ASSIGN	12395	1	1	100.00
CONT_ASSIGN	12397	1	1	100.00
CONT_ASSIGN	12399	1	1	100.00
CONT_ASSIGN	12400	1	1	100.00
CONT_ASSIGN	12402	1	1	100.00
CONT_ASSIGN	12404	1	1	100.00
CONT_ASSIGN	12406	1	1	100.00
CONT_ASSIGN	12408	1	1	100.00
CONT_ASSIGN	12410	1	1	100.00
CONT_ASSIGN	12412	1	1	100.00
CONT_ASSIGN	12414	1	1	100.00
CONT_ASSIGN	12415	1	1	100.00
CONT_ASSIGN	12417	1	1	100.00
CONT_ASSIGN	12419	1	1	100.00
CONT_ASSIGN	12421	1	1	100.00
CONT_ASSIGN	12423	1	1	100.00
CONT_ASSIGN	12425	1	1	100.00
CONT_ASSIGN	12427	1	1	100.00
CONT_ASSIGN	12429	1	1	100.00
CONT_ASSIGN	12430	1	1	100.00
CONT_ASSIGN	12432	1	1	100.00
CONT_ASSIGN	12434	1	1	100.00
CONT_ASSIGN	12436	1	1	100.00
CONT_ASSIGN	12438	1	1	100.00
CONT_ASSIGN	12440	1	1	100.00
CONT_ASSIGN	12442	1	1	100.00
CONT_ASSIGN	12444	1	1	100.00
CONT_ASSIGN	12445	1	1	100.00
CONT_ASSIGN	12447	1	1	100.00
CONT_ASSIGN	12449	1	1	100.00
CONT_ASSIGN	12451	1	1	100.00
CONT_ASSIGN	12453	1	1	100.00
CONT_ASSIGN	12455	1	1	100.00
CONT_ASSIGN	12457	1	1	100.00
CONT_ASSIGN	12459	1	1	100.00
CONT_ASSIGN	12460	1	1	100.00
CONT_ASSIGN	12462	1	1	100.00
CONT_ASSIGN	12464	1	1	100.00
CONT_ASSIGN	12466	1	1	100.00
CONT_ASSIGN	12468	1	1	100.00
CONT_ASSIGN	12470	1	1	100.00
CONT_ASSIGN	12472	1	1	100.00
CONT_ASSIGN	12474	1	1	100.00
CONT_ASSIGN	12475	1	1	100.00
CONT_ASSIGN	12477	1	1	100.00
CONT_ASSIGN	12479	1	1	100.00
CONT_ASSIGN	12481	1	1	100.00
CONT_ASSIGN	12483	1	1	100.00
CONT_ASSIGN	12485	1	1	100.00
CONT_ASSIGN	12487	1	1	100.00
CONT_ASSIGN	12489	1	1	100.00
CONT_ASSIGN	12490	1	1	100.00
CONT_ASSIGN	12492	1	1	100.00
CONT_ASSIGN	12494	1	1	100.00
CONT_ASSIGN	12496	1	1	100.00
CONT_ASSIGN	12498	1	1	100.00
CONT_ASSIGN	12500	1	1	100.00
CONT_ASSIGN	12502	1	1	100.00
CONT_ASSIGN	12504	1	1	100.00
CONT_ASSIGN	12505	1	1	100.00
CONT_ASSIGN	12507	1	1	100.00
CONT_ASSIGN	12508	1	1	100.00
CONT_ASSIGN	12510	1	1	100.00
CONT_ASSIGN	12512	1	1	100.00
CONT_ASSIGN	12514	1	1	100.00
CONT_ASSIGN	12516	1	1	100.00
CONT_ASSIGN	12518	1	1	100.00
CONT_ASSIGN	12520	1	1	100.00
CONT_ASSIGN	12522	1	1	100.00
CONT_ASSIGN	12523	1	1	100.00
CONT_ASSIGN	12525	1	1	100.00
CONT_ASSIGN	12526	1	1	100.00
CONT_ASSIGN	12528	1	1	100.00
CONT_ASSIGN	12529	1	1	100.00
CONT_ASSIGN	12531	1	1	100.00
CONT_ASSIGN	12533	1	1	100.00
CONT_ASSIGN	12535	1	1	100.00
CONT_ASSIGN	12537	1	1	100.00
CONT_ASSIGN	12539	1	1	100.00
CONT_ASSIGN	12541	1	1	100.00
CONT_ASSIGN	12543	1	1	100.00
CONT_ASSIGN	12544	1	1	100.00
CONT_ASSIGN	12546	1	1	100.00
CONT_ASSIGN	12548	1	1	100.00
CONT_ASSIGN	12550	1	1	100.00
CONT_ASSIGN	12552	1	1	100.00
CONT_ASSIGN	12554	1	1	100.00
CONT_ASSIGN	12556	1	1	100.00
CONT_ASSIGN	12558	1	1	100.00
CONT_ASSIGN	12559	1	1	100.00
CONT_ASSIGN	12561	1	1	100.00
CONT_ASSIGN	12562	1	1	100.00
CONT_ASSIGN	12564	1	1	100.00
CONT_ASSIGN	12565	1	1	100.00
CONT_ASSIGN	12567	1	1	100.00
CONT_ASSIGN	12568	1	1	100.00
CONT_ASSIGN	12570	1	1	100.00
CONT_ASSIGN	12571	1	1	100.00
CONT_ASSIGN	12573	1	1	100.00
CONT_ASSIGN	12574	1	1	100.00
CONT_ASSIGN	12576	1	1	100.00
CONT_ASSIGN	12577	1	1	100.00
CONT_ASSIGN	12579	1	1	100.00
CONT_ASSIGN	12580	1	1	100.00
CONT_ASSIGN	12582	1	1	100.00
CONT_ASSIGN	12583	1	1	100.00
CONT_ASSIGN	12585	1	1	100.00
CONT_ASSIGN	12586	1	1	100.00
CONT_ASSIGN	12588	1	1	100.00
CONT_ASSIGN	12589	1	1	100.00
CONT_ASSIGN	12591	1	1	100.00
CONT_ASSIGN	12593	1	1	100.00
CONT_ASSIGN	12595	1	1	100.00
CONT_ASSIGN	12597	1	1	100.00
CONT_ASSIGN	12599	1	1	100.00
CONT_ASSIGN	12601	1	1	100.00
CONT_ASSIGN	12603	1	1	100.00
CONT_ASSIGN	12604	1	1	100.00
CONT_ASSIGN	12606	1	1	100.00
CONT_ASSIGN	12608	1	1	100.00
CONT_ASSIGN	12610	1	1	100.00
CONT_ASSIGN	12612	1	1	100.00
CONT_ASSIGN	12614	1	1	100.00
CONT_ASSIGN	12616	1	1	100.00
CONT_ASSIGN	12618	1	1	100.00
CONT_ASSIGN	12619	1	1	100.00
CONT_ASSIGN	12621	1	1	100.00
CONT_ASSIGN	12623	1	1	100.00
CONT_ASSIGN	12625	1	1	100.00
CONT_ASSIGN	12627	1	1	100.00
CONT_ASSIGN	12629	1	1	100.00
CONT_ASSIGN	12631	1	1	100.00
CONT_ASSIGN	12633	1	1	100.00
CONT_ASSIGN	12634	1	1	100.00
CONT_ASSIGN	12636	1	1	100.00
CONT_ASSIGN	12638	1	1	100.00
CONT_ASSIGN	12640	1	1	100.00
CONT_ASSIGN	12642	1	1	100.00
CONT_ASSIGN	12644	1	1	100.00
CONT_ASSIGN	12646	1	1	100.00
CONT_ASSIGN	12648	1	1	100.00
CONT_ASSIGN	12649	1	1	100.00
CONT_ASSIGN	12651	1	1	100.00
CONT_ASSIGN	12653	1	1	100.00
CONT_ASSIGN	12655	1	1	100.00
CONT_ASSIGN	12657	1	1	100.00
CONT_ASSIGN	12659	1	1	100.00
CONT_ASSIGN	12661	1	1	100.00
CONT_ASSIGN	12663	1	1	100.00
CONT_ASSIGN	12664	1	1	100.00
CONT_ASSIGN	12666	1	1	100.00
CONT_ASSIGN	12668	1	1	100.00
CONT_ASSIGN	12670	1	1	100.00
CONT_ASSIGN	12672	1	1	100.00
CONT_ASSIGN	12674	1	1	100.00
CONT_ASSIGN	12676	1	1	100.00
CONT_ASSIGN	12678	1	1	100.00
CONT_ASSIGN	12679	1	1	100.00
CONT_ASSIGN	12681	1	1	100.00
CONT_ASSIGN	12683	1	1	100.00
CONT_ASSIGN	12685	1	1	100.00
CONT_ASSIGN	12687	1	1	100.00
CONT_ASSIGN	12689	1	1	100.00
CONT_ASSIGN	12691	1	1	100.00
CONT_ASSIGN	12693	1	1	100.00
CONT_ASSIGN	12694	1	1	100.00
CONT_ASSIGN	12696	1	1	100.00
CONT_ASSIGN	12698	1	1	100.00
CONT_ASSIGN	12700	1	1	100.00
CONT_ASSIGN	12702	1	1	100.00
CONT_ASSIGN	12704	1	1	100.00
CONT_ASSIGN	12706	1	1	100.00
CONT_ASSIGN	12708	1	1	100.00
CONT_ASSIGN	12709	1	1	100.00
CONT_ASSIGN	12711	1	1	100.00
CONT_ASSIGN	12713	1	1	100.00
CONT_ASSIGN	12715	1	1	100.00
CONT_ASSIGN	12717	1	1	100.00
CONT_ASSIGN	12719	1	1	100.00
CONT_ASSIGN	12721	1	1	100.00
CONT_ASSIGN	12723	1	1	100.00
CONT_ASSIGN	12724	1	1	100.00
CONT_ASSIGN	12726	1	1	100.00
CONT_ASSIGN	12728	1	1	100.00
CONT_ASSIGN	12730	1	1	100.00
CONT_ASSIGN	12732	1	1	100.00
CONT_ASSIGN	12734	1	1	100.00
CONT_ASSIGN	12736	1	1	100.00
CONT_ASSIGN	12738	1	1	100.00
CONT_ASSIGN	12739	1	1	100.00
CONT_ASSIGN	12741	1	1	100.00
CONT_ASSIGN	12742	1	1	100.00
CONT_ASSIGN	12744	1	1	100.00
CONT_ASSIGN	12746	1	1	100.00
CONT_ASSIGN	12748	1	1	100.00
CONT_ASSIGN	12750	1	1	100.00
CONT_ASSIGN	12752	1	1	100.00
CONT_ASSIGN	12754	1	1	100.00
CONT_ASSIGN	12756	1	1	100.00
CONT_ASSIGN	12757	1	1	100.00
CONT_ASSIGN	12759	1	1	100.00
CONT_ASSIGN	12760	1	1	100.00
CONT_ASSIGN	12762	1	1	100.00
CONT_ASSIGN	12763	1	1	100.00
CONT_ASSIGN	12765	1	1	100.00
CONT_ASSIGN	12767	1	1	100.00
CONT_ASSIGN	12769	1	1	100.00
CONT_ASSIGN	12771	1	1	100.00
CONT_ASSIGN	12773	1	1	100.00
CONT_ASSIGN	12775	1	1	100.00
CONT_ASSIGN	12777	1	1	100.00
CONT_ASSIGN	12778	1	1	100.00
CONT_ASSIGN	12780	1	1	100.00
CONT_ASSIGN	12782	1	1	100.00
CONT_ASSIGN	12784	1	1	100.00
CONT_ASSIGN	12786	1	1	100.00
CONT_ASSIGN	12788	1	1	100.00
CONT_ASSIGN	12790	1	1	100.00
CONT_ASSIGN	12792	1	1	100.00
CONT_ASSIGN	12793	1	1	100.00
CONT_ASSIGN	12795	1	1	100.00
CONT_ASSIGN	12797	1	1	100.00
CONT_ASSIGN	12798	1	1	100.00
CONT_ASSIGN	12800	1	1	100.00
CONT_ASSIGN	12801	1	1	100.00
CONT_ASSIGN	12802	1	1	100.00
CONT_ASSIGN	12804	1	1	100.00
CONT_ASSIGN	12806	1	1	100.00
CONT_ASSIGN	12807	1	1	100.00
CONT_ASSIGN	12809	1	1	100.00
CONT_ASSIGN	12811	1	1	100.00
CONT_ASSIGN	12812	1	1	100.00
CONT_ASSIGN	12813	1	1	100.00
CONT_ASSIGN	12815	1	1	100.00
CONT_ASSIGN	12817	1	1	100.00
CONT_ASSIGN	12819	1	1	100.00
CONT_ASSIGN	12821	1	1	100.00
CONT_ASSIGN	12823	1	1	100.00
CONT_ASSIGN	12825	1	1	100.00
CONT_ASSIGN	12827	1	1	100.00
CONT_ASSIGN	12829	1	1	100.00
CONT_ASSIGN	12830	1	1	100.00
CONT_ASSIGN	12832	1	1	100.00
CONT_ASSIGN	12834	1	1	100.00
CONT_ASSIGN	12835	1	1	100.00
CONT_ASSIGN	12837	1	1	100.00
CONT_ASSIGN	12839	1	1	100.00
CONT_ASSIGN	12840	1	1	100.00
CONT_ASSIGN	12842	1	1	100.00
CONT_ASSIGN	12844	1	1	100.00
CONT_ASSIGN	12845	1	1	100.00
CONT_ASSIGN	12847	1	1	100.00
CONT_ASSIGN	12848	1	1	100.00
CONT_ASSIGN	12850	1	1	100.00
CONT_ASSIGN	12852	1	1	100.00
CONT_ASSIGN	12853	1	1	100.00
CONT_ASSIGN	12855	1	1	100.00
CONT_ASSIGN	12856	1	1	100.00
ALWAYS	12860	109	109	100.00
ALWAYS	12973	393	393	100.00
ALWAYS	13701	3	3	100.00
ALWAYS	13709	3	3	100.00
CONT_ASSIGN	13717	1	1	100.00
CONT_ASSIGN	13720	1	1	100.00
CONT_ASSIGN	13724	1	1	100.00
CONT_ASSIGN	13730	1	1	100.00
CONT_ASSIGN	13738	1	1	100.00
CONT_ASSIGN	13739	1	1	100.00

Click here to see the source line report.

Cond Coverage for Module : flash_ctrl_core_reg_top

	Total	Covered	Percent
Conditions	1228	1222	99.51
Logical	1228	1222	99.51
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
67-11895	99.67
11896-11938	100.00
11938-12149	100.00
12152-12840	99.37
12845-13717	84.21

Branch Coverage for Module : flash_ctrl_core_reg_top

	Line No.	Total	Covered	Percent
Branches		123	123	100.00
TERNARY	11934	2	2	100.00
IF	77	3	3	100.00
TERNARY	136	3	3	100.00
IF	143	2	2	100.00
CASE	12974	109	109	100.00
IF	13701	2	2	100.00
IF	13709	2	2	100.00



11934        assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



77             if (!rst_ni) begin
               -1-  
78               err_q <= '0;
                 ==>
79             end else if (intg_err || reg_we_err) begin
                        -2-  
80               err_q <= 1'b1;
                 ==>
81             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T16,T43,T44
0	0	Covered	T1,T2,T3



136            reg_steer =
                          
137                tl_i.a_address[AW-1:0] inside {[432:435]} ? 2'd0 :
                                                             -1-  
                                                             ==>  
138                tl_i.a_address[AW-1:0] inside {[436:439]} ? 2'd1 :
                                                             -2-  
                                                             ==>  
                                                             ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T19,T12
0	1	Covered	T2,T17,T18
0	0	Covered	T1,T2,T3



143            if (intg_err) begin
               -1-  
144              reg_steer = 2'd2;
                 ==>
145            end
               MISSING_ELSE
               ==>

Branches:

-1-	Status	Tests
1	Covered	T266,T267,T268
0	Covered	T1,T2,T3



12974          unique case (1'b1)
                      -1-  
12975            addr_hit[0]: begin
12976              reg_rdata_next[0] = intr_state_prog_empty_qs;
                   ==>
12977              reg_rdata_next[1] = intr_state_prog_lvl_qs;
12978              reg_rdata_next[2] = intr_state_rd_full_qs;
12979              reg_rdata_next[3] = intr_state_rd_lvl_qs;
12980              reg_rdata_next[4] = intr_state_op_done_qs;
12981              reg_rdata_next[5] = intr_state_corr_err_qs;
12982            end
12983      
12984            addr_hit[1]: begin
12985              reg_rdata_next[0] = intr_enable_prog_empty_qs;
                   ==>
12986              reg_rdata_next[1] = intr_enable_prog_lvl_qs;
12987              reg_rdata_next[2] = intr_enable_rd_full_qs;
12988              reg_rdata_next[3] = intr_enable_rd_lvl_qs;
12989              reg_rdata_next[4] = intr_enable_op_done_qs;
12990              reg_rdata_next[5] = intr_enable_corr_err_qs;
12991            end
12992      
12993            addr_hit[2]: begin
12994              reg_rdata_next[0] = '0;
                   ==>
12995              reg_rdata_next[1] = '0;
12996              reg_rdata_next[2] = '0;
12997              reg_rdata_next[3] = '0;
12998              reg_rdata_next[4] = '0;
12999              reg_rdata_next[5] = '0;
13000            end
13001      
13002            addr_hit[3]: begin
13003              reg_rdata_next[0] = '0;
                   ==>
13004              reg_rdata_next[1] = '0;
13005              reg_rdata_next[2] = '0;
13006              reg_rdata_next[3] = '0;
13007              reg_rdata_next[4] = '0;
13008            end
13009      
13010            addr_hit[4]: begin
13011              reg_rdata_next[3:0] = dis_qs;
                   ==>
13012            end
13013      
13014            addr_hit[5]: begin
13015              reg_rdata_next[31:0] = exec_qs;
                   ==>
13016            end
13017      
13018            addr_hit[6]: begin
13019              reg_rdata_next[0] = init_qs;
                   ==>
13020            end
13021      
13022            addr_hit[7]: begin
13023              reg_rdata_next[0] = ctrl_regwen_qs;
                   ==>
13024            end
13025      
13026            addr_hit[8]: begin
13027              reg_rdata_next[0] = control_start_qs;
                   ==>
13028              reg_rdata_next[5:4] = control_op_qs;
13029              reg_rdata_next[6] = control_prog_sel_qs;
13030              reg_rdata_next[7] = control_erase_sel_qs;
13031              reg_rdata_next[8] = control_partition_sel_qs;
13032              reg_rdata_next[10:9] = control_info_sel_qs;
13033              reg_rdata_next[27:16] = control_num_qs;
13034            end
13035      
13036            addr_hit[9]: begin
13037              reg_rdata_next[19:0] = addr_qs;
                   ==>
13038            end
13039      
13040            addr_hit[10]: begin
13041              reg_rdata_next[0] = prog_type_en_normal_qs;
                   ==>
13042              reg_rdata_next[1] = prog_type_en_repair_qs;
13043            end
13044      
13045            addr_hit[11]: begin
13046              reg_rdata_next[0] = erase_suspend_qs;
                   ==>
13047            end
13048      
13049            addr_hit[12]: begin
13050              reg_rdata_next[0] = region_cfg_regwen_0_qs;
                   ==>
13051            end
13052      
13053            addr_hit[13]: begin
13054              reg_rdata_next[0] = region_cfg_regwen_1_qs;
                   ==>
13055            end
13056      
13057            addr_hit[14]: begin
13058              reg_rdata_next[0] = region_cfg_regwen_2_qs;
                   ==>
13059            end
13060      
13061            addr_hit[15]: begin
13062              reg_rdata_next[0] = region_cfg_regwen_3_qs;
                   ==>
13063            end
13064      
13065            addr_hit[16]: begin
13066              reg_rdata_next[0] = region_cfg_regwen_4_qs;
                   ==>
13067            end
13068      
13069            addr_hit[17]: begin
13070              reg_rdata_next[0] = region_cfg_regwen_5_qs;
                   ==>
13071            end
13072      
13073            addr_hit[18]: begin
13074              reg_rdata_next[0] = region_cfg_regwen_6_qs;
                   ==>
13075            end
13076      
13077            addr_hit[19]: begin
13078              reg_rdata_next[0] = region_cfg_regwen_7_qs;
                   ==>
13079            end
13080      
13081            addr_hit[20]: begin
13082              reg_rdata_next[3:0] = mp_region_cfg_0_en_0_qs;
                   ==>
13083              reg_rdata_next[7:4] = mp_region_cfg_0_rd_en_0_qs;
13084              reg_rdata_next[11:8] = mp_region_cfg_0_prog_en_0_qs;
13085              reg_rdata_next[15:12] = mp_region_cfg_0_erase_en_0_qs;
13086              reg_rdata_next[19:16] = mp_region_cfg_0_scramble_en_0_qs;
13087              reg_rdata_next[23:20] = mp_region_cfg_0_ecc_en_0_qs;
13088              reg_rdata_next[27:24] = mp_region_cfg_0_he_en_0_qs;
13089            end
13090      
13091            addr_hit[21]: begin
13092              reg_rdata_next[3:0] = mp_region_cfg_1_en_1_qs;
                   ==>
13093              reg_rdata_next[7:4] = mp_region_cfg_1_rd_en_1_qs;
13094              reg_rdata_next[11:8] = mp_region_cfg_1_prog_en_1_qs;
13095              reg_rdata_next[15:12] = mp_region_cfg_1_erase_en_1_qs;
13096              reg_rdata_next[19:16] = mp_region_cfg_1_scramble_en_1_qs;
13097              reg_rdata_next[23:20] = mp_region_cfg_1_ecc_en_1_qs;
13098              reg_rdata_next[27:24] = mp_region_cfg_1_he_en_1_qs;
13099            end
13100      
13101            addr_hit[22]: begin
13102              reg_rdata_next[3:0] = mp_region_cfg_2_en_2_qs;
                   ==>
13103              reg_rdata_next[7:4] = mp_region_cfg_2_rd_en_2_qs;
13104              reg_rdata_next[11:8] = mp_region_cfg_2_prog_en_2_qs;
13105              reg_rdata_next[15:12] = mp_region_cfg_2_erase_en_2_qs;
13106              reg_rdata_next[19:16] = mp_region_cfg_2_scramble_en_2_qs;
13107              reg_rdata_next[23:20] = mp_region_cfg_2_ecc_en_2_qs;
13108              reg_rdata_next[27:24] = mp_region_cfg_2_he_en_2_qs;
13109            end
13110      
13111            addr_hit[23]: begin
13112              reg_rdata_next[3:0] = mp_region_cfg_3_en_3_qs;
                   ==>
13113              reg_rdata_next[7:4] = mp_region_cfg_3_rd_en_3_qs;
13114              reg_rdata_next[11:8] = mp_region_cfg_3_prog_en_3_qs;
13115              reg_rdata_next[15:12] = mp_region_cfg_3_erase_en_3_qs;
13116              reg_rdata_next[19:16] = mp_region_cfg_3_scramble_en_3_qs;
13117              reg_rdata_next[23:20] = mp_region_cfg_3_ecc_en_3_qs;
13118              reg_rdata_next[27:24] = mp_region_cfg_3_he_en_3_qs;
13119            end
13120      
13121            addr_hit[24]: begin
13122              reg_rdata_next[3:0] = mp_region_cfg_4_en_4_qs;
                   ==>
13123              reg_rdata_next[7:4] = mp_region_cfg_4_rd_en_4_qs;
13124              reg_rdata_next[11:8] = mp_region_cfg_4_prog_en_4_qs;
13125              reg_rdata_next[15:12] = mp_region_cfg_4_erase_en_4_qs;
13126              reg_rdata_next[19:16] = mp_region_cfg_4_scramble_en_4_qs;
13127              reg_rdata_next[23:20] = mp_region_cfg_4_ecc_en_4_qs;
13128              reg_rdata_next[27:24] = mp_region_cfg_4_he_en_4_qs;
13129            end
13130      
13131            addr_hit[25]: begin
13132              reg_rdata_next[3:0] = mp_region_cfg_5_en_5_qs;
                   ==>
13133              reg_rdata_next[7:4] = mp_region_cfg_5_rd_en_5_qs;
13134              reg_rdata_next[11:8] = mp_region_cfg_5_prog_en_5_qs;
13135              reg_rdata_next[15:12] = mp_region_cfg_5_erase_en_5_qs;
13136              reg_rdata_next[19:16] = mp_region_cfg_5_scramble_en_5_qs;
13137              reg_rdata_next[23:20] = mp_region_cfg_5_ecc_en_5_qs;
13138              reg_rdata_next[27:24] = mp_region_cfg_5_he_en_5_qs;
13139            end
13140      
13141            addr_hit[26]: begin
13142              reg_rdata_next[3:0] = mp_region_cfg_6_en_6_qs;
                   ==>
13143              reg_rdata_next[7:4] = mp_region_cfg_6_rd_en_6_qs;
13144              reg_rdata_next[11:8] = mp_region_cfg_6_prog_en_6_qs;
13145              reg_rdata_next[15:12] = mp_region_cfg_6_erase_en_6_qs;
13146              reg_rdata_next[19:16] = mp_region_cfg_6_scramble_en_6_qs;
13147              reg_rdata_next[23:20] = mp_region_cfg_6_ecc_en_6_qs;
13148              reg_rdata_next[27:24] = mp_region_cfg_6_he_en_6_qs;
13149            end
13150      
13151            addr_hit[27]: begin
13152              reg_rdata_next[3:0] = mp_region_cfg_7_en_7_qs;
                   ==>
13153              reg_rdata_next[7:4] = mp_region_cfg_7_rd_en_7_qs;
13154              reg_rdata_next[11:8] = mp_region_cfg_7_prog_en_7_qs;
13155              reg_rdata_next[15:12] = mp_region_cfg_7_erase_en_7_qs;
13156              reg_rdata_next[19:16] = mp_region_cfg_7_scramble_en_7_qs;
13157              reg_rdata_next[23:20] = mp_region_cfg_7_ecc_en_7_qs;
13158              reg_rdata_next[27:24] = mp_region_cfg_7_he_en_7_qs;
13159            end
13160      
13161            addr_hit[28]: begin
13162              reg_rdata_next[8:0] = mp_region_0_base_0_qs;
                   ==>
13163              reg_rdata_next[18:9] = mp_region_0_size_0_qs;
13164            end
13165      
13166            addr_hit[29]: begin
13167              reg_rdata_next[8:0] = mp_region_1_base_1_qs;
                   ==>
13168              reg_rdata_next[18:9] = mp_region_1_size_1_qs;
13169            end
13170      
13171            addr_hit[30]: begin
13172              reg_rdata_next[8:0] = mp_region_2_base_2_qs;
                   ==>
13173              reg_rdata_next[18:9] = mp_region_2_size_2_qs;
13174            end
13175      
13176            addr_hit[31]: begin
13177              reg_rdata_next[8:0] = mp_region_3_base_3_qs;
                   ==>
13178              reg_rdata_next[18:9] = mp_region_3_size_3_qs;
13179            end
13180      
13181            addr_hit[32]: begin
13182              reg_rdata_next[8:0] = mp_region_4_base_4_qs;
                   ==>
13183              reg_rdata_next[18:9] = mp_region_4_size_4_qs;
13184            end
13185      
13186            addr_hit[33]: begin
13187              reg_rdata_next[8:0] = mp_region_5_base_5_qs;
                   ==>
13188              reg_rdata_next[18:9] = mp_region_5_size_5_qs;
13189            end
13190      
13191            addr_hit[34]: begin
13192              reg_rdata_next[8:0] = mp_region_6_base_6_qs;
                   ==>
13193              reg_rdata_next[18:9] = mp_region_6_size_6_qs;
13194            end
13195      
13196            addr_hit[35]: begin
13197              reg_rdata_next[8:0] = mp_region_7_base_7_qs;
                   ==>
13198              reg_rdata_next[18:9] = mp_region_7_size_7_qs;
13199            end
13200      
13201            addr_hit[36]: begin
13202              reg_rdata_next[3:0] = default_region_rd_en_qs;
                   ==>
13203              reg_rdata_next[7:4] = default_region_prog_en_qs;
13204              reg_rdata_next[11:8] = default_region_erase_en_qs;
13205              reg_rdata_next[15:12] = default_region_scramble_en_qs;
13206              reg_rdata_next[19:16] = default_region_ecc_en_qs;
13207              reg_rdata_next[23:20] = default_region_he_en_qs;
13208            end
13209      
13210            addr_hit[37]: begin
13211              reg_rdata_next[0] = bank0_info0_regwen_0_qs;
                   ==>
13212            end
13213      
13214            addr_hit[38]: begin
13215              reg_rdata_next[0] = bank0_info0_regwen_1_qs;
                   ==>
13216            end
13217      
13218            addr_hit[39]: begin
13219              reg_rdata_next[0] = bank0_info0_regwen_2_qs;
                   ==>
13220            end
13221      
13222            addr_hit[40]: begin
13223              reg_rdata_next[0] = bank0_info0_regwen_3_qs;
                   ==>
13224            end
13225      
13226            addr_hit[41]: begin
13227              reg_rdata_next[0] = bank0_info0_regwen_4_qs;
                   ==>
13228            end
13229      
13230            addr_hit[42]: begin
13231              reg_rdata_next[0] = bank0_info0_regwen_5_qs;
                   ==>
13232            end
13233      
13234            addr_hit[43]: begin
13235              reg_rdata_next[0] = bank0_info0_regwen_6_qs;
                   ==>
13236            end
13237      
13238            addr_hit[44]: begin
13239              reg_rdata_next[0] = bank0_info0_regwen_7_qs;
                   ==>
13240            end
13241      
13242            addr_hit[45]: begin
13243              reg_rdata_next[0] = bank0_info0_regwen_8_qs;
                   ==>
13244            end
13245      
13246            addr_hit[46]: begin
13247              reg_rdata_next[0] = bank0_info0_regwen_9_qs;
                   ==>
13248            end
13249      
13250            addr_hit[47]: begin
13251              reg_rdata_next[3:0] = bank0_info0_page_cfg_0_en_0_qs;
                   ==>
13252              reg_rdata_next[7:4] = bank0_info0_page_cfg_0_rd_en_0_qs;
13253              reg_rdata_next[11:8] = bank0_info0_page_cfg_0_prog_en_0_qs;
13254              reg_rdata_next[15:12] = bank0_info0_page_cfg_0_erase_en_0_qs;
13255              reg_rdata_next[19:16] = bank0_info0_page_cfg_0_scramble_en_0_qs;
13256              reg_rdata_next[23:20] = bank0_info0_page_cfg_0_ecc_en_0_qs;
13257              reg_rdata_next[27:24] = bank0_info0_page_cfg_0_he_en_0_qs;
13258            end
13259      
13260            addr_hit[48]: begin
13261              reg_rdata_next[3:0] = bank0_info0_page_cfg_1_en_1_qs;
                   ==>
13262              reg_rdata_next[7:4] = bank0_info0_page_cfg_1_rd_en_1_qs;
13263              reg_rdata_next[11:8] = bank0_info0_page_cfg_1_prog_en_1_qs;
13264              reg_rdata_next[15:12] = bank0_info0_page_cfg_1_erase_en_1_qs;
13265              reg_rdata_next[19:16] = bank0_info0_page_cfg_1_scramble_en_1_qs;
13266              reg_rdata_next[23:20] = bank0_info0_page_cfg_1_ecc_en_1_qs;
13267              reg_rdata_next[27:24] = bank0_info0_page_cfg_1_he_en_1_qs;
13268            end
13269      
13270            addr_hit[49]: begin
13271              reg_rdata_next[3:0] = bank0_info0_page_cfg_2_en_2_qs;
                   ==>
13272              reg_rdata_next[7:4] = bank0_info0_page_cfg_2_rd_en_2_qs;
13273              reg_rdata_next[11:8] = bank0_info0_page_cfg_2_prog_en_2_qs;
13274              reg_rdata_next[15:12] = bank0_info0_page_cfg_2_erase_en_2_qs;
13275              reg_rdata_next[19:16] = bank0_info0_page_cfg_2_scramble_en_2_qs;
13276              reg_rdata_next[23:20] = bank0_info0_page_cfg_2_ecc_en_2_qs;
13277              reg_rdata_next[27:24] = bank0_info0_page_cfg_2_he_en_2_qs;
13278            end
13279      
13280            addr_hit[50]: begin
13281              reg_rdata_next[3:0] = bank0_info0_page_cfg_3_en_3_qs;
                   ==>
13282              reg_rdata_next[7:4] = bank0_info0_page_cfg_3_rd_en_3_qs;
13283              reg_rdata_next[11:8] = bank0_info0_page_cfg_3_prog_en_3_qs;
13284              reg_rdata_next[15:12] = bank0_info0_page_cfg_3_erase_en_3_qs;
13285              reg_rdata_next[19:16] = bank0_info0_page_cfg_3_scramble_en_3_qs;
13286              reg_rdata_next[23:20] = bank0_info0_page_cfg_3_ecc_en_3_qs;
13287              reg_rdata_next[27:24] = bank0_info0_page_cfg_3_he_en_3_qs;
13288            end
13289      
13290            addr_hit[51]: begin
13291              reg_rdata_next[3:0] = bank0_info0_page_cfg_4_en_4_qs;
                   ==>
13292              reg_rdata_next[7:4] = bank0_info0_page_cfg_4_rd_en_4_qs;
13293              reg_rdata_next[11:8] = bank0_info0_page_cfg_4_prog_en_4_qs;
13294              reg_rdata_next[15:12] = bank0_info0_page_cfg_4_erase_en_4_qs;
13295              reg_rdata_next[19:16] = bank0_info0_page_cfg_4_scramble_en_4_qs;
13296              reg_rdata_next[23:20] = bank0_info0_page_cfg_4_ecc_en_4_qs;
13297              reg_rdata_next[27:24] = bank0_info0_page_cfg_4_he_en_4_qs;
13298            end
13299      
13300            addr_hit[52]: begin
13301              reg_rdata_next[3:0] = bank0_info0_page_cfg_5_en_5_qs;
                   ==>
13302              reg_rdata_next[7:4] = bank0_info0_page_cfg_5_rd_en_5_qs;
13303              reg_rdata_next[11:8] = bank0_info0_page_cfg_5_prog_en_5_qs;
13304              reg_rdata_next[15:12] = bank0_info0_page_cfg_5_erase_en_5_qs;
13305              reg_rdata_next[19:16] = bank0_info0_page_cfg_5_scramble_en_5_qs;
13306              reg_rdata_next[23:20] = bank0_info0_page_cfg_5_ecc_en_5_qs;
13307              reg_rdata_next[27:24] = bank0_info0_page_cfg_5_he_en_5_qs;
13308            end
13309      
13310            addr_hit[53]: begin
13311              reg_rdata_next[3:0] = bank0_info0_page_cfg_6_en_6_qs;
                   ==>
13312              reg_rdata_next[7:4] = bank0_info0_page_cfg_6_rd_en_6_qs;
13313              reg_rdata_next[11:8] = bank0_info0_page_cfg_6_prog_en_6_qs;
13314              reg_rdata_next[15:12] = bank0_info0_page_cfg_6_erase_en_6_qs;
13315              reg_rdata_next[19:16] = bank0_info0_page_cfg_6_scramble_en_6_qs;
13316              reg_rdata_next[23:20] = bank0_info0_page_cfg_6_ecc_en_6_qs;
13317              reg_rdata_next[27:24] = bank0_info0_page_cfg_6_he_en_6_qs;
13318            end
13319      
13320            addr_hit[54]: begin
13321              reg_rdata_next[3:0] = bank0_info0_page_cfg_7_en_7_qs;
                   ==>
13322              reg_rdata_next[7:4] = bank0_info0_page_cfg_7_rd_en_7_qs;
13323              reg_rdata_next[11:8] = bank0_info0_page_cfg_7_prog_en_7_qs;
13324              reg_rdata_next[15:12] = bank0_info0_page_cfg_7_erase_en_7_qs;
13325              reg_rdata_next[19:16] = bank0_info0_page_cfg_7_scramble_en_7_qs;
13326              reg_rdata_next[23:20] = bank0_info0_page_cfg_7_ecc_en_7_qs;
13327              reg_rdata_next[27:24] = bank0_info0_page_cfg_7_he_en_7_qs;
13328            end
13329      
13330            addr_hit[55]: begin
13331              reg_rdata_next[3:0] = bank0_info0_page_cfg_8_en_8_qs;
                   ==>
13332              reg_rdata_next[7:4] = bank0_info0_page_cfg_8_rd_en_8_qs;
13333              reg_rdata_next[11:8] = bank0_info0_page_cfg_8_prog_en_8_qs;
13334              reg_rdata_next[15:12] = bank0_info0_page_cfg_8_erase_en_8_qs;
13335              reg_rdata_next[19:16] = bank0_info0_page_cfg_8_scramble_en_8_qs;
13336              reg_rdata_next[23:20] = bank0_info0_page_cfg_8_ecc_en_8_qs;
13337              reg_rdata_next[27:24] = bank0_info0_page_cfg_8_he_en_8_qs;
13338            end
13339      
13340            addr_hit[56]: begin
13341              reg_rdata_next[3:0] = bank0_info0_page_cfg_9_en_9_qs;
                   ==>
13342              reg_rdata_next[7:4] = bank0_info0_page_cfg_9_rd_en_9_qs;
13343              reg_rdata_next[11:8] = bank0_info0_page_cfg_9_prog_en_9_qs;
13344              reg_rdata_next[15:12] = bank0_info0_page_cfg_9_erase_en_9_qs;
13345              reg_rdata_next[19:16] = bank0_info0_page_cfg_9_scramble_en_9_qs;
13346              reg_rdata_next[23:20] = bank0_info0_page_cfg_9_ecc_en_9_qs;
13347              reg_rdata_next[27:24] = bank0_info0_page_cfg_9_he_en_9_qs;
13348            end
13349      
13350            addr_hit[57]: begin
13351              reg_rdata_next[0] = bank0_info1_regwen_qs;
                   ==>
13352            end
13353      
13354            addr_hit[58]: begin
13355              reg_rdata_next[3:0] = bank0_info1_page_cfg_en_0_qs;
                   ==>
13356              reg_rdata_next[7:4] = bank0_info1_page_cfg_rd_en_0_qs;
13357              reg_rdata_next[11:8] = bank0_info1_page_cfg_prog_en_0_qs;
13358              reg_rdata_next[15:12] = bank0_info1_page_cfg_erase_en_0_qs;
13359              reg_rdata_next[19:16] = bank0_info1_page_cfg_scramble_en_0_qs;
13360              reg_rdata_next[23:20] = bank0_info1_page_cfg_ecc_en_0_qs;
13361              reg_rdata_next[27:24] = bank0_info1_page_cfg_he_en_0_qs;
13362            end
13363      
13364            addr_hit[59]: begin
13365              reg_rdata_next[0] = bank0_info2_regwen_0_qs;
                   ==>
13366            end
13367      
13368            addr_hit[60]: begin
13369              reg_rdata_next[0] = bank0_info2_regwen_1_qs;
                   ==>
13370            end
13371      
13372            addr_hit[61]: begin
13373              reg_rdata_next[3:0] = bank0_info2_page_cfg_0_en_0_qs;
                   ==>
13374              reg_rdata_next[7:4] = bank0_info2_page_cfg_0_rd_en_0_qs;
13375              reg_rdata_next[11:8] = bank0_info2_page_cfg_0_prog_en_0_qs;
13376              reg_rdata_next[15:12] = bank0_info2_page_cfg_0_erase_en_0_qs;
13377              reg_rdata_next[19:16] = bank0_info2_page_cfg_0_scramble_en_0_qs;
13378              reg_rdata_next[23:20] = bank0_info2_page_cfg_0_ecc_en_0_qs;
13379              reg_rdata_next[27:24] = bank0_info2_page_cfg_0_he_en_0_qs;
13380            end
13381      
13382            addr_hit[62]: begin
13383              reg_rdata_next[3:0] = bank0_info2_page_cfg_1_en_1_qs;
                   ==>
13384              reg_rdata_next[7:4] = bank0_info2_page_cfg_1_rd_en_1_qs;
13385              reg_rdata_next[11:8] = bank0_info2_page_cfg_1_prog_en_1_qs;
13386              reg_rdata_next[15:12] = bank0_info2_page_cfg_1_erase_en_1_qs;
13387              reg_rdata_next[19:16] = bank0_info2_page_cfg_1_scramble_en_1_qs;
13388              reg_rdata_next[23:20] = bank0_info2_page_cfg_1_ecc_en_1_qs;
13389              reg_rdata_next[27:24] = bank0_info2_page_cfg_1_he_en_1_qs;
13390            end
13391      
13392            addr_hit[63]: begin
13393              reg_rdata_next[0] = bank1_info0_regwen_0_qs;
                   ==>
13394            end
13395      
13396            addr_hit[64]: begin
13397              reg_rdata_next[0] = bank1_info0_regwen_1_qs;
                   ==>
13398            end
13399      
13400            addr_hit[65]: begin
13401              reg_rdata_next[0] = bank1_info0_regwen_2_qs;
                   ==>
13402            end
13403      
13404            addr_hit[66]: begin
13405              reg_rdata_next[0] = bank1_info0_regwen_3_qs;
                   ==>
13406            end
13407      
13408            addr_hit[67]: begin
13409              reg_rdata_next[0] = bank1_info0_regwen_4_qs;
                   ==>
13410            end
13411      
13412            addr_hit[68]: begin
13413              reg_rdata_next[0] = bank1_info0_regwen_5_qs;
                   ==>
13414            end
13415      
13416            addr_hit[69]: begin
13417              reg_rdata_next[0] = bank1_info0_regwen_6_qs;
                   ==>
13418            end
13419      
13420            addr_hit[70]: begin
13421              reg_rdata_next[0] = bank1_info0_regwen_7_qs;
                   ==>
13422            end
13423      
13424            addr_hit[71]: begin
13425              reg_rdata_next[0] = bank1_info0_regwen_8_qs;
                   ==>
13426            end
13427      
13428            addr_hit[72]: begin
13429              reg_rdata_next[0] = bank1_info0_regwen_9_qs;
                   ==>
13430            end
13431      
13432            addr_hit[73]: begin
13433              reg_rdata_next[3:0] = bank1_info0_page_cfg_0_en_0_qs;
                   ==>
13434              reg_rdata_next[7:4] = bank1_info0_page_cfg_0_rd_en_0_qs;
13435              reg_rdata_next[11:8] = bank1_info0_page_cfg_0_prog_en_0_qs;
13436              reg_rdata_next[15:12] = bank1_info0_page_cfg_0_erase_en_0_qs;
13437              reg_rdata_next[19:16] = bank1_info0_page_cfg_0_scramble_en_0_qs;
13438              reg_rdata_next[23:20] = bank1_info0_page_cfg_0_ecc_en_0_qs;
13439              reg_rdata_next[27:24] = bank1_info0_page_cfg_0_he_en_0_qs;
13440            end
13441      
13442            addr_hit[74]: begin
13443              reg_rdata_next[3:0] = bank1_info0_page_cfg_1_en_1_qs;
                   ==>
13444              reg_rdata_next[7:4] = bank1_info0_page_cfg_1_rd_en_1_qs;
13445              reg_rdata_next[11:8] = bank1_info0_page_cfg_1_prog_en_1_qs;
13446              reg_rdata_next[15:12] = bank1_info0_page_cfg_1_erase_en_1_qs;
13447              reg_rdata_next[19:16] = bank1_info0_page_cfg_1_scramble_en_1_qs;
13448              reg_rdata_next[23:20] = bank1_info0_page_cfg_1_ecc_en_1_qs;
13449              reg_rdata_next[27:24] = bank1_info0_page_cfg_1_he_en_1_qs;
13450            end
13451      
13452            addr_hit[75]: begin
13453              reg_rdata_next[3:0] = bank1_info0_page_cfg_2_en_2_qs;
                   ==>
13454              reg_rdata_next[7:4] = bank1_info0_page_cfg_2_rd_en_2_qs;
13455              reg_rdata_next[11:8] = bank1_info0_page_cfg_2_prog_en_2_qs;
13456              reg_rdata_next[15:12] = bank1_info0_page_cfg_2_erase_en_2_qs;
13457              reg_rdata_next[19:16] = bank1_info0_page_cfg_2_scramble_en_2_qs;
13458              reg_rdata_next[23:20] = bank1_info0_page_cfg_2_ecc_en_2_qs;
13459              reg_rdata_next[27:24] = bank1_info0_page_cfg_2_he_en_2_qs;
13460            end
13461      
13462            addr_hit[76]: begin
13463              reg_rdata_next[3:0] = bank1_info0_page_cfg_3_en_3_qs;
                   ==>
13464              reg_rdata_next[7:4] = bank1_info0_page_cfg_3_rd_en_3_qs;
13465              reg_rdata_next[11:8] = bank1_info0_page_cfg_3_prog_en_3_qs;
13466              reg_rdata_next[15:12] = bank1_info0_page_cfg_3_erase_en_3_qs;
13467              reg_rdata_next[19:16] = bank1_info0_page_cfg_3_scramble_en_3_qs;
13468              reg_rdata_next[23:20] = bank1_info0_page_cfg_3_ecc_en_3_qs;
13469              reg_rdata_next[27:24] = bank1_info0_page_cfg_3_he_en_3_qs;
13470            end
13471      
13472            addr_hit[77]: begin
13473              reg_rdata_next[3:0] = bank1_info0_page_cfg_4_en_4_qs;
                   ==>
13474              reg_rdata_next[7:4] = bank1_info0_page_cfg_4_rd_en_4_qs;
13475              reg_rdata_next[11:8] = bank1_info0_page_cfg_4_prog_en_4_qs;
13476              reg_rdata_next[15:12] = bank1_info0_page_cfg_4_erase_en_4_qs;
13477              reg_rdata_next[19:16] = bank1_info0_page_cfg_4_scramble_en_4_qs;
13478              reg_rdata_next[23:20] = bank1_info0_page_cfg_4_ecc_en_4_qs;
13479              reg_rdata_next[27:24] = bank1_info0_page_cfg_4_he_en_4_qs;
13480            end
13481      
13482            addr_hit[78]: begin
13483              reg_rdata_next[3:0] = bank1_info0_page_cfg_5_en_5_qs;
                   ==>
13484              reg_rdata_next[7:4] = bank1_info0_page_cfg_5_rd_en_5_qs;
13485              reg_rdata_next[11:8] = bank1_info0_page_cfg_5_prog_en_5_qs;
13486              reg_rdata_next[15:12] = bank1_info0_page_cfg_5_erase_en_5_qs;
13487              reg_rdata_next[19:16] = bank1_info0_page_cfg_5_scramble_en_5_qs;
13488              reg_rdata_next[23:20] = bank1_info0_page_cfg_5_ecc_en_5_qs;
13489              reg_rdata_next[27:24] = bank1_info0_page_cfg_5_he_en_5_qs;
13490            end
13491      
13492            addr_hit[79]: begin
13493              reg_rdata_next[3:0] = bank1_info0_page_cfg_6_en_6_qs;
                   ==>
13494              reg_rdata_next[7:4] = bank1_info0_page_cfg_6_rd_en_6_qs;
13495              reg_rdata_next[11:8] = bank1_info0_page_cfg_6_prog_en_6_qs;
13496              reg_rdata_next[15:12] = bank1_info0_page_cfg_6_erase_en_6_qs;
13497              reg_rdata_next[19:16] = bank1_info0_page_cfg_6_scramble_en_6_qs;
13498              reg_rdata_next[23:20] = bank1_info0_page_cfg_6_ecc_en_6_qs;
13499              reg_rdata_next[27:24] = bank1_info0_page_cfg_6_he_en_6_qs;
13500            end
13501      
13502            addr_hit[80]: begin
13503              reg_rdata_next[3:0] = bank1_info0_page_cfg_7_en_7_qs;
                   ==>
13504              reg_rdata_next[7:4] = bank1_info0_page_cfg_7_rd_en_7_qs;
13505              reg_rdata_next[11:8] = bank1_info0_page_cfg_7_prog_en_7_qs;
13506              reg_rdata_next[15:12] = bank1_info0_page_cfg_7_erase_en_7_qs;
13507              reg_rdata_next[19:16] = bank1_info0_page_cfg_7_scramble_en_7_qs;
13508              reg_rdata_next[23:20] = bank1_info0_page_cfg_7_ecc_en_7_qs;
13509              reg_rdata_next[27:24] = bank1_info0_page_cfg_7_he_en_7_qs;
13510            end
13511      
13512            addr_hit[81]: begin
13513              reg_rdata_next[3:0] = bank1_info0_page_cfg_8_en_8_qs;
                   ==>
13514              reg_rdata_next[7:4] = bank1_info0_page_cfg_8_rd_en_8_qs;
13515              reg_rdata_next[11:8] = bank1_info0_page_cfg_8_prog_en_8_qs;
13516              reg_rdata_next[15:12] = bank1_info0_page_cfg_8_erase_en_8_qs;
13517              reg_rdata_next[19:16] = bank1_info0_page_cfg_8_scramble_en_8_qs;
13518              reg_rdata_next[23:20] = bank1_info0_page_cfg_8_ecc_en_8_qs;
13519              reg_rdata_next[27:24] = bank1_info0_page_cfg_8_he_en_8_qs;
13520            end
13521      
13522            addr_hit[82]: begin
13523              reg_rdata_next[3:0] = bank1_info0_page_cfg_9_en_9_qs;
                   ==>
13524              reg_rdata_next[7:4] = bank1_info0_page_cfg_9_rd_en_9_qs;
13525              reg_rdata_next[11:8] = bank1_info0_page_cfg_9_prog_en_9_qs;
13526              reg_rdata_next[15:12] = bank1_info0_page_cfg_9_erase_en_9_qs;
13527              reg_rdata_next[19:16] = bank1_info0_page_cfg_9_scramble_en_9_qs;
13528              reg_rdata_next[23:20] = bank1_info0_page_cfg_9_ecc_en_9_qs;
13529              reg_rdata_next[27:24] = bank1_info0_page_cfg_9_he_en_9_qs;
13530            end
13531      
13532            addr_hit[83]: begin
13533              reg_rdata_next[0] = bank1_info1_regwen_qs;
                   ==>
13534            end
13535      
13536            addr_hit[84]: begin
13537              reg_rdata_next[3:0] = bank1_info1_page_cfg_en_0_qs;
                   ==>
13538              reg_rdata_next[7:4] = bank1_info1_page_cfg_rd_en_0_qs;
13539              reg_rdata_next[11:8] = bank1_info1_page_cfg_prog_en_0_qs;
13540              reg_rdata_next[15:12] = bank1_info1_page_cfg_erase_en_0_qs;
13541              reg_rdata_next[19:16] = bank1_info1_page_cfg_scramble_en_0_qs;
13542              reg_rdata_next[23:20] = bank1_info1_page_cfg_ecc_en_0_qs;
13543              reg_rdata_next[27:24] = bank1_info1_page_cfg_he_en_0_qs;
13544            end
13545      
13546            addr_hit[85]: begin
13547              reg_rdata_next[0] = bank1_info2_regwen_0_qs;
                   ==>
13548            end
13549      
13550            addr_hit[86]: begin
13551              reg_rdata_next[0] = bank1_info2_regwen_1_qs;
                   ==>
13552            end
13553      
13554            addr_hit[87]: begin
13555              reg_rdata_next[3:0] = bank1_info2_page_cfg_0_en_0_qs;
                   ==>
13556              reg_rdata_next[7:4] = bank1_info2_page_cfg_0_rd_en_0_qs;
13557              reg_rdata_next[11:8] = bank1_info2_page_cfg_0_prog_en_0_qs;
13558              reg_rdata_next[15:12] = bank1_info2_page_cfg_0_erase_en_0_qs;
13559              reg_rdata_next[19:16] = bank1_info2_page_cfg_0_scramble_en_0_qs;
13560              reg_rdata_next[23:20] = bank1_info2_page_cfg_0_ecc_en_0_qs;
13561              reg_rdata_next[27:24] = bank1_info2_page_cfg_0_he_en_0_qs;
13562            end
13563      
13564            addr_hit[88]: begin
13565              reg_rdata_next[3:0] = bank1_info2_page_cfg_1_en_1_qs;
                   ==>
13566              reg_rdata_next[7:4] = bank1_info2_page_cfg_1_rd_en_1_qs;
13567              reg_rdata_next[11:8] = bank1_info2_page_cfg_1_prog_en_1_qs;
13568              reg_rdata_next[15:12] = bank1_info2_page_cfg_1_erase_en_1_qs;
13569              reg_rdata_next[19:16] = bank1_info2_page_cfg_1_scramble_en_1_qs;
13570              reg_rdata_next[23:20] = bank1_info2_page_cfg_1_ecc_en_1_qs;
13571              reg_rdata_next[27:24] = bank1_info2_page_cfg_1_he_en_1_qs;
13572            end
13573      
13574            addr_hit[89]: begin
13575              reg_rdata_next[3:0] = hw_info_cfg_override_scramble_dis_qs;
                   ==>
13576              reg_rdata_next[7:4] = hw_info_cfg_override_ecc_dis_qs;
13577            end
13578      
13579            addr_hit[90]: begin
13580              reg_rdata_next[0] = bank_cfg_regwen_qs;
                   ==>
13581            end
13582      
13583            addr_hit[91]: begin
13584              reg_rdata_next[0] = mp_bank_cfg_shadowed_erase_en_0_qs;
                   ==>
13585              reg_rdata_next[1] = mp_bank_cfg_shadowed_erase_en_1_qs;
13586            end
13587      
13588            addr_hit[92]: begin
13589              reg_rdata_next[0] = op_status_done_qs;
                   ==>
13590              reg_rdata_next[1] = op_status_err_qs;
13591            end
13592      
13593            addr_hit[93]: begin
13594              reg_rdata_next[0] = status_rd_full_qs;
                   ==>
13595              reg_rdata_next[1] = status_rd_empty_qs;
13596              reg_rdata_next[2] = status_prog_full_qs;
13597              reg_rdata_next[3] = status_prog_empty_qs;
13598              reg_rdata_next[4] = status_init_wip_qs;
13599              reg_rdata_next[5] = status_initialized_qs;
13600            end
13601      
13602            addr_hit[94]: begin
13603              reg_rdata_next[10:0] = debug_state_qs;
                   ==>
13604            end
13605      
13606            addr_hit[95]: begin
13607              reg_rdata_next[0] = err_code_op_err_qs;
                   ==>
13608              reg_rdata_next[1] = err_code_mp_err_qs;
13609              reg_rdata_next[2] = err_code_rd_err_qs;
13610              reg_rdata_next[3] = err_code_prog_err_qs;
13611              reg_rdata_next[4] = err_code_prog_win_err_qs;
13612              reg_rdata_next[5] = err_code_prog_type_err_qs;
13613              reg_rdata_next[6] = err_code_update_err_qs;
13614              reg_rdata_next[7] = err_code_macro_err_qs;
13615            end
13616      
13617            addr_hit[96]: begin
13618              reg_rdata_next[0] = std_fault_status_reg_intg_err_qs;
                   ==>
13619              reg_rdata_next[1] = std_fault_status_prog_intg_err_qs;
13620              reg_rdata_next[2] = std_fault_status_lcmgr_err_qs;
13621              reg_rdata_next[3] = std_fault_status_lcmgr_intg_err_qs;
13622              reg_rdata_next[4] = std_fault_status_arb_fsm_err_qs;
13623              reg_rdata_next[5] = std_fault_status_storage_err_qs;
13624              reg_rdata_next[6] = std_fault_status_phy_fsm_err_qs;
13625              reg_rdata_next[7] = std_fault_status_ctrl_cnt_err_qs;
13626              reg_rdata_next[8] = std_fault_status_fifo_err_qs;
13627            end
13628      
13629            addr_hit[97]: begin
13630              reg_rdata_next[0] = fault_status_op_err_qs;
                   ==>
13631              reg_rdata_next[1] = fault_status_mp_err_qs;
13632              reg_rdata_next[2] = fault_status_rd_err_qs;
13633              reg_rdata_next[3] = fault_status_prog_err_qs;
13634              reg_rdata_next[4] = fault_status_prog_win_err_qs;
13635              reg_rdata_next[5] = fault_status_prog_type_err_qs;
13636              reg_rdata_next[6] = fault_status_seed_err_qs;
13637              reg_rdata_next[7] = fault_status_phy_relbl_err_qs;
13638              reg_rdata_next[8] = fault_status_phy_storage_err_qs;
13639              reg_rdata_next[9] = fault_status_spurious_ack_qs;
13640              reg_rdata_next[10] = fault_status_arb_err_qs;
13641              reg_rdata_next[11] = fault_status_host_gnt_err_qs;
13642            end
13643      
13644            addr_hit[98]: begin
13645              reg_rdata_next[19:0] = err_addr_qs;
                   ==>
13646            end
13647      
13648            addr_hit[99]: begin
13649              reg_rdata_next[7:0] = ecc_single_err_cnt_ecc_single_err_cnt_0_qs;
                   ==>
13650              reg_rdata_next[15:8] = ecc_single_err_cnt_ecc_single_err_cnt_1_qs;
13651            end
13652      
13653            addr_hit[100]: begin
13654              reg_rdata_next[19:0] = ecc_single_err_addr_0_qs;
                   ==>
13655            end
13656      
13657            addr_hit[101]: begin
13658              reg_rdata_next[19:0] = ecc_single_err_addr_1_qs;
                   ==>
13659            end
13660      
13661            addr_hit[102]: begin
13662              reg_rdata_next[0] = phy_alert_cfg_alert_ack_qs;
                   ==>
13663              reg_rdata_next[1] = phy_alert_cfg_alert_trig_qs;
13664            end
13665      
13666            addr_hit[103]: begin
13667              reg_rdata_next[0] = phy_status_init_wip_qs;
                   ==>
13668              reg_rdata_next[1] = phy_status_prog_normal_avail_qs;
13669              reg_rdata_next[2] = phy_status_prog_repair_avail_qs;
13670            end
13671      
13672            addr_hit[104]: begin
13673              reg_rdata_next[31:0] = scratch_qs;
                   ==>
13674            end
13675      
13676            addr_hit[105]: begin
13677              reg_rdata_next[4:0] = fifo_lvl_prog_qs;
                   ==>
13678              reg_rdata_next[12:8] = fifo_lvl_rd_qs;
13679            end
13680      
13681            addr_hit[106]: begin
13682              reg_rdata_next[0] = fifo_rst_qs;
                   ==>
13683            end
13684      
13685            addr_hit[107]: begin
13686              reg_rdata_next[4:0] = curr_fifo_lvl_prog_qs;
                   ==>
13687              reg_rdata_next[12:8] = curr_fifo_lvl_rd_qs;
13688            end
13689      
13690            default: begin
13691              reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T1,T2,T3
addr_hit[1]	Covered	T1,T2,T3
addr_hit[2]	Covered	T1,T2,T3
addr_hit[3]	Covered	T1,T2,T3
addr_hit[4]	Covered	T1,T2,T3
addr_hit[5]	Covered	T1,T2,T3
addr_hit[6]	Covered	T1,T2,T3
addr_hit[7]	Covered	T1,T2,T3
addr_hit[8]	Covered	T1,T2,T3
addr_hit[9]	Covered	T1,T2,T3
addr_hit[10]	Covered	T1,T2,T3
addr_hit[11]	Covered	T1,T2,T3
addr_hit[12]	Covered	T1,T2,T3
addr_hit[13]	Covered	T1,T2,T3
addr_hit[14]	Covered	T1,T2,T3
addr_hit[15]	Covered	T1,T2,T3
addr_hit[16]	Covered	T1,T2,T3
addr_hit[17]	Covered	T1,T2,T3
addr_hit[18]	Covered	T1,T2,T3
addr_hit[19]	Covered	T1,T2,T3
addr_hit[20]	Covered	T1,T2,T3
addr_hit[21]	Covered	T1,T2,T3
addr_hit[22]	Covered	T1,T2,T3
addr_hit[23]	Covered	T1,T2,T3
addr_hit[24]	Covered	T1,T2,T3
addr_hit[25]	Covered	T1,T2,T3
addr_hit[26]	Covered	T1,T2,T3
addr_hit[27]	Covered	T1,T2,T3
addr_hit[28]	Covered	T1,T2,T3
addr_hit[29]	Covered	T1,T2,T3
addr_hit[30]	Covered	T1,T2,T3
addr_hit[31]	Covered	T1,T2,T3
addr_hit[32]	Covered	T1,T2,T3
addr_hit[33]	Covered	T1,T2,T3
addr_hit[34]	Covered	T1,T2,T3
addr_hit[35]	Covered	T1,T2,T3
addr_hit[36]	Covered	T1,T2,T3
addr_hit[37]	Covered	T1,T2,T3
addr_hit[38]	Covered	T1,T2,T3
addr_hit[39]	Covered	T1,T2,T3
addr_hit[40]	Covered	T1,T2,T3
addr_hit[41]	Covered	T1,T2,T3
addr_hit[42]	Covered	T1,T2,T3
addr_hit[43]	Covered	T1,T2,T3
addr_hit[44]	Covered	T1,T2,T3
addr_hit[45]	Covered	T1,T2,T3
addr_hit[46]	Covered	T1,T2,T3
addr_hit[47]	Covered	T1,T2,T3
addr_hit[48]	Covered	T1,T2,T3
addr_hit[49]	Covered	T1,T2,T3
addr_hit[50]	Covered	T1,T2,T3
addr_hit[51]	Covered	T1,T2,T3
addr_hit[52]	Covered	T1,T2,T3
addr_hit[53]	Covered	T1,T2,T3
addr_hit[54]	Covered	T1,T2,T3
addr_hit[55]	Covered	T1,T2,T3
addr_hit[56]	Covered	T1,T2,T3
addr_hit[57]	Covered	T1,T2,T3
addr_hit[58]	Covered	T1,T2,T3
addr_hit[59]	Covered	T1,T2,T3
addr_hit[60]	Covered	T1,T2,T3
addr_hit[61]	Covered	T1,T2,T3
addr_hit[62]	Covered	T1,T2,T3
addr_hit[63]	Covered	T1,T2,T3
addr_hit[64]	Covered	T1,T2,T3
addr_hit[65]	Covered	T1,T2,T3
addr_hit[66]	Covered	T1,T2,T3
addr_hit[67]	Covered	T1,T2,T3
addr_hit[68]	Covered	T1,T2,T3
addr_hit[69]	Covered	T1,T2,T3
addr_hit[70]	Covered	T1,T2,T3
addr_hit[71]	Covered	T1,T2,T3
addr_hit[72]	Covered	T1,T2,T3
addr_hit[73]	Covered	T1,T2,T3
addr_hit[74]	Covered	T1,T2,T3
addr_hit[75]	Covered	T1,T2,T3
addr_hit[76]	Covered	T1,T2,T3
addr_hit[77]	Covered	T1,T2,T3
addr_hit[78]	Covered	T1,T2,T3
addr_hit[79]	Covered	T1,T2,T3
addr_hit[80]	Covered	T1,T2,T3
addr_hit[81]	Covered	T1,T2,T3
addr_hit[82]	Covered	T1,T2,T3
addr_hit[83]	Covered	T1,T2,T3
addr_hit[84]	Covered	T1,T2,T3
addr_hit[85]	Covered	T1,T2,T3
addr_hit[86]	Covered	T1,T2,T3
addr_hit[87]	Covered	T1,T2,T3
addr_hit[88]	Covered	T1,T2,T3
addr_hit[89]	Covered	T1,T2,T3
addr_hit[90]	Covered	T1,T2,T3
addr_hit[91]	Covered	T1,T2,T3
addr_hit[92]	Covered	T1,T2,T3
addr_hit[93]	Covered	T1,T2,T3
addr_hit[94]	Covered	T1,T2,T3
addr_hit[95]	Covered	T1,T2,T3
addr_hit[96]	Covered	T1,T2,T3
addr_hit[97]	Covered	T1,T2,T3
addr_hit[98]	Covered	T1,T2,T3
addr_hit[99]	Covered	T1,T2,T3
addr_hit[100]	Covered	T1,T2,T3
addr_hit[101]	Covered	T1,T2,T3
addr_hit[102]	Covered	T1,T2,T3
addr_hit[103]	Covered	T1,T2,T3
addr_hit[104]	Covered	T1,T2,T3
addr_hit[105]	Covered	T1,T2,T3
addr_hit[106]	Covered	T1,T2,T3
addr_hit[107]	Covered	T1,T2,T3
default	Covered	T1,T2,T3



13701          if (!rst_ni) begin
               -1-  
13702            rst_done <= '0;
                 ==>
13703          end else begin
13704            rst_done <= 1'b1;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3



13709          if (!rst_shadowed_ni) begin
               -1-  
13710            shadow_rst_done <= '0;
                 ==>
13711          end else begin
13712            shadow_rst_done <= 1'b1;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

Assert Coverage for Module : flash_ctrl_core_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	390820167	26251256	0	0
reAfterRv	390820167	26251237	0	0
rePulse	390820167	23784703	0	0
wePulse	390820167	2466534	0	0

en2addrHit

Name	Attempts	Real Successes
Total	390820167	26251256
T1	3906	1210
T2	10848	2880
T3	1224	61
T4	890	12
T7	972	116
T12	2002	131
T17	1544	393
T18	1950	380
T19	2303	391
T20	1473	361

reAfterRv

Name	Attempts	Real Successes
Total	390820167	26251237
T1	3906	1210
T2	10848	2880
T3	1224	61
T4	890	12
T7	972	116
T12	2002	131
T17	1544	393
T18	1950	380
T19	2303	391
T20	1473	361

rePulse

Name	Attempts	Real Successes
Total	390820167	23784703
T1	3906	1125
T2	10848	771
T3	1224	57
T4	890	11
T7	972	65
T12	2002	100
T17	1544	287
T18	1950	274
T19	2303	285
T20	1473	291

wePulse

Name	Attempts	Real Successes
Total	390820167	2466534
T1	3906	85
T2	10848	2109
T3	1224	4
T4	890	1
T7	972	51
T12	2002	31
T17	1544	106
T18	1950	106
T19	2303	106
T20	1473	70