Module Definition
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Module Instance : tb.dut.u_reg_core.u_intr_test_prog_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_intr_test_prog_lvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_intr_test_rd_full

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_intr_test_rd_lvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_intr_test_op_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_intr_test_corr_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_alert_test_recov_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_alert_test_fatal_std_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_alert_test_fatal_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_alert_test_fatal_prim_flash_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_alert_test_recov_prim_flash_alert

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_ctrl_regwen

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_debug_state

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_curr_fifo_lvl_prog

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_reg_core.u_curr_fifo_lvl_rd

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
99.88 100.00 99.51 100.00 100.00 u_reg_core


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_subreg_ext
Line No.TotalCoveredPercent
TOTAL55100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T94 T95 T96  30 1/1 assign qre = re; Tests: T36 T77 T78 
Line Coverage for Instance : tb.dut.u_reg_core.u_intr_test_prog_empty
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T269 T111 T112  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_intr_test_prog_lvl
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T269 T111 T112  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_intr_test_rd_full
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T269 T111 T112  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_intr_test_rd_lvl
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T269 T111 T112  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_intr_test_op_done
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T269 T111 T112  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_intr_test_corr_err
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T269 T111 T112  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_recov_err
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T94 T95 T96  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_fatal_std_err
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T94 T95 T96  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_fatal_err
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T94 T95 T96  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_fatal_prim_flash_alert
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T94 T95 T96  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_alert_test_recov_prim_flash_alert
Line No.TotalCoveredPercent
TOTAL22100.00
CONT_ASSIGN2600
CONT_ASSIGN2700
CONT_ASSIGN2811100.00
CONT_ASSIGN2911100.00
CONT_ASSIGN3000

25 // between qs and ds 26 unreachable assign ds = d; 27 unreachable assign qs = d; 28 1/1 assign q = wd; Tests: T1 T2 T3  29 1/1 assign qe = we; Tests: T94 T95 T96  30 unreachable assign qre = re;
Line Coverage for Instance : tb.dut.u_reg_core.u_ctrl_regwen
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T112 T69 T115 
Line Coverage for Instance : tb.dut.u_reg_core.u_debug_state
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T77 T78 T79 
Line Coverage for Instance : tb.dut.u_reg_core.u_curr_fifo_lvl_prog
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T36 T37 T38 
Line Coverage for Instance : tb.dut.u_reg_core.u_curr_fifo_lvl_rd
Line No.TotalCoveredPercent
TOTAL33100.00
CONT_ASSIGN2611100.00
CONT_ASSIGN2711100.00
CONT_ASSIGN2800
CONT_ASSIGN2900
CONT_ASSIGN3011100.00

25 // between qs and ds 26 1/1 assign ds = d; Tests: T1 T2 T3  27 1/1 assign qs = d; Tests: T1 T2 T3  28 unreachable assign q = wd; 29 unreachable assign qe = we; 30 1/1 assign qre = re; Tests: T36 T37 T38 
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