Module Definition
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Module Instance : tb.dut

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
94.85 97.12 94.40 98.44 100.00 84.29


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
95.83 95.73 93.97 98.31 91.84 98.25 96.89


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
tb


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
flash_ctrl_core_csr_assert 100.00 100.00
gen_alert_senders[0].u_alert_sender 100.00 100.00
gen_alert_senders[1].u_alert_sender 100.00 100.00
gen_alert_senders[2].u_alert_sender 100.00 100.00
gen_alert_senders[3].u_alert_sender 100.00 100.00
gen_alert_senders[4].u_alert_sender 77.78 77.78
tlul_assert_device 99.65 100.00 100.00 98.95
u_ctrl_arb 100.00 100.00 100.00 100.00 100.00 100.00
u_disable_buf 100.00 100.00 100.00
u_eflash 97.26 98.05 93.25 99.49 96.43 99.40 96.96
u_exec_en_buf 100.00 100.00
u_flash_ctrl_erase 100.00 100.00 100.00 100.00
u_flash_ctrl_prog 97.88 100.00 97.06 100.00 94.44
u_flash_ctrl_rd 94.44 83.02 93.94 100.00 100.00 95.24
u_flash_hw_if 96.34 99.02 94.44 95.83 92.11 96.62 100.00
u_flash_mp 99.69 100.00 98.77 100.00 100.00
u_intr_corr_err 93.75 100.00 75.00 100.00 100.00
u_intr_op_done 93.75 100.00 75.00 100.00 100.00
u_intr_prog_empty 86.94 90.00 77.78 80.00 100.00
u_intr_prog_lvl 86.94 90.00 77.78 80.00 100.00
u_intr_rd_full 86.94 90.00 77.78 80.00 100.00
u_intr_rd_lvl 86.94 90.00 77.78 80.00 100.00
u_lc_escalation_en_sync 100.00 100.00 100.00 100.00
u_lc_seed_hw_rd_en_sync 100.00 100.00 100.00 100.00
u_lfsr 100.00 100.00
u_prog_fifo 97.73 100.00 90.91 100.00 100.00
u_prog_tl_gate 86.16 100.00 89.29 57.14 96.88 87.50
u_reg_core 99.31 99.00 98.62 100.00 98.92 100.00
u_reg_idle 100.00 100.00 100.00
u_region_cfg 87.91 63.73 100.00 100.00
u_sw_rd_fifo 93.67 95.12 88.64 90.91 100.00
u_tl_adapter_eflash 93.13 92.89 80.86 97.66 94.25 100.00
u_tl_gate 85.54 100.00 89.29 57.14 93.75 87.50
u_to_prog_fifo 79.77 89.66 65.61 82.56 81.25
u_to_rd_fifo 86.03 87.86 75.35 80.00 86.96 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
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404 405 1/1 assign op_start = muxed_ctrl.start.q; Tests: T1 T2 T3  406 1/1 assign op_num_words = muxed_ctrl.num.q; Tests: T1 T2 T3  407 1/1 assign op_erase_type = flash_erase_e'(muxed_ctrl.erase_sel.q); Tests: T1 T2 T3  408 1/1 assign op_prog_type = flash_prog_e'(muxed_ctrl.prog_sel.q); Tests: T1 T2 T3  409 1/1 assign op_addr = muxed_addr[BusByteWidth +: BusAddrW]; Tests: T1 T2 T3  410 1/1 assign op_type = flash_op_e'(muxed_ctrl.op.q); Tests: T1 T2 T3  411 1/1 assign op_part = flash_part_e'(muxed_ctrl.partition_sel.q); Tests: T1 T2 T3  412 1/1 assign op_info_sel = muxed_ctrl.info_sel.q; Tests: T1 T2 T3  413 1/1 assign rd_op = op_type == FlashOpRead; Tests: T1 T2 T3  414 1/1 assign prog_op = op_type == FlashOpProgram; Tests: T1 T2 T3  415 1/1 assign erase_op = op_type == FlashOpErase; Tests: T1 T2 T3  416 1/1 assign sw_sel = if_sel == SwSel; Tests: T1 T2 T3  417 418 // hardware interface 419 flash_ctrl_lcmgr #( 420 .RndCnstAddrKey(RndCnstAddrKey), 421 .RndCnstDataKey(RndCnstDataKey), 422 .RndCnstAllSeeds(RndCnstAllSeeds) 423 ) u_flash_hw_if ( 424 .clk_i, 425 .rst_ni, 426 .clk_otp_i, 427 .rst_otp_ni, 428 429 .init_i(reg2hw.init), 430 .provision_en_i(lc_tx_test_true_strict(lc_seed_hw_rd_en)), 431 432 // combined disable 433 .disable_i(flash_disable[LcMgrDisableIdx]), 434 435 // interface to ctrl arb control ports 436 .ctrl_o(hw_ctrl), 437 .req_o(hw_req), 438 .addr_o(hw_addr), 439 .done_i(hw_done), 440 .err_i(hw_err), 441 442 // interface to ctrl_arb data ports 443 .wready_i(hw_wready), 444 .wvalid_o(hw_wvalid), 445 .wdata_o(hw_wdata), 446 447 // interface to hw interface read fifo 448 .rready_o(lcmgr_rready), 449 .rvalid_i(~sw_sel & rd_ctrl_wen), 450 .rdata_i(rd_ctrl_wdata), 451 452 // external rma request 453 .rma_req_i, 454 .rma_ack_o, 455 456 // outgoing seeds 457 .seeds_o(keymgr_o.seeds), 458 .seed_err_o(seed_err), 459 460 // phase indication 461 .phase_o(hw_phase), 462 463 // phy read buffer enable 464 .rd_buf_en_o(flash_phy_req.rd_buf_en), 465 466 // connection to otp 467 .otp_key_req_o(otp_o), 468 .otp_key_rsp_i(otp_i), 469 .addr_key_o(addr_key), 470 .data_key_o(data_key), 471 .rand_addr_key_o(rand_addr_key), 472 .rand_data_key_o(rand_data_key), 473 474 // entropy interface 475 .edn_req_o(lfsr_seed_en), 476 .edn_ack_i(1'b1), 477 .lfsr_en_o(lfsr_en), 478 .rand_i(rand_val), 479 480 // error indication 481 .fatal_err_o(lcmgr_err), 482 .intg_err_o(lcmgr_intg_err), 483 484 // disable access to flash storage after rma process 485 .dis_access_o(dis_access), 486 487 // init ongoing 488 .init_busy_o(ctrl_init_busy), 489 .initialized_o(ctrl_initialized), 490 491 .debug_state_o(hw2reg.debug_state.d) 492 ); 493 494 495 496 497 // Program FIFO 498 // Since the program and read FIFOs are never used at the same time, it should really be one 499 // FIFO with muxed inputs and outputs. This should be addressed once the flash integration 500 // strategy has been identified 501 1/1 assign prog_op_valid = op_start & prog_op; Tests: T1 T2 T3  502 503 tlul_pkg::tl_h2d_t prog_tl_h2d; 504 tlul_pkg::tl_d2h_t prog_tl_d2h; 505 506 // the program path also needs an lc gate to error back when flash is disabled. 507 // This is because tlul_adapter_sram does not actually have a way of signaling 508 // write errors, only read errors. 509 // SEC_CM: PROG_TL_LC_GATE.FSM.SPARSE 510 tlul_lc_gate u_prog_tl_gate ( 511 .clk_i, 512 .rst_ni, 513 .tl_h2d_i(tl_win_h2d[0]), 514 .tl_d2h_o(tl_win_d2h[0]), 515 .tl_h2d_o(prog_tl_h2d), 516 .tl_d2h_i(prog_tl_d2h), 517 .flush_req_i('0), 518 .flush_ack_o(), 519 .resp_pending_o(), 520 .lc_en_i(lc_ctrl_pkg::mubi4_to_lc_inv(flash_disable[ProgFifoIdx])), 521 .err_o(tl_prog_gate_intg_err) 522 ); 523 524 tlul_adapter_sram #( 525 .SramAw(1), //address unused 526 .SramDw(BusWidth), 527 .ByteAccess(0), //flash may not support byte access 528 .ErrOnRead(1), //reads not supported 529 .EnableDataIntgPt(1) //passthrough data integrity 530 ) u_to_prog_fifo ( 531 .clk_i, 532 .rst_ni, 533 .tl_i (prog_tl_h2d), 534 .tl_o (prog_tl_d2h), 535 .en_ifetch_i (prim_mubi_pkg::MuBi4False), 536 .req_o (sw_wvalid), 537 .req_type_o (), 538 .gnt_i (sw_wready), 539 .we_o (), 540 .addr_o (), 541 .wmask_o (), 542 .intg_error_o (), 543 .wdata_o (sw_wdata), 544 .rdata_i ('0), 545 .rvalid_i (1'b0), 546 .rerror_i (2'b0), 547 .compound_txn_in_progress_o (), 548 .readback_en_i (prim_mubi_pkg::MuBi4False), 549 .readback_error_o (), 550 .wr_collision_i (1'b0), 551 .write_pending_i (1'b0) 552 ); 553 554 prim_fifo_sync #( 555 .Width(BusFullWidth), 556 .Depth(ProgFifoDepth) 557 ) u_prog_fifo ( 558 .clk_i, 559 .rst_ni, 560 .clr_i (reg2hw.fifo_rst.q | fifo_clr | sw_ctrl_done), 561 .wvalid_i(prog_fifo_wvalid), 562 .wready_o(prog_fifo_wready), 563 .wdata_i (prog_fifo_wdata), 564 .depth_o (prog_fifo_depth), 565 .full_o (), 566 .rvalid_o(prog_fifo_rvalid), 567 .rready_i(prog_fifo_ren), 568 .rdata_o (prog_fifo_rdata), 569 .err_o () 570 ); 571 1/1 assign hw2reg.curr_fifo_lvl.prog.d = MaxFifoWidth'(prog_fifo_depth); Tests: T1 T2 T3  572 573 // Program handler is consumer of prog_fifo 574 logic [1:0] prog_type_en; 575 1/1 assign prog_type_en[FlashProgNormal] = flash_phy_rsp.prog_type_avail[FlashProgNormal] & Tests: T1 T2 T3  576 reg2hw.prog_type_en.normal.q; 577 1/1 assign prog_type_en[FlashProgRepair] = flash_phy_rsp.prog_type_avail[FlashProgRepair] & Tests: T1 T2 T3  578 reg2hw.prog_type_en.repair.q; 579 580 logic prog_cnt_err; 581 flash_ctrl_prog u_flash_ctrl_prog ( 582 .clk_i, 583 .rst_ni, 584 585 // Control interface 586 .op_start_i (prog_op_valid), 587 .op_num_words_i (op_num_words), 588 .op_done_o (prog_done), 589 .op_err_o (prog_err), 590 .op_addr_i (op_addr), 591 .op_addr_oob_i ('0), 592 .op_type_i (op_prog_type), 593 .type_avail_i (prog_type_en), 594 .op_err_addr_o (prog_err_addr), 595 .cnt_err_o (prog_cnt_err), 596 597 // FIFO Interface 598 .data_i (prog_fifo_rdata), 599 .data_rdy_i (prog_fifo_rvalid), 600 .data_rd_o (prog_fifo_ren), 601 602 // Flash Macro Interface 603 .flash_req_o (prog_flash_req), 604 .flash_addr_o (prog_flash_addr), 605 .flash_ovfl_o (prog_flash_ovfl), 606 .flash_data_o (flash_prog_data), 607 .flash_last_o (flash_prog_last), 608 .flash_type_o (flash_prog_type), 609 .flash_done_i (flash_prog_done), 610 .flash_prog_intg_err_i (flash_phy_rsp.prog_intg_err), 611 .flash_mp_err_i (flash_mp_err) 612 ); 613 614 615 616 // a read request is seen from software but a read operation is not enabled 617 // AND there are no pending entries to read from the fifo. 618 // This indicates software has issued a read when it should not have. 619 logic rd_no_op_d, rd_no_op_q; 620 logic sw_rd_op; 621 1/1 assign sw_rd_op = reg2hw.control.start.q & (reg2hw.control.op.q == FlashOpRead); Tests: T1 T2 T3  622 623 // If software ever attempts to read when the FIFO is empty AND if it has never 624 // initiated a transaction, OR when flash is disabled, then it is a read that 625 // can never complete, error back immediately. 626 1/1 assign rd_no_op_d = adapter_req & ((~sw_rd_op & ~sw_rfifo_rvalid) | Tests: T1 T2 T3  627 (prim_mubi_pkg::mubi4_test_true_loose(flash_disable[RdFifoIdx]))); 628 629 always_ff @(posedge clk_i or negedge rst_ni) begin 630 1/1 if (!rst_ni) begin Tests: T1 T2 T3  631 1/1 adapter_rvalid <= 1'b0; Tests: T1 T2 T3  632 1/1 rd_no_op_q <= 1'b0; Tests: T1 T2 T3  633 end else begin 634 1/1 adapter_rvalid <= adapter_req & sw_rfifo_rvalid; Tests: T1 T2 T3  635 1/1 rd_no_op_q <= rd_no_op_d; Tests: T1 T2 T3  636 end 637 end 638 639 // tlul adapter represents software's access interface to flash 640 tlul_adapter_sram #( 641 .SramAw(1), //address unused 642 .SramDw(BusWidth), 643 .ByteAccess(0), //flash may not support byte access 644 .ErrOnWrite(1), //writes not supported 645 .EnableDataIntgPt(1), 646 .SecFifoPtr(1) // SEC_CM: FIFO.CTR.REDUN 647 ) u_to_rd_fifo ( 648 .clk_i, 649 .rst_ni, 650 .tl_i (tl_win_h2d[1]), 651 .tl_o (tl_win_d2h[1]), 652 .en_ifetch_i (prim_mubi_pkg::MuBi4False), 653 .req_o (adapter_req), 654 .req_type_o (), 655 // if there is no valid read operation, don't hang the 656 // bus, just let things normally return 657 .gnt_i (sw_rfifo_rvalid | rd_no_op_d), 658 .we_o (), 659 .addr_o (), 660 .wmask_o (), 661 .wdata_o (), 662 .intg_error_o (adapter_fifo_err), 663 .rdata_i (sw_rfifo_rdata), 664 .rvalid_i (adapter_rvalid | rd_no_op_q), 665 .rerror_i ({rd_no_op_q, 1'b0}), 666 .compound_txn_in_progress_o (), 667 .readback_en_i (prim_mubi_pkg::MuBi4False), 668 .readback_error_o (), 669 .wr_collision_i (1'b0), 670 .write_pending_i (1'b0) 671 ); 672 673 1/1 assign sw_rfifo_wen = sw_sel & rd_ctrl_wen; Tests: T1 T2 T3  674 1/1 assign sw_rfifo_wdata = rd_ctrl_wdata; Tests: T1 T2 T3  675 1/1 assign sw_rfifo_rready = adapter_rvalid; Tests: T1 T2 T3  676 677 // the read fifo below is dedicated to the software read path. 678 prim_fifo_sync #( 679 .Width(BusFullWidth), 680 .Depth(RdFifoDepth) 681 ) u_sw_rd_fifo ( 682 .clk_i, 683 .rst_ni, 684 .clr_i (reg2hw.fifo_rst.q), 685 .wvalid_i(sw_rfifo_wen), 686 .wready_o(sw_rfifo_wready), 687 .wdata_i (sw_rfifo_wdata), 688 .full_o (sw_rfifo_full), 689 .depth_o (sw_rfifo_depth), 690 .rvalid_o(sw_rfifo_rvalid), 691 .rready_i(sw_rfifo_rready), 692 .rdata_o (sw_rfifo_rdata), 693 .err_o () 694 ); 695 1/1 assign hw2reg.curr_fifo_lvl.rd.d = sw_rfifo_depth; Tests: T1 T2 T3  696 697 logic rd_cnt_err; 698 // Read handler is consumer of rd_fifo 699 1/1 assign rd_op_valid = op_start & rd_op; Tests: T1 T2 T3  700 flash_ctrl_rd u_flash_ctrl_rd ( 701 .clk_i, 702 .rst_ni, 703 704 // To arbiter Interface 705 .op_start_i (rd_op_valid), 706 .op_num_words_i (op_num_words), 707 .op_done_o (rd_done), 708 .op_err_o (rd_err), 709 .op_err_addr_o (rd_err_addr), 710 .op_addr_i (op_addr), 711 .op_addr_oob_i ('0), 712 .cnt_err_o (rd_cnt_err), 713 714 // FIFO Interface 715 .data_rdy_i (sw_sel ? sw_rfifo_wready : lcmgr_rready), 716 .data_o (rd_ctrl_wdata), 717 .data_wr_o (rd_ctrl_wen), 718 719 // Flash Macro Interface 720 .flash_req_o (rd_flash_req), 721 .flash_addr_o (rd_flash_addr), 722 .flash_ovfl_o (rd_flash_ovfl), 723 .flash_data_i (flash_rd_data), 724 .flash_done_i (flash_rd_done), 725 .flash_mp_err_i (flash_mp_err), 726 .flash_rd_err_i (flash_rd_err) 727 ); 728 729 // Erase handler does not consume fifo 730 1/1 assign erase_op_valid = op_start & erase_op; Tests: T1 T2 T3  731 flash_ctrl_erase u_flash_ctrl_erase ( 732 // Software Interface 733 .op_start_i (erase_op_valid), 734 .op_type_i (op_erase_type), 735 .op_done_o (erase_done), 736 .op_err_o (erase_err), 737 .op_addr_i (op_addr), 738 .op_addr_oob_i ('0), 739 .op_err_addr_o (erase_err_addr), 740 741 // Flash Macro Interface 742 .flash_req_o (erase_flash_req), 743 .flash_addr_o (erase_flash_addr), 744 .flash_op_o (erase_flash_type), 745 .flash_done_i (flash_erase_done), 746 .flash_mp_err_i (flash_mp_err) 747 ); 748 749 // Final muxing to flash macro module 750 always_comb begin 751 1/1 unique case (op_type) Tests: T1 T2 T3  752 FlashOpRead: begin 753 1/1 flash_req = rd_flash_req; Tests: T1 T2 T3  754 1/1 flash_addr = rd_flash_addr; Tests: T1 T2 T3  755 end 756 FlashOpProgram: begin 757 1/1 flash_req = prog_flash_req; Tests: T3 T7 T19  758 1/1 flash_addr = prog_flash_addr; Tests: T3 T7 T19  759 end 760 FlashOpErase: begin 761 1/1 flash_req = erase_flash_req; Tests: T3 T15 T27  762 1/1 flash_addr = erase_flash_addr; Tests: T3 T15 T27  763 end 764 default: begin 765 flash_req = 1'b0; 766 flash_addr = '0; 767 end 768 endcase // unique case (op_type) 769 end 770 771 772 773 ////////////////////////////////////// 774 // Info partition properties configuration 775 ////////////////////////////////////// 776 777 778 ////////////////////////////////////// 779 // flash memory properties 780 ////////////////////////////////////// 781 // direct assignment since prog/rd/erase_ctrl do not make use of op_part 782 flash_part_e flash_part_sel; 783 logic [InfoTypesWidth-1:0] flash_info_sel; 784 1/1 assign flash_part_sel = op_part; Tests: T1 T2 T3  785 1/1 assign flash_info_sel = op_info_sel; Tests: T1 T2 T3  786 787 // tie off hardware clear path 788 assign hw2reg.erase_suspend.d = 1'b0; 789 790 // Flash memory Properties 791 // Memory property is page based and thus should use phy addressing 792 // This should move to flash_phy long term 793 lc_ctrl_pkg::lc_tx_t lc_escalate_en; 794 flash_mp u_flash_mp ( 795 .clk_i, 796 .rst_ni, 797 798 // This is only used in SVAs, hence we do not have to feed in a copy. 799 .lc_escalate_en_i(lc_escalate_en), 800 801 // disable flash through memory protection 802 .flash_disable_i(flash_disable[MpDisableIdx]), 803 804 // hw info configuration overrides 805 .hw_info_scramble_dis_i(mubi4_t'(reg2hw.hw_info_cfg_override.scramble_dis.q)), 806 .hw_info_ecc_dis_i(mubi4_t'(reg2hw.hw_info_cfg_override.ecc_dis.q)), 807 808 // arbiter interface selection 809 .if_sel_i(if_sel), 810 811 // sw configuration for data partition 812 .region_cfgs_i(region_cfgs), 813 .bank_cfgs_i(bank_cfgs), 814 815 // sw configuration for info partition 816 .info_page_cfgs_i(info_page_cfgs), 817 818 // read / prog / erase controls 819 .req_i(flash_req), 820 .phase_i(phase), 821 .req_addr_i(flash_addr[BusAddrW-1 -: AllPagesW]), 822 .req_part_i(flash_part_sel), 823 .info_sel_i(flash_info_sel), 824 .addr_ovfl_i(rd_flash_ovfl | prog_flash_ovfl), 825 .rd_i(rd_op), 826 .prog_i(prog_op), 827 .pg_erase_i(erase_op & (erase_flash_type == FlashErasePage)), 828 .bk_erase_i(erase_op & (erase_flash_type == FlashEraseBank)), 829 .erase_suspend_i(reg2hw.erase_suspend), 830 .erase_suspend_done_o(hw2reg.erase_suspend.de), 831 .rd_done_o(flash_rd_done), 832 .prog_done_o(flash_prog_done), 833 .erase_done_o(flash_erase_done), 834 .error_o(flash_mp_err), 835 836 // flash phy interface 837 .req_o(flash_phy_req.req), 838 .scramble_en_o(flash_phy_req.scramble_en), 839 .ecc_en_o(flash_phy_req.ecc_en), 840 .he_en_o(flash_phy_req.he_en), 841 .rd_o(flash_phy_req.rd), 842 .prog_o(flash_phy_req.prog), 843 .pg_erase_o(flash_phy_req.pg_erase), 844 .bk_erase_o(flash_phy_req.bk_erase), 845 .erase_suspend_o(flash_phy_req.erase_suspend), 846 .rd_done_i(flash_phy_rsp.rd_done), 847 .prog_done_i(flash_phy_rsp.prog_done), 848 .erase_done_i(flash_phy_rsp.erase_done) 849 ); 850 851 852 // software interface feedback 853 // most values (other than flash_phy_busy) should only update when software operations 854 // are actually selected 855 assign hw2reg.op_status.done.d = 1'b1; 856 1/1 assign hw2reg.op_status.done.de = sw_ctrl_done; Tests: T1 T2 T3  857 assign hw2reg.op_status.err.d = 1'b1; 858 1/1 assign hw2reg.op_status.err.de = |sw_ctrl_err; Tests: T1 T2 T3  859 1/1 assign hw2reg.status.rd_full.d = sw_rfifo_full; Tests: T1 T2 T3  860 1/1 assign hw2reg.status.rd_full.de = sw_sel; Tests: T1 T2 T3  861 1/1 assign hw2reg.status.rd_empty.d = ~sw_rfifo_rvalid; Tests: T1 T2 T3  862 1/1 assign hw2reg.status.rd_empty.de = sw_sel; Tests: T1 T2 T3  863 1/1 assign hw2reg.status.prog_full.d = ~prog_fifo_wready; Tests: T1 T2 T3  864 1/1 assign hw2reg.status.prog_full.de = sw_sel; Tests: T1 T2 T3  865 1/1 assign hw2reg.status.prog_empty.d = ~prog_fifo_rvalid; Tests: T1 T2 T3  866 1/1 assign hw2reg.status.prog_empty.de = sw_sel; Tests: T1 T2 T3  867 1/1 assign hw2reg.status.init_wip.d = flash_phy_busy | ctrl_init_busy; Tests: T1 T2 T3  868 assign hw2reg.status.init_wip.de = 1'b1; 869 1/1 assign hw2reg.status.initialized.d = ctrl_initialized & ~flash_phy_busy; Tests: T1 T2 T3  870 assign hw2reg.status.initialized.de = 1'b1; 871 assign hw2reg.control.start.d = 1'b0; 872 1/1 assign hw2reg.control.start.de = sw_ctrl_done; Tests: T1 T2 T3  873 // if software operation selected, based on transaction start 874 // if software operation not selected, software is free to change contents 875 1/1 assign hw2reg.ctrl_regwen.d = sw_sel ? !op_start : 1'b1; Tests: T1 T2 T3  876 877 // phy status 878 1/1 assign hw2reg.phy_status.init_wip.d = flash_phy_busy; Tests: T1 T2 T3  879 assign hw2reg.phy_status.init_wip.de = 1'b1; 880 0/1 ==> assign hw2reg.phy_status.prog_normal_avail.d = flash_phy_rsp.prog_type_avail[FlashProgNormal]; 881 assign hw2reg.phy_status.prog_normal_avail.de = 1'b1; 882 0/1 ==> assign hw2reg.phy_status.prog_repair_avail.d = flash_phy_rsp.prog_type_avail[FlashProgRepair]; 883 assign hw2reg.phy_status.prog_repair_avail.de = 1'b1; 884 885 // Flash Interface 886 1/1 assign flash_phy_req.addr = flash_addr; Tests: T1 T2 T3  887 1/1 assign flash_phy_req.part = flash_part_sel; Tests: T1 T2 T3  888 1/1 assign flash_phy_req.info_sel = flash_info_sel; Tests: T1 T2 T3  889 1/1 assign flash_phy_req.prog_type = flash_prog_type; Tests: T1 T2 T3  890 1/1 assign flash_phy_req.prog_data = flash_prog_data; Tests: T1 T2 T3  891 1/1 assign flash_phy_req.prog_last = flash_prog_last; Tests: T1 T2 T3  892 1/1 assign flash_phy_req.region_cfgs = region_cfgs; Tests: T1 T2 T3  893 1/1 assign flash_phy_req.addr_key = addr_key; Tests: T1 T2 T3  894 1/1 assign flash_phy_req.data_key = data_key; Tests: T1 T2 T3  895 1/1 assign flash_phy_req.rand_addr_key = rand_addr_key; Tests: T1 T2 T3  896 1/1 assign flash_phy_req.rand_data_key = rand_data_key; Tests: T1 T2 T3  897 1/1 assign flash_phy_req.alert_trig = reg2hw.phy_alert_cfg.alert_trig.q; Tests: T1 T2 T3  898 1/1 assign flash_phy_req.alert_ack = reg2hw.phy_alert_cfg.alert_ack.q; Tests: T1 T2 T3  899 1/1 assign flash_phy_req.jtag_req.tck = cio_tck_i; Tests: T4 T5 T6  900 1/1 assign flash_phy_req.jtag_req.tms = cio_tms_i; Tests: T4 T5 T6  901 1/1 assign flash_phy_req.jtag_req.tdi = cio_tdi_i; Tests: T4 T5 T6  902 assign flash_phy_req.jtag_req.trst_n = '0; 903 1/1 assign cio_tdo_o = flash_phy_rsp.jtag_rsp.tdo; Tests: T90 T91 T92  904 0/1 ==> assign cio_tdo_en_o = flash_phy_rsp.jtag_rsp.tdo_oe; 905 1/1 assign flash_rd_err = flash_phy_rsp.rd_err; Tests: T1 T2 T3  906 1/1 assign flash_rd_data = flash_phy_rsp.rd_data; Tests: T1 T2 T3  907 1/1 assign flash_phy_busy = flash_phy_rsp.init_busy; Tests: T1 T2 T3  908 909 910 // Interface to pwrmgr 911 // flash is not idle as long as there is a stateful operation ongoing 912 logic flash_idle_d; 913 1/1 assign flash_idle_d = ~(flash_phy_req.req & Tests: T1 T2 T3  914 (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase)); 915 916 prim_flop #( 917 .Width(1), 918 .ResetValue(1'b1) 919 ) u_reg_idle ( 920 .clk_i, 921 .rst_ni, 922 .d_i(flash_idle_d), 923 .q_o(pwrmgr_o.flash_idle) 924 ); 925 926 ////////////////////////////////////// 927 // Alert senders 928 ////////////////////////////////////// 929 930 931 logic [NumAlerts-1:0] alert_srcs; 932 logic [NumAlerts-1:0] alert_tests; 933 logic fatal_prim_flash_alert, recov_prim_flash_alert; 934 935 // An excessive number of recoverable errors may also indicate an attack 936 logic recov_err; 937 1/1 assign recov_err = (sw_ctrl_done & |sw_ctrl_err) | Tests: T1 T2 T3  938 flash_phy_rsp.macro_err | 939 update_err; 940 941 logic fatal_err; 942 1/1 assign fatal_err = |reg2hw.fault_status; Tests: T1 T2 T3  943 944 logic fatal_std_err; 945 1/1 assign fatal_std_err = |reg2hw.std_fault_status; Tests: T1 T2 T3  946 947 lc_ctrl_pkg::lc_tx_t local_esc; 948 1/1 assign local_esc = lc_ctrl_pkg::lc_tx_bool_to_lc_tx(fatal_std_err); Tests: T1 T2 T3  949 950 1/1 assign alert_srcs = { Tests: T1 T2 T3  951 recov_prim_flash_alert, 952 fatal_prim_flash_alert, 953 fatal_err, 954 fatal_std_err, 955 recov_err 956 }; 957 958 1/1 assign alert_tests = { Tests: T1 T2 T3  959 reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe, 960 reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe, 961 reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe, 962 reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe, 963 reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe 964 }; 965 966 // The alert generated for errors reported in the fault status CSR (fatal_err) is not fatal. 967 // This is to enable firmware dealing with multi-bit ECC errors (phy_relbl_err) as well as ICV 968 // (phy_storage_err) errors inside the PHY during firmware selection and verification. 969 // Once firmware has cleared the corresponding bits in the fault status CSR and the alert 970 // handler has acknowledged the alert, the prim_alert_sender will stop triggering the alert. 971 // After firmware has passed the firmware selection / verification stage, the alert handler 972 // config can be adjusted to still classify the alert as fatal on the receiver side. 973 // 974 // This doesn't hold for the other errors conditions reported in the fault status CSR. The 975 // corresponding bits in the register cannot be unset. The alert thus keeps triggering until 976 // reset for these bits. 977 // 978 // For more details, refer to lowRISC/OpenTitan#21353. 979 localparam logic [NumAlerts-1:0] IsFatal = {1'b0, 1'b1, 1'b0, 1'b1, 1'b0}; 980 for (genvar i = 0; i < NumAlerts; i++) begin : gen_alert_senders 981 prim_alert_sender #( 982 .AsyncOn(AlertAsyncOn[i]), 983 .IsFatal(IsFatal[i]) 984 ) u_alert_sender ( 985 .clk_i, 986 .rst_ni, 987 .alert_req_i(alert_srcs[i]), 988 .alert_test_i(alert_tests[i]), 989 .alert_ack_o(), 990 .alert_state_o(), 991 .alert_rx_i(alert_rx_i[i]), 992 .alert_tx_o(alert_tx_o[i]) 993 ); 994 end 995 996 ////////////////////////////////////// 997 // Flash Disable and execute enable 998 ////////////////////////////////////// 999 1000 prim_lc_sync #( 1001 .NumCopies(1) 1002 ) u_lc_escalation_en_sync ( 1003 .clk_i, 1004 .rst_ni, 1005 .lc_en_i(lc_escalate_en_i), 1006 .lc_en_o({lc_escalate_en}) 1007 ); 1008 1009 lc_ctrl_pkg::lc_tx_t escalate_en; 1010 // SEC_CM: MEM.CTRL.LOCAL_ESC 1011 1/1 assign escalate_en = lc_ctrl_pkg::lc_tx_or_hi(dis_access, local_esc); Tests: T1 T2 T3  1012 1013 // flash functional disable 1014 lc_ctrl_pkg::lc_tx_t lc_disable; 1015 1/1 assign lc_disable = lc_ctrl_pkg::lc_tx_or_hi(lc_escalate_en, escalate_en); Tests: T1 T2 T3  1016 1017 // Normally, faults (those registered in fault_status) should also cause flash access 1018 // to disable. However, most errors encountered by hardware during flash access 1019 // are registered as faults (since they functionally never happen). Out of an abundance 1020 // of caution for the first iteration, we will not kill flash access based on those 1021 // faults immediately just in case there are unexpected corner conditions. 1022 // In other words...cowardice. 1023 // SEC_CM: MEM.CTRL.GLOBAL_ESC 1024 // SEC_CM: MEM_DISABLE.CONFIG.MUBI 1025 mubi4_t lc_conv_disable; 1026 mubi4_t flash_disable_pre_buf; 1027 1/1 assign lc_conv_disable = lc_ctrl_pkg::lc_to_mubi4(lc_disable); Tests: T1 T2 T3  1028 1/1 assign flash_disable_pre_buf = prim_mubi_pkg::mubi4_or_hi( Tests: T1 T2 T3  1029 lc_conv_disable, 1030 mubi4_t'(reg2hw.dis.q)); 1031 1032 prim_mubi4_sync #( 1033 .NumCopies(int'(FlashDisableLast)), 1034 .AsyncOn(0) 1035 ) u_disable_buf ( 1036 .clk_i, 1037 .rst_ni, 1038 .mubi_i(flash_disable_pre_buf), 1039 .mubi_o(flash_disable) 1040 ); 1041 1042 1/1 assign flash_phy_req.flash_disable = flash_disable[PhyDisableIdx]; Tests: T1 T2 T3  1043 1044 logic [prim_mubi_pkg::MuBi4Width-1:0] sw_flash_exec_en; 1045 mubi4_t flash_exec_en; 1046 1047 // SEC_CM: EXEC.CONFIG.REDUN 1048 prim_sec_anchor_buf #( 1049 .Width(prim_mubi_pkg::MuBi4Width) 1050 ) u_exec_en_buf ( 1051 .in_i(prim_mubi_pkg::mubi4_bool_to_mubi(reg2hw.exec.q == unsigned'(ExecEn))), 1052 .out_o(sw_flash_exec_en) 1053 ); 1054 1055 mubi4_t disable_exec; 1056 1/1 assign disable_exec = mubi4_t'(~flash_disable[IFetchDisableIdx]); Tests: T1 T2 T3  1057 1/1 assign flash_exec_en = prim_mubi_pkg::mubi4_and_hi( Tests: T1 T2 T3  1058 disable_exec, 1059 mubi4_t'(sw_flash_exec_en) 1060 ); 1061 1062 ////////////////////////////////////// 1063 // Errors and Interrupts 1064 ////////////////////////////////////// 1065 1066 // all software interface errors are treated as synchronous errors 1067 assign hw2reg.err_code.op_err.d = 1'b1; 1068 assign hw2reg.err_code.mp_err.d = 1'b1; 1069 assign hw2reg.err_code.rd_err.d = 1'b1; 1070 assign hw2reg.err_code.prog_err.d = 1'b1; 1071 assign hw2reg.err_code.prog_win_err.d = 1'b1; 1072 assign hw2reg.err_code.prog_type_err.d = 1'b1; 1073 assign hw2reg.err_code.update_err.d = 1'b1; 1074 assign hw2reg.err_code.macro_err.d = 1'b1; 1075 1/1 assign hw2reg.err_code.op_err.de = sw_ctrl_err.invalid_op_err; Tests: T1 T2 T3  1076 1/1 assign hw2reg.err_code.mp_err.de = sw_ctrl_err.mp_err; Tests: T1 T2 T3  1077 1/1 assign hw2reg.err_code.rd_err.de = sw_ctrl_err.rd_err; Tests: T1 T2 T3  1078 1/1 assign hw2reg.err_code.prog_err.de = sw_ctrl_err.prog_err; Tests: T1 T2 T3  1079 1/1 assign hw2reg.err_code.prog_win_err.de = sw_ctrl_err.prog_win_err; Tests: T1 T2 T3  1080 1/1 assign hw2reg.err_code.prog_type_err.de = sw_ctrl_err.prog_type_err; Tests: T1 T2 T3  1081 1/1 assign hw2reg.err_code.update_err.de = update_err; Tests: T1 T2 T3  1082 0/1 ==> assign hw2reg.err_code.macro_err.de = flash_phy_rsp.macro_err; 1083 1/1 assign hw2reg.err_addr.d = {ctrl_err_addr, {BusByteWidth{1'h0}}}; Tests: T1 T2 T3  1084 1/1 assign hw2reg.err_addr.de = sw_ctrl_err.mp_err | Tests: T1 T2 T3  1085 sw_ctrl_err.rd_err | 1086 sw_ctrl_err.prog_err; 1087 1088 1089 // all hardware interface errors are considered faults 1090 // There are two types of faults 1091 // standard faults - things like fsm / counter / tlul integrity 1092 // custom faults - things like hardware interface not working correctly 1093 assign hw2reg.fault_status.op_err.d = 1'b1; 1094 assign hw2reg.fault_status.mp_err.d = 1'b1; 1095 assign hw2reg.fault_status.rd_err.d = 1'b1; 1096 assign hw2reg.fault_status.prog_err.d = 1'b1; 1097 assign hw2reg.fault_status.prog_win_err.d = 1'b1; 1098 assign hw2reg.fault_status.prog_type_err.d = 1'b1; 1099 assign hw2reg.fault_status.seed_err.d = 1'b1; 1100 assign hw2reg.fault_status.phy_relbl_err.d = 1'b1; 1101 assign hw2reg.fault_status.phy_storage_err.d = 1'b1; 1102 assign hw2reg.fault_status.spurious_ack.d = 1'b1; 1103 assign hw2reg.fault_status.arb_err.d = 1'b1; 1104 assign hw2reg.fault_status.host_gnt_err.d = 1'b1; 1105 1/1 assign hw2reg.fault_status.op_err.de = hw_err.invalid_op_err; Tests: T1 T2 T3  1106 1/1 assign hw2reg.fault_status.mp_err.de = hw_err.mp_err; Tests: T1 T2 T3  1107 1/1 assign hw2reg.fault_status.rd_err.de = hw_err.rd_err; Tests: T1 T2 T3  1108 1/1 assign hw2reg.fault_status.prog_err.de = hw_err.prog_err; Tests: T1 T2 T3  1109 1/1 assign hw2reg.fault_status.prog_win_err.de = hw_err.prog_win_err; Tests: T1 T2 T3  1110 1/1 assign hw2reg.fault_status.prog_type_err.de = hw_err.prog_type_err; Tests: T1 T2 T3  1111 1/1 assign hw2reg.fault_status.seed_err.de = seed_err; Tests: T1 T2 T3  1112 1/1 assign hw2reg.fault_status.phy_relbl_err.de = flash_phy_rsp.storage_relbl_err; Tests: T1 T2 T3  1113 1/1 assign hw2reg.fault_status.phy_storage_err.de = flash_phy_rsp.storage_intg_err; Tests: T1 T2 T3  1114 1/1 assign hw2reg.fault_status.spurious_ack.de = flash_phy_rsp.spurious_ack; Tests: T1 T2 T3  1115 1/1 assign hw2reg.fault_status.arb_err.de = flash_phy_rsp.arb_err; Tests: T1 T2 T3  1116 1/1 assign hw2reg.fault_status.host_gnt_err.de = flash_phy_rsp.host_gnt_err; Tests: T1 T2 T3  1117 1118 // standard faults 1119 assign hw2reg.std_fault_status.reg_intg_err.d = 1'b1; 1120 assign hw2reg.std_fault_status.prog_intg_err.d = 1'b1; 1121 assign hw2reg.std_fault_status.lcmgr_err.d = 1'b1; 1122 assign hw2reg.std_fault_status.lcmgr_intg_err.d = 1'b1; 1123 assign hw2reg.std_fault_status.arb_fsm_err.d = 1'b1; 1124 assign hw2reg.std_fault_status.storage_err.d = 1'b1; 1125 assign hw2reg.std_fault_status.phy_fsm_err.d = 1'b1; 1126 assign hw2reg.std_fault_status.ctrl_cnt_err.d = 1'b1; 1127 assign hw2reg.std_fault_status.fifo_err.d = 1'b1; 1128 1/1 assign hw2reg.std_fault_status.reg_intg_err.de = intg_err | eflash_cmd_intg_err | Tests: T1 T2 T3  1129 tl_gate_intg_err | tl_prog_gate_intg_err; 1130 1/1 assign hw2reg.std_fault_status.prog_intg_err.de = flash_phy_rsp.prog_intg_err; Tests: T1 T2 T3  1131 1/1 assign hw2reg.std_fault_status.lcmgr_err.de = lcmgr_err; Tests: T1 T2 T3  1132 1/1 assign hw2reg.std_fault_status.lcmgr_intg_err.de = lcmgr_intg_err; Tests: T1 T2 T3  1133 1/1 assign hw2reg.std_fault_status.arb_fsm_err.de = arb_fsm_err; Tests: T1 T2 T3  1134 1/1 assign hw2reg.std_fault_status.storage_err.de = storage_err; Tests: T1 T2 T3  1135 1/1 assign hw2reg.std_fault_status.phy_fsm_err.de = flash_phy_rsp.fsm_err; Tests: T1 T2 T3  1136 1/1 assign hw2reg.std_fault_status.ctrl_cnt_err.de = rd_cnt_err | prog_cnt_err; Tests: T1 T2 T3  1137 1/1 assign hw2reg.std_fault_status.fifo_err.de = flash_phy_rsp.fifo_err | adapter_fifo_err; Tests: T1 T2 T3  1138 1139 // Correctable ECC count / address 1140 for (genvar i = 0; i < NumBanks; i++) begin : gen_ecc_single_err_reg 1141 2/2 assign hw2reg.ecc_single_err_cnt[i].de = flash_phy_rsp.ecc_single_err[i]; Tests: T1 T2 T3  | T1 T2 T3  1142 2/2 assign hw2reg.ecc_single_err_cnt[i].d = &reg2hw.ecc_single_err_cnt[i].q ? Tests: T1 T2 T3  | T1 T2 T3  1143 reg2hw.ecc_single_err_cnt[i].q : 1144 reg2hw.ecc_single_err_cnt[i].q + 1'b1; 1145 1146 2/2 assign hw2reg.ecc_single_err_addr[i].de = flash_phy_rsp.ecc_single_err[i]; Tests: T1 T2 T3  | T1 T2 T3  1147 2/2 assign hw2reg.ecc_single_err_addr[i].d = {flash_phy_rsp.ecc_addr[i], {BusByteWidth{1'b0}}}; Tests: T1 T2 T3  | T1 T2 T3  1148 end 1149 1150 logic [LastIntrIdx-1:0] intr_event; 1151 // Status types 1152 1/1 assign intr_event[ProgEmpty] = !prog_fifo_rvalid; Tests: T1 T2 T3  1153 // Check whether this FIFO has been drained to a certain level. 1154 1/1 assign intr_event[ProgLvl] = reg2hw.fifo_lvl.prog.q >= MaxFifoWidth'(prog_fifo_depth); Tests: T1 T2 T3  1155 1/1 assign intr_event[RdFull] = sw_rfifo_full; Tests: T1 T2 T3  1156 // Check whether this FIFO has been filled to a certain level. 1157 1/1 assign intr_event[RdLvl] = reg2hw.fifo_lvl.rd.q <= sw_rfifo_depth; Tests: T1 T2 T3  1158 // Event types 1159 1/1 assign intr_event[OpDone] = sw_ctrl_done; Tests: T1 T2 T3  1160 1/1 assign intr_event[CorrErr] = |flash_phy_rsp.ecc_single_err; Tests: T1 T2 T3  1161 1162 prim_intr_hw #( 1163 .Width(1), 1164 .IntrT ("Status") 1165 ) u_intr_prog_empty ( 1166 .clk_i, 1167 .rst_ni, 1168 .event_intr_i (intr_event[ProgEmpty]), 1169 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.prog_empty.q), 1170 .reg2hw_intr_test_q_i (reg2hw.intr_test.prog_empty.q), 1171 .reg2hw_intr_test_qe_i (reg2hw.intr_test.prog_empty.qe), 1172 .reg2hw_intr_state_q_i (reg2hw.intr_state.prog_empty.q), 1173 .hw2reg_intr_state_de_o (hw2reg.intr_state.prog_empty.de), 1174 .hw2reg_intr_state_d_o (hw2reg.intr_state.prog_empty.d), 1175 .intr_o (intr_prog_empty_o) 1176 ); 1177 1178 prim_intr_hw #( 1179 .Width(1), 1180 .IntrT ("Status") 1181 ) u_intr_prog_lvl ( 1182 .clk_i, 1183 .rst_ni, 1184 .event_intr_i (intr_event[ProgLvl]), 1185 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.prog_lvl.q), 1186 .reg2hw_intr_test_q_i (reg2hw.intr_test.prog_lvl.q), 1187 .reg2hw_intr_test_qe_i (reg2hw.intr_test.prog_lvl.qe), 1188 .reg2hw_intr_state_q_i (reg2hw.intr_state.prog_lvl.q), 1189 .hw2reg_intr_state_de_o (hw2reg.intr_state.prog_lvl.de), 1190 .hw2reg_intr_state_d_o (hw2reg.intr_state.prog_lvl.d), 1191 .intr_o (intr_prog_lvl_o) 1192 ); 1193 1194 prim_intr_hw #( 1195 .Width(1), 1196 .IntrT ("Status") 1197 ) u_intr_rd_full ( 1198 .clk_i, 1199 .rst_ni, 1200 .event_intr_i (intr_event[RdFull]), 1201 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rd_full.q), 1202 .reg2hw_intr_test_q_i (reg2hw.intr_test.rd_full.q), 1203 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rd_full.qe), 1204 .reg2hw_intr_state_q_i (reg2hw.intr_state.rd_full.q), 1205 .hw2reg_intr_state_de_o (hw2reg.intr_state.rd_full.de), 1206 .hw2reg_intr_state_d_o (hw2reg.intr_state.rd_full.d), 1207 .intr_o (intr_rd_full_o) 1208 ); 1209 1210 prim_intr_hw #( 1211 .Width(1), 1212 .IntrT ("Status") 1213 ) u_intr_rd_lvl ( 1214 .clk_i, 1215 .rst_ni, 1216 .event_intr_i (intr_event[RdLvl]), 1217 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.rd_lvl.q), 1218 .reg2hw_intr_test_q_i (reg2hw.intr_test.rd_lvl.q), 1219 .reg2hw_intr_test_qe_i (reg2hw.intr_test.rd_lvl.qe), 1220 .reg2hw_intr_state_q_i (reg2hw.intr_state.rd_lvl.q), 1221 .hw2reg_intr_state_de_o (hw2reg.intr_state.rd_lvl.de), 1222 .hw2reg_intr_state_d_o (hw2reg.intr_state.rd_lvl.d), 1223 .intr_o (intr_rd_lvl_o) 1224 ); 1225 1226 prim_intr_hw #( 1227 .Width(1), 1228 .IntrT ("Event") 1229 ) u_intr_op_done ( 1230 .clk_i, 1231 .rst_ni, 1232 .event_intr_i (intr_event[OpDone]), 1233 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.op_done.q), 1234 .reg2hw_intr_test_q_i (reg2hw.intr_test.op_done.q), 1235 .reg2hw_intr_test_qe_i (reg2hw.intr_test.op_done.qe), 1236 .reg2hw_intr_state_q_i (reg2hw.intr_state.op_done.q), 1237 .hw2reg_intr_state_de_o (hw2reg.intr_state.op_done.de), 1238 .hw2reg_intr_state_d_o (hw2reg.intr_state.op_done.d), 1239 .intr_o (intr_op_done_o) 1240 ); 1241 1242 prim_intr_hw #( 1243 .Width(1), 1244 .IntrT ("Event") 1245 ) u_intr_corr_err ( 1246 .clk_i, 1247 .rst_ni, 1248 .event_intr_i (intr_event[CorrErr]), 1249 .reg2hw_intr_enable_q_i (reg2hw.intr_enable.corr_err.q), 1250 .reg2hw_intr_test_q_i (reg2hw.intr_test.corr_err.q), 1251 .reg2hw_intr_test_qe_i (reg2hw.intr_test.corr_err.qe), 1252 .reg2hw_intr_state_q_i (reg2hw.intr_state.corr_err.q), 1253 .hw2reg_intr_state_de_o (hw2reg.intr_state.corr_err.de), 1254 .hw2reg_intr_state_d_o (hw2reg.intr_state.corr_err.d), 1255 .intr_o (intr_corr_err_o) 1256 ); 1257 1258 // Unused bits 1259 logic [BusByteWidth-1:0] unused_byte_sel; 1260 logic [top_pkg::TL_AW-1:0] unused_scratch; 1261 1262 // Unused signals 1263 1/1 assign unused_byte_sel = muxed_addr[BusByteWidth-1:0]; Tests: T1 T2 T3  1264 1/1 assign unused_scratch = reg2hw.scratch; Tests: T1 T2 T3  1265 1266 1267 ////////////////////////////////////// 1268 // flash phy module 1269 ////////////////////////////////////// 1270 logic flash_host_req; 1271 logic flash_host_req_rdy; 1272 logic flash_host_req_done; 1273 logic flash_host_rderr; 1274 logic [flash_ctrl_pkg::BusFullWidth-1:0] flash_host_rdata; 1275 logic [flash_ctrl_pkg::BusAddrW-1:0] flash_host_addr; 1276 1277 lc_ctrl_pkg::lc_tx_t host_enable; 1278 1279 // if flash disable is activated, error back from the adapter interface immediately 1280 1/1 assign host_enable = lc_ctrl_pkg::mubi4_to_lc_inv(flash_disable[HostDisableIdx]); Tests: T1 T2 T3  1281 1282 tlul_pkg::tl_h2d_t gate_tl_h2d; 1283 tlul_pkg::tl_d2h_t gate_tl_d2h; 1284 1285 // SEC_CM: MEM_TL_LC_GATE.FSM.SPARSE 1286 tlul_lc_gate u_tl_gate ( 1287 .clk_i, 1288 .rst_ni, 1289 .tl_h2d_i(mem_tl_i), 1290 .tl_d2h_o(mem_tl_o), 1291 .tl_h2d_o(gate_tl_h2d), 1292 .tl_d2h_i(gate_tl_d2h), 1293 .flush_req_i('0), 1294 .flush_ack_o(), 1295 .resp_pending_o(), 1296 .lc_en_i(host_enable), 1297 .err_o(tl_gate_intg_err) 1298 ); 1299 1300 // SEC_CM: HOST.BUS.INTEGRITY 1301 // SEC_CM: MEM.ADDR_INFECTION 1302 tlul_adapter_sram #( 1303 .SramAw(BusAddrW), 1304 .SramDw(BusWidth), 1305 .SramBusBankAW(BusBankAddrW), 1306 .Outstanding(2), 1307 .ByteAccess(0), 1308 .ErrOnWrite(1), 1309 .CmdIntgCheck(1), 1310 .EnableRspIntgGen(1), 1311 .EnableDataIntgGen(0), 1312 .EnableDataIntgPt(1), 1313 .SecFifoPtr(1), 1314 .DataXorAddr(1) 1315 ) u_tl_adapter_eflash ( 1316 .clk_i, 1317 .rst_ni, 1318 .tl_i (gate_tl_h2d), 1319 .tl_o (gate_tl_d2h), 1320 .en_ifetch_i (flash_exec_en), 1321 .req_o (flash_host_req), 1322 .req_type_o (), 1323 .gnt_i (flash_host_req_rdy), 1324 .we_o (), 1325 .addr_o (flash_host_addr), 1326 .wdata_o (), 1327 .wmask_o (), 1328 .intg_error_o (eflash_cmd_intg_err), 1329 .rdata_i (flash_host_rdata), 1330 .rvalid_i (flash_host_req_done), 1331 .rerror_i ({flash_host_rderr,1'b0}), 1332 .compound_txn_in_progress_o (), 1333 .readback_en_i (prim_mubi_pkg::MuBi4False), 1334 .readback_error_o (), 1335 .wr_collision_i (1'b0), 1336 .write_pending_i (1'b0) 1337 ); 1338 1339 flash_phy #( 1340 .SecScrambleEn(SecScrambleEn) 1341 ) u_eflash ( 1342 .clk_i, 1343 .rst_ni, 1344 .host_req_i (flash_host_req), 1345 .host_addr_i (flash_host_addr), 1346 .host_req_rdy_o (flash_host_req_rdy), 1347 .host_req_done_o (flash_host_req_done), 1348 .host_rderr_o (flash_host_rderr), 1349 .host_rdata_o (flash_host_rdata), 1350 .flash_ctrl_i (flash_phy_req), 1351 .flash_ctrl_o (flash_phy_rsp), 1352 .tl_i (prim_tl_i), 1353 .tl_o (prim_tl_o), 1354 .obs_ctrl_i, 1355 .fla_obs_o, 1356 .lc_nvm_debug_en_i, 1357 .flash_bist_enable_i, 1358 .flash_power_down_h_i, 1359 .flash_power_ready_h_i, 1360 .flash_test_mode_a_io, 1361 .flash_test_voltage_h_io, 1362 .fatal_prim_flash_alert_o(fatal_prim_flash_alert), 1363 .recov_prim_flash_alert_o(recov_prim_flash_alert), 1364 .scanmode_i, 1365 .scan_en_i, 1366 .scan_rst_ni 1367 ); 1368 1369 ///////////////////////////////// 1370 // Assertions 1371 ///////////////////////////////// 1372 1373 `ASSERT_KNOWN(TlDValidKnownO_A, core_tl_o.d_valid ) 1374 `ASSERT_KNOWN(TlAReadyKnownO_A, core_tl_o.a_ready ) 1375 `ASSERT_KNOWN_IF(RspPayLoad_A, core_tl_o, core_tl_o.d_valid) 1376 `ASSERT_KNOWN(PrimTlDValidKnownO_A, prim_tl_o.d_valid ) 1377 `ASSERT_KNOWN(PrimTlAReadyKnownO_A, prim_tl_o.a_ready ) 1378 `ASSERT_KNOWN_IF(PrimRspPayLoad_A, prim_tl_o, prim_tl_o.d_valid) 1379 `ASSERT_KNOWN(MemTlDValidKnownO_A, mem_tl_o.d_valid ) 1380 `ASSERT_KNOWN(MemTlAReadyKnownO_A, mem_tl_o.a_ready ) 1381 `ASSERT_KNOWN_IF(MemRspPayLoad_A, mem_tl_o, mem_tl_o.d_valid) 1382 `ASSERT_KNOWN(FlashKnownO_A, {flash_phy_req.req, flash_phy_req.rd, 1383 flash_phy_req.prog, flash_phy_req.pg_erase, 1384 flash_phy_req.bk_erase}) 1385 `ASSERT_KNOWN_IF(FlashAddrKnown_A, flash_phy_req.addr, flash_phy_req.req) 1386 `ASSERT_KNOWN_IF(FlashProgKnown_A, flash_phy_req.prog_data, 1387 flash_phy_req.prog & flash_phy_req.req) 1388 `ASSERT_KNOWN(IntrProgEmptyKnownO_A, intr_prog_empty_o) 1389 `ASSERT_KNOWN(IntrProgLvlKnownO_A, intr_prog_lvl_o ) 1390 `ASSERT_KNOWN(IntrProgRdFullKnownO_A, intr_rd_full_o ) 1391 `ASSERT_KNOWN(IntrRdLvlKnownO_A, intr_rd_lvl_o ) 1392 `ASSERT_KNOWN(IntrOpDoneKnownO_A, intr_op_done_o ) 1393 `ASSERT_KNOWN(IntrErrO_A, intr_corr_err_o ) 1394 `ASSERT_KNOWN(TdoKnown_A, cio_tdo_o ) 1395 `ASSERT(TdoEnIsOne_A, cio_tdo_en_o === 1'b1) 1396 1397 // combined indication that an operation has started 1398 // This is used only for assertions 1399 logic unused_op_valid; 1400 1/1 assign unused_op_valid = prog_op_valid | rd_op_valid | erase_op_valid; Tests: T1 T2 T3 

Cond Coverage for Module : flash_ctrl
TotalCoveredPercent
Conditions12511894.40
Logical12511894.40
Non-Logical00
Event00

 LINE       331
 EXPRESSION (sw_wvalid & prog_op_valid)
             ----1----   ------2------
-1--2-StatusTests
01CoveredT3,T7,T19
10CoveredT10,T25,T93
11CoveredT3,T7,T19

 LINE       413
 EXPRESSION (op_type == FlashOpRead)
            ------------1-----------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       414
 EXPRESSION (op_type == FlashOpProgram)
            -------------1-------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T7,T19

 LINE       415
 EXPRESSION (op_type == FlashOpErase)
            ------------1------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT3,T15,T27

 LINE       416
 EXPRESSION (if_sel == SwSel)
            --------1--------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       423
 EXPRESSION (((~sw_sel)) & rd_ctrl_wen)
             -----1-----   -----2-----
-1--2-StatusTests
01CoveredT1,T3,T18
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       501
 EXPRESSION (op_start & prog_op)
             ----1---   ---2---
-1--2-StatusTests
01CoveredT3,T7,T16
10CoveredT1,T2,T3
11CoveredT3,T7,T19

 LINE       557
 EXPRESSION (reg2hw.fifo_rst.q | fifo_clr | sw_ctrl_done)
             --------1--------   ----2---   ------3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT1,T3,T7
010CoveredT1,T2,T3
100Not Covered

 LINE       575
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgNormal] & reg2hw.prog_type_en.normal.q)
             -----------------------1----------------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT94,T95,T96
11CoveredT1,T2,T3

 LINE       577
 EXPRESSION (flash_phy_rsp.prog_type_avail[FlashProgRepair] & reg2hw.prog_type_en.repair.q)
             -----------------------1----------------------   --------------2-------------
-1--2-StatusTests
01Not Covered
10CoveredT97,T98,T99
11CoveredT1,T2,T3

 LINE       621
 EXPRESSION (reg2hw.control.start.q & (reg2hw.control.op.q == FlashOpRead))
             -----------1----------   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T19
11CoveredT1,T3,T18

 LINE       621
 SUB-EXPRESSION (reg2hw.control.op.q == FlashOpRead)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       634
 EXPRESSION (adapter_req & sw_rfifo_rvalid)
             -----1-----   -------2-------
-1--2-StatusTests
01CoveredT1,T3,T18
10CoveredT15,T10,T49
11CoveredT1,T3,T18

 LINE       647
 EXPRESSION (sw_rfifo_rvalid | rd_no_op_d)
             -------1-------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T50,T23
10CoveredT1,T3,T18

 LINE       647
 EXPRESSION (adapter_rvalid | rd_no_op_q)
             -------1------   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT10,T50,T23
10CoveredT1,T3,T18

 LINE       673
 EXPRESSION (sw_sel & rd_ctrl_wen)
             ---1--   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T18

 LINE       699
 EXPRESSION (op_start & rd_op)
             ----1---   --2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT3,T7,T19
11CoveredT1,T2,T3

 LINE       700
 EXPRESSION (sw_sel ? sw_rfifo_wready : lcmgr_rready)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       730
 EXPRESSION (op_start & erase_op)
             ----1---   ----2---
-1--2-StatusTests
01CoveredT3,T15,T27
10CoveredT1,T2,T3
11CoveredT3,T15,T27

 LINE       794
 EXPRESSION (rd_flash_ovfl | prog_flash_ovfl)
             ------1------   -------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT100,T101

 LINE       794
 EXPRESSION (erase_op & (erase_flash_type == FlashErasePage))
             ----1---   ------------------2-----------------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT102,T70,T71
11CoveredT3,T15,T27

 LINE       794
 SUB-EXPRESSION (erase_flash_type == FlashErasePage)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       794
 EXPRESSION (erase_op & (erase_flash_type == FlashEraseBank))
             ----1---   ------------------2-----------------
-1--2-StatusTests
01CoveredT7,T14,T19
10CoveredT3,T15,T27
11CoveredT102,T70,T71

 LINE       794
 SUB-EXPRESSION (erase_flash_type == FlashEraseBank)
                ------------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT7,T14,T19

 LINE       867
 EXPRESSION (flash_phy_busy | ctrl_init_busy)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T2,T3

 LINE       869
 EXPRESSION (ctrl_initialized & ((~flash_phy_busy)))
             --------1-------   ---------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T93,T103
11CoveredT1,T2,T3

 LINE       875
 EXPRESSION (sw_sel ? ((!op_start)) : 1'b1)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       913
 SUB-EXPRESSION (flash_phy_req.req & (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase))
                 --------1--------   -----------------------------------2----------------------------------
-1--2-StatusTests
01Not Covered
10CoveredT1,T2,T3
11CoveredT3,T7,T19

 LINE       913
 SUB-EXPRESSION (flash_phy_req.prog | flash_phy_req.pg_erase | flash_phy_req.bk_erase)
                 ---------1--------   -----------2----------   -----------3----------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT70,T71,T72
010CoveredT3,T15,T27
100CoveredT3,T7,T19

 LINE       937
 EXPRESSION ((sw_ctrl_done & ((|sw_ctrl_err))) | flash_phy_rsp.macro_err | update_err)
             ----------------1----------------   -----------2-----------   -----3----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001Not Covered
010Not Covered
100CoveredT27,T28,T30

 LINE       937
 SUB-EXPRESSION (sw_ctrl_done & ((|sw_ctrl_err)))
                 ------1-----   --------2-------
-1--2-StatusTests
01CoveredT28,T30,T9
10CoveredT1,T3,T7
11CoveredT27,T28,T30

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.recov_prim_flash_alert.q & reg2hw.alert_test.recov_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------
-1--2-StatusTests
01CoveredT104,T105,T106
10CoveredT1,T2,T3
11CoveredT104,T105,T106

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_prim_flash_alert.q & reg2hw.alert_test.fatal_prim_flash_alert.qe)
                 ---------------------1--------------------   ---------------------2---------------------
-1--2-StatusTests
01CoveredT104,T105,T106
10CoveredT1,T2,T3
11CoveredT104,T105,T106

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_err.q & reg2hw.alert_test.fatal_err.qe)
                 --------------1--------------   ---------------2--------------
-1--2-StatusTests
01CoveredT104,T105,T106
10CoveredT1,T2,T3
11CoveredT104,T105,T106

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.fatal_std_err.q & reg2hw.alert_test.fatal_std_err.qe)
                 ----------------1----------------   -----------------2----------------
-1--2-StatusTests
01CoveredT104,T105,T106
10CoveredT1,T2,T3
11CoveredT104,T105,T106

 LINE       958
 SUB-EXPRESSION (reg2hw.alert_test.recov_err.q & reg2hw.alert_test.recov_err.qe)
                 --------------1--------------   ---------------2--------------
-1--2-StatusTests
01CoveredT104,T105,T106
10CoveredT1,T2,T3
11CoveredT104,T105,T106

 LINE       1084
 EXPRESSION (sw_ctrl_err.mp_err | sw_ctrl_err.rd_err | sw_ctrl_err.prog_err)
             ---------1--------   ---------2--------   ----------3---------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT9
010CoveredT28,T29,T107
100CoveredT27,T30,T59

 LINE       1128
 EXPRESSION (intg_err | eflash_cmd_intg_err | tl_gate_intg_err | tl_prog_gate_intg_err)
             ----1---   ---------2---------   --------3-------   ----------4----------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT44,T47,T48
0010CoveredT44,T47,T48
0100CoveredT10,T23,T51
1000CoveredT44,T47,T48

 LINE       1136
 EXPRESSION (rd_cnt_err | prog_cnt_err)
             -----1----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT44,T47,T48
10CoveredT44,T47,T48

 LINE       1137
 EXPRESSION (flash_phy_rsp.fifo_err | adapter_fifo_err)
             -----------1----------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT44,T47,T48
10CoveredT44,T47,T48

 LINE       1142
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[0].q)) ? reg2hw.ecc_single_err_cnt[0].q : ((reg2hw.ecc_single_err_cnt[0].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T108,T109

 LINE       1142
 EXPRESSION (((&reg2hw.ecc_single_err_cnt[1].q)) ? reg2hw.ecc_single_err_cnt[1].q : ((reg2hw.ecc_single_err_cnt[1].q + 1'b1)))
             -----------------1-----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT41,T108,T109

 LINE       1400
 EXPRESSION (prog_op_valid | rd_op_valid | erase_op_valid)
             ------1------   -----2-----   -------3------
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT3,T15,T27
010CoveredT1,T2,T3
100CoveredT3,T7,T19

Toggle Coverage for Module : flash_ctrl
TotalCoveredPercent
Totals 122 111 90.98
Total Bits 2750 2707 98.44
Total Bits 0->1 1375 1354 98.47
Total Bits 1->0 1375 1353 98.40

Ports 122 111 90.98
Port Bits 2750 2707 98.44
Port Bits 0->1 1375 1354 98.47
Port Bits 1->0 1375 1353 98.40

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T19,T15,T26 Yes T1,T2,T3 INPUT
rst_shadowed_ni Yes Yes T19,T15,T26 Yes T1,T2,T3 INPUT
clk_otp_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_otp_ni Yes Yes T19,T15,T26 Yes T1,T2,T3 INPUT
lc_creator_seed_sw_rw_en_i[3:0] Yes Yes T7,T18,T27 Yes T1,T7,T18 INPUT
lc_owner_seed_sw_rw_en_i[3:0] Yes Yes T7,T19,T8 Yes T1,T7,T18 INPUT
lc_iso_part_sw_rd_en_i[3:0] Yes Yes T19,T26,T27 Yes T1,T7,T18 INPUT
lc_iso_part_sw_wr_en_i[3:0] Yes Yes T19,T26,T27 Yes T1,T7,T18 INPUT
lc_seed_hw_rd_en_i[3:0] Yes Yes T52,T110,T111 Yes T52,T110,T111 INPUT
lc_escalate_en_i[0] No No Yes T8,T87,T112 INPUT
lc_escalate_en_i[1] No Yes *T113,*T112,*T114 No INPUT
lc_escalate_en_i[2] No No Yes T8,T113,T112 INPUT
lc_escalate_en_i[3] No Yes T113,T112,T115 No INPUT
lc_nvm_debug_en_i[3:0] Yes Yes T52,T110,T111 Yes T52,T110,T5 INPUT
core_tl_i.d_ready Yes Yes T3,T14,T19 Yes T1,T2,T3 INPUT
core_tl_i.a_user.data_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_user.instr_type[3:0] Yes Yes T17,T24,T45 Yes T17,T24,T45 INPUT
core_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_mask[3:0] Yes Yes T1,T3,T7 Yes T1,T3,T7 INPUT
core_tl_i.a_address[31:0] Yes Yes T1,T7,T18 Yes T1,T3,T7 INPUT
core_tl_i.a_source[7:0] Yes Yes T3,T7,T18 Yes T3,T7,T18 INPUT
core_tl_i.a_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
core_tl_i.a_opcode[2:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_i.a_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
core_tl_o.a_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_error Yes Yes T1,T2,T3 Yes T19,T15,T26 OUTPUT
core_tl_o.d_user.data_intg[6:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[5:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_data[31:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_source[7:0] Yes Yes T1,T3,T7 Yes T1,T2,T3 OUTPUT
core_tl_o.d_size[1:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_opcode[0] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 OUTPUT
core_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
core_tl_o.d_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
prim_tl_i.d_ready Yes Yes T3,T14,T19 Yes T1,T2,T3 INPUT
prim_tl_i.a_user.data_intg[6:0] Yes Yes T28,T24,T52 Yes T17,T24,T116 INPUT
prim_tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T28,T24 Yes T22,T24,T11 INPUT
prim_tl_i.a_user.instr_type[3:0] Yes Yes T1,T28,T24 Yes T7,T28,T22 INPUT
prim_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_data[31:0] Yes Yes T17,T24,T11 Yes T1,T20,T24 INPUT
prim_tl_i.a_mask[3:0] Yes Yes T1,T24,T11 Yes T22,T24,T116 INPUT
prim_tl_i.a_address[31:0] Yes Yes T20,T28,T22 Yes T7,T28,T24 INPUT
prim_tl_i.a_source[7:0] Yes Yes T7,T24,T116 Yes T1,T24,T52 INPUT
prim_tl_i.a_size[1:0] Yes Yes T1,T7,T24 Yes T20,T17,T24 INPUT
prim_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
prim_tl_i.a_opcode[2:0] Yes Yes T1,T28,T17 Yes T28,T22,T24 INPUT
prim_tl_i.a_valid Yes Yes T117,T66,T67 Yes T117,T66,T67 INPUT
prim_tl_o.a_ready Yes Yes T117,T66,T67 Yes T117,T66,T67 OUTPUT
prim_tl_o.d_error Yes Yes T68,T118,T119 Yes T117,T67,T68 OUTPUT
prim_tl_o.d_user.data_intg[6:0] Yes Yes T66,T68,T118 Yes T66,T68,T118 OUTPUT
prim_tl_o.d_user.rsp_intg[5:0] Yes Yes *T117,*T66,*T67 Yes T117,T66,T67 OUTPUT
prim_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_data[31:0] Yes Yes T66,T68,T118 Yes T117,T66,T67 OUTPUT
prim_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_source[7:0] Yes Yes T117,T66,T67 Yes T117,T66,T67 OUTPUT
prim_tl_o.d_size[1:0] Yes Yes T117,T66,T67 Yes T117,T66,T67 OUTPUT
prim_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_opcode[0] Yes Yes *T117,*T66,*T67 Yes T117,T66,T67 OUTPUT
prim_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
prim_tl_o.d_valid Yes Yes T117,T66,T67 Yes T117,T66,T67 OUTPUT
mem_tl_i.d_ready Yes Yes T3,T14,T19 Yes T1,T2,T3 INPUT
mem_tl_i.a_user.data_intg[6:0] Yes Yes T15,T26,T24 Yes T15,T26,T24 INPUT
mem_tl_i.a_user.cmd_intg[6:0] Yes Yes T2,T14,T16 Yes T2,T14,T16 INPUT
mem_tl_i.a_user.instr_type[3:0] Yes Yes T14,T26,T24 Yes T14,T26,T4 INPUT
mem_tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_data[31:0] Yes Yes T26,T24,T120 Yes T15,T26,T4 INPUT
mem_tl_i.a_mask[3:0] Yes Yes T26,T24,T120 Yes T26,T4,T24 INPUT
mem_tl_i.a_address[31:0] Yes Yes T26,T24,T52 Yes T26,T24,T52 INPUT
mem_tl_i.a_source[7:0] Yes Yes T2,T14,T16 Yes T2,T14,T16 INPUT
mem_tl_i.a_size[1:0] Yes Yes T26,T24,T52 Yes T15,T26,T24 INPUT
mem_tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
mem_tl_i.a_opcode[2:0] Yes Yes T26,T24,T52 Yes T15,T26,T4 INPUT
mem_tl_i.a_valid Yes Yes T2,T14,T16 Yes T2,T14,T16 INPUT
mem_tl_o.a_ready Yes Yes T1,T2,T3 Yes T2,T14,T19 OUTPUT
mem_tl_o.d_error Yes Yes T1,T2,T3 Yes T14,T19,T8 OUTPUT
mem_tl_o.d_user.data_intg[6:0] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
mem_tl_o.d_user.rsp_intg[5:0] Yes Yes *T2,*T14,*T19 Yes T1,T2,T3 OUTPUT
mem_tl_o.d_user.rsp_intg[6] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_data[31:0] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
mem_tl_o.d_sink Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_source[7:0] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
mem_tl_o.d_size[1:0] Yes Yes T117,T67,T68 Yes T117,T67,T68 OUTPUT
mem_tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_opcode[0] Yes Yes *T117,*T67,*T68 Yes T117,T67,T68 OUTPUT
mem_tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
mem_tl_o.d_valid Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
otp_o.addr_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_o.data_req Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
otp_i.seed_valid Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_i.rand_key[127:0] Yes Yes T14,T19,T20 Yes T2,T7,T18 INPUT
otp_i.key[127:0] Yes Yes T7,T18,T19 Yes T1,T3,T7 INPUT
otp_i.addr_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
otp_i.data_ack Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rma_req_i[3:0] Yes Yes T76,T121,T77 Yes T122,T76,T123 INPUT
rma_seed_i[31:0] Yes Yes T124,T125,T126 Yes T123,T121,T77 INPUT
rma_ack_o[3:0] Yes Yes T127,T128,T129 Yes T124,T125,T126 OUTPUT
pwrmgr_o.flash_idle Yes Yes T3,T7,T19 Yes T3,T7,T19 OUTPUT
keymgr_o.seeds[0][0] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][1] Yes Yes T2,T16,T15 Yes T2,T16,T15 OUTPUT
keymgr_o.seeds[0][2] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[0][3] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][4] Yes Yes T16,T15,T26 Yes T16,T15,T26 OUTPUT
keymgr_o.seeds[0][5] Yes Yes T16,T15,T27 Yes T16,T15,T27 OUTPUT
keymgr_o.seeds[0][6] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][7] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][8] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][9] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][10] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][11] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][12] Yes Yes T14,T28,T52 Yes T14,T28,T52 OUTPUT
keymgr_o.seeds[0][13] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][14] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[0][15] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][16] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][17] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][18] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][19] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][20] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][21] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][22] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][23] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][24] Yes Yes T14,T4,T27 Yes T14,T4,T27 OUTPUT
keymgr_o.seeds[0][25] Yes Yes T14,T16,T26 Yes T14,T16,T26 OUTPUT
keymgr_o.seeds[0][26] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][27] Yes Yes T3,T16,T15 Yes T3,T16,T15 OUTPUT
keymgr_o.seeds[0][28] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][29] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][30] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][31] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][32] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][33] Yes Yes T15,T26,T4 Yes T15,T26,T4 OUTPUT
keymgr_o.seeds[0][34] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][35] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][36] Yes Yes T16,T15,T4 Yes T16,T15,T4 OUTPUT
keymgr_o.seeds[0][37] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][38] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][39] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][40] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][41] Yes Yes T14,T15,T28 Yes T14,T15,T28 OUTPUT
keymgr_o.seeds[0][42] Yes Yes T15,T26,T22 Yes T15,T26,T22 OUTPUT
keymgr_o.seeds[0][43] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][44] Yes Yes T2,T15,T26 Yes T2,T15,T26 OUTPUT
keymgr_o.seeds[0][45] Yes Yes T14,T16,T15 Yes T14,T16,T15 OUTPUT
keymgr_o.seeds[0][46] Yes Yes T2,T3,T26 Yes T2,T3,T26 OUTPUT
keymgr_o.seeds[0][47] Yes Yes T2,T16,T15 Yes T2,T16,T15 OUTPUT
keymgr_o.seeds[0][48] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[0][49] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][50] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][51] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][52] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][53] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][54] Yes Yes T2,T14,T15 Yes T2,T14,T15 OUTPUT
keymgr_o.seeds[0][55] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][56] Yes Yes T16,T26,T4 Yes T16,T26,T4 OUTPUT
keymgr_o.seeds[0][57] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][58] Yes Yes T15,T26,T27 Yes T15,T26,T27 OUTPUT
keymgr_o.seeds[0][59] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][60] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][61] Yes Yes T26,T4,T24 Yes T26,T4,T24 OUTPUT
keymgr_o.seeds[0][62] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][63] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][64] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][65] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][66] Yes Yes T3,T14,T28 Yes T3,T14,T28 OUTPUT
keymgr_o.seeds[0][67] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][68] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[0][69] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][70] Yes Yes T3,T14,T26 Yes T3,T14,T26 OUTPUT
keymgr_o.seeds[0][71] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][72] Yes Yes T15,T27,T24 Yes T15,T27,T24 OUTPUT
keymgr_o.seeds[0][73] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][74] Yes Yes T3,T15,T26 Yes T3,T15,T26 OUTPUT
keymgr_o.seeds[0][75] Yes Yes T3,T15,T27 Yes T3,T15,T27 OUTPUT
keymgr_o.seeds[0][76] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][77] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][78] Yes Yes T16,T15,T26 Yes T16,T15,T26 OUTPUT
keymgr_o.seeds[0][79] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][80] Yes Yes T3,T26,T4 Yes T3,T26,T4 OUTPUT
keymgr_o.seeds[0][81] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][82] Yes Yes T16,T27,T28 Yes T16,T27,T28 OUTPUT
keymgr_o.seeds[0][83] Yes Yes T2,T14,T27 Yes T2,T14,T27 OUTPUT
keymgr_o.seeds[0][84] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][85] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][86] Yes Yes T3,T15,T28 Yes T3,T15,T28 OUTPUT
keymgr_o.seeds[0][87] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][88] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][89] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][90] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][91] Yes Yes T2,T14,T15 Yes T2,T14,T15 OUTPUT
keymgr_o.seeds[0][92] Yes Yes T2,T16,T26 Yes T2,T16,T26 OUTPUT
keymgr_o.seeds[0][93] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][94] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][95] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][96] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][97] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][98] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][99] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][100] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][101] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][102] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][103] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][104] Yes Yes T2,T16,T4 Yes T2,T16,T4 OUTPUT
keymgr_o.seeds[0][105] Yes Yes T14,T16,T15 Yes T14,T16,T15 OUTPUT
keymgr_o.seeds[0][106] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][107] Yes Yes T2,T16,T24 Yes T2,T16,T24 OUTPUT
keymgr_o.seeds[0][108] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][109] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][110] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][111] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][112] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][113] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][114] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][115] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][116] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][117] Yes Yes T3,T14,T26 Yes T3,T14,T26 OUTPUT
keymgr_o.seeds[0][118] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][119] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][120] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][121] Yes Yes T3,T16,T4 Yes T3,T16,T4 OUTPUT
keymgr_o.seeds[0][122] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][123] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][124] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][125] Yes Yes T26,T4,T27 Yes T26,T4,T27 OUTPUT
keymgr_o.seeds[0][126] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][127] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][128] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][129] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][130] Yes Yes T14,T26,T4 Yes T14,T26,T4 OUTPUT
keymgr_o.seeds[0][131] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][132] Yes Yes T2,T3,T15 Yes T2,T3,T15 OUTPUT
keymgr_o.seeds[0][133] Yes Yes T2,T16,T26 Yes T2,T16,T26 OUTPUT
keymgr_o.seeds[0][134] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][135] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][136] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][137] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][138] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][139] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][140] Yes Yes T3,T16,T26 Yes T3,T16,T26 OUTPUT
keymgr_o.seeds[0][141] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][142] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][143] Yes Yes T16,T26,T27 Yes T16,T26,T27 OUTPUT
keymgr_o.seeds[0][144] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][145] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][146] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][147] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][148] Yes Yes T16,T15,T26 Yes T16,T15,T26 OUTPUT
keymgr_o.seeds[0][149] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][150] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][151] Yes Yes T2,T26,T4 Yes T2,T26,T4 OUTPUT
keymgr_o.seeds[0][152] Yes Yes T2,T14,T26 Yes T2,T14,T26 OUTPUT
keymgr_o.seeds[0][153] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][154] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][155] Yes Yes T2,T16,T26 Yes T2,T16,T26 OUTPUT
keymgr_o.seeds[0][156] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][157] Yes Yes T14,T16,T15 Yes T14,T16,T15 OUTPUT
keymgr_o.seeds[0][158] Yes Yes T3,T14,T4 Yes T3,T14,T4 OUTPUT
keymgr_o.seeds[0][159] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[0][160] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][161] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[0][162] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][163] Yes Yes T14,T15,T26 Yes T14,T15,T26 OUTPUT
keymgr_o.seeds[0][164] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][165] Yes Yes T2,T3,T26 Yes T2,T3,T26 OUTPUT
keymgr_o.seeds[0][166] Yes Yes T2,T15,T26 Yes T2,T15,T26 OUTPUT
keymgr_o.seeds[0][167] Yes Yes T2,T26,T22 Yes T2,T26,T22 OUTPUT
keymgr_o.seeds[0][168] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][169] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][170] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][171] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][172] Yes Yes T2,T15,T26 Yes T2,T15,T26 OUTPUT
keymgr_o.seeds[0][173] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][174] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][175] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[0][176] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][177] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][178] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][179] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][180] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][181] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][182] Yes Yes T2,T3,T15 Yes T2,T3,T15 OUTPUT
keymgr_o.seeds[0][183] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][184] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][185] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][186] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][187] Yes Yes T2,T3,T15 Yes T2,T3,T15 OUTPUT
keymgr_o.seeds[0][188] Yes Yes T16,T15,T26 Yes T16,T15,T26 OUTPUT
keymgr_o.seeds[0][190:189] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][191] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[0][192] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][193] Yes Yes T2,T16,T15 Yes T2,T16,T15 OUTPUT
keymgr_o.seeds[0][194] Yes Yes T16,T26,T27 Yes T16,T26,T27 OUTPUT
keymgr_o.seeds[0][195] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][196] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[0][197] Yes Yes T2,T26,T27 Yes T2,T26,T27 OUTPUT
keymgr_o.seeds[0][198] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][199] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][200] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][201] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[0][202] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][203] Yes Yes T2,T14,T15 Yes T2,T14,T15 OUTPUT
keymgr_o.seeds[0][204] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[0][205] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][206] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][207] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][208] Yes Yes T4,T27,T28 Yes T4,T27,T28 OUTPUT
keymgr_o.seeds[0][209] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][210] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][211] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][212] Yes Yes T2,T26,T4 Yes T2,T26,T4 OUTPUT
keymgr_o.seeds[0][213] Yes Yes T2,T15,T26 Yes T2,T15,T26 OUTPUT
keymgr_o.seeds[0][214] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][215] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][216] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][217] Yes Yes T26,T22,T24 Yes T26,T22,T24 OUTPUT
keymgr_o.seeds[0][218] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][219] Yes Yes T2,T16,T15 Yes T2,T16,T15 OUTPUT
keymgr_o.seeds[0][220] Yes Yes T4,T27,T28 Yes T4,T27,T28 OUTPUT
keymgr_o.seeds[0][221] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][222] Yes Yes T3,T26,T27 Yes T3,T26,T27 OUTPUT
keymgr_o.seeds[0][223] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][224] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][225] Yes Yes T3,T4,T52 Yes T3,T4,T52 OUTPUT
keymgr_o.seeds[0][226] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][227] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[0][228] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][229] Yes Yes T15,T4,T27 Yes T15,T4,T27 OUTPUT
keymgr_o.seeds[0][230] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][231] Yes Yes T3,T14,T26 Yes T3,T14,T26 OUTPUT
keymgr_o.seeds[0][232] Yes Yes T14,T15,T26 Yes T14,T15,T26 OUTPUT
keymgr_o.seeds[0][233] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[0][234] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][235] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][236] Yes Yes T14,T15,T26 Yes T14,T15,T26 OUTPUT
keymgr_o.seeds[0][237] Yes Yes T2,T3,T27 Yes T2,T3,T27 OUTPUT
keymgr_o.seeds[0][238] Yes Yes T3,T26,T24 Yes T3,T26,T24 OUTPUT
keymgr_o.seeds[0][239] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][240] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[0][241] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[0][242] Yes Yes T2,T3,T15 Yes T2,T3,T15 OUTPUT
keymgr_o.seeds[0][243] Yes Yes T2,T14,T27 Yes T2,T14,T27 OUTPUT
keymgr_o.seeds[0][244] Yes Yes T16,T15,T26 Yes T16,T15,T26 OUTPUT
keymgr_o.seeds[0][245] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][246] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[0][247] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[0][248] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][249] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][250] Yes Yes T14,T26,T4 Yes T14,T26,T4 OUTPUT
keymgr_o.seeds[0][251] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[0][252] Yes Yes T3,T14,T4 Yes T3,T14,T4 OUTPUT
keymgr_o.seeds[0][253] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[0][254] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[0][255] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][0] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][1] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][2] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][3] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][4] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[1][5] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][6] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][7] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][8] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][9] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][10] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][11] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][12] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][13] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][14] Yes Yes T14,T16,T15 Yes T14,T16,T15 OUTPUT
keymgr_o.seeds[1][15] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][16] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][19:17] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][20] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][21] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][22] Yes Yes T3,T15,T26 Yes T3,T15,T26 OUTPUT
keymgr_o.seeds[1][23] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][24] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][25] Yes Yes T14,T4,T22 Yes T14,T4,T22 OUTPUT
keymgr_o.seeds[1][26] Yes Yes T3,T26,T4 Yes T3,T26,T4 OUTPUT
keymgr_o.seeds[1][27] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][28] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][29] Yes Yes T2,T16,T15 Yes T2,T16,T15 OUTPUT
keymgr_o.seeds[1][30] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][31] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][32] Yes Yes T3,T15,T4 Yes T3,T15,T4 OUTPUT
keymgr_o.seeds[1][33] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][34] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][35] Yes Yes T2,T16,T27 Yes T2,T16,T27 OUTPUT
keymgr_o.seeds[1][36] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][37] Yes Yes T16,T22,T24 Yes T16,T22,T24 OUTPUT
keymgr_o.seeds[1][38] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][39] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][40] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][41] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][42] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][43] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][44] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][45] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][46] Yes Yes T14,T26,T4 Yes T14,T26,T4 OUTPUT
keymgr_o.seeds[1][47] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][48] Yes Yes T2,T16,T15 Yes T2,T16,T15 OUTPUT
keymgr_o.seeds[1][49] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][50] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][51] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[1][52] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][53] Yes Yes T3,T26,T27 Yes T3,T26,T27 OUTPUT
keymgr_o.seeds[1][54] Yes Yes T2,T3,T15 Yes T2,T3,T15 OUTPUT
keymgr_o.seeds[1][55] Yes Yes T2,T14,T15 Yes T2,T14,T15 OUTPUT
keymgr_o.seeds[1][56] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][57] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][58] Yes Yes T4,T27,T52 Yes T4,T27,T52 OUTPUT
keymgr_o.seeds[1][59] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][60] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][61] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][62] Yes Yes T2,T4,T52 Yes T2,T4,T52 OUTPUT
keymgr_o.seeds[1][63] Yes Yes T15,T27,T22 Yes T15,T27,T22 OUTPUT
keymgr_o.seeds[1][64] Yes Yes T2,T16,T4 Yes T2,T16,T4 OUTPUT
keymgr_o.seeds[1][65] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][66] Yes Yes T2,T16,T22 Yes T2,T16,T22 OUTPUT
keymgr_o.seeds[1][67] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][68] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][69] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][70] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][71] Yes Yes T14,T16,T26 Yes T14,T16,T26 OUTPUT
keymgr_o.seeds[1][72] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][73] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][74] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][75] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][76] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][77] Yes Yes T3,T15,T26 Yes T3,T15,T26 OUTPUT
keymgr_o.seeds[1][78] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[1][79] Yes Yes T2,T16,T15 Yes T2,T16,T15 OUTPUT
keymgr_o.seeds[1][80] Yes Yes T2,T15,T27 Yes T2,T15,T27 OUTPUT
keymgr_o.seeds[1][81] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][82] Yes Yes T14,T16,T26 Yes T14,T16,T26 OUTPUT
keymgr_o.seeds[1][83] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][84] Yes Yes T3,T4,T22 Yes T3,T4,T22 OUTPUT
keymgr_o.seeds[1][85] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][86] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][87] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][88] Yes Yes T2,T3,T26 Yes T2,T3,T26 OUTPUT
keymgr_o.seeds[1][89] Yes Yes T2,T15,T4 Yes T2,T15,T4 OUTPUT
keymgr_o.seeds[1][90] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][91] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][92] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][93] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][94] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][95] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][96] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][97] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][98] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][99] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][100] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][101] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][102] Yes Yes T2,T14,T4 Yes T2,T14,T4 OUTPUT
keymgr_o.seeds[1][103] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][104] Yes Yes T14,T16,T26 Yes T14,T16,T26 OUTPUT
keymgr_o.seeds[1][105] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][106] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][107] Yes Yes T2,T16,T26 Yes T2,T16,T26 OUTPUT
keymgr_o.seeds[1][108] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][109] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][110] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][111] Yes Yes T16,T27,T28 Yes T16,T27,T28 OUTPUT
keymgr_o.seeds[1][112] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][113] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][114] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][115] Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
keymgr_o.seeds[1][116] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[1][117] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][118] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][119] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][120] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][121] Yes Yes T2,T15,T26 Yes T2,T15,T26 OUTPUT
keymgr_o.seeds[1][122] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][123] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][124] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][125] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][126] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][127] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][128] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][129] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][130] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][131] Yes Yes T14,T15,T27 Yes T14,T15,T27 OUTPUT
keymgr_o.seeds[1][132] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][133] Yes Yes T3,T16,T15 Yes T3,T16,T15 OUTPUT
keymgr_o.seeds[1][134] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][135] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][136] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][137] Yes Yes T2,T16,T15 Yes T2,T16,T15 OUTPUT
keymgr_o.seeds[1][138] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][139] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[1][140] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][141] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][142] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][143] Yes Yes T4,T27,T52 Yes T4,T27,T52 OUTPUT
keymgr_o.seeds[1][144] Yes Yes T2,T3,T26 Yes T2,T3,T26 OUTPUT
keymgr_o.seeds[1][145] Yes Yes T2,T15,T4 Yes T2,T15,T4 OUTPUT
keymgr_o.seeds[1][146] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][147] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][148] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][149] Yes Yes T26,T27,T22 Yes T26,T27,T22 OUTPUT
keymgr_o.seeds[1][150] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][152:151] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][153] Yes Yes T4,T27,T28 Yes T4,T27,T28 OUTPUT
keymgr_o.seeds[1][154] Yes Yes T2,T3,T26 Yes T2,T3,T26 OUTPUT
keymgr_o.seeds[1][155] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][156] Yes Yes T3,T15,T26 Yes T3,T15,T26 OUTPUT
keymgr_o.seeds[1][157] Yes Yes T14,T28,T24 Yes T14,T28,T24 OUTPUT
keymgr_o.seeds[1][158] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][159] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[1][160] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][161] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[1][162] Yes Yes T3,T15,T26 Yes T3,T15,T26 OUTPUT
keymgr_o.seeds[1][163] Yes Yes T2,T3,T15 Yes T2,T3,T15 OUTPUT
keymgr_o.seeds[1][164] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][165] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][166] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][167] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][168] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][169] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][170] Yes Yes T3,T16,T15 Yes T3,T16,T15 OUTPUT
keymgr_o.seeds[1][171] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][172] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][173] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][174] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][175] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][176] Yes Yes T15,T27,T28 Yes T15,T27,T28 OUTPUT
keymgr_o.seeds[1][177] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][178] Yes Yes T14,T16,T15 Yes T14,T16,T15 OUTPUT
keymgr_o.seeds[1][179] Yes Yes T3,T26,T4 Yes T3,T26,T4 OUTPUT
keymgr_o.seeds[1][180] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][181] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][182] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[1][183] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][184] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][185] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][186] Yes Yes T2,T3,T15 Yes T2,T3,T15 OUTPUT
keymgr_o.seeds[1][187] Yes Yes T16,T26,T27 Yes T16,T26,T27 OUTPUT
keymgr_o.seeds[1][188] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][189] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[1][190] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][191] Yes Yes T16,T26,T28 Yes T16,T26,T28 OUTPUT
keymgr_o.seeds[1][192] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][193] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][194] Yes Yes T15,T4,T28 Yes T15,T4,T28 OUTPUT
keymgr_o.seeds[1][195] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[1][196] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][197] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][198] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][199] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][200] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][201] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][202] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][203] Yes Yes T2,T26,T4 Yes T2,T26,T4 OUTPUT
keymgr_o.seeds[1][204] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][205] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][206] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][207] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][208] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][209] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][210] Yes Yes T14,T26,T4 Yes T14,T26,T4 OUTPUT
keymgr_o.seeds[1][211] Yes Yes T26,T4,T27 Yes T26,T4,T27 OUTPUT
keymgr_o.seeds[1][212] Yes Yes T2,T4,T28 Yes T2,T4,T28 OUTPUT
keymgr_o.seeds[1][213] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][214] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][215] Yes Yes T2,T14,T26 Yes T2,T14,T26 OUTPUT
keymgr_o.seeds[1][216] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][217] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][218] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[1][219] Yes Yes T2,T3,T14 Yes T2,T3,T14 OUTPUT
keymgr_o.seeds[1][220] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][221] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][222] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][223] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][225:224] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][226] Yes Yes T2,T14,T16 Yes T2,T14,T16 OUTPUT
keymgr_o.seeds[1][227] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][228] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][229] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][230] Yes Yes T14,T4,T27 Yes T14,T4,T27 OUTPUT
keymgr_o.seeds[1][231] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][232] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[1][233] Yes Yes T3,T15,T26 Yes T3,T15,T26 OUTPUT
keymgr_o.seeds[1][234] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][235] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
keymgr_o.seeds[1][236] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][237] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][238] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][239] Yes Yes T3,T14,T16 Yes T3,T14,T16 OUTPUT
keymgr_o.seeds[1][240] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][241] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][242] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][243] Yes Yes T3,T14,T26 Yes T3,T14,T26 OUTPUT
keymgr_o.seeds[1][244] Yes Yes T1,T3,T7 Yes T1,T3,T7 OUTPUT
keymgr_o.seeds[1][245] Yes Yes T3,T14,T15 Yes T3,T14,T15 OUTPUT
keymgr_o.seeds[1][246] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][247] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][248] Yes Yes T3,T16,T27 Yes T3,T16,T27 OUTPUT
keymgr_o.seeds[1][249] Yes Yes T1,T2,T7 Yes T1,T2,T7 OUTPUT
keymgr_o.seeds[1][250] Yes Yes T2,T3,T16 Yes T2,T3,T16 OUTPUT
keymgr_o.seeds[1][251] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][252] Yes Yes T14,T16,T27 Yes T14,T16,T27 OUTPUT
keymgr_o.seeds[1][253] Yes Yes T14,T26,T4 Yes T14,T26,T4 OUTPUT
keymgr_o.seeds[1][254] Yes Yes T1,T7,T18 Yes T1,T7,T18 OUTPUT
keymgr_o.seeds[1][255] Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
cio_tck_i No No No INPUT
cio_tms_i No No No INPUT
cio_tdi_i No No No INPUT
cio_tdo_en_o No No No OUTPUT
cio_tdo_o No No Yes T90,T91,T92 OUTPUT
intr_corr_err_o Yes Yes T26,T42,T43 Yes T26,T42,T43 OUTPUT
intr_prog_empty_o Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
intr_prog_lvl_o Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
intr_rd_full_o Yes Yes T35,T37,T38 Yes T35,T37,T38 OUTPUT
intr_rd_lvl_o Yes Yes T39,T35,T40 Yes T39,T35,T40 OUTPUT
intr_op_done_o Yes Yes T26,T27,T28 Yes T26,T27,T28 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T27,T28,T30 Yes T27,T28,T30 INPUT
alert_rx_i[0].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[0].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[1].ack_p Yes Yes T9,T10,T104 Yes T9,T10,T104 INPUT
alert_rx_i[1].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[1].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[2].ack_p Yes Yes T26,T28,T24 Yes T26,T28,T24 INPUT
alert_rx_i[2].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[2].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[3].ack_p Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_rx_i[3].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[3].ping_p Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[4].ack_p Yes Yes T104,T105,T106 Yes T104,T105,T106 INPUT
alert_rx_i[4].ping_n Unreachable Unreachable Unreachable INPUT
alert_rx_i[4].ping_p Unreachable Unreachable Unreachable INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T27,T28,T30 Yes T27,T28,T30 OUTPUT
alert_tx_o[1].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[1].alert_p Yes Yes T9,T10,T130 Yes T9,T10,T130 OUTPUT
alert_tx_o[2].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[2].alert_p Yes Yes T26,T28,T24 Yes T26,T28,T24 OUTPUT
alert_tx_o[3].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[3].alert_p Yes Yes T104,T105,T106 Yes T104,T105,T106 OUTPUT
alert_tx_o[4].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[4].alert_p Yes Yes T104,T105,T106 Yes T104,T105,T106 OUTPUT
obs_ctrl_i.obmen[3:0] No No No INPUT
obs_ctrl_i.obmsl[3:0] No No No INPUT
obs_ctrl_i.obgsl[3:0] No No No INPUT
fla_obs_o[7:0] Unreachable Unreachable Unreachable OUTPUT
scan_en_i Unreachable Unreachable Unreachable INPUT
scanmode_i[3:0] Unreachable Unreachable Unreachable INPUT
scan_rst_ni Unreachable Unreachable Unreachable INPUT
flash_bist_enable_i[3:0] Unreachable Unreachable Unreachable INPUT
flash_power_down_h_i Yes Yes T1,T2,T3 Yes T19,T15,T26 INPUT
flash_power_ready_h_i Yes Yes T15,T93,T103 Yes T15,T93,T103 INPUT
flash_test_mode_a_io[1:0] No No No INOUT
flash_test_voltage_h_io No No No INOUT

*Tests covering at least one bit in the range

Branch Coverage for Module : flash_ctrl
Line No.TotalCoveredPercent
Branches 14 14 100.00
TERNARY 875 2 2 100.00
TERNARY 1142 2 2 100.00
TERNARY 1142 2 2 100.00
TERNARY 700 2 2 100.00
IF 630 2 2 100.00
CASE 751 4 4 100.00


875 assign hw2reg.ctrl_regwen.d = sw_sel ? !op_start : 1'b1; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


1142 assign hw2reg.ecc_single_err_cnt[i].d = ®2hw.ecc_single_err_cnt[i].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T41,T108,T109
0 Covered T1,T2,T3


1142 assign hw2reg.ecc_single_err_cnt[i].d = ®2hw.ecc_single_err_cnt[i].q ? -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T41,T108,T109
0 Covered T1,T2,T3


700 flash_ctrl_rd u_flash_ctrl_rd ( 701 .clk_i, 702 .rst_ni, 703 704 // To arbiter Interface 705 .op_start_i (rd_op_valid), 706 .op_num_words_i (op_num_words), 707 .op_done_o (rd_done), 708 .op_err_o (rd_err), 709 .op_err_addr_o (rd_err_addr), 710 .op_addr_i (op_addr), 711 .op_addr_oob_i ('0), 712 .cnt_err_o (rd_cnt_err), 713 714 // FIFO Interface 715 .data_rdy_i (sw_sel ? sw_rfifo_wready : lcmgr_rready), -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


630 if (!rst_ni) begin -1- 631 adapter_rvalid <= 1'b0; ==> 632 rd_no_op_q <= 1'b0; 633 end else begin 634 adapter_rvalid <= adapter_req & sw_rfifo_rvalid; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


751 unique case (op_type) -1- 752 FlashOpRead: begin 753 flash_req = rd_flash_req; ==> 754 flash_addr = rd_flash_addr; 755 end 756 FlashOpProgram: begin 757 flash_req = prog_flash_req; ==> 758 flash_addr = prog_flash_addr; 759 end 760 FlashOpErase: begin 761 flash_req = erase_flash_req; ==> 762 flash_addr = erase_flash_addr; 763 end 764 default: begin 765 flash_req = 1'b0; ==>

Branches:
-1-StatusTests
FlashOpRead Covered T1,T2,T3
FlashOpProgram Covered T3,T7,T19
FlashOpErase Covered T3,T15,T27
default Covered T1,T2,T3


Assert Coverage for Module : flash_ctrl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 70 70 100.00 59 84.29
Cover properties 0 0 0
Cover sequences 0 0 0
Total 70 70 100.00 59 84.29




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
FifoDepthCheck_A 1056 1056 0 0
FlashAddrKnown_A 387955770 264422591 0 0
FlashAddrKnown_AKnownEnable 387955770 387167133 0 0
FlashKnownO_A 387955770 387167133 0 0
FlashProgKnown_A 387955770 159864268 0 0
FlashProgKnown_AKnownEnable 387955770 387167133 0 0
FpvSecCmAddrCntAlertCheck_A 387955770 50 0 0
FpvSecCmArbFsmCheck_A 387955770 50 0 0
FpvSecCmEflashReqFifoRptrCheck_A 387955770 0 0 0
FpvSecCmEflashReqFifoWptrCheck_A 387955770 0 0 0
FpvSecCmEflashRspFifoRptrCheck_A 387955770 0 0 0
FpvSecCmEflashRspFifoWptrCheck_A 387955770 0 0 0
FpvSecCmEflashSramReqFifoRptrCheck_A 387955770 0 0 0
FpvSecCmEflashSramReqFifoWptrCheck_A 387955770 0 0 0
FpvSecCmLcCtrlFsmCheck_A 387955770 50 0 0
FpvSecCmLcCtrlRmaFsmCheck_A 387955770 50 0 0
FpvSecCmPageCntAlertCheck_A 387955770 50 0 0
FpvSecCmProgCnt_A 387955770 50 0 0
FpvSecCmRdCnt_A 387955770 50 0 0
FpvSecCmRdReqFifoRptrCheck_A 387955770 0 0 0
FpvSecCmRdReqFifoWptrCheck_A 387955770 0 0 0
FpvSecCmRdRspFifoRptrCheck_A 387955770 50 0 0
FpvSecCmRdRspFifoWptrCheck_A 387955770 50 0 0
FpvSecCmRdSramReqFifoRptrCheck_A 387955770 0 0 0
FpvSecCmRdSramReqFifoWptrCheck_A 387955770 0 0 0
FpvSecCmRegWeOnehotCheck_A 387955770 50 0 0
FpvSecCmSeedCntAlertCheck_A 387955770 50 0 0
FpvSecCmTlLcGateFsm_A 387955770 50 0 0
FpvSecCmTlProgLcGateFsm_A 387955770 50 0 0
FpvSecCmWipeIdx_A 387955770 50 0 0
FpvSecCmWordCntAlertCheck_A 387955770 50 0 0
IntrErrO_A 387955770 387167133 0 0
IntrOpDoneKnownO_A 387955770 387167133 0 0
IntrProgEmptyKnownO_A 387955770 387167133 0 0
IntrProgLvlKnownO_A 387955770 387167133 0 0
IntrProgRdFullKnownO_A 387955770 387167133 0 0
IntrRdLvlKnownO_A 387955770 387167133 0 0
MemRspPayLoad_A 387955770 5261662 0 0
MemRspPayLoad_AKnownEnable 387955770 387167133 0 0
MemTlAReadyKnownO_A 387955770 387167133 0 0
MemTlDValidKnownO_A 387955770 387167133 0 0
PrimRspPayLoad_A 387955770 0 0 0
PrimRspPayLoad_AKnownEnable 387955770 387167133 0 0
PrimTlAReadyKnownO_A 387955770 387167133 0 0
PrimTlDValidKnownO_A 387955770 387167133 0 0
RspPayLoad_A 387746155 39324318 0 0
RspPayLoad_AKnownEnable 387955770 387167133 0 0
TdoEnIsOne_A 387955770 387167133 0 0
TdoKnown_A 387955770 387167133 0 0
TlAReadyKnownO_A 387955770 387167133 0 0
TlDValidKnownO_A 387955770 387167133 0 0
gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A 387955770 50 0 0
gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A 387955770 50 0 0
gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A 387955770 50 0 0
gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A 387955770 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A 387955770 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A 387955770 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A 387955770 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A 387955770 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A 387955770 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A 387955770 50 0 0
gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A 387955770 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A 387955770 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A 387955770 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A 387955770 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A 387955770 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A 387955770 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A 387955770 50 0 0
gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A 387955770 50 0 0
gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A 387955770 26 0 0


FifoDepthCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

FlashAddrKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 264422591 0 0
T1 2386 526 0 0
T2 1619 160 0 0
T3 2624 711 0 0
T7 3618 2350 0 0
T8 758 226 0 0
T14 57474 2199 0 0
T16 2778 936 0 0
T18 1453 671 0 0
T19 1592 322 0 0
T20 1905 674 0 0

FlashAddrKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

FlashKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

FlashProgKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 159864268 0 0
T3 2624 241 0 0
T7 3618 2190 0 0
T8 758 66 0 0
T9 0 33 0 0
T14 57474 0 0 0
T15 82187 8343 0 0
T16 2778 713 0 0
T18 1453 0 0 0
T19 1592 2 0 0
T20 1905 0 0 0
T26 2605 61 0 0
T28 0 330 0 0
T30 0 182316 0 0

FlashProgKnown_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

FpvSecCmAddrCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmArbFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmEflashReqFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmEflashReqFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmEflashRspFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmEflashRspFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmEflashSramReqFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmEflashSramReqFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmLcCtrlFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmLcCtrlRmaFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmPageCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmProgCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmRdCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmRdReqFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmRdReqFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmRdRspFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmRdRspFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmRdSramReqFifoRptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmRdSramReqFifoWptrCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

FpvSecCmRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmSeedCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmTlLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmTlProgLcGateFsm_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmWipeIdx_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

FpvSecCmWordCntAlertCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

IntrErrO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IntrOpDoneKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IntrProgEmptyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IntrProgLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IntrProgRdFullKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

IntrRdLvlKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

MemRspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 5261662 0 0
T2 1619 10 0 0
T3 2624 0 0 0
T7 3618 0 0 0
T8 758 23 0 0
T10 0 1 0 0
T14 57474 2047 0 0
T15 82187 0 0 0
T16 2778 50 0 0
T17 0 67 0 0
T18 1453 0 0 0
T19 1592 0 0 0
T20 1905 0 0 0
T24 0 500 0 0
T26 0 17 0 0
T27 0 17 0 0
T28 0 11 0 0

MemRspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

MemTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

MemTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

PrimRspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 0 0 0

PrimRspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

PrimTlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

PrimTlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

RspPayLoad_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387746155 39324318 0 0
T1 2386 528 0 0
T2 1619 61 0 0
T3 2624 590 0 0
T7 3618 1298 0 0
T8 758 168 0 0
T14 57474 21829 0 0
T16 2778 562 0 0
T18 1453 537 0 0
T19 1592 108 0 0
T20 1905 539 0 0

RspPayLoad_AKnownEnable
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

TdoEnIsOne_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

TdoKnown_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

TlAReadyKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

TlDValidKnownO_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 387167133 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

gen_phy_assertions[0].FpvSecCmPhyFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_assertions[0].FpvSecCmPhyProgFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_assertions[1].FpvSecCmPhyFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_assertions[1].FpvSecCmPhyProgFsmCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyHostCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdDataFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRdRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[0].FpvSecCmPhyRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyHostCnt_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdDataFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRdRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoRPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_phy_cnt_errs[1].FpvSecCmPhyRspFifoWPtr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 50 0 0
T44 152600 10 0 0
T47 153730 10 0 0
T48 95707 10 0 0
T60 145059 10 0 0
T131 98244 10 0 0

gen_reg_we_assert_generic.FpvSecCmPrimRegWeOnehotCheck_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955770 26 0 0
T44 152600 6 0 0
T47 153730 6 0 0
T48 95707 4 0 0
T60 145059 6 0 0
T131 98244 4 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%