Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
80.00 80.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
97.24 98.80 94.66 100.00 90.62 99.37 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
u_flash


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
gen_prim_flash_banks[0].u_prim_flash_bank 96.40 98.24 91.16 93.75 98.85 100.00
gen_prim_flash_banks[1].u_prim_flash_bank 95.15 98.24 91.16 87.50 98.85 100.00
u_reg_top 98.94 99.31 95.82 100.00 99.56 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : prim_generic_flash
Line No.TotalCoveredPercent
TOTAL10880.00
CONT_ASSIGN5211100.00
CONT_ASSIGN10100
CONT_ASSIGN10200
CONT_ASSIGN10300
CONT_ASSIGN104100.00
CONT_ASSIGN105100.00
CONT_ASSIGN10611100.00
CONT_ASSIGN10711100.00
CONT_ASSIGN10811100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13311100.00
CONT_ASSIGN13811100.00
CONT_ASSIGN14211100.00

51 logic [NumBanks-1:0] init_busy; 52 1/1 assign init_busy_o = |init_busy; Tests: T1 T2 T3  53 54 // this represents the type of program operations that are supported 55 assign prog_type_avail_o[flash_ctrl_pkg::FlashProgNormal] = 1'b1; 56 assign prog_type_avail_o[flash_ctrl_pkg::FlashProgRepair] = 1'b1; 57 58 for (genvar bank = 0; bank < NumBanks; bank++) begin : gen_prim_flash_banks 59 60 prim_generic_flash_bank #( 61 .InfosPerBank(InfosPerBank), 62 .InfoTypes(InfoTypes), 63 .InfoTypesWidth(InfoTypesWidth), 64 .PagesPerBank(PagesPerBank), 65 .WordsPerPage(WordsPerPage), 66 .DataWidth(DataWidth) 67 ) u_prim_flash_bank ( 68 .clk_i, 69 .rst_ni, 70 .rd_i(flash_req_i[bank].rd_req), 71 .prog_i(flash_req_i[bank].prog_req), 72 .prog_last_i(flash_req_i[bank].prog_last), 73 .prog_type_i(flash_req_i[bank].prog_type), 74 .pg_erase_i(flash_req_i[bank].pg_erase_req), 75 .bk_erase_i(flash_req_i[bank].bk_erase_req), 76 .erase_suspend_req_i(flash_req_i[bank].erase_suspend_req), 77 .he_i(flash_req_i[bank].he), 78 .addr_i(flash_req_i[bank].addr), 79 .part_i(flash_req_i[bank].part), 80 .info_sel_i(flash_req_i[bank].info_sel), 81 .prog_data_i(flash_req_i[bank].prog_full_data), 82 .ack_o(flash_rsp_o[bank].ack), 83 .done_o(flash_rsp_o[bank].done), 84 .rd_data_o(flash_rsp_o[bank].rdata), 85 .init_i(init), 86 .init_busy_o(init_busy[bank]), 87 .flash_power_ready_h_i, 88 .flash_power_down_h_i 89 ); 90 end 91 92 logic unused_scanmode; 93 logic unused_scan_en; 94 logic unused_scan_rst_n; 95 logic [TestModeWidth-1:0] unused_flash_test_mode; 96 logic unused_flash_test_voltage; 97 logic unused_tck; 98 logic unused_tdi; 99 logic unused_tms; 100 101 unreachable assign unused_scanmode = ^scanmode_i; 102 unreachable assign unused_scan_en = scan_en_i; 103 unreachable assign unused_scan_rst_n = scan_rst_ni; 104 0/1 ==> assign unused_flash_test_mode = flash_test_mode_a_io; 105 0/1 ==> assign unused_flash_test_voltage = flash_test_voltage_h_io; 106 1/1 assign unused_tck = tck_i; Tests: T1 T2 T3  107 1/1 assign unused_tdi = tdi_i; Tests: T1 T2 T3  108 1/1 assign unused_tms = tms_i; Tests: T1 T2 T3  109 assign tdo_o = '0; 110 111 //////////////////////////////////// 112 // TL-UL Test Interface Emulation // 113 //////////////////////////////////// 114 115 logic intg_err; 116 flash_ctrl_reg_pkg::flash_ctrl_prim_reg2hw_t reg2hw; 117 flash_ctrl_reg_pkg::flash_ctrl_prim_hw2reg_t hw2reg; 118 flash_ctrl_prim_reg_top u_reg_top ( 119 .clk_i, 120 .rst_ni, 121 .tl_i (tl_i), 122 .tl_o (tl_o), 123 .reg2hw (reg2hw), 124 .hw2reg (hw2reg), 125 .intg_err_o(intg_err) 126 ); 127 128 logic unused_reg_sig; 129 1/1 assign unused_reg_sig = ^reg2hw; Tests: T1 T2 T3  130 assign hw2reg = '0; 131 132 logic unused_bist_enable; 133 1/1 assign unused_bist_enable = ^bist_enable_i; Tests: T1 T2 T3  134 135 // open source model has no error response at the moment 136 assign flash_err_o = 1'b0; 137 138 1/1 assign fatal_alert_o = intg_err; Tests: T1 T2 T3  139 assign recov_alert_o = 1'b0; 140 141 logic unused_obs; 142 1/1 assign unused_obs = |obs_ctrl_i; Tests: T4 T5 T6 
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