Unified Coverage Report :: Module :: flash_ctrl_prim_reg_top

Module : flash_ctrl_prim_reg_top

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_flash_ctrl_prim_reg_top_1.0/rtl/flash_ctrl_prim_reg_top.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top	100.00	100.00	100.00			100.00	100.00

---

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.94	99.31	95.82	100.00		99.56	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
80.00	80.00						gen_generic.u_impl_generic

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_chk	100.00	100.00		100.00			100.00
u_csr0_regwen	100.00	100.00	100.00			100.00
u_csr10	100.00	100.00	100.00			100.00
u_csr11	100.00	100.00	100.00			100.00
u_csr12	100.00	100.00	100.00			100.00
u_csr13_field0	100.00	100.00	100.00			100.00
u_csr13_field1	100.00	100.00	100.00			100.00
u_csr14_field0	100.00	100.00	100.00			100.00
u_csr14_field1	100.00	100.00	100.00			100.00
u_csr15_field0	100.00	100.00	100.00			100.00
u_csr15_field1	100.00	100.00	100.00			100.00
u_csr16_field0	100.00	100.00	100.00			100.00
u_csr16_field1	100.00	100.00	100.00			100.00
u_csr17_field0	100.00	100.00	100.00			100.00
u_csr17_field1	100.00	100.00	100.00			100.00
u_csr18	100.00	100.00	100.00			100.00
u_csr19	100.00	100.00	100.00			100.00
u_csr1_field0	100.00	100.00	100.00			100.00
u_csr1_field1	100.00	100.00	100.00			100.00
u_csr20_field0	88.89	100.00	66.67			100.00
u_csr20_field1	88.89	100.00	66.67			100.00
u_csr20_field2	55.19	55.56	50.00			60.00
u_csr2_field0	88.89	100.00	66.67			100.00
u_csr2_field1	88.89	100.00	66.67			100.00
u_csr2_field2	88.89	100.00	66.67			100.00
u_csr2_field3	96.30	100.00	88.89			100.00
u_csr2_field4	88.89	100.00	66.67			100.00
u_csr2_field5	88.89	100.00	66.67			100.00
u_csr2_field6	88.89	100.00	66.67			100.00
u_csr2_field7	96.30	100.00	88.89			100.00
u_csr3_field0	100.00	100.00	100.00			100.00
u_csr3_field1	100.00	100.00	100.00			100.00
u_csr3_field2	100.00	100.00	100.00			100.00
u_csr3_field3	100.00	100.00	100.00			100.00
u_csr3_field4	100.00	100.00	100.00			100.00
u_csr3_field5	100.00	100.00	100.00			100.00
u_csr3_field6	100.00	100.00	100.00			100.00
u_csr3_field7	100.00	100.00	100.00			100.00
u_csr3_field8	100.00	100.00	100.00			100.00
u_csr3_field9	100.00	100.00	100.00			100.00
u_csr4_field0	100.00	100.00	100.00			100.00
u_csr4_field1	100.00	100.00	100.00			100.00
u_csr4_field2	100.00	100.00	100.00			100.00
u_csr4_field3	100.00	100.00	100.00			100.00
u_csr5_field0	100.00	100.00	100.00			100.00
u_csr5_field1	100.00	100.00	100.00			100.00
u_csr5_field2	100.00	100.00	100.00			100.00
u_csr5_field3	100.00	100.00	100.00			100.00
u_csr5_field4	100.00	100.00	100.00			100.00
u_csr6_field0	100.00	100.00	100.00			100.00
u_csr6_field1	100.00	100.00	100.00			100.00
u_csr6_field2	100.00	100.00	100.00			100.00
u_csr6_field3	100.00	100.00	100.00			100.00
u_csr6_field4	100.00	100.00	100.00			100.00
u_csr6_field5	100.00	100.00	100.00			100.00
u_csr6_field6	100.00	100.00	100.00			100.00
u_csr6_field7	100.00	100.00	100.00			100.00
u_csr6_field8	100.00	100.00	100.00			100.00
u_csr7_field0	100.00	100.00	100.00			100.00
u_csr7_field1	100.00	100.00	100.00			100.00
u_csr8	100.00	100.00	100.00			100.00
u_csr9	100.00	100.00	100.00			100.00
u_prim_reg_we_check	100.00	100.00		100.00
u_reg_if	98.67	97.14	97.53			100.00	100.00
u_rsp_intg_gen	100.00	100.00					100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : flash_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
TOTAL		219	219	100.00
ALWAYS	68	4	4	100.00
CONT_ASSIGN	77	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	90	1	1	100.00
CONT_ASSIGN	118	1	1	100.00
CONT_ASSIGN	119	1	1	100.00
CONT_ASSIGN	299	1	1	100.00
CONT_ASSIGN	576	1	1	100.00
CONT_ASSIGN	851	1	1	100.00
CONT_ASSIGN	964	1	1	100.00
CONT_ASSIGN	1104	1	1	100.00
CONT_ASSIGN	1352	1	1	100.00
CONT_ASSIGN	1411	1	1	100.00
CONT_ASSIGN	1442	1	1	100.00
CONT_ASSIGN	1473	1	1	100.00
CONT_ASSIGN	1504	1	1	100.00
CONT_ASSIGN	1535	1	1	100.00
CONT_ASSIGN	1566	1	1	100.00
CONT_ASSIGN	1625	1	1	100.00
CONT_ASSIGN	1684	1	1	100.00
CONT_ASSIGN	1743	1	1	100.00
CONT_ASSIGN	1802	1	1	100.00
CONT_ASSIGN	1861	1	1	100.00
CONT_ASSIGN	1892	1	1	100.00
ALWAYS	2006	22	22	100.00
CONT_ASSIGN	2030	1	1	100.00
ALWAYS	2034	1	1	100.00
CONT_ASSIGN	2059	1	1	100.00
CONT_ASSIGN	2061	1	1	100.00
CONT_ASSIGN	2062	1	1	100.00
CONT_ASSIGN	2064	1	1	100.00
CONT_ASSIGN	2066	1	1	100.00
CONT_ASSIGN	2067	1	1	100.00
CONT_ASSIGN	2069	1	1	100.00
CONT_ASSIGN	2071	1	1	100.00
CONT_ASSIGN	2073	1	1	100.00
CONT_ASSIGN	2075	1	1	100.00
CONT_ASSIGN	2077	1	1	100.00
CONT_ASSIGN	2079	1	1	100.00
CONT_ASSIGN	2081	1	1	100.00
CONT_ASSIGN	2083	1	1	100.00
CONT_ASSIGN	2084	1	1	100.00
CONT_ASSIGN	2086	1	1	100.00
CONT_ASSIGN	2088	1	1	100.00
CONT_ASSIGN	2090	1	1	100.00
CONT_ASSIGN	2092	1	1	100.00
CONT_ASSIGN	2094	1	1	100.00
CONT_ASSIGN	2096	1	1	100.00
CONT_ASSIGN	2098	1	1	100.00
CONT_ASSIGN	2100	1	1	100.00
CONT_ASSIGN	2102	1	1	100.00
CONT_ASSIGN	2104	1	1	100.00
CONT_ASSIGN	2105	1	1	100.00
CONT_ASSIGN	2107	1	1	100.00
CONT_ASSIGN	2109	1	1	100.00
CONT_ASSIGN	2111	1	1	100.00
CONT_ASSIGN	2113	1	1	100.00
CONT_ASSIGN	2114	1	1	100.00
CONT_ASSIGN	2116	1	1	100.00
CONT_ASSIGN	2118	1	1	100.00
CONT_ASSIGN	2120	1	1	100.00
CONT_ASSIGN	2122	1	1	100.00
CONT_ASSIGN	2124	1	1	100.00
CONT_ASSIGN	2125	1	1	100.00
CONT_ASSIGN	2127	1	1	100.00
CONT_ASSIGN	2129	1	1	100.00
CONT_ASSIGN	2131	1	1	100.00
CONT_ASSIGN	2133	1	1	100.00
CONT_ASSIGN	2135	1	1	100.00
CONT_ASSIGN	2137	1	1	100.00
CONT_ASSIGN	2139	1	1	100.00
CONT_ASSIGN	2141	1	1	100.00
CONT_ASSIGN	2143	1	1	100.00
CONT_ASSIGN	2144	1	1	100.00
CONT_ASSIGN	2146	1	1	100.00
CONT_ASSIGN	2148	1	1	100.00
CONT_ASSIGN	2149	1	1	100.00
CONT_ASSIGN	2151	1	1	100.00
CONT_ASSIGN	2152	1	1	100.00
CONT_ASSIGN	2154	1	1	100.00
CONT_ASSIGN	2155	1	1	100.00
CONT_ASSIGN	2157	1	1	100.00
CONT_ASSIGN	2158	1	1	100.00
CONT_ASSIGN	2160	1	1	100.00
CONT_ASSIGN	2161	1	1	100.00
CONT_ASSIGN	2163	1	1	100.00
CONT_ASSIGN	2164	1	1	100.00
CONT_ASSIGN	2166	1	1	100.00
CONT_ASSIGN	2168	1	1	100.00
CONT_ASSIGN	2169	1	1	100.00
CONT_ASSIGN	2171	1	1	100.00
CONT_ASSIGN	2173	1	1	100.00
CONT_ASSIGN	2174	1	1	100.00
CONT_ASSIGN	2176	1	1	100.00
CONT_ASSIGN	2178	1	1	100.00
CONT_ASSIGN	2179	1	1	100.00
CONT_ASSIGN	2181	1	1	100.00
CONT_ASSIGN	2183	1	1	100.00
CONT_ASSIGN	2184	1	1	100.00
CONT_ASSIGN	2186	1	1	100.00
CONT_ASSIGN	2188	1	1	100.00
CONT_ASSIGN	2189	1	1	100.00
CONT_ASSIGN	2191	1	1	100.00
CONT_ASSIGN	2192	1	1	100.00
CONT_ASSIGN	2194	1	1	100.00
CONT_ASSIGN	2195	1	1	100.00
CONT_ASSIGN	2197	1	1	100.00
CONT_ASSIGN	2199	1	1	100.00
ALWAYS	2203	22	22	100.00
ALWAYS	2229	63	63	100.00
CONT_ASSIGN	2366	0	0
CONT_ASSIGN	2374	1	1	100.00
CONT_ASSIGN	2375	1	1	100.00

Click here to see the source line report.

---

Cond Coverage for Module : flash_ctrl_prim_reg_top

	Total	Covered	Percent
Conditions	287	287	100.00
Logical	287	287	100.00
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (reg_we && ((!addrmiss)))
             ---1--    ------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T117,T67,T68
1	1	Covered	T117,T66,T67

 LINE       70
 EXPRESSION (intg_err || reg_we_err)
             ----1---    -----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T44,T47,T48
1	0	Covered	T265,T266,T267

 LINE       77
 EXPRESSION (err_q | intg_err | reg_we_err)
             --1--   ----2---   -----3----

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T44,T47,T48
0	1	0	Covered	T265,T266,T267
1	0	0	Covered	T44,T47,T48

 LINE       119
 EXPRESSION (addrmiss | wr_err | intg_err)
             ----1---   ---2--   ----3---

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T1,T2,T3
0	0	1	Covered	T265,T266,T267
0	1	0	Covered	T117,T67,T68
1	0	0	Covered	T117,T67,T68

 LINE       299
 EXPRESSION (csr1_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T68,T257

 LINE       576
 EXPRESSION (csr3_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T118,T257

 LINE       851
 EXPRESSION (csr4_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T118,T257

 LINE       964
 EXPRESSION (csr5_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T118,T258
1	1	Covered	T66,T68,T118

 LINE       1104
 EXPRESSION (csr6_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T258
1	1	Covered	T66,T68,T118

 LINE       1352
 EXPRESSION (csr7_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T258
1	1	Covered	T66,T68,T118

 LINE       1411
 EXPRESSION (csr8_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T257,T259

 LINE       1442
 EXPRESSION (csr9_we & csr0_regwen_qs)
             ---1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T118,T258
1	1	Covered	T66,T68,T118

 LINE       1473
 EXPRESSION (csr10_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T118,T258
1	1	Covered	T66,T68,T118

 LINE       1504
 EXPRESSION (csr11_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T68,T118,T258
1	1	Covered	T66,T68,T257

 LINE       1535
 EXPRESSION (csr12_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T118,T257

 LINE       1566
 EXPRESSION (csr13_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T68,T257

 LINE       1625
 EXPRESSION (csr14_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T257,T259

 LINE       1684
 EXPRESSION (csr15_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T68,T118

 LINE       1743
 EXPRESSION (csr16_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T257,T259

 LINE       1802
 EXPRESSION (csr17_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T118,T257

 LINE       1861
 EXPRESSION (csr18_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T118
1	1	Covered	T66,T118,T257

 LINE       1892
 EXPRESSION (csr19_we & csr0_regwen_qs)
             ----1---   -------2------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T66,T68,T258
1	1	Covered	T66,T68,T118

 LINE       2007
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR0_REGWEN_OFFSET)
            -------------------------------1-------------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T167,T40

 LINE       2008
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR1_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T17,T52,T315

 LINE       2009
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR2_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T116,T52,T264

 LINE       2010
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR3_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T28,T52,T151

 LINE       2011
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR4_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T28,T52,T320

 LINE       2012
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR5_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T72,T174

 LINE       2013
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR6_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T321,T295

 LINE       2014
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR7_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T23,T176

 LINE       2015
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR8_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T151,T233

 LINE       2016
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR9_OFFSET)
            ----------------------------1---------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T233,T103

 LINE       2017
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR10_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T217,T113

 LINE       2018
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR11_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T322,T323

 LINE       2019
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR12_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T122,T233

 LINE       2020
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR13_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T317,T324

 LINE       2021
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR14_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T116,T52,T31

 LINE       2022
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR15_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T318,T323

 LINE       2023
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR16_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T52,T319,T325

 LINE       2024
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR17_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T20,T28
1	Covered	T7,T52,T150

 LINE       2025
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR18_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T24,T52,T63

 LINE       2026
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR19_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T24,T52,T193

 LINE       2027
 EXPRESSION (reg_addr == flash_ctrl_reg_pkg::FLASH_CTRL_CSR20_OFFSET)
            ----------------------------1----------------------------

-1-	Status	Tests
0	Covered	T1,T7,T20
1	Covered	T24,T11,T52

 LINE       2030
 EXPRESSION ((reg_re || reg_we) ? ((~|addr_hit)) : 1'b0)
             ---------1--------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T117,T66,T67

 LINE       2030
 SUB-EXPRESSION (reg_re || reg_we)
                 ---1--    ---2--

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T117,T66,T67
1	0	Covered	T117,T66,T67

 LINE       2034
 EXPRESSION 
 Number  Term
      1  reg_we & 
      2  ((addr_hit[0] & ((|(4'b1 & (~reg_be))))) | (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | (addr_hit[20] & ((|(4'b1 & (~reg_be)))))))

-1-	-2-	Status	Tests
0	1	Covered	T7,T28,T11
1	0	Covered	T117,T66,T67
1	1	Covered	T117,T67,T68

 LINE       2034
 SUB-EXPRESSION 
 Number  Term
      1  (addr_hit[0] & ((|(4'b1 & (~reg_be))))) | 
      2  (addr_hit[1] & ((|(4'b0011 & (~reg_be))))) | 
      3  (addr_hit[2] & ((|(4'b1 & (~reg_be))))) | 
      4  (addr_hit[3] & ((|(4'b1111 & (~reg_be))))) | 
      5  (addr_hit[4] & ((|(4'b0011 & (~reg_be))))) | 
      6  (addr_hit[5] & ((|(4'b0111 & (~reg_be))))) | 
      7  (addr_hit[6] & ((|(4'b1111 & (~reg_be))))) | 
      8  (addr_hit[7] & ((|(4'b0111 & (~reg_be))))) | 
      9  (addr_hit[8] & ((|(4'b1111 & (~reg_be))))) | 
     10  (addr_hit[9] & ((|(4'b1111 & (~reg_be))))) | 
     11  (addr_hit[10] & ((|(4'b1111 & (~reg_be))))) | 
     12  (addr_hit[11] & ((|(4'b1111 & (~reg_be))))) | 
     13  (addr_hit[12] & ((|(4'b0011 & (~reg_be))))) | 
     14  (addr_hit[13] & ((|(4'b0111 & (~reg_be))))) | 
     15  (addr_hit[14] & ((|(4'b0011 & (~reg_be))))) | 
     16  (addr_hit[15] & ((|(4'b0011 & (~reg_be))))) | 
     17  (addr_hit[16] & ((|(4'b0011 & (~reg_be))))) | 
     18  (addr_hit[17] & ((|(4'b0011 & (~reg_be))))) | 
     19  (addr_hit[18] & ((|(4'b1 & (~reg_be))))) | 
     20  (addr_hit[19] & ((|(4'b1 & (~reg_be))))) | 
     21  (addr_hit[20] & ((|(4'b1 & (~reg_be))))))

Sensitive Expression == 1	Status	Tests
ALL ZEROS	Covered	T1,T20,T22
21 (addr_hit[20] & ((|(4'...	Covered	T11,T52,T326
20 (addr_hit[19] & ((|(4'...	Covered	T52,T326,T188
19 (addr_hit[18] & ((|(4'...	Covered	T52,T157,T323
18 (addr_hit[17] & ((|(4'...	Covered	T7,T52,T150
17 (addr_hit[16] & ((|(4'...	Covered	T52,T319,T325
16 (addr_hit[15] & ((|(4'...	Covered	T52,T318,T323
15 (addr_hit[14] & ((|(4'...	Covered	T116,T52,T31
14 (addr_hit[13] & ((|(4'...	Covered	T52,T317,T323
13 (addr_hit[12] & ((|(4'...	Covered	T52,T233,T323
12 (addr_hit[11] & ((|(4'...	Covered	T52,T322,T323
11 (addr_hit[10] & ((|(4'...	Covered	T52,T217,T113
10 (addr_hit[9] & ((|(4'b...	Covered	T52,T233,T103
9 (addr_hit[8] & ((|(4'b...	Covered	T52,T151,T233
8 (addr_hit[7] & ((|(4'b...	Covered	T52,T176,T327
7 (addr_hit[6] & ((|(4'b...	Covered	T52,T321,T295
6 (addr_hit[5] & ((|(4'b...	Covered	T52,T72,T174
5 (addr_hit[4] & ((|(4'b...	Covered	T28,T52,T320
4 (addr_hit[3] & ((|(4'b...	Covered	T28,T52,T151
3 (addr_hit[2] & ((|(4'b...	Covered	T116,T52,T328
2 (addr_hit[1] & ((|(4'b...	Covered	T52,T315,T155
1 (addr_hit[0] & ((|(4'b...	Covered	T167,T40,T329

 LINE       2034
 SUB-EXPRESSION (addr_hit[0] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T200,T326
1	1	Covered	T167,T40,T329

 LINE       2034
 SUB-EXPRESSION (addr_hit[1] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T17,T52,T323
1	1	Covered	T52,T315,T155

 LINE       2034
 SUB-EXPRESSION (addr_hit[2] & ((|(4'b1 & (~reg_be)))))
                 -----1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T264,T214
1	1	Covered	T116,T52,T328

 LINE       2034
 SUB-EXPRESSION (addr_hit[3] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T233,T326
1	1	Covered	T28,T52,T151

 LINE       2034
 SUB-EXPRESSION (addr_hit[4] & ((|(4'b0011 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T323,T326
1	1	Covered	T28,T52,T320

 LINE       2034
 SUB-EXPRESSION (addr_hit[5] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T323,T326
1	1	Covered	T52,T72,T174

 LINE       2034
 SUB-EXPRESSION (addr_hit[6] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T326,T330,T331
1	1	Covered	T52,T321,T295

 LINE       2034
 SUB-EXPRESSION (addr_hit[7] & ((|(4'b0111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T23,T323
1	1	Covered	T52,T176,T327

 LINE       2034
 SUB-EXPRESSION (addr_hit[8] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T332,T333
1	1	Covered	T52,T151,T233

 LINE       2034
 SUB-EXPRESSION (addr_hit[9] & ((|(4'b1111 & (~reg_be)))))
                 -----1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T334,T335,T336
1	1	Covered	T52,T233,T103

 LINE       2034
 SUB-EXPRESSION (addr_hit[10] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T323,T337
1	1	Covered	T52,T217,T113

 LINE       2034
 SUB-EXPRESSION (addr_hit[11] & ((|(4'b1111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T337,T333,T335
1	1	Covered	T52,T322,T323

 LINE       2034
 SUB-EXPRESSION (addr_hit[12] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T122,T6
1	1	Covered	T52,T233,T323

 LINE       2034
 SUB-EXPRESSION (addr_hit[13] & ((|(4'b0111 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T324,T335
1	1	Covered	T52,T317,T323

 LINE       2034
 SUB-EXPRESSION (addr_hit[14] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T193,T233
1	1	Covered	T116,T52,T31

 LINE       2034
 SUB-EXPRESSION (addr_hit[15] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T323,T326
1	1	Covered	T52,T318,T323

 LINE       2034
 SUB-EXPRESSION (addr_hit[16] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T52,T338,T337
1	1	Covered	T52,T319,T325

 LINE       2034
 SUB-EXPRESSION (addr_hit[17] & ((|(4'b0011 & (~reg_be)))))
                 ------1-----   -------------2------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T20,T28
1	0	Covered	T52,T152,T339
1	1	Covered	T7,T52,T150

 LINE       2034
 SUB-EXPRESSION (addr_hit[18] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T24,T52,T63
1	1	Covered	T52,T157,T323

 LINE       2034
 SUB-EXPRESSION (addr_hit[19] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T24,T52,T193
1	1	Covered	T52,T326,T188

 LINE       2034
 SUB-EXPRESSION (addr_hit[20] & ((|(4'b1 & (~reg_be)))))
                 ------1-----   -----------2-----------

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T20
1	0	Covered	T24,T323,T326
1	1	Covered	T11,T52,T326

 LINE       2059
 EXPRESSION (addr_hit[0] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T167,T40
1	1	0	Covered	T67,T237,T246
1	1	1	Covered	T66,T68,T118

 LINE       2062
 EXPRESSION (addr_hit[1] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T17,T52,T315
1	1	0	Covered	T67,T237,T246
1	1	1	Covered	T66,T68,T118

 LINE       2067
 EXPRESSION (addr_hit[2] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T1,T116,T52
1	1	0	Covered	T117,T67,T237
1	1	1	Covered	T66,T68,T118

 LINE       2084
 EXPRESSION (addr_hit[3] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T28,T52,T151
1	1	0	Covered	T117,T67,T237
1	1	1	Covered	T66,T68,T118

 LINE       2105
 EXPRESSION (addr_hit[4] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T28,T52,T182
1	1	0	Covered	T67,T237,T246
1	1	1	Covered	T66,T68,T118

 LINE       2114
 EXPRESSION (addr_hit[5] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T235,T72
1	1	0	Covered	T67,T237,T246
1	1	1	Covered	T66,T68,T118

 LINE       2125
 EXPRESSION (addr_hit[6] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T24,T52,T151
1	1	0	Covered	T117,T67,T237
1	1	1	Covered	T66,T68,T118

 LINE       2144
 EXPRESSION (addr_hit[7] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T17,T11,T52
1	1	0	Covered	T117,T67,T68
1	1	1	Covered	T66,T68,T118

 LINE       2149
 EXPRESSION (addr_hit[8] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T63,T31
1	1	0	Covered	T67,T246,T248
1	1	1	Covered	T66,T68,T118

 LINE       2152
 EXPRESSION (addr_hit[9] & reg_we & ((!reg_error)))
             -----1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T233,T103
1	1	0	Covered	T117,T67,T237
1	1	1	Covered	T66,T68,T118

 LINE       2155
 EXPRESSION (addr_hit[10] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T212,T214
1	1	0	Covered	T67,T246,T248
1	1	1	Covered	T66,T68,T118

 LINE       2158
 EXPRESSION (addr_hit[11] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T316,T233
1	1	0	Covered	T67,T237,T247
1	1	1	Covered	T66,T68,T118

 LINE       2161
 EXPRESSION (addr_hit[12] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T104,T122
1	1	0	Covered	T117,T67,T237
1	1	1	Covered	T66,T68,T118

 LINE       2164
 EXPRESSION (addr_hit[13] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T71,T317
1	1	0	Covered	T67,T68,T237
1	1	1	Covered	T66,T68,T118

 LINE       2169
 EXPRESSION (addr_hit[14] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T116,T52,T31
1	1	0	Covered	T67,T237,T246
1	1	1	Covered	T66,T68,T118

 LINE       2174
 EXPRESSION (addr_hit[15] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T122,T318
1	1	0	Covered	T67,T237,T247
1	1	1	Covered	T66,T68,T118

 LINE       2179
 EXPRESSION (addr_hit[16] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T52,T150,T319
1	1	0	Covered	T67,T246,T247
1	1	1	Covered	T66,T68,T118

 LINE       2184
 EXPRESSION (addr_hit[17] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T7,T52,T251
1	1	0	Covered	T117,T67,T237
1	1	1	Covered	T66,T68,T118

 LINE       2189
 EXPRESSION (addr_hit[18] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T24,T52,T63
1	1	0	Covered	T67,T237,T118
1	1	1	Covered	T66,T68,T118

 LINE       2192
 EXPRESSION (addr_hit[19] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T24,T52,T193
1	1	0	Covered	T117,T67,T237
1	1	1	Covered	T66,T68,T118

 LINE       2195
 EXPRESSION (addr_hit[20] & reg_we & ((!reg_error)))
             ------1-----   ---2--   -------3------

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T66,T68,T118
1	0	1	Covered	T20,T28,T24
1	1	0	Covered	T117,T67,T237
1	1	1	Covered	T66,T68,T118

---

Branch Coverage for Module : flash_ctrl_prim_reg_top

	Line No.	Total	Covered	Percent
Branches		27	27	100.00
TERNARY	2030	2	2	100.00
IF	68	3	3	100.00
CASE	2230	22	22	100.00

2030         assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ;
                                                  -1-  
                                                  ==>  
                                                  ==>  

Branches:

-1-	Status	Tests
1	Covered	T117,T66,T67
0	Covered	T1,T2,T3

68             if (!rst_ni) begin
               -1-  
69               err_q <= '0;
                 ==>
70             end else if (intg_err || reg_we_err) begin
                        -2-  
71               err_q <= 1'b1;
                 ==>
72             end
               MISSING_ELSE
               ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T2,T3
0	1	Covered	T44,T47,T48
0	0	Covered	T1,T2,T3

2230           unique case (1'b1)
                      -1-  
2231             addr_hit[0]: begin
2232               reg_rdata_next[0] = csr0_regwen_qs;
                   ==>
2233             end
2234       
2235             addr_hit[1]: begin
2236               reg_rdata_next[7:0] = csr1_field0_qs;
                   ==>
2237               reg_rdata_next[12:8] = csr1_field1_qs;
2238             end
2239       
2240             addr_hit[2]: begin
2241               reg_rdata_next[0] = csr2_field0_qs;
                   ==>
2242               reg_rdata_next[1] = csr2_field1_qs;
2243               reg_rdata_next[2] = csr2_field2_qs;
2244               reg_rdata_next[3] = csr2_field3_qs;
2245               reg_rdata_next[4] = csr2_field4_qs;
2246               reg_rdata_next[5] = csr2_field5_qs;
2247               reg_rdata_next[6] = csr2_field6_qs;
2248               reg_rdata_next[7] = csr2_field7_qs;
2249             end
2250       
2251             addr_hit[3]: begin
2252               reg_rdata_next[3:0] = csr3_field0_qs;
                   ==>
2253               reg_rdata_next[7:4] = csr3_field1_qs;
2254               reg_rdata_next[10:8] = csr3_field2_qs;
2255               reg_rdata_next[13:11] = csr3_field3_qs;
2256               reg_rdata_next[16:14] = csr3_field4_qs;
2257               reg_rdata_next[19:17] = csr3_field5_qs;
2258               reg_rdata_next[20] = csr3_field6_qs;
2259               reg_rdata_next[23:21] = csr3_field7_qs;
2260               reg_rdata_next[25:24] = csr3_field8_qs;
2261               reg_rdata_next[27:26] = csr3_field9_qs;
2262             end
2263       
2264             addr_hit[4]: begin
2265               reg_rdata_next[2:0] = csr4_field0_qs;
                   ==>
2266               reg_rdata_next[5:3] = csr4_field1_qs;
2267               reg_rdata_next[8:6] = csr4_field2_qs;
2268               reg_rdata_next[11:9] = csr4_field3_qs;
2269             end
2270       
2271             addr_hit[5]: begin
2272               reg_rdata_next[2:0] = csr5_field0_qs;
                   ==>
2273               reg_rdata_next[4:3] = csr5_field1_qs;
2274               reg_rdata_next[13:5] = csr5_field2_qs;
2275               reg_rdata_next[18:14] = csr5_field3_qs;
2276               reg_rdata_next[22:19] = csr5_field4_qs;
2277             end
2278       
2279             addr_hit[6]: begin
2280               reg_rdata_next[2:0] = csr6_field0_qs;
                   ==>
2281               reg_rdata_next[5:3] = csr6_field1_qs;
2282               reg_rdata_next[13:6] = csr6_field2_qs;
2283               reg_rdata_next[16:14] = csr6_field3_qs;
2284               reg_rdata_next[18:17] = csr6_field4_qs;
2285               reg_rdata_next[20:19] = csr6_field5_qs;
2286               reg_rdata_next[22:21] = csr6_field6_qs;
2287               reg_rdata_next[23] = csr6_field7_qs;
2288               reg_rdata_next[24] = csr6_field8_qs;
2289             end
2290       
2291             addr_hit[7]: begin
2292               reg_rdata_next[7:0] = csr7_field0_qs;
                   ==>
2293               reg_rdata_next[16:8] = csr7_field1_qs;
2294             end
2295       
2296             addr_hit[8]: begin
2297               reg_rdata_next[31:0] = csr8_qs;
                   ==>
2298             end
2299       
2300             addr_hit[9]: begin
2301               reg_rdata_next[31:0] = csr9_qs;
                   ==>
2302             end
2303       
2304             addr_hit[10]: begin
2305               reg_rdata_next[31:0] = csr10_qs;
                   ==>
2306             end
2307       
2308             addr_hit[11]: begin
2309               reg_rdata_next[31:0] = csr11_qs;
                   ==>
2310             end
2311       
2312             addr_hit[12]: begin
2313               reg_rdata_next[9:0] = csr12_qs;
                   ==>
2314             end
2315       
2316             addr_hit[13]: begin
2317               reg_rdata_next[19:0] = csr13_field0_qs;
                   ==>
2318               reg_rdata_next[20] = csr13_field1_qs;
2319             end
2320       
2321             addr_hit[14]: begin
2322               reg_rdata_next[7:0] = csr14_field0_qs;
                   ==>
2323               reg_rdata_next[8] = csr14_field1_qs;
2324             end
2325       
2326             addr_hit[15]: begin
2327               reg_rdata_next[7:0] = csr15_field0_qs;
                   ==>
2328               reg_rdata_next[8] = csr15_field1_qs;
2329             end
2330       
2331             addr_hit[16]: begin
2332               reg_rdata_next[7:0] = csr16_field0_qs;
                   ==>
2333               reg_rdata_next[8] = csr16_field1_qs;
2334             end
2335       
2336             addr_hit[17]: begin
2337               reg_rdata_next[7:0] = csr17_field0_qs;
                   ==>
2338               reg_rdata_next[8] = csr17_field1_qs;
2339             end
2340       
2341             addr_hit[18]: begin
2342               reg_rdata_next[0] = csr18_qs;
                   ==>
2343             end
2344       
2345             addr_hit[19]: begin
2346               reg_rdata_next[0] = csr19_qs;
                   ==>
2347             end
2348       
2349             addr_hit[20]: begin
2350               reg_rdata_next[0] = csr20_field0_qs;
                   ==>
2351               reg_rdata_next[1] = csr20_field1_qs;
2352               reg_rdata_next[2] = csr20_field2_qs;
2353             end
2354       
2355             default: begin
2356               reg_rdata_next = '1;
                   ==>

Branches:

-1-	Status	Tests
addr_hit[0]	Covered	T2,T3,T18
addr_hit[1]	Covered	T2,T3,T18
addr_hit[2]	Covered	T2,T3,T18
addr_hit[3]	Covered	T2,T3,T18
addr_hit[4]	Covered	T2,T3,T18
addr_hit[5]	Covered	T2,T3,T18
addr_hit[6]	Covered	T2,T3,T18
addr_hit[7]	Covered	T2,T3,T18
addr_hit[8]	Covered	T2,T3,T18
addr_hit[9]	Covered	T2,T3,T18
addr_hit[10]	Covered	T2,T3,T18
addr_hit[11]	Covered	T2,T3,T18
addr_hit[12]	Covered	T2,T3,T18
addr_hit[13]	Covered	T2,T3,T18
addr_hit[14]	Covered	T2,T3,T18
addr_hit[15]	Covered	T2,T3,T18
addr_hit[16]	Covered	T2,T3,T18
addr_hit[17]	Covered	T2,T3,T7
addr_hit[18]	Covered	T2,T3,T18
addr_hit[19]	Covered	T2,T3,T18
addr_hit[20]	Covered	T2,T3,T18
default	Covered	T1,T2,T3

---

Assert Coverage for Module : flash_ctrl_prim_reg_top

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
en2addrHit	390543610	55555	0	0
reAfterRv	390543610	55555	0	0
rePulse	390543610	37830	0	0
wePulse	390543610	17725	0	0

en2addrHit

Name	Attempts	Real Successes	Failures	Incomplete
Total	390543610	55555	0	0
T66	2587	128	0	0
T67	5438	72	0	0
T68	9759	186	0	0
T117	2984	22	0	0
T118	10393	168	0	0
T237	5747	45	0	0
T246	3584	21	0	0
T257	3520	60	0	0
T258	5137	130	0	0
T259	4083	61	0	0

reAfterRv

Name	Attempts	Real Successes	Failures	Incomplete
Total	390543610	55555	0	0
T66	2587	128	0	0
T67	5438	72	0	0
T68	9759	186	0	0
T117	2984	22	0	0
T118	10393	168	0	0
T237	5747	45	0	0
T246	3584	21	0	0
T257	3520	60	0	0
T258	5137	130	0	0
T259	4083	61	0	0

rePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	390543610	37830	0	0
T66	2587	86	0	0
T67	5438	2	0	0
T68	9759	141	0	0
T117	2984	10	0	0
T118	10393	125	0	0
T237	5747	5	0	0
T246	3584	5	0	0
T257	3520	39	0	0
T258	5137	88	0	0
T259	4083	40	0	0

wePulse

Name	Attempts	Real Successes	Failures	Incomplete
Total	390543610	17725	0	0
T66	2587	42	0	0
T67	5438	70	0	0
T68	9759	45	0	0
T117	2984	12	0	0
T118	10393	43	0	0
T237	5747	40	0	0
T246	3584	16	0	0
T257	3520	21	0	0
T258	5137	42	0	0
T259	4083	21	0	0