Unified Coverage Report :: Module

Module : tlul_rsp_intg_gen

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.42	90.83					100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_31/flash_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_tlul_trans_intg_0.1/rtl/tlul_rsp_intg_gen.sv

Module self-instances :

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.33	66.67					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.91	100.00	95.65			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.00	80.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	92.86					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.96	100.00	91.84			100.00	100.00	u_reg_if

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00

Module Instance : tb.dut.u_to_prog_fifo.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
83.96	100.00	65.52			85.71	84.62	u_to_prog_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_to_rd_fifo.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.67	83.33					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
92.89	100.00	75.00			96.55	100.00	u_to_rd_fifo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_reg_core.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.88	100.00	99.51			100.00	100.00	u_reg_core

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rsp_intg.u_rsp_gen	100.00	100.00

Module Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
57.14	71.43	50.00			50.00		gen_err_resp.err_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Module Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.67	100.00	90.00			100.00		u_tlul_err_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Module Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
84.44	100.00	70.00			83.33		u_tlul_err_resp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Module Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.06	100.00	79.69			96.55	100.00	u_tl_adapter_eflash

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_rsp_intg.u_rsp_gen	100.00	100.00

Module Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00	100.00	u_reg_top

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_data_intg.u_tlul_data_integ_enc	100.00	100.00
gen_rsp_intg.u_rsp_gen	100.00	100.00

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_rsp_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_tl_adapter_eflash.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         1/1              assign data_intg = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :

SCORE	LINE
90.00	80.00

tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	32	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



31                        end else begin : gen_passthrough_rsp_intg
32         0/1     ==>      assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

SCORE	LINE
100.00	100.00

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Line Coverage for Module : tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )
Line Coverage for Module self-instances :

SCORE	LINE
91.67	83.33

tb.dut.u_to_prog_fifo.u_rsp_gen

SCORE	LINE
91.67	83.33

tb.dut.u_to_rd_fifo.u_rsp_gen

SCORE	LINE
83.33	66.67

tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



31                        end else begin : gen_passthrough_rsp_intg
32         0/1     ==>      assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         1/1              assign data_intg = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Module : tlul_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	11635	11635	0	0
PayLoadWidthCheck	11635	11635	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	11635	11635
T1	10	10
T2	10	10
T3	10	10
T7	10	10
T8	10	10
T14	10	10
T16	10	10
T18	10	10
T19	10	10
T20	10	10

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	11635	11635
T1	10	10
T2	10	10
T3	10	10
T7	10	10
T8	10	10
T14	10	10
T16	10	10
T18	10	10
T19	10	10
T20	10	10

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	4	66.67
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



31                        end else begin : gen_passthrough_rsp_intg
32         0/1     ==>      assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         0/1     ==>      assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1271	1271	0	0
PayLoadWidthCheck	1271	1271	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	4	80.00
CONT_ASSIGN	32	1	0	0.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



31                        end else begin : gen_passthrough_rsp_intg
32         0/1     ==>      assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1271	1271	0	0
PayLoadWidthCheck	1271	1271	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_to_prog_fifo.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



31                        end else begin : gen_passthrough_rsp_intg
32         0/1     ==>      assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         1/1              assign data_intg = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_to_prog_fifo.u_rsp_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1056	1056	0	0
PayLoadWidthCheck	1056	1056	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_to_rd_fifo.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	5	83.33
CONT_ASSIGN	32	1	0	0.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



31                        end else begin : gen_passthrough_rsp_intg
32         0/1     ==>      assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         1/1              assign data_intg = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_to_rd_fifo.u_rsp_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1056	1056	0	0
PayLoadWidthCheck	1056	1056	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         1/1              assign data_intg = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_reg_core.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1271	1271	0	0
PayLoadWidthCheck	1271	1271	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1271	1271	0	0
PayLoadWidthCheck	1271	1271	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1056	1056	0	0
PayLoadWidthCheck	1056	1056	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1056	1056	0	0
PayLoadWidthCheck	1056	1056	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen

	Line No.	Total	Covered	Percent
TOTAL		6	6	100.00
CONT_ASSIGN	25	1	1	100.00
CONT_ASSIGN	43	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43         1/1              assign data_intg = tl_i.d_user.data_intg;
           Tests:       T1 T2 T3 
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_tl_adapter_eflash.u_rsp_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1056	1056	0	0
PayLoadWidthCheck	1056	1056	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1056	1056
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

Line Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

	Line No.	Total	Covered	Percent
TOTAL		5	5	100.00
CONT_ASSIGN	25	1	1	100.00
ALWAYS	47	3	3	100.00
CONT_ASSIGN	53	1	1	100.00



24                      
25         1/1              assign rsp = extract_d2h_rsp_intg(tl_i);
           Tests:       T1 T2 T3 
26                      
27                          prim_secded_inv_64_57_enc u_rsp_gen (
28                            .data_i(D2HRspMaxWidth'(rsp)),
29                            .data_o({rsp_intg, unused_payload})
30                          );
31                        end else begin : gen_passthrough_rsp_intg
32                          assign rsp_intg = tl_i.d_user.rsp_intg;
33                        end
34                      
35                        logic [DataIntgWidth-1:0] data_intg;
36                        if (EnableDataIntgGen) begin : gen_data_intg
37                          logic [DataMaxWidth-1:0] unused_data;
38                          tlul_data_integ_enc u_tlul_data_integ_enc (
39                            .data_i(DataMaxWidth'(tl_i.d_data)),
40                            .data_intg_o({data_intg, unused_data})
41                          );
42                        end else begin : gen_passthrough_data_intg
43                          assign data_intg = tl_i.d_user.data_intg;
44                        end
45                      
46                        always_comb begin
47         1/1              tl_o = tl_i;
           Tests:       T1 T2 T3 
48         1/1              tl_o.d_user.rsp_intg = rsp_intg;
           Tests:       T1 T2 T3 
49         1/1              tl_o.d_user.data_intg = data_intg;
           Tests:       T1 T2 T3 
50                        end
51                      
52                        logic unused_tl;
53         1/1            assign unused_tl = ^tl_i;
           Tests:       T1 T2 T3

Assert Coverage for Instance : tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataWidthCheck_A	1271	1271	0	0
PayLoadWidthCheck	1271	1271	0	0

DataWidthCheck_A

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1

PayLoadWidthCheck

Name	Attempts	Real Successes
Total	1271	1271
T1	1	1
T2	1	1
T3	1	1
T7	1	1
T8	1	1
T14	1	1
T16	1	1
T18	1	1
T19	1	1
T20	1	1