Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts



Module Instance : tb.dut.u_flash_mp

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.64 100.00 98.56 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
99.69 100.00 98.77 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_hw_sel 100.00 100.00 100.00
u_sw_sel 100.00 100.00 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_mp
Line No.TotalCoveredPercent
TOTAL7676100.00
CONT_ASSIGN7811100.00
CONT_ASSIGN7911100.00
CONT_ASSIGN8011100.00
CONT_ASSIGN10011100.00
CONT_ASSIGN10411100.00
CONT_ASSIGN10511100.00
CONT_ASSIGN12111100.00
CONT_ASSIGN12911100.00
CONT_ASSIGN13211100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN14911100.00
CONT_ASSIGN17411100.00
CONT_ASSIGN17911100.00
CONT_ASSIGN18011100.00
ALWAYS18500
ALWAYS18522100.00
CONT_ASSIGN19111100.00
CONT_ASSIGN19511100.00
CONT_ASSIGN19811100.00
CONT_ASSIGN20111100.00
CONT_ASSIGN20411100.00
CONT_ASSIGN20611100.00
CONT_ASSIGN20911100.00
CONT_ASSIGN21211100.00
CONT_ASSIGN21511100.00
ALWAYS2401010100.00
CONT_ASSIGN26211100.00
CONT_ASSIGN26311100.00
CONT_ASSIGN26611100.00
CONT_ASSIGN26911100.00
CONT_ASSIGN27011100.00
CONT_ASSIGN27111100.00
CONT_ASSIGN27311100.00
CONT_ASSIGN27411100.00
CONT_ASSIGN27711100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN28111100.00
CONT_ASSIGN28911100.00
CONT_ASSIGN29011100.00
CONT_ASSIGN29111100.00
CONT_ASSIGN29211100.00
CONT_ASSIGN29311100.00
CONT_ASSIGN29411100.00
CONT_ASSIGN29511100.00
CONT_ASSIGN29611100.00
CONT_ASSIGN30111100.00
ALWAYS30766100.00
CONT_ASSIGN31611100.00
CONT_ASSIGN31711100.00
CONT_ASSIGN31811100.00
CONT_ASSIGN31911100.00
CONT_ASSIGN32411100.00
CONT_ASSIGN32511100.00
CONT_ASSIGN32611100.00
CONT_ASSIGN37511100.00

77 78 1/1 assign bank_page_addr = req_addr_i; Tests: T1 T2 T3  79 1/1 assign bank_addr = req_addr_i[AllPagesW-1 -: BankW]; Tests: T1 T2 T3  80 1/1 assign page_addr = req_addr_i[PageW-1:0]; Tests: T1 T2 T3  81 82 logic [NumBanks-1:0] bk_erase_en; 83 logic data_rd_en; 84 logic data_prog_en; 85 logic data_pg_erase_en; 86 logic data_bk_erase_en; 87 logic data_scramble_en; 88 logic data_ecc_en; 89 logic data_he_en; 90 logic info_rd_en; 91 logic info_prog_en; 92 logic info_pg_erase_en; 93 logic info_bk_erase_en; 94 logic info_scramble_en; 95 logic info_ecc_en; 96 logic info_he_en; 97 98 // Memory properties handling for hardware interface 99 logic hw_sel; 100 1/1 assign hw_sel = if_sel_i == HwSel; Tests: T1 T2 T3  101 102 logic data_part_sel; 103 logic info_part_sel; 104 1/1 assign data_part_sel = req_part_i == FlashPartData; Tests: T1 T2 T3  105 1/1 assign info_part_sel = req_part_i == FlashPartInfo; Tests: T1 T2 T3  106 107 108 //////////////////////////////////////// 109 // Check address out of bounds 110 // Applies for all partitions 111 //////////////////////////////////////// 112 logic addr_invalid; 113 logic bank_invalid; 114 logic [PageW-1:0] end_addr; 115 116 // when number of banks are power of 2, invalid bank is handled by addr_ovfl_i 117 if (NumBanks % 2 > 0) begin : gen_bank_check 118 assign bank_invalid = bank_addr > NumBanks; 119 end else begin : gen_no_bank_check 120 logic [BankW-1:0] unused_bank_addr; 121 1/1 assign unused_bank_addr = bank_addr; Tests: T1 T2 T3  122 assign bank_invalid = '0; 123 end 124 125 // address is invalid if: 126 // the address extends beyond the end of the partition in question 127 // the bank selection is invalid 128 // if the address overflowed the control counters 129 1/1 assign end_addr = data_part_sel ? DataPartitionEndAddr : Tests: T1 T2 T3  130 InfoPartitionEndAddr[info_sel_i]; 131 132 1/1 assign addr_invalid = req_i & Tests: T1 T2 T3  133 (page_addr > end_addr | 134 bank_invalid | 135 addr_ovfl_i 136 ); 137 138 //////////////////////////////////////// 139 // Check data partition access 140 //////////////////////////////////////// 141 logic invalid_data_txn; 142 data_region_attr_t sw_data_attrs [TotalRegions]; 143 mp_region_cfg_t sw_sel_cfg; 144 mp_region_cfg_t hw_sel_cfg; 145 146 // wrap software configurations into software attributes 147 for(genvar i = 0; i < TotalRegions; i++) begin : gen_region_attrs 148 assign sw_data_attrs[i].phase = PhaseInvalid; 149 9/9 assign sw_data_attrs[i].cfg = region_cfgs_i[i]; Tests: T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  | T1 T2 T3  150 end 151 152 flash_mp_data_region_sel #( 153 .Regions(TotalRegions) 154 ) u_sw_sel ( 155 .req_i(req_i & ~hw_sel), 156 .phase_i(PhaseInvalid), 157 .addr_i(bank_page_addr), 158 .region_attrs_i(sw_data_attrs), 159 .sel_cfg_o(sw_sel_cfg) 160 ); 161 162 flash_mp_data_region_sel #( 163 .Regions(HwDataRules) 164 ) u_hw_sel ( 165 .req_i(req_i & hw_sel), 166 .phase_i(phase_i), 167 .addr_i(bank_page_addr), 168 .region_attrs_i(HwDataAttr), 169 .sel_cfg_o(hw_sel_cfg) 170 ); 171 172 // select between hardware and software interfaces 173 mp_region_cfg_t data_region_cfg; 174 1/1 assign data_region_cfg = hw_sel ? hw_sel_cfg : sw_sel_cfg; Tests: T1 T2 T3  175 176 // tie off unused signals 177 logic [31:0] unused_region_base; 178 logic [31:0] unused_region_size; 179 1/1 assign unused_region_base = 32'(data_region_cfg.base); Tests: T1 T2 T3  180 1/1 assign unused_region_size = 32'(data_region_cfg.size); Tests: T1 T2 T3  181 182 // check for bank erase 183 // bank erase allowed for only data partition and software interface 184 always_comb begin 185 1/1 for (int unsigned i = 0; i < NumBanks; i++) begin: bank_comps Tests: T1 T2 T3  186 1/1 bk_erase_en[i] = (bank_addr == i[BankW-1:0]) & bank_cfgs_i[i].q & ~hw_sel; Tests: T1 T2 T3  187 end 188 end 189 190 logic data_en; 191 1/1 assign data_en = data_part_sel & Tests: T1 T2 T3  192 ~addr_invalid & 193 mubi4_test_true_strict(data_region_cfg.en); 194 195 1/1 assign data_rd_en = data_en & rd_i & Tests: T1 T2 T3  196 mubi4_test_true_strict(data_region_cfg.rd_en); 197 198 1/1 assign data_prog_en = data_en & prog_i & Tests: T1 T2 T3  199 mubi4_test_true_strict(data_region_cfg.prog_en); 200 201 1/1 assign data_pg_erase_en = data_en & pg_erase_i & Tests: T1 T2 T3  202 mubi4_test_true_strict(data_region_cfg.erase_en); 203 204 1/1 assign data_bk_erase_en = bk_erase_i & |bk_erase_en; Tests: T1 T2 T3  205 206 1/1 assign data_scramble_en = data_en & (rd_i | prog_i) & Tests: T1 T2 T3  207 mubi4_test_true_strict(data_region_cfg.scramble_en); 208 209 1/1 assign data_ecc_en = data_en & (rd_i | prog_i) & Tests: T1 T2 T3  210 mubi4_test_true_strict(data_region_cfg.ecc_en); 211 212 1/1 assign data_he_en = data_en & Tests: T1 T2 T3  213 mubi4_test_true_strict(data_region_cfg.he_en); 214 215 1/1 assign invalid_data_txn = req_i & data_part_sel & Tests: T1 T2 T3  216 ~(data_rd_en | 217 data_prog_en | 218 data_pg_erase_en | 219 data_bk_erase_en 220 ); 221 222 //////////////////////////////////////// 223 // Check info partition access 224 //////////////////////////////////////// 225 226 // hardware interface permission check 227 info_page_cfg_t hw_page_cfg_pre, hw_page_cfg; 228 229 // rule match used for assertions only 230 logic [HwInfoRules-1:0] unused_rule_match; 231 232 // software interface permission check 233 logic [InfoPageW-1:0] info_page_addr; 234 info_page_cfg_t page_cfg; 235 logic info_en; 236 logic invalid_info_txn; 237 238 // select appropriate hw page configuration based on phase and page matching 239 always_comb begin 240 1/1 hw_page_cfg_pre = '0; Tests: T1 T2 T3  241 1/1 unused_rule_match = '0; Tests: T1 T2 T3  242 1/1 if (hw_sel && req_i) begin Tests: T1 T2 T3  243 1/1 for (int unsigned i = 0; i < HwInfoRules; i++) begin: hw_info_region_comps Tests: T1 T2 T3  244 // select the appropriate hardware page 245 1/1 if (bank_page_addr == HwInfoPageAttr[i].page.addr && Tests: T1 T2 T3  246 info_sel_i == HwInfoPageAttr[i].page.sel && 247 phase_i == HwInfoPageAttr[i].phase) begin 248 1/1 unused_rule_match[i] = 1'b1; Tests: T1 T2 T3  249 1/1 hw_page_cfg_pre = HwInfoPageAttr[i].cfg; Tests: T1 T2 T3  250 end MISSING_ELSE 251 end 252 end MISSING_ELSE 253 254 1/1 hw_page_cfg = hw_page_cfg_pre; Tests: T1 T2 T3  255 1/1 hw_page_cfg.scramble_en = prim_mubi_pkg::mubi4_and_hi(hw_page_cfg_pre.scramble_en, Tests: T1 T2 T3  256 mubi4_t'(~hw_info_scramble_dis_i)); 257 1/1 hw_page_cfg.ecc_en = prim_mubi_pkg::mubi4_and_hi(hw_page_cfg_pre.ecc_en, Tests: T1 T2 T3  258 mubi4_t'(~hw_info_ecc_dis_i)); 259 end 260 261 // select appropriate page configuration 262 1/1 assign info_page_addr = req_addr_i[InfoPageW-1:0]; Tests: T1 T2 T3  263 1/1 assign page_cfg = hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr]; Tests: T1 T2 T3  264 265 // final operation 266 1/1 assign info_en = info_part_sel & Tests: T1 T2 T3  267 ~addr_invalid & 268 mubi4_test_true_strict(page_cfg.en); 269 1/1 assign info_rd_en = info_en & rd_i & mubi4_test_true_strict(page_cfg.rd_en); Tests: T1 T2 T3  270 1/1 assign info_prog_en = info_en & prog_i & mubi4_test_true_strict(page_cfg.prog_en); Tests: T1 T2 T3  271 1/1 assign info_pg_erase_en = info_en & pg_erase_i & mubi4_test_true_strict(page_cfg.erase_en); Tests: T1 T2 T3  272 // when info is selected for bank erase, the page configuration does not matter 273 1/1 assign info_bk_erase_en = info_part_sel & bk_erase_i & |bk_erase_en; Tests: T1 T2 T3  274 1/1 assign info_scramble_en = info_en & (rd_i | prog_i) & Tests: T1 T2 T3  275 mubi4_test_true_strict(page_cfg.scramble_en); 276 277 1/1 assign info_ecc_en = info_en & (rd_i | prog_i) & mubi4_test_true_strict(page_cfg.ecc_en); Tests: T1 T2 T3  278 1/1 assign info_he_en = info_en & mubi4_test_true_strict(page_cfg.he_en); Tests: T1 T2 T3  279 280 // check for invalid transactions 281 1/1 assign invalid_info_txn = req_i & info_part_sel & Tests: T1 T2 T3  282 ~(info_rd_en | info_prog_en | info_pg_erase_en | 283 info_bk_erase_en); 284 285 286 //////////////////////////////////////// 287 // Combine all check results 288 //////////////////////////////////////// 289 1/1 assign rd_o = req_i & (data_rd_en | info_rd_en); Tests: T1 T2 T3  290 1/1 assign prog_o = req_i & (data_prog_en | info_prog_en); Tests: T1 T2 T3  291 1/1 assign pg_erase_o = req_i & (data_pg_erase_en | info_pg_erase_en); Tests: T1 T2 T3  292 1/1 assign bk_erase_o = req_i & (data_bk_erase_en | info_bk_erase_en); Tests: T1 T2 T3  293 1/1 assign scramble_en_o = req_i & (data_scramble_en | info_scramble_en); Tests: T1 T2 T3  294 1/1 assign ecc_en_o = req_i & (data_ecc_en | info_ecc_en); Tests: T1 T2 T3  295 1/1 assign he_en_o = req_i & (data_he_en | info_he_en); Tests: T1 T2 T3  296 1/1 assign req_o = rd_o | prog_o | pg_erase_o | bk_erase_o; Tests: T1 T2 T3  297 298 logic txn_err; 299 logic no_allowed_txn; 300 // if flash_disable is true, transaction is always invalid 301 1/1 assign no_allowed_txn = req_i & Tests: T1 T2 T3  302 ((prim_mubi_pkg::mubi4_test_true_loose(flash_disable_i)) | 303 (addr_invalid | invalid_data_txn | invalid_info_txn)); 304 305 // return done and error the next cycle 306 always_ff @(posedge clk_i or negedge rst_ni) begin 307 1/1 if (!rst_ni) begin Tests: T1 T2 T3  308 1/1 txn_err <= 1'b0; Tests: T1 T2 T3  309 1/1 end else if (txn_err) begin Tests: T1 T2 T3  310 1/1 txn_err <= 1'b0; Tests: T27 T30 T9  311 1/1 end else if (no_allowed_txn) begin Tests: T1 T2 T3  312 1/1 txn_err <= 1'b1; Tests: T27 T30 T9  313 end MISSING_ELSE 314 end 315 316 1/1 assign rd_done_o = rd_done_i | txn_err; Tests: T1 T2 T3  317 1/1 assign prog_done_o = prog_done_i | txn_err; Tests: T1 T2 T3  318 1/1 assign erase_done_o = erase_done_i | txn_err; Tests: T1 T2 T3  319 1/1 assign error_o = txn_err; Tests: T1 T2 T3  320 321 // if no ongoing erase operation, immediately return 322 // if ongoing erase operation, wait for flash phy return 323 logic erase_valid; 324 1/1 assign erase_valid = pg_erase_o | bk_erase_o; Tests: T1 T2 T3  325 1/1 assign erase_suspend_o = erase_valid & erase_suspend_i; Tests: T1 T2 T3  326 1/1 assign erase_suspend_done_o = erase_suspend_i & ~erase_valid | Tests: T1 T2 T3  327 erase_suspend_o & erase_done_o; 328 329 330 ////////////////////////////////////////////// 331 // Assertions, Assumptions, and Coverpoints // 332 ////////////////////////////////////////////// 333 334 // Bank erase enable should always be one-hot. We cannot erase multiple banks 335 // at the same time 336 `ASSERT(bkEraseEnOnehot_A, (req_o & bk_erase_o) |-> $onehot(bk_erase_en)) 337 // Requests can only happen one at a time 338 `ASSERT(requestTypesOnehot_A, req_o |-> $onehot({rd_o, prog_o, pg_erase_o, bk_erase_o})) 339 // Info / data errors are mutually exclusive 340 `ASSERT(invalidReqOnehot_A, req_o |-> $onehot0({invalid_data_txn, invalid_info_txn})) 341 // Cannot match more than one info rule at a time 342 `ASSERT(hwInfoRuleOnehot_A, req_i & hw_sel |-> $onehot0(unused_rule_match)) 343 // An input request should lead to an output request if there are no errors 344 `ASSERT(InReqOutReq_A, req_i |-> req_o | no_allowed_txn) 345 // An Info request should not lead to data requests 346 `ASSERT(InfoReqToData_A, req_i & info_part_sel |-> ~|{data_en, 347 data_rd_en, 348 data_prog_en, 349 data_pg_erase_en}) 350 // A data request should not lead to info requests 351 `ASSERT(DataReqToInfo_A, req_i & data_part_sel |-> 352 ~|{info_en, 353 info_rd_en, 354 info_prog_en, 355 info_pg_erase_en, 356 info_bk_erase_en}) 357 358 // If a bank erase request only selects data, then info should be erased 359 `ASSERT(BankEraseData_A, req_i & bk_erase_i & |bk_erase_en & data_part_sel |-> data_bk_erase_en & 360 ~info_bk_erase_en) 361 362 // If a bank erase request also selects the info partition, then both data 363 // and info must be erased 364 `ASSERT(BankEraseInfo_A, req_i & bk_erase_i & |bk_erase_en & info_part_sel |-> &{data_bk_erase_en, 365 info_bk_erase_en}) 366 367 // When no transactions are allowed, the output request should always be 0. 368 // The assertion is disabled during escalation since req_o takes a few cycles to 369 // go to 0 if escalation is asserted mid transaction. 370 `ASSERT(NoReqWhenErr_A, no_allowed_txn |-> ~req_o, 371 clk_i, !rst_ni || lc_ctrl_pkg::lc_tx_test_true_loose(lc_escalate_en_i)) 372 373 // This signal is only used in the assertion above. 374 lc_ctrl_pkg::lc_tx_t unused_escalate_en; 375 1/1 assign unused_escalate_en = lc_escalate_en_i; Tests: T1 T2 T3 

Cond Coverage for Module : flash_mp
TotalCoveredPercent
Conditions13913798.56
Logical13913798.56
Non-Logical00
Event00

 LINE       100
 EXPRESSION (if_sel_i == HwSel)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       104
 EXPRESSION (req_part_i == FlashPartData)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       105
 EXPRESSION (req_part_i == FlashPartInfo)
            --------------1--------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       129
 EXPRESSION (data_part_sel ? flash_ctrl_pkg::DataPartitionEndAddr : flash_ctrl_pkg::InfoPartitionEndAddr[info_sel_i])
             ------1------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       132
 EXPRESSION (req_i & ((page_addr > end_addr) | bank_invalid | addr_ovfl_i))
             --1--   --------------------------2--------------------------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT1,T2,T3
11CoveredT150,T182,T222

 LINE       132
 SUB-EXPRESSION ((page_addr > end_addr) | bank_invalid | addr_ovfl_i)
                 -----------1----------   ------2-----   -----3-----
-1--2--3-StatusTests
000CoveredT1,T2,T3
001CoveredT100,T101
010Unreachable
100CoveredT26,T27,T28

 LINE       154
 EXPRESSION (req_i & ((~hw_sel)))
             --1--   -----2-----
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T2,T3
11CoveredT1,T3,T7

 LINE       164
 EXPRESSION (req_i & hw_sel)
             --1--   ---2--
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT1,T3,T7
11CoveredT1,T2,T3

 LINE       174
 EXPRESSION (hw_sel ? hw_sel_cfg : sw_sel_cfg)
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       186
 EXPRESSION ((bank_addr == i[0]) & bank_cfgs_i[i].q & ((~hw_sel)))
             ---------1---------   --------2-------   -----3-----
-1--2--3-StatusTests
011CoveredT14,T15,T22
101CoveredT1,T2,T3
110CoveredT93,T85,T124
111CoveredT14,T15,T22

 LINE       186
 SUB-EXPRESSION (bank_addr == i[0])
                ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       204
 EXPRESSION (bk_erase_i & ((|bk_erase_en)))
             -----1----   --------2-------
-1--2-StatusTests
01CoveredT14,T15,T22
10CoveredT102,T36,T238
11CoveredT70,T71,T72

 LINE       215
 EXPRESSION (req_i & data_part_sel & ( ~ (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en) ))
             --1--   ------2------   -----------------------------------3-----------------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T2,T3
110CoveredT1,T3,T7
111CoveredT30,T49,T116

 LINE       215
 SUB-EXPRESSION (data_rd_en | data_prog_en | data_pg_erase_en | data_bk_erase_en)
                 -----1----   ------2-----   --------3-------   --------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT70,T71,T72
0010CoveredT3,T15,T27
0100CoveredT3,T7,T19
1000CoveredT1,T3,T18

 LINE       242
 EXPRESSION (hw_sel && req_i)
             ---1--    --2--
-1--2-StatusTests
01CoveredT1,T3,T7
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       245
 EXPRESSION 
 Number  Term
      1  (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr) && 
      2  (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel) && 
      3  (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase))
-1--2--3-StatusTests
011CoveredT1,T2,T3
101Not Covered
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (bank_page_addr == flash_ctrl_pkg::HwInfoPageAttr[i].page.addr)
                -------------------------------1-------------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (info_sel_i == flash_ctrl_pkg::HwInfoPageAttr[i].page.sel)
                -----------------------------1----------------------------
-1-StatusTests
0CoveredT11,T12,T13
1CoveredT1,T2,T3

 LINE       245
 SUB-EXPRESSION (phase_i == flash_ctrl_pkg::HwInfoPageAttr[i].phase)
                --------------------------1-------------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       263
 EXPRESSION (hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr])
             ---1--
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       273
 EXPRESSION (info_part_sel & bk_erase_i & ((|bk_erase_en)))
             ------1------   -----2----   --------3-------
-1--2--3-StatusTests
011CoveredT70,T71,T72
101CoveredT22,T102,T89
110CoveredT102,T36,T238
111CoveredT36,T73,T156

 LINE       281
 EXPRESSION (req_i & info_part_sel & ( ~ (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en) ))
             --1--   ------2------   -----------------------------------3-----------------------------------
-1--2--3-StatusTests
011CoveredT1,T2,T3
101CoveredT1,T3,T7
110CoveredT1,T2,T3
111CoveredT27,T30,T59

 LINE       281
 SUB-EXPRESSION (info_rd_en | info_prog_en | info_pg_erase_en | info_bk_erase_en)
                 -----1----   ------2-----   --------3-------   --------4-------
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT36,T73,T156
0010CoveredT27,T22,T120
0100CoveredT8,T28,T30
1000CoveredT1,T2,T3

 LINE       289
 EXPRESSION (req_i & (data_rd_en | info_rd_en))
             --1--   ------------2------------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT3,T7,T19
11CoveredT1,T2,T3

 LINE       289
 SUB-EXPRESSION (data_rd_en | info_rd_en)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT1,T3,T18

 LINE       290
 EXPRESSION (req_i & (data_prog_en | info_prog_en))
             --1--   --------------2--------------
-1--2-StatusTests
01CoveredT8,T28,T30
10CoveredT1,T2,T3
11CoveredT3,T7,T19

 LINE       290
 SUB-EXPRESSION (data_prog_en | info_prog_en)
                 ------1-----   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT8,T28,T30
10CoveredT3,T7,T19

 LINE       291
 EXPRESSION (req_i & (data_pg_erase_en | info_pg_erase_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT27,T22,T120
10CoveredT1,T2,T3
11CoveredT3,T15,T27

 LINE       291
 SUB-EXPRESSION (data_pg_erase_en | info_pg_erase_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT27,T22,T120
10CoveredT3,T15,T27

 LINE       292
 EXPRESSION (req_i & (data_bk_erase_en | info_bk_erase_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT70,T71,T72
10CoveredT1,T2,T3
11CoveredT70,T71,T72

 LINE       292
 SUB-EXPRESSION (data_bk_erase_en | info_bk_erase_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT70,T71,T72

 LINE       293
 EXPRESSION (req_i & (data_scramble_en | info_scramble_en))
             --1--   ------------------2------------------
-1--2-StatusTests
01CoveredT8,T26,T27
10CoveredT1,T3,T7
11CoveredT1,T2,T3

 LINE       293
 SUB-EXPRESSION (data_scramble_en | info_scramble_en)
                 --------1-------   --------2-------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT18,T19,T20

 LINE       294
 EXPRESSION (req_i & (data_ecc_en | info_ecc_en))
             --1--   -------------2-------------
-1--2-StatusTests
01CoveredT8,T26,T27
10CoveredT1,T3,T7
11CoveredT1,T2,T3

 LINE       294
 SUB-EXPRESSION (data_ecc_en | info_ecc_en)
                 -----1-----   -----2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT18,T20,T26

 LINE       295
 EXPRESSION (req_i & (data_he_en | info_he_en))
             --1--   ------------2------------
-1--2-StatusTests
01CoveredT8,T26,T27
10CoveredT1,T3,T7
11CoveredT1,T2,T3

 LINE       295
 SUB-EXPRESSION (data_he_en | info_he_en)
                 -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T2,T3
10CoveredT14,T16,T15

 LINE       296
 EXPRESSION (rd_o | prog_o | pg_erase_o | bk_erase_o)
             --1-   ---2--   -----3----   -----4----
-1--2--3--4-StatusTests
0000CoveredT1,T2,T3
0001CoveredT70,T71,T72
0010CoveredT3,T15,T27
0100CoveredT3,T7,T19
1000CoveredT1,T2,T3

 LINE       316
 EXPRESSION (rd_done_i | txn_err)
             ----1----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT27,T30,T9
10CoveredT1,T2,T3

 LINE       317
 EXPRESSION (prog_done_i | txn_err)
             -----1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT27,T30,T9
10CoveredT3,T7,T19

 LINE       318
 EXPRESSION (erase_done_i | txn_err)
             ------1-----   ---2---
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT27,T30,T9
10CoveredT3,T15,T27

 LINE       324
 EXPRESSION (pg_erase_o | bk_erase_o)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT70,T71,T72
10CoveredT3,T15,T27

 LINE       325
 EXPRESSION (erase_valid & erase_suspend_i)
             -----1-----   -------2-------
-1--2-StatusTests
01CoveredT71,T74,T183
10CoveredT3,T15,T27
11CoveredT15,T93,T71

 LINE       326
 EXPRESSION ((erase_suspend_i & ((~erase_valid))) | (erase_suspend_o & erase_done_o))
             ------------------1-----------------   ----------------2---------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT15,T93,T71
10CoveredT71,T74,T183

 LINE       326
 SUB-EXPRESSION (erase_suspend_i & ((~erase_valid)))
                 -------1-------   --------2-------
-1--2-StatusTests
01CoveredT1,T2,T3
10CoveredT15,T93,T71
11CoveredT71,T74,T183

 LINE       326
 SUB-EXPRESSION (erase_suspend_o & erase_done_o)
                 -------1-------   ------2-----
-1--2-StatusTests
01CoveredT3,T15,T27
10CoveredT15,T93,T71
11CoveredT15,T93,T71

Branch Coverage for Module : flash_mp
Line No.TotalCoveredPercent
Branches 12 12 100.00
TERNARY 129 2 2 100.00
TERNARY 174 2 2 100.00
TERNARY 263 2 2 100.00
IF 242 2 2 100.00
IF 307 4 4 100.00


129 assign end_addr = data_part_sel ? DataPartitionEndAddr : -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


174 assign data_region_cfg = hw_sel ? hw_sel_cfg : sw_sel_cfg; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


263 assign page_cfg = hw_sel ? hw_page_cfg : info_page_cfgs_i[bank_addr][info_sel_i][info_page_addr]; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


242 if (hw_sel && req_i) begin -1- 243 for (int unsigned i = 0; i < HwInfoRules; i++) begin: hw_info_region_comps ==> 244 // select the appropriate hardware page 245 if (bank_page_addr == HwInfoPageAttr[i].page.addr && 246 info_sel_i == HwInfoPageAttr[i].page.sel && 247 phase_i == HwInfoPageAttr[i].phase) begin 248 unused_rule_match[i] = 1'b1; 249 hw_page_cfg_pre = HwInfoPageAttr[i].cfg; 250 end 251 end 252 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


307 if (!rst_ni) begin -1- 308 txn_err <= 1'b0; ==> 309 end else if (txn_err) begin -2- 310 txn_err <= 1'b0; ==> 311 end else if (no_allowed_txn) begin -3- 312 txn_err <= 1'b1; ==> 313 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T27,T30,T9
0 0 1 Covered T27,T30,T9
0 0 0 Covered T1,T2,T3


Assert Coverage for Module : flash_mp
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 10 10 100.00 10 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 10 10 100.00 10 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
BankEraseData_A 387955939 6685937 0 0
BankEraseInfo_A 387955939 9110060 0 0
DataReqToInfo_A 387955939 238332937 0 0
InReqOutReq_A 387955939 264547657 0 0
InfoReqToData_A 387955939 26214720 0 0
NoReqWhenErr_A 383283986 124872 0 0
bkEraseEnOnehot_A 387955939 15795997 0 0
hwInfoRuleOnehot_A 387955939 154280556 0 0
invalidReqOnehot_A 387955939 264422737 0 0
requestTypesOnehot_A 387955939 264422737 0 0


BankEraseData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 6685937 0 0
T29 2850 0 0 0
T70 70059 65540 0 0
T71 0 131247 0 0
T72 0 65540 0 0
T74 0 262471 0 0
T76 3338 0 0 0
T85 0 131080 0 0
T88 0 131080 0 0
T93 63949 0 0 0
T182 42577 0 0 0
T183 0 262475 0 0
T200 0 131080 0 0
T239 0 196620 0 0
T240 0 65540 0 0
T241 1455 0 0 0
T242 1997 0 0 0
T243 2357 0 0 0
T244 84369 0 0 0
T245 201268 0 0 0

BankEraseInfo_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 9110060 0 0
T36 120660 720940 0 0
T40 121280 0 0 0
T73 0 655400 0 0
T103 82671 0 0 0
T121 3342 0 0 0
T132 0 524320 0 0
T134 0 131080 0 0
T136 0 262160 0 0
T156 0 327700 0 0
T158 0 65540 0 0
T159 0 524320 0 0
T160 0 589860 0 0
T161 0 852020 0 0
T165 1536 0 0 0
T166 6054 0 0 0
T167 48017 0 0 0
T168 44385 0 0 0
T169 3471 0 0 0
T170 264512 0 0 0

DataReqToInfo_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 238332937 0 0
T1 2386 366 0 0
T2 1619 0 0 0
T3 2624 551 0 0
T7 3618 2190 0 0
T8 758 0 0 0
T14 57474 2039 0 0
T15 0 20959 0 0
T16 2778 776 0 0
T18 1453 511 0 0
T19 1592 2 0 0
T20 1905 514 0 0
T26 0 61 0 0

InReqOutReq_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 264547657 0 0
T1 2386 526 0 0
T2 1619 160 0 0
T3 2624 711 0 0
T7 3618 2350 0 0
T8 758 226 0 0
T14 57474 2199 0 0
T16 2778 936 0 0
T18 1453 671 0 0
T19 1592 322 0 0
T20 1905 674 0 0

InfoReqToData_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 26214720 0 0
T1 2386 160 0 0
T2 1619 160 0 0
T3 2624 160 0 0
T7 3618 160 0 0
T8 758 226 0 0
T14 57474 160 0 0
T16 2778 160 0 0
T18 1453 160 0 0
T19 1592 320 0 0
T20 1905 160 0 0

NoReqWhenErr_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 383283986 124872 0 0
T9 549 0 0 0
T10 795 0 0 0
T17 75910 198 0 0
T22 210407 0 0 0
T24 6305 0 0 0
T27 5600 10 0 0
T28 2201 0 0 0
T30 209846 406 0 0
T33 0 546 0 0
T41 0 424 0 0
T49 46019 700 0 0
T50 0 608 0 0
T59 70189 136 0 0
T116 0 2 0 0
T235 0 24 0 0

bkEraseEnOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 15795997 0 0
T29 2850 0 0 0
T36 0 720940 0 0
T70 70059 65540 0 0
T71 0 131247 0 0
T72 0 65540 0 0
T73 0 655400 0 0
T74 0 262471 0 0
T76 3338 0 0 0
T85 0 131080 0 0
T93 63949 0 0 0
T182 42577 0 0 0
T183 0 262475 0 0
T239 0 196620 0 0
T240 0 65540 0 0
T241 1455 0 0 0
T242 1997 0 0 0
T243 2357 0 0 0
T244 84369 0 0 0
T245 201268 0 0 0

hwInfoRuleOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 154280556 0 0
T1 2386 160 0 0
T2 1619 160 0 0
T3 2624 160 0 0
T7 3618 160 0 0
T8 758 160 0 0
T14 57474 160 0 0
T16 2778 160 0 0
T18 1453 160 0 0
T19 1592 320 0 0
T20 1905 160 0 0

invalidReqOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 264422737 0 0
T1 2386 526 0 0
T2 1619 160 0 0
T3 2624 711 0 0
T7 3618 2350 0 0
T8 758 226 0 0
T14 57474 2199 0 0
T16 2778 936 0 0
T18 1453 671 0 0
T19 1592 322 0 0
T20 1905 674 0 0

requestTypesOnehot_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 264422737 0 0
T1 2386 526 0 0
T2 1619 160 0 0
T3 2624 711 0 0
T7 3618 2350 0 0
T8 758 226 0 0
T14 57474 2199 0 0
T16 2778 936 0 0
T18 1453 671 0 0
T19 1592 322 0 0
T20 1905 674 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%