Module Definition
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Module Instance : tb.dut.u_intr_prog_empty

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_prog_lvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_rd_full

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_rd_lvl

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
86.94 90.00 77.78 80.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_op_done

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children



Module Instance : tb.dut.u_intr_corr_err

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 100.00 75.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Line Coverage for Module self-instances :
SCORELINE
86.94 90.00
tb.dut.u_intr_prog_empty

SCORELINE
86.94 90.00
tb.dut.u_intr_prog_lvl

SCORELINE
86.94 90.00
tb.dut.u_intr_rd_full

SCORELINE
86.94 90.00
tb.dut.u_intr_rd_lvl

Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 1/2 ==> else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Line Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Line Coverage for Module self-instances :
SCORELINE
93.75 100.00
tb.dut.u_intr_op_done

SCORELINE
93.75 100.00
tb.dut.u_intr_corr_err

Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Cond Coverage for Module self-instances :
SCORECOND
86.94 77.78
tb.dut.u_intr_prog_empty

SCORECOND
86.94 77.78
tb.dut.u_intr_prog_lvl

SCORECOND
86.94 77.78
tb.dut.u_intr_rd_full

SCORECOND
86.94 77.78
tb.dut.u_intr_rd_lvl

TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT1,T2,T3
11CoveredT26,T27,T28

Cond Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Cond Coverage for Module self-instances :
SCORECOND
93.75 75.00
tb.dut.u_intr_op_done

SCORECOND
93.75 75.00
tb.dut.u_intr_corr_err

TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10CoveredT1,T3,T7

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT1,T3,T7
11CoveredT26,T27,T28

Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Status" )
Branch Coverage for Module self-instances :
SCOREBRANCH
86.94 80.00
tb.dut.u_intr_prog_empty

SCOREBRANCH
86.94 80.00
tb.dut.u_intr_prog_lvl

SCOREBRANCH
86.94 80.00
tb.dut.u_intr_rd_full

SCOREBRANCH
86.94 80.00
tb.dut.u_intr_rd_lvl

Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Branch Coverage for Module : prim_intr_hw ( parameter Width=1,FlopOutput=1,IntrT="Event" )
Branch Coverage for Module self-instances :
SCOREBRANCH
93.75 100.00
tb.dut.u_intr_op_done

SCOREBRANCH
93.75 100.00
tb.dut.u_intr_corr_err

Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Module : prim_intr_hw
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 6336 6336 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 6336 6336 0 0
T1 6 6 0 0
T2 6 6 0 0
T3 6 6 0 0
T7 6 6 0 0
T8 6 6 0 0
T14 6 6 0 0
T16 6 6 0 0
T18 6 6 0 0
T19 6 6 0 0
T20 6 6 0 0

Line Coverage for Instance : tb.dut.u_intr_prog_empty
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 1/2 ==> else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_intr_prog_empty
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT3,T7,T19
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT3,T7,T19
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT26,T28,T29
10CoveredT1,T2,T3
11CoveredT26,T27,T28

Branch Coverage for Instance : tb.dut.u_intr_prog_empty
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_prog_empty
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1056 1056 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_prog_lvl
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 1/2 ==> else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_intr_prog_lvl
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT30,T31,T32
01Not Covered
10CoveredT1,T2,T3

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT30,T31,T32
01Not Covered
10CoveredT1,T2,T3

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT30,T31,T32
10CoveredT1,T2,T3
11CoveredT26,T27,T28

Branch Coverage for Instance : tb.dut.u_intr_prog_lvl
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_prog_lvl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1056 1056 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_rd_full
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 1/2 ==> else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_intr_rd_full
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT33,T34,T35

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT33,T34,T35

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT33,T34,T36
11CoveredT35,T37,T38

Branch Coverage for Instance : tb.dut.u_intr_rd_full
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_rd_full
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1056 1056 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_rd_lvl
Line No.TotalCoveredPercent
TOTAL10990.00
ALWAYS754375.00
CONT_ASSIGN8111100.00
CONT_ASSIGN8311100.00
CONT_ASSIGN8811100.00
ALWAYS9533100.00

74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 2/2 if (!rst_ni) test_q <= '0; Tests: T1 T2 T3  | T1 T2 T3  76 1/2 ==> else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; Tests: T1 T2 T3  MISSING_ELSE 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 1/1 assign hw2reg_intr_state_d_o = event_intr_i | test_q; Tests: T1 T2 T3  82 83 1/1 assign status = event_intr_i | test_q; Tests: T1 T2 T3  84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 1/1 assign unused_reg2hw = ^reg2hw_intr_state_q_i; Tests: T1 T2 T3  89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_intr_rd_lvl
TotalCoveredPercent
Conditions9777.78
Logical9777.78
Non-Logical00
Event00

 LINE       81
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT33,T39,T34

 LINE       83
 EXPRESSION (event_intr_i | g_intr_status.test_q)
             ------1-----   ----------2---------
-1--2-StatusTests
00CoveredT1,T2,T3
01Not Covered
10CoveredT33,T39,T34

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT33,T34,T36
11CoveredT39,T35,T40

Branch Coverage for Instance : tb.dut.u_intr_rd_lvl
Line No.TotalCoveredPercent
Branches 5 4 80.00
IF 75 3 2 66.67
IF 95 2 2 100.00


75 if (!rst_ni) test_q <= '0; -1- ==> 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; -2- ==> MISSING_ELSE ==>

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Not Covered
0 0 Covered T1,T2,T3


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_rd_lvl
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1056 1056 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_op_done
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_intr_op_done
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT1,T3,T7
10CoveredT1,T3,T7

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT1,T3,T7
11CoveredT26,T27,T28

Branch Coverage for Instance : tb.dut.u_intr_op_done
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_op_done
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1056 1056 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

Line Coverage for Instance : tb.dut.u_intr_corr_err
Line No.TotalCoveredPercent
TOTAL77100.00
CONT_ASSIGN6211100.00
CONT_ASSIGN6411100.00
CONT_ASSIGN6711100.00
CONT_ASSIGN6911100.00
ALWAYS9533100.00

61 logic [Width-1:0] new_event; 62 1/1 assign new_event = Tests: T1 T2 T3  63 (({Width{reg2hw_intr_test_qe_i}} & reg2hw_intr_test_q_i) | event_intr_i); 64 1/1 assign hw2reg_intr_state_de_o = |new_event; Tests: T1 T2 T3  65 // for scalar interrupts, this resolves to '1' with new event 66 // for vector interrupts, new events are OR'd in to existing interrupt state 67 1/1 assign hw2reg_intr_state_d_o = new_event | reg2hw_intr_state_q_i; Tests: T1 T2 T3  68 69 1/1 assign status = reg2hw_intr_state_q_i ; Tests: T1 T2 T3  70 end : g_intr_event 71 else if (IntrT == "Status") begin : g_intr_status 72 logic [Width-1:0] test_q; // Storing test. Cleared by SW 73 74 always_ff @(posedge clk_i or negedge rst_ni) begin 75 if (!rst_ni) test_q <= '0; 76 else if (reg2hw_intr_test_qe_i) test_q <= reg2hw_intr_test_q_i; 77 end 78 79 // TODO: In Status type, INTR_STATE is better to be external type and RO. 80 assign hw2reg_intr_state_de_o = 1'b 1; // always represent the status 81 assign hw2reg_intr_state_d_o = event_intr_i | test_q; 82 83 assign status = event_intr_i | test_q; 84 85 // To make the timing same to event type, status signal does not use CSR.q, 86 // rather the input of the CSR. 87 logic unused_reg2hw; 88 assign unused_reg2hw = ^reg2hw_intr_state_q_i; 89 end : g_intr_status 90 91 92 if (FlopOutput == 1) begin : gen_flop_intr_output 93 // flop the interrupt output 94 always_ff @(posedge clk_i or negedge rst_ni) begin 95 1/1 if (!rst_ni) begin Tests: T1 T2 T3  96 1/1 intr_o <= '0; Tests: T1 T2 T3  97 end else begin 98 1/1 intr_o <= status & reg2hw_intr_enable_q_i; Tests: T1 T2 T3 

Cond Coverage for Instance : tb.dut.u_intr_corr_err
TotalCoveredPercent
Conditions12975.00
Logical12975.00
Non-Logical00
Event00

 LINE       62
 EXPRESSION ((({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i) | event_intr_i)
             -----------------------------1----------------------------   ------2-----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T17,T25
10Not Covered

 LINE       62
 SUB-EXPRESSION (({Width {reg2hw_intr_test_qe_i}}) & reg2hw_intr_test_q_i)
                 ----------------1----------------   ----------2---------
-1--2-StatusTests
01CoveredT1,T2,T3
10Not Covered
11Not Covered

 LINE       67
 EXPRESSION (g_intr_event.new_event | reg2hw_intr_state_q_i)
             -----------1----------   ----------2----------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT26,T17,T25
10CoveredT26,T17,T25

 LINE       98
 EXPRESSION (status & reg2hw_intr_enable_q_i)
             ---1--   -----------2----------
-1--2-StatusTests
01CoveredT26,T27,T28
10CoveredT17,T25,T41
11CoveredT26,T42,T43

Branch Coverage for Instance : tb.dut.u_intr_corr_err
Line No.TotalCoveredPercent
Branches 2 2 100.00
IF 95 2 2 100.00


95 if (!rst_ni) begin -1- 96 intr_o <= '0; ==> 97 end else begin 98 intr_o <= status & reg2hw_intr_enable_q_i; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


Assert Coverage for Instance : tb.dut.u_intr_corr_err
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 1 1 100.00 1 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 1 1 100.00 1 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
IntrTKind_A 1056 1056 0 0


IntrTKind_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 1056 1056 0 0
T1 1 1 0 0
T2 1 1 0 0
T3 1 1 0 0
T7 1 1 0 0
T8 1 1 0 0
T14 1 1 0 0
T16 1 1 0 0
T18 1 1 0 0
T19 1 1 0 0
T20 1 1 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%