Module Definition
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Module Instance : tb.dut.u_flash_hw_if

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.96 100.00 93.75 92.11 98.94 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
96.34 99.02 94.44 95.83 92.11 96.62 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.85 97.12 94.40 98.44 100.00 84.29 dut


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
u_addr_cnt 100.00 100.00
u_addr_sync_reqack 96.46 95.83 100.00 90.00 100.00
u_bus_intg 100.00 100.00
u_data_intg_chk 100.00 100.00 100.00
u_data_sync_reqack 96.46 95.83 100.00 90.00 100.00
u_page_cnt 78.79 78.79
u_prim_flop_err_sts 100.00 100.00 100.00
u_rma_state_regs 100.00 100.00 100.00 100.00
u_seed_cnt 100.00 100.00
u_state_regs 100.00 100.00 100.00 100.00
u_sync_flash_init 100.00 100.00 100.00
u_sync_rma_req 100.00 100.00 100.00 100.00
u_wipe_idx_cnt 100.00 100.00
u_word_cnt 100.00 100.00


Since this is the module's only instance, the coverage report is the same as for the module.
Line Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
TOTAL242242100.00
CONT_ASSIGN14911100.00
ALWAYS15233100.00
CONT_ASSIGN17011100.00
CONT_ASSIGN17111100.00
ALWAYS17477100.00
CONT_ASSIGN18511100.00
ALWAYS22755100.00
CONT_ASSIGN24311100.00
CONT_ASSIGN24711100.00
ALWAYS25133100.00
CONT_ASSIGN26111100.00
CONT_ASSIGN26211100.00
ALWAYS26466100.00
CONT_ASSIGN27811100.00
CONT_ASSIGN27911100.00
CONT_ASSIGN28011100.00
ALWAYS35999100.00
CONT_ASSIGN38011100.00
ALWAYS3868585100.00
CONT_ASSIGN60711100.00
ALWAYS61333100.00
ALWAYS67377100.00
ALWAYS6881010100.00
ALWAYS70522100.00
CONT_ASSIGN71411100.00
CONT_ASSIGN71511100.00
CONT_ASSIGN73711100.00
CONT_ASSIGN74111100.00
CONT_ASSIGN74211100.00
CONT_ASSIGN75411100.00
ALWAYS7616666100.00
CONT_ASSIGN89111100.00
CONT_ASSIGN89211100.00
CONT_ASSIGN89311100.00
CONT_ASSIGN89400
CONT_ASSIGN89500
CONT_ASSIGN89611100.00
CONT_ASSIGN89711100.00
CONT_ASSIGN89811100.00
CONT_ASSIGN90011100.00
CONT_ASSIGN90211100.00
CONT_ASSIGN90511100.00
CONT_ASSIGN90611100.00
CONT_ASSIGN90811100.00
CONT_ASSIGN90911100.00
CONT_ASSIGN91111100.00
CONT_ASSIGN91411100.00
CONT_ASSIGN91811100.00
CONT_ASSIGN92111100.00
ALWAYS93200
CONT_ASSIGN93911100.00

Click here to see the source line report.

Cond Coverage for Module : flash_ctrl_lcmgr
TotalCoveredPercent
Conditions969093.75
Logical969093.75
Non-Logical00
Event00

 LINE       170
 EXPRESSION (phase == PhaseSeed)
            ----------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       171
 EXPRESSION (phase == PhaseRma)
            ---------1---------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT122,T76,T123

 LINE       185
 EXPRESSION (seed_err_q | seed_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT116,T193,T121
10Not Covered

 LINE       231
 EXPRESSION (addr_cnt_err_q | addr_cnt_err_d)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT44,T47,T48
10CoveredT44,T47,T48

 LINE       232
 EXPRESSION (seed_cnt_err_q | seed_cnt_err_d)
             -------1------   -------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT44,T47,T48
10CoveredT44,T47,T48

 LINE       247
 EXPRESSION (data_invalid_q | (rvalid_i & ((~data_intg_ok))))
             -------1------   ---------------2--------------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT130,T194,T195
10CoveredT130,T194,T195

 LINE       247
 SUB-EXPRESSION (rvalid_i & ((~data_intg_ok)))
                 ----1---   --------2--------
-1--2-StatusTests
01CoveredT130,T194,T195
10CoveredT1,T2,T3
11CoveredT130,T194,T195

 LINE       266
 EXPRESSION (seed_phase && validate_q && rvalid_i)
             -----1----    -----2----    ----3---
-1--2--3-StatusTests
011Not Covered
101CoveredT1,T2,T3
110CoveredT1,T2,T3
111CoveredT1,T2,T3

 LINE       270
 EXPRESSION (seed_phase && rvalid_i)
             -----1----    ----2---
-1--2-StatusTests
01CoveredT180,T85,T124
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       363
 EXPRESSION (addr_key_req_d && addr_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01CoveredT76,T77,T78
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       368
 EXPRESSION (data_key_req_d && data_key_ack_q)
             -------1------    -------2------
-1--2-StatusTests
01CoveredT75,T79,T80
10CoveredT1,T2,T3
11CoveredT1,T2,T3

 LINE       457
 EXPRESSION (provision_en_i ? StReadSeeds : StWait)
             -------1------
-1-StatusTests
0CoveredT121,T196,T197
1CoveredT1,T2,T3

 LINE       473
 EXPRESSION (seed_cnt_q == flash_ctrl_pkg::NumSeeds)
            --------------------1-------------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       516
 EXPRESSION ((rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0]) && rma_wipe_done)
             --------------------------1-------------------------    ------2------
-1--2-StatusTests
01CoveredT85,T124,T125
10CoveredT85,T124,T125
11CoveredT85,T124,T125

 LINE       516
 SUB-EXPRESSION (rma_wipe_idx == MaxWipeEntry[(WipeIdxWidth - 1):0])
                --------------------------1-------------------------
-1-StatusTests
0CoveredT11,T122,T76
1CoveredT85,T124,T125

 LINE       678
 EXPRESSION (page_err_q | page_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT44,T47,T48
10CoveredT44,T47,T48

 LINE       679
 EXPRESSION (word_err_q | word_err_d)
             -----1----   -----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT44,T47,T48
10CoveredT44,T47,T48

 LINE       680
 EXPRESSION (rma_idx_err_q | rma_idx_err_d)
             ------1------   ------2------
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT44,T47,T48
10CoveredT44,T47,T48

 LINE       693
 EXPRESSION (wvalid_o && wready_i)
             ----1---    ----2---
-1--2-StatusTests
01Not Covered
10CoveredT198,T199
11CoveredT122,T123,T180

 LINE       697
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT11,T180,T85
10Unreachable
11CoveredT180,T85,T124

 LINE       705
 EXPRESSION (prog_cnt_en && wvalid_o && wready_i)
             -----1-----    ----2---    ----3---
-1--2--3-StatusTests
011Not Covered
101Not Covered
110CoveredT198,T199
111CoveredT122,T123,T180

 LINE       835
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && wready_i)
             -----------------------1----------------------    ----2---
-1--2-StatusTests
01CoveredT122,T123,T180
10CoveredT198,T199
11CoveredT122,T123,T180

 LINE       835
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------
-1-StatusTests
0CoveredT11,T122,T123
1CoveredT122,T123,T180

 LINE       856
 EXPRESSION ((beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0]) && done_i)
             -----------------------1----------------------    ---2--
-1--2-StatusTests
01Not Covered
10CoveredT180,T85,T124
11CoveredT180,T85,T124

 LINE       856
 SUB-EXPRESSION (beat_cnt == MaxBeatCnt[(BeatCntWidth - 1):0])
                -----------------------1----------------------
-1-StatusTests
0CoveredT11,T12,T180
1CoveredT180,T85,T124

 LINE       862
 EXPRESSION (rvalid_i && rready_o)
             ----1---    ----2---
-1--2-StatusTests
01CoveredT11,T180,T85
10Unreachable
11CoveredT180,T85,T124

 LINE       863
 EXPRESSION (prog_data[beat_cnt] != rdata_i[(flash_ctrl_pkg::BusWidth - 1):0])
            ---------------------------------1--------------------------------
-1-StatusTests
0CoveredT11,T12,T180
1CoveredT85,T94,T88

 LINE       892
 EXPRESSION (seed_phase ? start : rma_start)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       893
 EXPRESSION (seed_phase ? op : rma_op)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       896
 EXPRESSION (seed_phase ? part_sel : rma_part_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       897
 EXPRESSION (seed_phase ? info_sel : rma_info_sel)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       898
 EXPRESSION (seed_phase ? num_words : rma_num_words)
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       900
 EXPRESSION (seed_phase ? ({addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}) : ({rma_addr, {flash_ctrl_pkg::BusByteWidth {1'b0}}}))
             -----1----
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT1,T2,T3

 LINE       906
 EXPRESSION (seed_phase | rma_phase)
             -----1----   ----2----
-1--2-StatusTests
00CoveredT1,T2,T3
01CoveredT122,T76,T123
10CoveredT1,T2,T3

 LINE       914
 EXPRESSION (page_err_q | word_err_q | fsm_err | state_err | rma_idx_err_q | addr_cnt_err_q | seed_cnt_err_q)
             -----1----   -----2----   ---3---   ----4----   ------5------   -------6------   -------7------
-1--2--3--4--5--6--7-StatusTests
0000000CoveredT1,T2,T3
0000001CoveredT44,T47,T48
0000010CoveredT44,T47,T48
0000100CoveredT44,T47,T48
0001000CoveredT85,T88,T200
0010000CoveredT44,T47,T48
0100000CoveredT44,T47,T48
1000000CoveredT44,T47,T48

FSM Coverage for Module : flash_ctrl_lcmgr
Summary for FSM :: state_q
TotalCoveredPercent
States 11 11 100.00 (Not included in score)
Transitions 25 23 92.00
Sequences 0 0

State, Transition and Sequence Details for FSM :: state_q
statesLine No.CoveredTests
StDisabled 545 Covered T8,T9,T10
StEntropyReseed 499 Covered T122,T123,T121
StIdle 432 Covered T1,T2,T3
StInvalid 520 Covered T85,T88,T200
StReadEval 478 Covered T1,T2,T3
StReadSeeds 457 Covered T1,T2,T3
StReqAddrKey 436 Covered T1,T2,T3
StReqDataKey 446 Covered T1,T2,T3
StRmaRsp 520 Covered T124,T125,T126
StRmaWipe 434 Covered T122,T76,T123
StWait 457 Covered T1,T2,T3


transitionsLine No.CoveredTests
StEntropyReseed->StDisabled 572 Covered T77,T197,T201
StEntropyReseed->StRmaWipe 507 Covered T122,T123,T121
StIdle->StDisabled 572 Covered T44,T47,T48
StIdle->StReqAddrKey 436 Covered T1,T2,T3
StIdle->StRmaWipe 434 Covered T122,T123,T180
StInvalid->StDisabled 572 Not Covered
StReadEval->StDisabled 572 Covered T202,T80,T203
StReadEval->StReadSeeds 485 Covered T1,T2,T3
StReadSeeds->StDisabled 572 Covered T130,T76,T194
StReadSeeds->StReadEval 478 Covered T1,T2,T3
StReadSeeds->StWait 475 Covered T1,T2,T3
StReqAddrKey->StDisabled 572 Covered T77,T79,T204
StReqAddrKey->StReqDataKey 446 Covered T1,T2,T3
StReqAddrKey->StRmaWipe 444 Covered T76,T78,T190
StReqDataKey->StDisabled 572 Covered T75,T79,T205
StReqDataKey->StReadSeeds 457 Covered T1,T2,T3
StReqDataKey->StRmaWipe 454 Covered T80,T191,T192
StReqDataKey->StWait 457 Covered T121,T196,T197
StRmaRsp->StDisabled 572 Covered T206,T207
StRmaRsp->StInvalid 534 Not Covered
StRmaWipe->StDisabled 572 Covered T122,T123,T121
StRmaWipe->StInvalid 520 Covered T85,T88,T200
StRmaWipe->StRmaRsp 520 Covered T124,T125,T126
StWait->StDisabled 572 Covered T8,T9,T10
StWait->StEntropyReseed 499 Covered T122,T123,T121


Summary for FSM :: rma_state_q
TotalCoveredPercent
States 10 10 100.00 (Not included in score)
Transitions 13 12 92.31
Sequences 0 0

State, Transition and Sequence Details for FSM :: rma_state_q
statesLine No.CoveredTests
StRmaDisabled 785 Covered T8,T9,T10
StRmaErase 796 Covered T122,T76,T123
StRmaEraseWait 809 Covered T122,T123,T121
StRmaIdle 800 Covered T1,T2,T3
StRmaInvalid 872 Covered T44,T47,T48
StRmaPageSel 787 Covered T122,T76,T123
StRmaProgram 822 Covered T122,T123,T180
StRmaProgramWait 836 Covered T122,T123,T180
StRmaRdVerify 847 Covered T180,T85,T124
StRmaWordSel 815 Covered T122,T123,T121


transitionsLine No.CoveredTests
StRmaErase->StRmaEraseWait 809 Covered T122,T123,T121
StRmaEraseWait->StRmaWordSel 815 Covered T122,T123,T121
StRmaIdle->StRmaDisabled 785 Covered T8,T9,T10
StRmaIdle->StRmaPageSel 787 Covered T122,T76,T123
StRmaPageSel->StRmaDisabled 794 Not Covered
StRmaPageSel->StRmaErase 796 Covered T122,T76,T123
StRmaPageSel->StRmaIdle 800 Covered T85,T124,T125
StRmaProgram->StRmaProgramWait 836 Covered T122,T123,T180
StRmaProgramWait->StRmaRdVerify 847 Covered T180,T85,T124
StRmaRdVerify->StRmaWordSel 859 Covered T180,T85,T124
StRmaWordSel->StRmaDisabled 820 Covered T121,T77,T196
StRmaWordSel->StRmaPageSel 826 Covered T85,T124,T125
StRmaWordSel->StRmaProgram 822 Covered T122,T123,T180



Branch Coverage for Module : flash_ctrl_lcmgr
Line No.TotalCoveredPercent
Branches 94 93 98.94
TERNARY 892 2 2 100.00
TERNARY 893 2 2 100.00
TERNARY 896 2 2 100.00
TERNARY 897 2 2 100.00
TERNARY 898 2 2 100.00
TERNARY 900 2 2 100.00
IF 152 2 2 100.00
IF 174 2 2 100.00
IF 227 2 2 100.00
IF 251 2 2 100.00
IF 264 4 4 100.00
IF 359 5 5 100.00
CASE 427 27 26 96.30
IF 569 2 2 100.00
IF 613 2 2 100.00
IF 673 2 2 100.00
IF 688 7 7 100.00
IF 705 2 2 100.00
CASE 777 23 23 100.00


892 assign ctrl_o.start.q = seed_phase ? start : rma_start; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


893 assign ctrl_o.op.q = seed_phase ? op : rma_op; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


896 assign ctrl_o.partition_sel.q = seed_phase ? part_sel : rma_part_sel; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


897 assign ctrl_o.info_sel.q = seed_phase ? info_sel : rma_info_sel; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


898 assign ctrl_o.num = seed_phase ? num_words : rma_num_words; -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


900 assign addr_o = seed_phase ? {addr, {BusByteWidth{1'b0}}} : -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


152 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, lcmgr_state_e, StIdle) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


174 if (!rst_ni) begin -1- 175 rma_ack_q <= lc_ctrl_pkg::Off; ==> 176 validate_q <= 1'b0; 177 seed_err_q <= '0; 178 end else begin 179 rma_ack_q <= rma_ack_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


227 if (!rst_ni) begin -1- 228 addr_cnt_err_q <= '0; ==> 229 seed_cnt_err_q <= '0; 230 end else begin 231 addr_cnt_err_q <= addr_cnt_err_q | addr_cnt_err_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


251 if (!rst_ni) begin -1- 252 data_invalid_q <= '0; ==> 253 end else begin 254 data_invalid_q <= data_invalid_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


264 if (!rst_ni) begin -1- 265 seeds_q <= RndCnstAllSeeds; ==> 266 end else if (seed_phase && validate_q && rvalid_i) begin -2- 267 // validate current value 268 seeds_q[seed_idx][rd_idx] <= seeds_q[seed_idx][rd_idx] & ==> 269 rdata_i[BusWidth-1:0]; 270 end else if (seed_phase && rvalid_i) begin -3- 271 seeds_q[seed_idx][rd_idx] <= rdata_i[BusWidth-1:0]; ==> 272 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 1 Covered T1,T2,T3
0 0 0 Covered T1,T2,T3


359 if (!rst_ni) begin -1- 360 addr_key_o <= RndCnstAddrKey; ==> 361 data_key_o <= RndCnstDataKey; 362 end else begin 363 if (addr_key_req_d && addr_key_ack_q) begin -2- 364 addr_key_o <= flash_key_t'(otp_key_rsp_i.key); ==> 365 rand_addr_key_o <= flash_key_t'(otp_key_rsp_i.rand_key); 366 end MISSING_ELSE ==> 367 368 if (data_key_req_d && data_key_ack_q) begin -3- 369 data_key_o <= flash_key_t'(otp_key_rsp_i.key); ==> 370 rand_data_key_o <= flash_key_t'(otp_key_rsp_i.rand_key); 371 end MISSING_ELSE ==>

Branches:
-1--2--3-StatusTests
1 - - Covered T1,T2,T3
0 1 - Covered T1,T2,T3
0 0 - Covered T1,T2,T3
0 - 1 Covered T1,T2,T3
0 - 0 Covered T1,T2,T3


427 unique case (state_q) -1- 428 429 // If rma request is seen, directly transition to wipe. 430 // Since init has not been called, there are no guarantees 431 // to entropy behavior, thus do not reseed 432 StIdle: begin 433 if (lc_tx_test_true_strict(rma_req[RmaReqInit])) begin -2- 434 state_d = StRmaWipe; ==> 435 end else if (init_q) begin -3- 436 state_d = StReqAddrKey; ==> 437 end MISSING_ELSE ==> 438 end 439 440 StReqAddrKey: begin 441 phase = PhaseSeed; 442 addr_key_req_d = 1'b1; 443 if (lc_tx_test_true_strict(rma_req[RmaReqKey])) begin -4- 444 state_d = StRmaWipe; ==> 445 end else if (addr_key_ack_q) begin -5- 446 state_d = StReqDataKey; ==> 447 end MISSING_ELSE ==> 448 end 449 450 StReqDataKey: begin 451 phase = PhaseSeed; 452 data_key_req_d = 1'b1; 453 if (lc_tx_test_true_strict(rma_req[RmaReqKey])) begin -6- 454 state_d = StRmaWipe; ==> 455 end else if (data_key_ack_q) begin -7- 456 // provision_en is only a "good" value after otp/lc initialization 457 state_d = provision_en_i ? StReadSeeds : StWait; -8- ==> ==> 458 end MISSING_ELSE ==> 459 end 460 461 // read seeds 462 StReadSeeds: begin 463 // seeds can be updated in this state 464 phase = PhaseSeed; 465 466 // kick off flash transaction 467 start = 1'b1; 468 addr = BusAddrW'(seed_page_addr); 469 info_sel = seed_info_sel; 470 471 // we have checked all seeds, proceed 472 addr_cnt_en = rvalid_i; 473 if (seed_cnt_q == NumSeeds) begin -9- 474 start = 1'b0; ==> 475 state_d = StWait; 476 end else if (done_i) begin -10- 477 seed_err_d = |err_i; ==> 478 state_d = StReadEval; 479 end MISSING_ELSE ==> 480 end // case: StReadSeeds 481 482 StReadEval: begin 483 phase = PhaseSeed; 484 addr_cnt_clr = 1'b1; 485 state_d = StReadSeeds; 486 487 if (validate_q) begin -11- 488 seed_cnt_en = 1'b1; ==> 489 validate_d = 1'b0; 490 end else begin 491 validate_d = 1'b1; ==> 492 end 493 end 494 495 // Waiting for an rma entry command 496 StWait: begin 497 rd_buf_en_o = 1'b1; 498 if (lc_tx_test_true_strict(rma_req[RmaReqWait])) begin -12- 499 state_d = StEntropyReseed; ==> 500 end MISSING_ELSE ==> 501 end 502 503 // Reseed entropy 504 StEntropyReseed: begin 505 edn_req_o = 1'b1; 506 if(edn_ack_i) begin -13- 507 state_d = StRmaWipe; ==> 508 end MISSING_ELSE ==> 509 end 510 511 StRmaWipe: begin 512 phase = PhaseRma; 513 lfsr_en_o = 1'b1; 514 rma_wipe_req = 1'b1; 515 516 if (rma_wipe_idx == MaxWipeEntry[WipeIdxWidth-1:0] && rma_wipe_done) begin -14- 517 // first check for error status 518 // If error status is set, go directly to invalid terminal state 519 // If error status is good, go to second check 520 state_d = lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q) ? StInvalid : StRmaRsp; ==> 521 end else if (rma_wipe_done) begin -15- 522 rma_wipe_idx_incr = 1; ==> 523 end MISSING_ELSE ==> 524 end 525 526 // response to rma request 527 // Second check for error status: 528 // If error status indicates error, jump to invalid terminal state 529 // Otherwise assign output to error status; 530 StRmaRsp: begin 531 phase = PhaseRma; 532 dis_access_o = lc_ctrl_pkg::On; 533 if (lc_ctrl_pkg::lc_tx_test_false_loose(err_sts_q)) begin -16- 534 state_d = StInvalid; ==> 535 end else begin 536 rma_ack_d = err_sts_q; ==> 537 end 538 end 539 540 // Disabled state is functionally equivalent to invalid, just without the 541 // the explicit error-ing 542 StDisabled: begin 543 dis_access_o = lc_ctrl_pkg::On; ==> 544 rma_ack_d = lc_ctrl_pkg::Off; 545 state_d = StDisabled; 546 end 547 548 StInvalid: begin 549 dis_access_o = lc_ctrl_pkg::On; ==> 550 state_err = 1'b1; 551 rma_ack_d = lc_ctrl_pkg::Off; 552 state_d = StInvalid; 553 end 554 555 // Invalid catch-all state 556 default: begin 557 dis_access_o = lc_ctrl_pkg::On; ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12--13--14--15--16-StatusTests
StIdle 1 - - - - - - - - - - - - - - Covered T122,T123,T180
StIdle 0 1 - - - - - - - - - - - - - Covered T1,T2,T3
StIdle 0 0 - - - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - - 1 - - - - - - - - - - - - Covered T76,T78,T190
StReqAddrKey - - 0 1 - - - - - - - - - - - Covered T1,T2,T3
StReqAddrKey - - 0 0 - - - - - - - - - - - Covered T1,T2,T3
StReqDataKey - - - - 1 - - - - - - - - - - Covered T80,T191,T192
StReqDataKey - - - - 0 1 1 - - - - - - - - Covered T1,T2,T3
StReqDataKey - - - - 0 1 0 - - - - - - - - Covered T121,T196,T197
StReqDataKey - - - - 0 0 - - - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 1 - - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 0 1 - - - - - - Covered T1,T2,T3
StReadSeeds - - - - - - - 0 0 - - - - - - Covered T1,T2,T3
StReadEval - - - - - - - - - 1 - - - - - Covered T1,T2,T3
StReadEval - - - - - - - - - 0 - - - - - Covered T1,T2,T3
StWait - - - - - - - - - - 1 - - - - Covered T122,T123,T121
StWait - - - - - - - - - - 0 - - - - Covered T1,T2,T3
StEntropyReseed - - - - - - - - - - - 1 - - - Covered T11,T122,T123
StEntropyReseed - - - - - - - - - - - 0 - - - Not Covered
StRmaWipe - - - - - - - - - - - - 1 - - Covered T11,T12,T85
StRmaWipe - - - - - - - - - - - - 0 1 - Covered T11,T12,T85
StRmaWipe - - - - - - - - - - - - 0 0 - Covered T11,T122,T76
StRmaRsp - - - - - - - - - - - - - - 1 Covered T11,T12,T13
StRmaRsp - - - - - - - - - - - - - - 0 Covered T11,T12,T124
StDisabled - - - - - - - - - - - - - - - Covered T8,T9,T10
StInvalid - - - - - - - - - - - - - - - Covered T11,T12,T85
default - - - - - - - - - - - - - - - Covered T11,T12,T13


569 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i) && -1- 570 state_d != StInvalid && 571 !rma_done) begin 572 state_d = StDisabled; ==> 573 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T8,T9,T10
0 Covered T1,T2,T3


613 `PRIM_FLOP_SPARSE_FSM(u_rma_state_regs, rma_state_d, rma_state_q, rma_state_e, StRmaIdle) -1- ==> ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


673 if (!rst_ni) begin -1- 674 page_err_q <= '0; ==> 675 word_err_q <= '0; 676 rma_idx_err_q <= '0; 677 end else begin 678 page_err_q <= page_err_q | page_err_d; ==>

Branches:
-1-StatusTests
1 Covered T1,T2,T3
0 Covered T1,T2,T3


688 if (!rst_ni) begin -1- 689 beat_cnt <= '0; ==> 690 end else if (beat_cnt_clr) begin -2- 691 beat_cnt <= '0; ==> 692 end else if (prog_cnt_en) begin -3- 693 if (wvalid_o && wready_i) begin -4- 694 beat_cnt <= beat_cnt + 1'b1; ==> 695 end MISSING_ELSE ==> 696 end else if (rd_cnt_en) begin -5- 697 if (rvalid_i && rready_o) begin -6- 698 beat_cnt <= beat_cnt + 1'b1; ==> 699 end MISSING_ELSE ==> 700 end MISSING_ELSE ==>

Branches:
-1--2--3--4--5--6-StatusTests
1 - - - - - Covered T1,T2,T3
0 1 - - - - Covered T11,T12,T180
0 0 1 1 - - Covered T11,T122,T123
0 0 1 0 - - Covered T11,T12,T13
0 0 0 - 1 1 Covered T11,T12,T180
0 0 0 - 1 0 Covered T11,T12,T180
0 0 0 - 0 - Covered T1,T2,T3


705 if (prog_cnt_en && wvalid_o && wready_i) begin -1- 706 prog_data[beat_cnt] <= rand_i; ==> 707 end MISSING_ELSE ==>

Branches:
-1-StatusTests
1 Covered T11,T122,T123
0 Covered T1,T2,T3


777 unique case (rma_state_q) -1- 778 // Transition to invalid state via disable only when any ongoing stateful 779 // operations are complete. This ensures we do not electrically disturb 780 // any ongoing operation. 781 // This of course cannot be guaranteed if the FSM state is directly disturbed, 782 // and that is considered an extremely invasive attack. 783 StRmaIdle: begin 784 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin -2- 785 rma_state_d = StRmaDisabled; ==> 786 end else if (rma_wipe_req_int) begin -3- 787 rma_state_d = StRmaPageSel; ==> 788 page_cnt_ld = 1'b1; 789 end MISSING_ELSE ==> 790 end 791 792 StRmaPageSel: begin 793 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin -4- 794 rma_state_d = StRmaDisabled; ==> 795 end else if (page_cnt < end_page) begin -5- 796 rma_state_d = StRmaErase; ==> 797 end else begin 798 rma_wipe_done = 1'b1; ==> 799 page_cnt_clr = 1'b1; 800 rma_state_d = StRmaIdle; 801 end 802 end 803 804 StRmaErase: begin 805 rma_start = 1'b1; 806 rma_op = FlashOpErase; 807 if (done_i) begin -6- 808 err_sts_set = |err_i; ==> 809 rma_state_d = StRmaEraseWait; 810 end MISSING_ELSE ==> 811 end 812 813 StRmaEraseWait: begin 814 word_cnt_ld = 1'b1; ==> 815 rma_state_d = StRmaWordSel; 816 end 817 818 StRmaWordSel: begin 819 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin -7- 820 rma_state_d = StRmaDisabled; ==> 821 end else if (word_cnt < BusWordsPerPage) begin -8- 822 rma_state_d = StRmaProgram; ==> 823 end else begin 824 word_cnt_clr = 1'b1; ==> 825 page_cnt_incr = 1'b1; 826 rma_state_d = StRmaPageSel; 827 end 828 end 829 830 StRmaProgram: begin 831 rma_start = 1'b1; 832 rma_op = FlashOpProgram; 833 prog_cnt_en = 1'b1; 834 835 if ((beat_cnt == MaxBeatCnt[BeatCntWidth-1:0]) && wready_i) begin -9- 836 rma_state_d = StRmaProgramWait; ==> 837 end MISSING_ELSE ==> 838 end 839 840 StRmaProgramWait: begin 841 rma_start = 1'b1; 842 rma_op = FlashOpProgram; 843 844 if (done_i) begin -10- 845 beat_cnt_clr = 1'b1; ==> 846 err_sts_set = |err_i; 847 rma_state_d = StRmaRdVerify; 848 end MISSING_ELSE ==> 849 end 850 851 StRmaRdVerify: begin 852 rma_start = 1'b1; 853 rma_op = FlashOpRead; 854 rd_cnt_en = 1'b1; 855 856 if ((beat_cnt == MaxBeatCnt[BeatCntWidth-1:0]) && done_i) begin -11- 857 beat_cnt_clr = 1'b1; ==> 858 word_cnt_incr = 1'b1; 859 rma_state_d = StRmaWordSel; 860 end MISSING_ELSE ==> 861 862 if (rvalid_i && rready_o) begin -12- 863 err_sts_set = prog_data[beat_cnt] != rdata_i[BusWidth-1:0]; ==> 864 end MISSING_ELSE ==> 865 end 866 867 StRmaDisabled: begin 868 rma_state_d = StRmaDisabled; ==> 869 end 870 871 StRmaInvalid: begin 872 rma_state_d = StRmaInvalid; ==> 873 err_sts_set = 1'b1; 874 fsm_err = 1'b1; 875 end 876 877 default: begin 878 rma_state_d = StRmaInvalid; ==>

Branches:
-1--2--3--4--5--6--7--8--9--10--11--12-StatusTests
StRmaIdle 1 - - - - - - - - - - Covered T8,T9,T10
StRmaIdle 0 1 - - - - - - - - - Covered T11,T122,T76
StRmaIdle 0 0 - - - - - - - - - Covered T1,T2,T3
StRmaPageSel - - 1 - - - - - - - - Covered T11,T12,T13
StRmaPageSel - - 0 1 - - - - - - - Covered T11,T122,T76
StRmaPageSel - - 0 0 - - - - - - - Covered T11,T12,T85
StRmaErase - - - - 1 - - - - - - Covered T11,T122,T123
StRmaErase - - - - 0 - - - - - - Covered T11,T122,T76
StRmaEraseWait - - - - - - - - - - - Covered T11,T122,T123
StRmaWordSel - - - - - 1 - - - - - Covered T11,T121,T12
StRmaWordSel - - - - - 0 1 - - - - Covered T11,T122,T123
StRmaWordSel - - - - - 0 0 - - - - Covered T11,T12,T85
StRmaProgram - - - - - - - 1 - - - Covered T11,T122,T123
StRmaProgram - - - - - - - 0 - - - Covered T11,T122,T123
StRmaProgramWait - - - - - - - - 1 - - Covered T11,T12,T180
StRmaProgramWait - - - - - - - - 0 - - Covered T11,T122,T123
StRmaRdVerify - - - - - - - - - 1 - Covered T11,T12,T180
StRmaRdVerify - - - - - - - - - 0 - Covered T11,T12,T180
StRmaRdVerify - - - - - - - - - - 1 Covered T11,T12,T180
StRmaRdVerify - - - - - - - - - - 0 Covered T11,T12,T180
StRmaDisabled - - - - - - - - - - - Covered T8,T9,T10
StRmaInvalid - - - - - - - - - - - Covered T11,T12,T13
default - - - - - - - - - - - Covered T11,T12,T13


Assert Coverage for Module : flash_ctrl_lcmgr
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
DisableChk_A 375903717 4772832 0 48
ProgRdVerify_A 374734461 2043538 0 0
u_rma_state_regs_A 387955939 387167302 0 0
u_state_regs_A 387955939 387167302 0 0


DisableChk_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 375903717 4772832 0 48
T4 1505 0 0 0
T8 758 225 0 1
T9 4649 555 0 0
T10 0 474 0 1
T15 82187 0 0 0
T21 0 555 0 0
T22 210407 0 0 0
T23 0 366 0 1
T26 2605 0 0 0
T27 5600 0 0 0
T28 2201 0 0 0
T30 209846 0 0 0
T51 0 0 0 1
T59 70189 0 0 0
T75 0 10 0 0
T76 0 10 0 0
T84 0 500 0 1
T87 0 0 0 1
T113 0 0 0 1
T122 0 489976 0 0
T130 0 3 0 0
T187 0 0 0 1
T188 0 0 0 1
T208 0 0 0 1

ProgRdVerify_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 374734461 2043538 0 0
T77 4240 0 0 0
T100 61545 0 0 0
T124 0 65920 0 0
T125 0 65920 0 0
T126 0 65920 0 0
T127 0 131840 0 0
T128 0 131840 0 0
T129 0 131840 0 0
T180 100116 4 0 0
T185 82727 0 0 0
T209 0 65920 0 0
T210 0 65920 0 0
T211 0 65920 0 0
T212 1570 0 0 0
T213 126766 0 0 0
T214 68280 0 0 0
T215 47535 0 0 0
T216 51891 0 0 0
T217 1512 0 0 0

u_rma_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 387167302 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

u_state_regs_A
NameAttemptsReal SuccessesFailuresIncomplete
Total 387955939 387167302 0 0
T1 2386 2315 0 0
T2 1619 1564 0 0
T3 2624 2529 0 0
T7 3618 3564 0 0
T8 758 694 0 0
T14 57474 57387 0 0
T16 2778 2678 0 0
T18 1453 1380 0 0
T19 1592 1428 0 0
T20 1905 1841 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%