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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.27 95.73 93.97 98.31 92.52 98.27 96.89 98.21


Total test records in report: 1273
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T488 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3701338390 Sep 04 09:05:41 AM UTC 24 Sep 04 09:09:19 AM UTC 24 1873321500 ps
T285 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.3677061408 Sep 04 08:49:39 AM UTC 24 Sep 04 09:09:21 AM UTC 24 816045700 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.973518665 Sep 04 09:06:10 AM UTC 24 Sep 04 09:09:23 AM UTC 24 1581572800 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.3611401942 Sep 04 09:00:41 AM UTC 24 Sep 04 09:09:26 AM UTC 24 4032473100 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.589770365 Sep 04 09:08:45 AM UTC 24 Sep 04 09:09:28 AM UTC 24 2361215300 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.4244724228 Sep 04 09:08:28 AM UTC 24 Sep 04 09:09:33 AM UTC 24 22527700 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.3045607724 Sep 04 09:06:17 AM UTC 24 Sep 04 09:09:48 AM UTC 24 34729433600 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.387115249 Sep 04 09:06:15 AM UTC 24 Sep 04 09:09:48 AM UTC 24 8081733900 ps
T132 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.1226502269 Sep 04 09:03:06 AM UTC 24 Sep 04 09:09:50 AM UTC 24 6041588900 ps
T286 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.500793593 Sep 04 08:50:45 AM UTC 24 Sep 04 09:09:56 AM UTC 24 400073600 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.2042928991 Sep 04 09:03:02 AM UTC 24 Sep 04 09:10:17 AM UTC 24 250551600 ps
T133 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.1036767878 Sep 04 09:08:57 AM UTC 24 Sep 04 09:10:32 AM UTC 24 1698338200 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.174883974 Sep 04 08:49:40 AM UTC 24 Sep 04 09:10:34 AM UTC 24 755383900 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.2890063022 Sep 04 09:06:27 AM UTC 24 Sep 04 09:10:37 AM UTC 24 2360075000 ps
T274 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.2433852692 Sep 04 09:08:20 AM UTC 24 Sep 04 09:10:44 AM UTC 24 10020062600 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.1970627334 Sep 04 09:10:45 AM UTC 24 Sep 04 09:11:23 AM UTC 24 9848000 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.4154322360 Sep 04 09:09:49 AM UTC 24 Sep 04 09:11:24 AM UTC 24 6252162100 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.2778091450 Sep 04 09:10:37 AM UTC 24 Sep 04 09:11:26 AM UTC 24 432556500 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.2516222285 Sep 04 09:10:33 AM UTC 24 Sep 04 09:11:26 AM UTC 24 33978800 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.136511445 Sep 04 09:10:35 AM UTC 24 Sep 04 09:11:30 AM UTC 24 30089200 ps
T122 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.830720143 Sep 04 08:57:41 AM UTC 24 Sep 04 09:11:34 AM UTC 24 187355466000 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.2716221758 Sep 04 09:09:28 AM UTC 24 Sep 04 09:11:35 AM UTC 24 2348908900 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1793895662 Sep 04 09:09:20 AM UTC 24 Sep 04 09:11:42 AM UTC 24 5846008800 ps
T305 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.3054342305 Sep 04 09:09:24 AM UTC 24 Sep 04 09:11:50 AM UTC 24 533783300 ps
T83 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1275742421 Sep 04 09:08:41 AM UTC 24 Sep 04 09:11:50 AM UTC 24 77614400 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.1768967449 Sep 04 09:11:26 AM UTC 24 Sep 04 09:11:54 AM UTC 24 58334400 ps
T278 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.3190488456 Sep 04 09:11:27 AM UTC 24 Sep 04 09:11:55 AM UTC 24 15222800 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.3650438224 Sep 04 09:11:27 AM UTC 24 Sep 04 09:11:56 AM UTC 24 17731200 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.3653592418 Sep 04 09:06:08 AM UTC 24 Sep 04 09:11:56 AM UTC 24 2857482600 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.4058467154 Sep 04 09:11:34 AM UTC 24 Sep 04 09:12:04 AM UTC 24 63152200 ps
T303 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.2428284719 Sep 04 09:08:39 AM UTC 24 Sep 04 09:12:15 AM UTC 24 4180001200 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.2715101065 Sep 04 09:04:22 AM UTC 24 Sep 04 09:12:29 AM UTC 24 15461712100 ps
T53 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.3946472321 Sep 04 09:11:57 AM UTC 24 Sep 04 09:12:39 AM UTC 24 135928000 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.1448270590 Sep 04 09:09:04 AM UTC 24 Sep 04 09:12:44 AM UTC 24 4936533600 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.3502634820 Sep 04 09:09:49 AM UTC 24 Sep 04 09:12:54 AM UTC 24 3725968700 ps
T287 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.66036976 Sep 04 08:54:10 AM UTC 24 Sep 04 09:12:57 AM UTC 24 2630306900 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.4179753980 Sep 04 09:11:25 AM UTC 24 Sep 04 09:13:00 AM UTC 24 1054088900 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.189495010 Sep 04 09:09:34 AM UTC 24 Sep 04 09:13:02 AM UTC 24 1376533200 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.365515812 Sep 04 09:09:27 AM UTC 24 Sep 04 09:13:06 AM UTC 24 3060133400 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.1685977684 Sep 04 09:09:51 AM UTC 24 Sep 04 09:13:08 AM UTC 24 22203666400 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.683418680 Sep 04 09:09:57 AM UTC 24 Sep 04 09:13:13 AM UTC 24 20665388400 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.3868402260 Sep 04 09:12:30 AM UTC 24 Sep 04 09:13:40 AM UTC 24 6446496600 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.3744204015 Sep 04 09:10:18 AM UTC 24 Sep 04 09:14:03 AM UTC 24 24278081500 ps
T203 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2100134060 Sep 04 09:11:31 AM UTC 24 Sep 04 09:14:05 AM UTC 24 10012575600 ps
T315 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.1908158584 Sep 04 09:14:07 AM UTC 24 Sep 04 09:14:25 AM UTC 24 91091300 ps
T513 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.1635212945 Sep 04 09:11:36 AM UTC 24 Sep 04 09:14:59 AM UTC 24 138956100 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.843233032 Sep 04 09:13:14 AM UTC 24 Sep 04 09:15:07 AM UTC 24 17272366400 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.2409698452 Sep 04 09:14:26 AM UTC 24 Sep 04 09:15:11 AM UTC 24 41848800 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.76736196 Sep 04 09:12:45 AM UTC 24 Sep 04 09:15:12 AM UTC 24 7100994400 ps
T306 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.300896331 Sep 04 09:11:51 AM UTC 24 Sep 04 09:15:28 AM UTC 24 13415679600 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3070496289 Sep 04 09:11:56 AM UTC 24 Sep 04 09:15:38 AM UTC 24 137058700 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3459853891 Sep 04 09:13:03 AM UTC 24 Sep 04 09:15:38 AM UTC 24 2620364400 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.58041911 Sep 04 09:12:58 AM UTC 24 Sep 04 09:15:49 AM UTC 24 781808200 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.702719896 Sep 04 09:15:11 AM UTC 24 Sep 04 09:15:50 AM UTC 24 73083200 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.1013432190 Sep 04 09:15:00 AM UTC 24 Sep 04 09:15:52 AM UTC 24 41834900 ps
T518 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.1896259876 Sep 04 09:15:29 AM UTC 24 Sep 04 09:15:57 AM UTC 24 48472900 ps
T519 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2311831625 Sep 04 09:15:08 AM UTC 24 Sep 04 09:16:02 AM UTC 24 234213100 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.4044333427 Sep 04 09:15:38 AM UTC 24 Sep 04 09:16:03 AM UTC 24 15856900 ps
T272 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.2039123261 Sep 04 09:15:39 AM UTC 24 Sep 04 09:16:08 AM UTC 24 14997700 ps
T521 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.2951376362 Sep 04 09:15:52 AM UTC 24 Sep 04 09:16:22 AM UTC 24 52892200 ps
T134 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1579099434 Sep 04 09:08:44 AM UTC 24 Sep 04 09:16:26 AM UTC 24 4749750900 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.886767678 Sep 04 09:15:13 AM UTC 24 Sep 04 09:16:34 AM UTC 24 2197901600 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.662033237 Sep 04 09:09:22 AM UTC 24 Sep 04 09:16:36 AM UTC 24 4044449700 ps
T523 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.630253317 Sep 04 09:13:07 AM UTC 24 Sep 04 09:16:48 AM UTC 24 1354196400 ps
T275 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.176694513 Sep 04 09:15:50 AM UTC 24 Sep 04 09:16:51 AM UTC 24 10034001300 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1538904707 Sep 04 09:13:01 AM UTC 24 Sep 04 09:16:52 AM UTC 24 6111378500 ps
T525 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.2055546553 Sep 04 09:12:40 AM UTC 24 Sep 04 09:16:58 AM UTC 24 5004705700 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.1822060893 Sep 04 09:16:35 AM UTC 24 Sep 04 09:17:04 AM UTC 24 1424128100 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.298821472 Sep 04 09:13:09 AM UTC 24 Sep 04 09:17:12 AM UTC 24 8527435200 ps
T204 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.1203333578 Sep 04 09:03:10 AM UTC 24 Sep 04 09:17:15 AM UTC 24 80142860500 ps
T313 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.4286906863 Sep 04 09:16:02 AM UTC 24 Sep 04 09:17:47 AM UTC 24 54182600 ps
T135 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.923105348 Sep 04 09:11:57 AM UTC 24 Sep 04 09:17:47 AM UTC 24 37780534500 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.380188245 Sep 04 09:16:52 AM UTC 24 Sep 04 09:18:16 AM UTC 24 2682729800 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.3590623143 Sep 04 09:16:27 AM UTC 24 Sep 04 09:18:32 AM UTC 24 8007976500 ps
T529 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.1070248118 Sep 04 09:11:50 AM UTC 24 Sep 04 09:18:41 AM UTC 24 5433156300 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.3489782153 Sep 04 09:16:58 AM UTC 24 Sep 04 09:19:03 AM UTC 24 1128234400 ps
T168 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.3026535664 Sep 04 09:15:58 AM UTC 24 Sep 04 09:19:11 AM UTC 24 52672500 ps
T205 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.948152359 Sep 04 08:58:20 AM UTC 24 Sep 04 09:19:32 AM UTC 24 350238601300 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.3184902144 Sep 04 09:13:41 AM UTC 24 Sep 04 09:19:40 AM UTC 24 12366113600 ps
T180 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.2127993603 Sep 04 09:19:12 AM UTC 24 Sep 04 09:19:40 AM UTC 24 24107300 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.428339594 Sep 04 09:17:13 AM UTC 24 Sep 04 09:19:46 AM UTC 24 6149373400 ps
T309 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.55411257 Sep 04 09:16:04 AM UTC 24 Sep 04 09:19:49 AM UTC 24 9831849000 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.582558732 Sep 04 09:15:53 AM UTC 24 Sep 04 09:20:02 AM UTC 24 44998700 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.4044386059 Sep 04 09:18:33 AM UTC 24 Sep 04 09:20:08 AM UTC 24 4518257200 ps
T84 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.2611873916 Sep 04 09:16:22 AM UTC 24 Sep 04 09:20:21 AM UTC 24 37536500 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.740083737 Sep 04 09:17:47 AM UTC 24 Sep 04 09:20:25 AM UTC 24 692710800 ps
T201 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.839693531 Sep 04 09:19:47 AM UTC 24 Sep 04 09:20:26 AM UTC 24 13348600 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.1419703187 Sep 04 09:16:53 AM UTC 24 Sep 04 09:20:29 AM UTC 24 10042138300 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.1163124331 Sep 04 09:20:09 AM UTC 24 Sep 04 09:20:33 AM UTC 24 28890500 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.102653416 Sep 04 09:08:35 AM UTC 24 Sep 04 09:20:34 AM UTC 24 1425469200 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.2145443836 Sep 04 09:20:03 AM UTC 24 Sep 04 09:20:36 AM UTC 24 43900900 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.3631292019 Sep 04 09:19:33 AM UTC 24 Sep 04 09:20:36 AM UTC 24 235578200 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.1012030881 Sep 04 09:20:22 AM UTC 24 Sep 04 09:20:39 AM UTC 24 15651500 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.578012575 Sep 04 09:19:41 AM UTC 24 Sep 04 09:20:41 AM UTC 24 28444300 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.1997517345 Sep 04 09:19:41 AM UTC 24 Sep 04 09:20:43 AM UTC 24 112205100 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.2355245033 Sep 04 09:20:26 AM UTC 24 Sep 04 09:20:49 AM UTC 24 131542000 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.1310933933 Sep 04 09:18:18 AM UTC 24 Sep 04 09:20:55 AM UTC 24 547973900 ps
T124 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.300567144 Sep 04 08:50:26 AM UTC 24 Sep 04 09:21:06 AM UTC 24 731840123900 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.945989384 Sep 04 09:19:50 AM UTC 24 Sep 04 09:21:07 AM UTC 24 2026650000 ps
T212 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.201647409 Sep 04 09:17:49 AM UTC 24 Sep 04 09:21:08 AM UTC 24 4108322600 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.3527879257 Sep 04 09:12:55 AM UTC 24 Sep 04 09:21:22 AM UTC 24 3766309200 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3679085804 Sep 04 09:20:45 AM UTC 24 Sep 04 09:21:26 AM UTC 24 1201142300 ps
T206 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.189125503 Sep 04 09:08:40 AM UTC 24 Sep 04 09:21:40 AM UTC 24 80139966000 ps
T314 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1175082497 Sep 04 09:20:36 AM UTC 24 Sep 04 09:21:43 AM UTC 24 5113941800 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.510032400 Sep 04 09:17:16 AM UTC 24 Sep 04 09:21:56 AM UTC 24 2073732100 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.2577002753 Sep 04 09:18:43 AM UTC 24 Sep 04 09:22:15 AM UTC 24 11473381000 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2817160793 Sep 04 09:20:42 AM UTC 24 Sep 04 09:22:21 AM UTC 24 3135772700 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.4179615585 Sep 04 09:21:07 AM UTC 24 Sep 04 09:22:45 AM UTC 24 2014689100 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.1836120847 Sep 04 09:07:30 AM UTC 24 Sep 04 09:23:02 AM UTC 24 1712399900 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.885135225 Sep 04 09:19:04 AM UTC 24 Sep 04 09:23:02 AM UTC 24 76666876600 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.957223001 Sep 04 09:21:08 AM UTC 24 Sep 04 09:23:06 AM UTC 24 774329800 ps
T213 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.3135480968 Sep 04 09:21:26 AM UTC 24 Sep 04 09:23:16 AM UTC 24 581917300 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.2794311943 Sep 04 08:58:53 AM UTC 24 Sep 04 09:23:16 AM UTC 24 366294200 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.2492624869 Sep 04 09:20:40 AM UTC 24 Sep 04 09:23:19 AM UTC 24 73663100 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.578532727 Sep 04 09:23:03 AM UTC 24 Sep 04 09:23:34 AM UTC 24 32805400 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.1857716861 Sep 04 09:26:54 AM UTC 24 Sep 04 09:27:17 AM UTC 24 26594100 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.3185549451 Sep 04 09:21:44 AM UTC 24 Sep 04 09:23:37 AM UTC 24 1224731000 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.1305223104 Sep 04 09:23:03 AM UTC 24 Sep 04 09:23:40 AM UTC 24 76121400 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.215394209 Sep 04 09:20:29 AM UTC 24 Sep 04 09:23:45 AM UTC 24 120114800 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.1035040414 Sep 04 09:23:06 AM UTC 24 Sep 04 09:23:47 AM UTC 24 29065300 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.3060951194 Sep 04 09:20:26 AM UTC 24 Sep 04 09:23:50 AM UTC 24 10012908300 ps
T181 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.3610985689 Sep 04 09:23:17 AM UTC 24 Sep 04 09:23:54 AM UTC 24 14226900 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3643174919 Sep 04 09:22:23 AM UTC 24 Sep 04 09:23:55 AM UTC 24 3726025700 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.3143166373 Sep 04 09:23:38 AM UTC 24 Sep 04 09:24:00 AM UTC 24 48489900 ps
T125 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.2950897779 Sep 04 08:50:33 AM UTC 24 Sep 04 09:24:00 AM UTC 24 439062423100 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.2490089656 Sep 04 09:23:41 AM UTC 24 Sep 04 09:24:06 AM UTC 24 43778500 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.1646986345 Sep 04 09:23:16 AM UTC 24 Sep 04 09:24:06 AM UTC 24 875206600 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.882577283 Sep 04 09:23:35 AM UTC 24 Sep 04 09:24:07 AM UTC 24 172093700 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.3602438016 Sep 04 09:23:48 AM UTC 24 Sep 04 09:24:13 AM UTC 24 49377200 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1284668773 Sep 04 09:21:08 AM UTC 24 Sep 04 09:24:41 AM UTC 24 4612234200 ps
T54 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.3664388183 Sep 04 09:24:08 AM UTC 24 Sep 04 09:24:45 AM UTC 24 487405100 ps
T126 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.1522988587 Sep 04 08:49:29 AM UTC 24 Sep 04 09:24:50 AM UTC 24 83855686300 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.3685677079 Sep 04 09:21:41 AM UTC 24 Sep 04 09:24:54 AM UTC 24 5133820500 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.831047092 Sep 04 09:23:20 AM UTC 24 Sep 04 09:24:56 AM UTC 24 1512539300 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.4032085984 Sep 04 09:24:00 AM UTC 24 Sep 04 09:25:12 AM UTC 24 2342068500 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.361223663 Sep 04 09:21:57 AM UTC 24 Sep 04 09:25:31 AM UTC 24 2585404700 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.1013323046 Sep 04 09:03:43 AM UTC 24 Sep 04 09:25:34 AM UTC 24 1529006000 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.4247208398 Sep 04 09:17:05 AM UTC 24 Sep 04 09:25:36 AM UTC 24 3637744800 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2887911494 Sep 04 09:23:46 AM UTC 24 Sep 04 09:25:49 AM UTC 24 10012239500 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2900296392 Sep 04 09:08:45 AM UTC 24 Sep 04 09:25:53 AM UTC 24 3764256000 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.981308167 Sep 04 09:22:46 AM UTC 24 Sep 04 09:25:58 AM UTC 24 21411678100 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.4094543045 Sep 04 09:14:03 AM UTC 24 Sep 04 09:26:12 AM UTC 24 217767460600 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1645631456 Sep 04 09:22:16 AM UTC 24 Sep 04 09:26:23 AM UTC 24 2860274200 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3786132412 Sep 04 09:24:50 AM UTC 24 Sep 04 09:26:38 AM UTC 24 814933800 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.1536700947 Sep 04 09:26:13 AM UTC 24 Sep 04 09:26:38 AM UTC 24 20579300 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.547686267 Sep 04 09:23:51 AM UTC 24 Sep 04 09:26:40 AM UTC 24 120948500 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2932982806 Sep 04 09:24:46 AM UTC 24 Sep 04 09:26:44 AM UTC 24 4030253000 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3423187570 Sep 04 09:24:56 AM UTC 24 Sep 04 09:26:49 AM UTC 24 727214700 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.1173264741 Sep 04 09:22:29 AM UTC 24 Sep 04 09:26:52 AM UTC 24 24661845400 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.2940791057 Sep 04 09:24:08 AM UTC 24 Sep 04 09:26:52 AM UTC 24 1571918100 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2135490089 Sep 04 09:26:24 AM UTC 24 Sep 04 09:27:06 AM UTC 24 306289700 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.3184103599 Sep 04 09:25:50 AM UTC 24 Sep 04 09:27:10 AM UTC 24 4058223900 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.1443208457 Sep 04 09:11:55 AM UTC 24 Sep 04 09:27:11 AM UTC 24 40128857500 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.4238492351 Sep 04 09:26:54 AM UTC 24 Sep 04 09:27:15 AM UTC 24 15541500 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.2414666560 Sep 04 09:26:50 AM UTC 24 Sep 04 09:27:18 AM UTC 24 25498300 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.2273671635 Sep 04 09:26:41 AM UTC 24 Sep 04 09:27:22 AM UTC 24 18919700 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.1257115800 Sep 04 09:26:39 AM UTC 24 Sep 04 09:27:27 AM UTC 24 60312800 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.1563618005 Sep 04 09:27:11 AM UTC 24 Sep 04 09:27:37 AM UTC 24 113604100 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.672989782 Sep 04 09:26:39 AM UTC 24 Sep 04 09:27:44 AM UTC 24 295282700 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3304572447 Sep 04 09:24:06 AM UTC 24 Sep 04 09:27:47 AM UTC 24 35456200 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.3227740346 Sep 04 09:26:45 AM UTC 24 Sep 04 09:28:00 AM UTC 24 21621388400 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.2768543660 Sep 04 09:27:12 AM UTC 24 Sep 04 09:28:11 AM UTC 24 26241800 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.4075788765 Sep 04 09:25:32 AM UTC 24 Sep 04 09:28:14 AM UTC 24 2720061900 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.3803190877 Sep 04 08:49:29 AM UTC 24 Sep 04 09:28:16 AM UTC 24 809461612800 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.3545380586 Sep 04 09:24:46 AM UTC 24 Sep 04 09:28:27 AM UTC 24 7874728800 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.2491743090 Sep 04 08:50:37 AM UTC 24 Sep 04 09:28:40 AM UTC 24 162154832500 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1325434898 Sep 04 09:28:16 AM UTC 24 Sep 04 09:28:42 AM UTC 24 58231800 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.3267834389 Sep 04 09:25:14 AM UTC 24 Sep 04 09:28:50 AM UTC 24 21837308600 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.388277036 Sep 04 09:12:05 AM UTC 24 Sep 04 09:29:03 AM UTC 24 684664800 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1140595242 Sep 04 09:27:38 AM UTC 24 Sep 04 09:29:13 AM UTC 24 1642438200 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.699117571 Sep 04 09:28:50 AM UTC 24 Sep 04 09:29:23 AM UTC 24 21004200 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.3521341221 Sep 04 09:27:19 AM UTC 24 Sep 04 09:29:25 AM UTC 24 11620877400 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.2453609 Sep 04 09:28:28 AM UTC 24 Sep 04 09:29:30 AM UTC 24 41008300 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.2050739648 Sep 04 08:53:52 AM UTC 24 Sep 04 09:29:32 AM UTC 24 95819567500 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.1521595976 Sep 04 09:28:49 AM UTC 24 Sep 04 09:29:39 AM UTC 24 46540800 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.1150101396 Sep 04 09:29:14 AM UTC 24 Sep 04 09:29:40 AM UTC 24 52228900 ps
T281 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.777599515 Sep 04 09:29:24 AM UTC 24 Sep 04 09:29:55 AM UTC 24 58682900 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.2137206641 Sep 04 09:28:50 AM UTC 24 Sep 04 09:29:55 AM UTC 24 233258500 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.223676959 Sep 04 09:29:26 AM UTC 24 Sep 04 09:29:55 AM UTC 24 27629400 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.2078216040 Sep 04 09:29:33 AM UTC 24 Sep 04 09:30:01 AM UTC 24 337203000 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.4045088397 Sep 04 09:20:35 AM UTC 24 Sep 04 09:30:06 AM UTC 24 160437100 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.2966144224 Sep 04 09:27:48 AM UTC 24 Sep 04 09:30:07 AM UTC 24 663911900 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.181299392 Sep 04 09:25:35 AM UTC 24 Sep 04 09:30:14 AM UTC 24 14291861600 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.1120686754 Sep 04 09:27:27 AM UTC 24 Sep 04 09:30:18 AM UTC 24 154189100 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.1105292878 Sep 04 09:25:58 AM UTC 24 Sep 04 09:30:25 AM UTC 24 20061807000 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.2572684252 Sep 04 09:29:04 AM UTC 24 Sep 04 09:30:31 AM UTC 24 467686400 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.823175486 Sep 04 09:28:12 AM UTC 24 Sep 04 09:30:36 AM UTC 24 2747971300 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.2591838944 Sep 04 09:27:45 AM UTC 24 Sep 04 09:31:09 AM UTC 24 5158321600 ps
T222 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.700135332 Sep 04 09:27:18 AM UTC 24 Sep 04 09:31:33 AM UTC 24 696875700 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.1906307721 Sep 04 09:08:32 AM UTC 24 Sep 04 09:31:34 AM UTC 24 375660200 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.2435702886 Sep 04 09:31:11 AM UTC 24 Sep 04 09:31:37 AM UTC 24 27175500 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.3463292008 Sep 04 09:30:08 AM UTC 24 Sep 04 09:31:45 AM UTC 24 6745362700 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.3615163518 Sep 04 09:25:54 AM UTC 24 Sep 04 09:31:52 AM UTC 24 49689767400 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.544611584 Sep 04 09:30:19 AM UTC 24 Sep 04 09:32:01 AM UTC 24 556335600 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1484178373 Sep 04 09:29:31 AM UTC 24 Sep 04 09:32:08 AM UTC 24 10019282700 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.1253196626 Sep 04 09:29:56 AM UTC 24 Sep 04 09:32:17 AM UTC 24 1572917700 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.340070924 Sep 04 09:31:34 AM UTC 24 Sep 04 09:32:20 AM UTC 24 29352600 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.731496099 Sep 04 09:31:35 AM UTC 24 Sep 04 09:32:20 AM UTC 24 53839600 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.3995626645 Sep 04 09:32:02 AM UTC 24 Sep 04 09:32:28 AM UTC 24 91156500 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.3121881705 Sep 04 09:31:45 AM UTC 24 Sep 04 09:32:30 AM UTC 24 13002900 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.427752706 Sep 04 09:32:09 AM UTC 24 Sep 04 09:32:33 AM UTC 24 15079900 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.3897270770 Sep 04 09:31:37 AM UTC 24 Sep 04 09:32:35 AM UTC 24 69312500 ps
T273 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3885233813 Sep 04 09:32:18 AM UTC 24 Sep 04 09:32:43 AM UTC 24 43778700 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.2902945167 Sep 04 09:32:21 AM UTC 24 Sep 04 09:32:46 AM UTC 24 104878200 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.773013805 Sep 04 09:23:56 AM UTC 24 Sep 04 09:33:13 AM UTC 24 2809060300 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.928912924 Sep 04 09:31:52 AM UTC 24 Sep 04 09:33:17 AM UTC 24 430042300 ps
T136 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.886311212 Sep 04 09:30:07 AM UTC 24 Sep 04 09:33:17 AM UTC 24 45278703200 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.2222057382 Sep 04 09:30:02 AM UTC 24 Sep 04 09:33:23 AM UTC 24 136657100 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3011928883 Sep 04 09:27:07 AM UTC 24 Sep 04 09:33:32 AM UTC 24 10012786300 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.130001550 Sep 04 09:28:15 AM UTC 24 Sep 04 09:33:40 AM UTC 24 47392844500 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.3512426709 Sep 04 09:16:37 AM UTC 24 Sep 04 09:33:43 AM UTC 24 1519226600 ps
T99 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_type.46427512 Sep 04 08:49:39 AM UTC 24 Sep 04 09:33:46 AM UTC 24 1156460500 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.4182191372 Sep 04 09:29:40 AM UTC 24 Sep 04 09:33:59 AM UTC 24 107462800 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.4089124719 Sep 04 09:30:14 AM UTC 24 Sep 04 09:34:03 AM UTC 24 2933760300 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1222741123 Sep 04 09:30:31 AM UTC 24 Sep 04 09:34:04 AM UTC 24 1650141200 ps
T137 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.3792128877 Sep 04 09:27:35 AM UTC 24 Sep 04 09:34:18 AM UTC 24 264617820300 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.4261614176 Sep 04 09:24:54 AM UTC 24 Sep 04 09:34:19 AM UTC 24 18430331800 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.3224582341 Sep 04 09:16:09 AM UTC 24 Sep 04 09:34:38 AM UTC 24 180202379900 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.2409060342 Sep 04 09:28:01 AM UTC 24 Sep 04 09:34:40 AM UTC 24 13702281900 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.560036604 Sep 04 09:34:04 AM UTC 24 Sep 04 09:34:54 AM UTC 24 44913700 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.1555942680 Sep 04 09:34:19 AM UTC 24 Sep 04 09:34:56 AM UTC 24 11906500 ps
T308 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.2984285186 Sep 04 09:32:35 AM UTC 24 Sep 04 09:34:57 AM UTC 24 5031090400 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.3832639213 Sep 04 09:34:40 AM UTC 24 Sep 04 09:35:02 AM UTC 24 26124500 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.189778474 Sep 04 09:33:18 AM UTC 24 Sep 04 09:37:10 AM UTC 24 13459187900 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1191712190 Sep 04 09:34:00 AM UTC 24 Sep 04 09:35:04 AM UTC 24 27605700 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.3923338189 Sep 04 09:33:18 AM UTC 24 Sep 04 09:35:05 AM UTC 24 3891488000 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.1302483042 Sep 04 09:34:39 AM UTC 24 Sep 04 09:35:07 AM UTC 24 15249200 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.1863963092 Sep 04 09:27:16 AM UTC 24 Sep 04 09:35:11 AM UTC 24 344961600 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.413883755 Sep 04 09:32:21 AM UTC 24 Sep 04 09:35:13 AM UTC 24 10011853800 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.4261202929 Sep 04 09:34:05 AM UTC 24 Sep 04 09:35:15 AM UTC 24 227445200 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.653137767 Sep 04 09:34:54 AM UTC 24 Sep 04 09:35:16 AM UTC 24 131209700 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.3330795127 Sep 04 09:34:58 AM UTC 24 Sep 04 09:35:17 AM UTC 24 88478100 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.564070276 Sep 04 09:33:41 AM UTC 24 Sep 04 09:35:22 AM UTC 24 551394200 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.2727976104 Sep 04 09:33:23 AM UTC 24 Sep 04 09:35:34 AM UTC 24 1540074100 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.2033649083 Sep 04 09:34:20 AM UTC 24 Sep 04 09:35:51 AM UTC 24 1638153100 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.1131449570 Sep 04 09:34:56 AM UTC 24 Sep 04 09:36:00 AM UTC 24 10035836400 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.2011002364 Sep 04 09:32:34 AM UTC 24 Sep 04 09:36:15 AM UTC 24 173978500 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.4270898267 Sep 04 09:35:08 AM UTC 24 Sep 04 09:36:42 AM UTC 24 2816054200 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.653291544 Sep 04 09:33:47 AM UTC 24 Sep 04 09:36:42 AM UTC 24 2074325400 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.2361491673 Sep 04 09:32:28 AM UTC 24 Sep 04 09:36:52 AM UTC 24 57021700 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1922908429 Sep 04 09:30:36 AM UTC 24 Sep 04 09:36:56 AM UTC 24 11940206700 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.1641022280 Sep 04 09:32:47 AM UTC 24 Sep 04 09:37:02 AM UTC 24 132664500 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.1388135884 Sep 04 09:35:17 AM UTC 24 Sep 04 09:37:07 AM UTC 24 1002509500 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.4229017789 Sep 04 09:29:56 AM UTC 24 Sep 04 09:37:11 AM UTC 24 7146225400 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.3950812706 Sep 04 08:54:02 AM UTC 24 Sep 04 09:37:22 AM UTC 24 306491968100 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.2940727111 Sep 04 09:36:43 AM UTC 24 Sep 04 09:37:25 AM UTC 24 110604600 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.2923030115 Sep 04 09:35:22 AM UTC 24 Sep 04 09:37:26 AM UTC 24 2027130500 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.2273605787 Sep 04 09:36:43 AM UTC 24 Sep 04 09:37:28 AM UTC 24 77406500 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.871077657 Sep 04 09:37:08 AM UTC 24 Sep 04 09:37:33 AM UTC 24 16170200 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.4276664275 Sep 04 09:37:11 AM UTC 24 Sep 04 09:37:36 AM UTC 24 15846900 ps
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