| T1084 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.1025615258 |
|
|
Sep 04 09:57:33 AM UTC 24 |
Sep 04 10:02:20 AM UTC 24 |
3140320500 ps |
| T1085 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.2504298292 |
|
|
Sep 04 09:59:50 AM UTC 24 |
Sep 04 10:02:21 AM UTC 24 |
162860900 ps |
| T1086 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.3177643093 |
|
|
Sep 04 10:00:01 AM UTC 24 |
Sep 04 10:02:21 AM UTC 24 |
20280700 ps |
| T1087 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.392494661 |
|
|
Sep 04 10:02:00 AM UTC 24 |
Sep 04 10:02:22 AM UTC 24 |
27351300 ps |
| T1088 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.1589235840 |
|
|
Sep 04 10:00:10 AM UTC 24 |
Sep 04 10:02:23 AM UTC 24 |
45854100 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.3328452606 |
|
|
Sep 04 10:01:55 AM UTC 24 |
Sep 04 10:02:24 AM UTC 24 |
81524100 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2740914728 |
|
|
Sep 04 10:02:05 AM UTC 24 |
Sep 04 10:02:25 AM UTC 24 |
14940200 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.2594485737 |
|
|
Sep 04 09:59:24 AM UTC 24 |
Sep 04 10:02:33 AM UTC 24 |
41375500 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.2542386828 |
|
|
Sep 04 09:59:37 AM UTC 24 |
Sep 04 10:02:37 AM UTC 24 |
44392600 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3348682962 |
|
|
Sep 04 09:55:48 AM UTC 24 |
Sep 04 10:02:37 AM UTC 24 |
11753847900 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.3953488202 |
|
|
Sep 04 08:58:46 AM UTC 24 |
Sep 04 10:02:40 AM UTC 24 |
244563715500 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.4180210142 |
|
|
Sep 04 09:58:03 AM UTC 24 |
Sep 04 10:02:46 AM UTC 24 |
12444166500 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.2468191458 |
|
|
Sep 04 09:44:09 AM UTC 24 |
Sep 04 10:02:57 AM UTC 24 |
474677400 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.1903970848 |
|
|
Sep 04 10:00:27 AM UTC 24 |
Sep 04 10:03:06 AM UTC 24 |
79960000 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.3040740991 |
|
|
Sep 04 10:00:07 AM UTC 24 |
Sep 04 10:03:12 AM UTC 24 |
73236100 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.390608431 |
|
|
Sep 04 10:00:55 AM UTC 24 |
Sep 04 10:03:29 AM UTC 24 |
77789400 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.3169436848 |
|
|
Sep 04 09:42:24 AM UTC 24 |
Sep 04 10:03:29 AM UTC 24 |
760524989700 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.1113527491 |
|
|
Sep 04 10:00:55 AM UTC 24 |
Sep 04 10:03:31 AM UTC 24 |
76622800 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.3941189187 |
|
|
Sep 04 10:00:52 AM UTC 24 |
Sep 04 10:03:31 AM UTC 24 |
82950000 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.3185767650 |
|
|
Sep 04 10:00:44 AM UTC 24 |
Sep 04 10:03:34 AM UTC 24 |
72367500 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.759736048 |
|
|
Sep 04 10:00:41 AM UTC 24 |
Sep 04 10:03:36 AM UTC 24 |
189428300 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.3288927038 |
|
|
Sep 04 09:59:29 AM UTC 24 |
Sep 04 10:03:41 AM UTC 24 |
25863600 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.107411703 |
|
|
Sep 04 10:00:14 AM UTC 24 |
Sep 04 10:03:42 AM UTC 24 |
70215100 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.3998147117 |
|
|
Sep 04 09:59:21 AM UTC 24 |
Sep 04 10:03:45 AM UTC 24 |
27536000 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.4084362164 |
|
|
Sep 04 10:00:53 AM UTC 24 |
Sep 04 10:03:49 AM UTC 24 |
38326600 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.1259942086 |
|
|
Sep 04 10:01:39 AM UTC 24 |
Sep 04 10:03:55 AM UTC 24 |
38039000 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.1369193756 |
|
|
Sep 04 10:00:49 AM UTC 24 |
Sep 04 10:03:55 AM UTC 24 |
64573500 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3029085562 |
|
|
Sep 04 10:00:46 AM UTC 24 |
Sep 04 10:04:00 AM UTC 24 |
77529000 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.992342651 |
|
|
Sep 04 10:01:24 AM UTC 24 |
Sep 04 10:04:01 AM UTC 24 |
281740500 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3172291899 |
|
|
Sep 04 10:01:05 AM UTC 24 |
Sep 04 10:04:04 AM UTC 24 |
140738400 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1244949836 |
|
|
Sep 04 10:01:13 AM UTC 24 |
Sep 04 10:04:10 AM UTC 24 |
40630500 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2062448798 |
|
|
Sep 04 10:01:18 AM UTC 24 |
Sep 04 10:04:14 AM UTC 24 |
62555200 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3057466318 |
|
|
Sep 04 10:01:02 AM UTC 24 |
Sep 04 10:04:16 AM UTC 24 |
150032300 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.614674761 |
|
|
Sep 04 10:01:26 AM UTC 24 |
Sep 04 10:04:22 AM UTC 24 |
39054900 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.303709522 |
|
|
Sep 04 10:01:37 AM UTC 24 |
Sep 04 10:04:31 AM UTC 24 |
72139000 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.758410317 |
|
|
Sep 04 10:01:49 AM UTC 24 |
Sep 04 10:04:32 AM UTC 24 |
36967100 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.3513593137 |
|
|
Sep 04 10:01:26 AM UTC 24 |
Sep 04 10:04:34 AM UTC 24 |
71141800 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.2704386022 |
|
|
Sep 04 10:01:54 AM UTC 24 |
Sep 04 10:04:36 AM UTC 24 |
94261500 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.2870406863 |
|
|
Sep 04 10:01:33 AM UTC 24 |
Sep 04 10:04:38 AM UTC 24 |
134075800 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.4183056581 |
|
|
Sep 04 10:01:55 AM UTC 24 |
Sep 04 10:04:41 AM UTC 24 |
76799700 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.2833272556 |
|
|
Sep 04 10:01:50 AM UTC 24 |
Sep 04 10:04:41 AM UTC 24 |
39398700 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.3595987860 |
|
|
Sep 04 10:01:59 AM UTC 24 |
Sep 04 10:04:51 AM UTC 24 |
145151200 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.1708791806 |
|
|
Sep 04 10:01:55 AM UTC 24 |
Sep 04 10:04:51 AM UTC 24 |
87088900 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.7383327 |
|
|
Sep 04 10:01:41 AM UTC 24 |
Sep 04 10:04:53 AM UTC 24 |
81157600 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.2593980982 |
|
|
Sep 04 09:46:08 AM UTC 24 |
Sep 04 10:04:56 AM UTC 24 |
175913400 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1513142734 |
|
|
Sep 04 10:01:06 AM UTC 24 |
Sep 04 10:04:56 AM UTC 24 |
73397900 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.2638117503 |
|
|
Sep 04 10:01:44 AM UTC 24 |
Sep 04 10:04:56 AM UTC 24 |
129243300 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.1962602798 |
|
|
Sep 04 10:01:40 AM UTC 24 |
Sep 04 10:04:57 AM UTC 24 |
42027500 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.111186591 |
|
|
Sep 04 10:01:34 AM UTC 24 |
Sep 04 10:04:57 AM UTC 24 |
76621500 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.3375901637 |
|
|
Sep 04 10:02:02 AM UTC 24 |
Sep 04 10:05:28 AM UTC 24 |
63443400 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.3345115152 |
|
|
Sep 04 09:16:49 AM UTC 24 |
Sep 04 10:07:25 AM UTC 24 |
6197688500 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.2221424212 |
|
|
Sep 04 09:20:56 AM UTC 24 |
Sep 04 10:15:22 AM UTC 24 |
10861196200 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.2024132342 |
|
|
Sep 04 09:24:42 AM UTC 24 |
Sep 04 10:16:51 AM UTC 24 |
5491092500 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.1462993111 |
|
|
Sep 04 08:49:40 AM UTC 24 |
Sep 04 10:30:54 AM UTC 24 |
1574057300 ps |
| T41 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.1504534966 |
|
|
Sep 04 08:52:54 AM UTC 24 |
Sep 04 10:49:06 AM UTC 24 |
4040157500 ps |
| T42 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.1226290002 |
|
|
Sep 04 09:01:49 AM UTC 24 |
Sep 04 10:50:03 AM UTC 24 |
5233140800 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3535425804 |
|
|
Sep 04 08:56:38 AM UTC 24 |
Sep 04 10:50:09 AM UTC 24 |
11831699700 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.3426125814 |
|
|
Sep 04 09:07:20 AM UTC 24 |
Sep 04 10:57:35 AM UTC 24 |
7301371100 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3734203158 |
|
|
Sep 04 10:02:05 AM UTC 24 |
Sep 04 10:02:32 AM UTC 24 |
46544300 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.905525964 |
|
|
Sep 04 10:02:10 AM UTC 24 |
Sep 04 10:02:38 AM UTC 24 |
11328000 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2242317563 |
|
|
Sep 04 10:02:19 AM UTC 24 |
Sep 04 10:02:38 AM UTC 24 |
53850100 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.3564747151 |
|
|
Sep 04 10:02:16 AM UTC 24 |
Sep 04 10:02:40 AM UTC 24 |
15216600 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.3716057363 |
|
|
Sep 04 10:02:17 AM UTC 24 |
Sep 04 10:02:42 AM UTC 24 |
26771700 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1337156986 |
|
|
Sep 04 10:02:22 AM UTC 24 |
Sep 04 10:02:46 AM UTC 24 |
66437900 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.4079675516 |
|
|
Sep 04 10:02:22 AM UTC 24 |
Sep 04 10:02:46 AM UTC 24 |
40778800 ps |
| T71 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.2462251014 |
|
|
Sep 04 10:02:26 AM UTC 24 |
Sep 04 10:02:51 AM UTC 24 |
310072400 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1791165455 |
|
|
Sep 04 10:02:33 AM UTC 24 |
Sep 04 10:02:59 AM UTC 24 |
218154900 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.1336186886 |
|
|
Sep 04 10:02:39 AM UTC 24 |
Sep 04 10:03:00 AM UTC 24 |
15151100 ps |
| T72 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2275040335 |
|
|
Sep 04 10:02:25 AM UTC 24 |
Sep 04 10:03:00 AM UTC 24 |
189408500 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2132618043 |
|
|
Sep 04 10:02:38 AM UTC 24 |
Sep 04 10:03:03 AM UTC 24 |
34989000 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3073329864 |
|
|
Sep 04 10:02:39 AM UTC 24 |
Sep 04 10:03:03 AM UTC 24 |
100959500 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1823146597 |
|
|
Sep 04 10:02:47 AM UTC 24 |
Sep 04 10:03:05 AM UTC 24 |
30836300 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.2400662758 |
|
|
Sep 04 10:02:39 AM UTC 24 |
Sep 04 10:03:12 AM UTC 24 |
37822100 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2181052747 |
|
|
Sep 04 10:02:47 AM UTC 24 |
Sep 04 10:03:12 AM UTC 24 |
150388000 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.1661541583 |
|
|
Sep 04 10:02:48 AM UTC 24 |
Sep 04 10:03:15 AM UTC 24 |
590389300 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.399031639 |
|
|
Sep 04 10:02:58 AM UTC 24 |
Sep 04 10:03:21 AM UTC 24 |
51694100 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.321384906 |
|
|
Sep 04 10:02:22 AM UTC 24 |
Sep 04 10:03:24 AM UTC 24 |
280689500 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.273068157 |
|
|
Sep 04 10:03:04 AM UTC 24 |
Sep 04 10:03:24 AM UTC 24 |
44666700 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2986375893 |
|
|
Sep 04 10:03:04 AM UTC 24 |
Sep 04 10:03:24 AM UTC 24 |
19052900 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1614576874 |
|
|
Sep 04 10:02:52 AM UTC 24 |
Sep 04 10:03:24 AM UTC 24 |
370002400 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3971241453 |
|
|
Sep 04 10:02:23 AM UTC 24 |
Sep 04 10:03:26 AM UTC 24 |
1233114700 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.4088305923 |
|
|
Sep 04 10:03:01 AM UTC 24 |
Sep 04 10:03:26 AM UTC 24 |
112000500 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.775519228 |
|
|
Sep 04 10:03:01 AM UTC 24 |
Sep 04 10:03:32 AM UTC 24 |
12668700 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2682977885 |
|
|
Sep 04 10:03:05 AM UTC 24 |
Sep 04 10:03:35 AM UTC 24 |
31864500 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.1792838790 |
|
|
Sep 04 10:02:47 AM UTC 24 |
Sep 04 10:03:36 AM UTC 24 |
21222600 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.3776329152 |
|
|
Sep 04 10:03:13 AM UTC 24 |
Sep 04 10:03:39 AM UTC 24 |
60096600 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.3774314663 |
|
|
Sep 04 10:03:16 AM UTC 24 |
Sep 04 10:03:42 AM UTC 24 |
1084303600 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.3698435577 |
|
|
Sep 04 10:02:23 AM UTC 24 |
Sep 04 10:03:43 AM UTC 24 |
12429367700 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.2760833278 |
|
|
Sep 04 10:02:47 AM UTC 24 |
Sep 04 10:03:44 AM UTC 24 |
462713700 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.1390492600 |
|
|
Sep 04 10:03:27 AM UTC 24 |
Sep 04 10:03:45 AM UTC 24 |
53964900 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1373865953 |
|
|
Sep 04 10:03:22 AM UTC 24 |
Sep 04 10:03:46 AM UTC 24 |
1020760500 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4056218732 |
|
|
Sep 04 10:03:30 AM UTC 24 |
Sep 04 10:03:48 AM UTC 24 |
19589900 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.773835252 |
|
|
Sep 04 10:03:07 AM UTC 24 |
Sep 04 10:03:49 AM UTC 24 |
262564100 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.460171702 |
|
|
Sep 04 10:03:24 AM UTC 24 |
Sep 04 10:03:50 AM UTC 24 |
32430500 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1787293554 |
|
|
Sep 04 10:03:25 AM UTC 24 |
Sep 04 10:03:50 AM UTC 24 |
53219100 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.4191486091 |
|
|
Sep 04 10:03:27 AM UTC 24 |
Sep 04 10:03:50 AM UTC 24 |
29399000 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.2649948889 |
|
|
Sep 04 10:03:32 AM UTC 24 |
Sep 04 10:03:52 AM UTC 24 |
22040800 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.3887260669 |
|
|
Sep 04 10:03:25 AM UTC 24 |
Sep 04 10:03:57 AM UTC 24 |
40916400 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.1313490322 |
|
|
Sep 04 10:03:36 AM UTC 24 |
Sep 04 10:03:57 AM UTC 24 |
64786100 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.400736912 |
|
|
Sep 04 10:03:13 AM UTC 24 |
Sep 04 10:03:58 AM UTC 24 |
2567652200 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.2011059047 |
|
|
Sep 04 10:03:36 AM UTC 24 |
Sep 04 10:04:00 AM UTC 24 |
241170600 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1217885656 |
|
|
Sep 04 10:03:42 AM UTC 24 |
Sep 04 10:04:01 AM UTC 24 |
45262600 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.705734947 |
|
|
Sep 04 10:03:43 AM UTC 24 |
Sep 04 10:04:02 AM UTC 24 |
20020300 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.224458562 |
|
|
Sep 04 10:03:39 AM UTC 24 |
Sep 04 10:04:03 AM UTC 24 |
12500300 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.517553129 |
|
|
Sep 04 10:02:47 AM UTC 24 |
Sep 04 10:04:07 AM UTC 24 |
1317225700 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3263463377 |
|
|
Sep 04 10:03:44 AM UTC 24 |
Sep 04 10:04:07 AM UTC 24 |
24989500 ps |
| T321 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.3325904109 |
|
|
Sep 04 10:03:43 AM UTC 24 |
Sep 04 10:04:07 AM UTC 24 |
28410600 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2453584508 |
|
|
Sep 04 10:03:46 AM UTC 24 |
Sep 04 10:04:08 AM UTC 24 |
122880300 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.456453159 |
|
|
Sep 04 10:03:34 AM UTC 24 |
Sep 04 10:04:09 AM UTC 24 |
102059400 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.1131400553 |
|
|
Sep 04 10:03:50 AM UTC 24 |
Sep 04 10:04:13 AM UTC 24 |
135592600 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.2828369258 |
|
|
Sep 04 10:03:52 AM UTC 24 |
Sep 04 10:04:17 AM UTC 24 |
20838800 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.2178838239 |
|
|
Sep 04 10:03:53 AM UTC 24 |
Sep 04 10:04:19 AM UTC 24 |
29226200 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.913085988 |
|
|
Sep 04 10:03:55 AM UTC 24 |
Sep 04 10:04:19 AM UTC 24 |
362036800 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.4158539315 |
|
|
Sep 04 10:03:56 AM UTC 24 |
Sep 04 10:04:20 AM UTC 24 |
330878800 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1309000073 |
|
|
Sep 04 10:03:32 AM UTC 24 |
Sep 04 10:04:20 AM UTC 24 |
1215226900 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1800833619 |
|
|
Sep 04 10:03:58 AM UTC 24 |
Sep 04 10:04:20 AM UTC 24 |
166003900 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.1338052576 |
|
|
Sep 04 10:03:51 AM UTC 24 |
Sep 04 10:04:21 AM UTC 24 |
190430900 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.3730358153 |
|
|
Sep 04 10:04:01 AM UTC 24 |
Sep 04 10:04:21 AM UTC 24 |
18632600 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.1971394502 |
|
|
Sep 04 10:03:52 AM UTC 24 |
Sep 04 10:04:22 AM UTC 24 |
17341300 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.4049659645 |
|
|
Sep 04 10:03:57 AM UTC 24 |
Sep 04 10:04:23 AM UTC 24 |
158676600 ps |
| T325 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.4223359698 |
|
|
Sep 04 10:04:02 AM UTC 24 |
Sep 04 10:04:25 AM UTC 24 |
61465200 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.2702924494 |
|
|
Sep 04 10:04:03 AM UTC 24 |
Sep 04 10:04:25 AM UTC 24 |
65108800 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.2411864915 |
|
|
Sep 04 10:03:47 AM UTC 24 |
Sep 04 10:04:26 AM UTC 24 |
222527500 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.3109332582 |
|
|
Sep 04 10:04:08 AM UTC 24 |
Sep 04 10:04:27 AM UTC 24 |
69101300 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.823210292 |
|
|
Sep 04 10:04:04 AM UTC 24 |
Sep 04 10:04:27 AM UTC 24 |
348918000 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.3510613060 |
|
|
Sep 04 10:04:01 AM UTC 24 |
Sep 04 10:04:28 AM UTC 24 |
21790700 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.4264639576 |
|
|
Sep 04 10:04:02 AM UTC 24 |
Sep 04 10:04:29 AM UTC 24 |
25379500 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.386824541 |
|
|
Sep 04 10:03:30 AM UTC 24 |
Sep 04 10:04:29 AM UTC 24 |
869143000 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.3840571249 |
|
|
Sep 04 10:04:09 AM UTC 24 |
Sep 04 10:04:30 AM UTC 24 |
12211500 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.1435573540 |
|
|
Sep 04 10:04:05 AM UTC 24 |
Sep 04 10:04:32 AM UTC 24 |
155898500 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.3520489954 |
|
|
Sep 04 10:04:10 AM UTC 24 |
Sep 04 10:04:32 AM UTC 24 |
18397300 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.831406681 |
|
|
Sep 04 10:03:45 AM UTC 24 |
Sep 04 10:04:32 AM UTC 24 |
63582400 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1251511650 |
|
|
Sep 04 10:04:10 AM UTC 24 |
Sep 04 10:04:33 AM UTC 24 |
77791600 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1651581200 |
|
|
Sep 04 10:04:17 AM UTC 24 |
Sep 04 10:04:35 AM UTC 24 |
39594500 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.2950459417 |
|
|
Sep 04 10:03:33 AM UTC 24 |
Sep 04 10:04:37 AM UTC 24 |
2525671500 ps |
| T296 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.2040751866 |
|
|
Sep 04 10:04:15 AM UTC 24 |
Sep 04 10:04:38 AM UTC 24 |
190558000 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.189276540 |
|
|
Sep 04 10:04:24 AM UTC 24 |
Sep 04 10:04:42 AM UTC 24 |
16025000 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.725276050 |
|
|
Sep 04 10:04:23 AM UTC 24 |
Sep 04 10:04:42 AM UTC 24 |
21222800 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1181821596 |
|
|
Sep 04 10:04:21 AM UTC 24 |
Sep 04 10:04:42 AM UTC 24 |
16331700 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.3348108213 |
|
|
Sep 04 10:04:22 AM UTC 24 |
Sep 04 10:04:43 AM UTC 24 |
81274400 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.366305765 |
|
|
Sep 04 10:03:49 AM UTC 24 |
Sep 04 10:04:43 AM UTC 24 |
1917959300 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.2385162847 |
|
|
Sep 04 10:04:15 AM UTC 24 |
Sep 04 10:04:44 AM UTC 24 |
167448000 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.1419872323 |
|
|
Sep 04 10:04:23 AM UTC 24 |
Sep 04 10:04:44 AM UTC 24 |
41334500 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.86900843 |
|
|
Sep 04 10:03:13 AM UTC 24 |
Sep 04 10:04:46 AM UTC 24 |
17280825100 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.727219955 |
|
|
Sep 04 10:04:26 AM UTC 24 |
Sep 04 10:04:47 AM UTC 24 |
94674500 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.737179666 |
|
|
Sep 04 10:04:29 AM UTC 24 |
Sep 04 10:04:48 AM UTC 24 |
63150300 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.4084368210 |
|
|
Sep 04 10:04:21 AM UTC 24 |
Sep 04 10:04:49 AM UTC 24 |
269204500 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.696552745 |
|
|
Sep 04 10:04:21 AM UTC 24 |
Sep 04 10:04:49 AM UTC 24 |
109207700 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.3791878112 |
|
|
Sep 04 10:04:22 AM UTC 24 |
Sep 04 10:04:50 AM UTC 24 |
126450400 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1967675399 |
|
|
Sep 04 10:04:27 AM UTC 24 |
Sep 04 10:04:50 AM UTC 24 |
87357700 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.1879090916 |
|
|
Sep 04 10:04:25 AM UTC 24 |
Sep 04 10:04:51 AM UTC 24 |
62687800 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.1425434283 |
|
|
Sep 04 10:04:19 AM UTC 24 |
Sep 04 10:04:52 AM UTC 24 |
14843300 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.2858804608 |
|
|
Sep 04 10:04:29 AM UTC 24 |
Sep 04 10:04:52 AM UTC 24 |
19110100 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2161945938 |
|
|
Sep 04 10:04:30 AM UTC 24 |
Sep 04 10:04:52 AM UTC 24 |
51760200 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.522491724 |
|
|
Sep 04 10:04:31 AM UTC 24 |
Sep 04 10:04:52 AM UTC 24 |
113720500 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.450900308 |
|
|
Sep 04 10:04:34 AM UTC 24 |
Sep 04 10:04:54 AM UTC 24 |
71229400 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.495223726 |
|
|
Sep 04 10:04:32 AM UTC 24 |
Sep 04 10:04:54 AM UTC 24 |
67948300 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.1932633561 |
|
|
Sep 04 10:04:30 AM UTC 24 |
Sep 04 10:04:55 AM UTC 24 |
17120100 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2297959757 |
|
|
Sep 04 10:04:34 AM UTC 24 |
Sep 04 10:04:56 AM UTC 24 |
13744400 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3660334138 |
|
|
Sep 04 10:04:35 AM UTC 24 |
Sep 04 10:04:57 AM UTC 24 |
17700100 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.1880928035 |
|
|
Sep 04 10:04:37 AM UTC 24 |
Sep 04 10:04:57 AM UTC 24 |
109855800 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3071057770 |
|
|
Sep 04 10:04:32 AM UTC 24 |
Sep 04 10:04:58 AM UTC 24 |
97946500 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1849122271 |
|
|
Sep 04 10:04:11 AM UTC 24 |
Sep 04 10:04:58 AM UTC 24 |
653197700 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2655635100 |
|
|
Sep 04 10:04:36 AM UTC 24 |
Sep 04 10:05:00 AM UTC 24 |
127568000 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3279065010 |
|
|
Sep 04 10:04:32 AM UTC 24 |
Sep 04 10:05:01 AM UTC 24 |
264459600 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.3556848550 |
|
|
Sep 04 10:04:41 AM UTC 24 |
Sep 04 10:05:02 AM UTC 24 |
12396900 ps |
| T323 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2357923111 |
|
|
Sep 04 10:04:42 AM UTC 24 |
Sep 04 10:05:02 AM UTC 24 |
16614600 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.639878298 |
|
|
Sep 04 10:04:42 AM UTC 24 |
Sep 04 10:05:03 AM UTC 24 |
18148600 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.3504536798 |
|
|
Sep 04 10:04:38 AM UTC 24 |
Sep 04 10:05:03 AM UTC 24 |
25618600 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.3811919896 |
|
|
Sep 04 10:04:38 AM UTC 24 |
Sep 04 10:05:03 AM UTC 24 |
370722900 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.257331617 |
|
|
Sep 04 10:03:46 AM UTC 24 |
Sep 04 10:05:04 AM UTC 24 |
12146181800 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1336968754 |
|
|
Sep 04 10:04:45 AM UTC 24 |
Sep 04 10:05:05 AM UTC 24 |
70826500 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.2910820437 |
|
|
Sep 04 10:04:44 AM UTC 24 |
Sep 04 10:05:06 AM UTC 24 |
96026100 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1872461487 |
|
|
Sep 04 10:04:44 AM UTC 24 |
Sep 04 10:05:07 AM UTC 24 |
39569300 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1949185429 |
|
|
Sep 04 10:04:44 AM UTC 24 |
Sep 04 10:05:07 AM UTC 24 |
318638100 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.3587801054 |
|
|
Sep 04 10:04:48 AM UTC 24 |
Sep 04 10:05:07 AM UTC 24 |
28338300 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.1496290047 |
|
|
Sep 04 10:04:43 AM UTC 24 |
Sep 04 10:05:09 AM UTC 24 |
234876500 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2482195240 |
|
|
Sep 04 10:04:49 AM UTC 24 |
Sep 04 10:05:10 AM UTC 24 |
89687800 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.3034720460 |
|
|
Sep 04 10:04:52 AM UTC 24 |
Sep 04 10:05:11 AM UTC 24 |
139267600 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1851088424 |
|
|
Sep 04 10:04:50 AM UTC 24 |
Sep 04 10:05:12 AM UTC 24 |
89016400 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.2390739563 |
|
|
Sep 04 10:04:46 AM UTC 24 |
Sep 04 10:05:13 AM UTC 24 |
23629900 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.956671034 |
|
|
Sep 04 10:04:52 AM UTC 24 |
Sep 04 10:05:13 AM UTC 24 |
15277100 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.3229015925 |
|
|
Sep 04 10:04:52 AM UTC 24 |
Sep 04 10:05:15 AM UTC 24 |
13945700 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.2936179597 |
|
|
Sep 04 10:04:55 AM UTC 24 |
Sep 04 10:05:16 AM UTC 24 |
75037200 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.1420302663 |
|
|
Sep 04 10:04:53 AM UTC 24 |
Sep 04 10:05:16 AM UTC 24 |
19964300 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2384859348 |
|
|
Sep 04 10:04:53 AM UTC 24 |
Sep 04 10:05:17 AM UTC 24 |
137019900 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1278910248 |
|
|
Sep 04 10:04:55 AM UTC 24 |
Sep 04 10:05:17 AM UTC 24 |
22410000 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.4222515949 |
|
|
Sep 04 10:04:59 AM UTC 24 |
Sep 04 10:05:17 AM UTC 24 |
16399600 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.24442401 |
|
|
Sep 04 10:04:59 AM UTC 24 |
Sep 04 10:05:18 AM UTC 24 |
14720100 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.2825077430 |
|
|
Sep 04 10:04:53 AM UTC 24 |
Sep 04 10:05:18 AM UTC 24 |
39833400 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.2707894017 |
|
|
Sep 04 10:04:53 AM UTC 24 |
Sep 04 10:05:18 AM UTC 24 |
545139000 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.2645349247 |
|
|
Sep 04 10:04:51 AM UTC 24 |
Sep 04 10:05:21 AM UTC 24 |
102682500 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3993467657 |
|
|
Sep 04 10:04:59 AM UTC 24 |
Sep 04 10:05:21 AM UTC 24 |
36774400 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.2839687269 |
|
|
Sep 04 10:04:58 AM UTC 24 |
Sep 04 10:05:21 AM UTC 24 |
34588300 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.3966601079 |
|
|
Sep 04 10:05:03 AM UTC 24 |
Sep 04 10:05:21 AM UTC 24 |
11372700 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.2944865450 |
|
|
Sep 04 10:05:03 AM UTC 24 |
Sep 04 10:05:21 AM UTC 24 |
12000000 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.2593007831 |
|
|
Sep 04 10:04:56 AM UTC 24 |
Sep 04 10:05:21 AM UTC 24 |
19218200 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.87916 |
|
|
Sep 04 10:04:57 AM UTC 24 |
Sep 04 10:05:22 AM UTC 24 |
78927200 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.2662017283 |
|
|
Sep 04 10:04:57 AM UTC 24 |
Sep 04 10:05:23 AM UTC 24 |
153653800 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2176392397 |
|
|
Sep 04 10:04:57 AM UTC 24 |
Sep 04 10:05:24 AM UTC 24 |
57757100 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.394562884 |
|
|
Sep 04 10:04:57 AM UTC 24 |
Sep 04 10:05:24 AM UTC 24 |
78380100 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.136746242 |
|
|
Sep 04 10:04:50 AM UTC 24 |
Sep 04 10:05:24 AM UTC 24 |
39634500 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1692650476 |
|
|
Sep 04 10:05:01 AM UTC 24 |
Sep 04 10:05:25 AM UTC 24 |
114649600 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.2528560326 |
|
|
Sep 04 10:05:00 AM UTC 24 |
Sep 04 10:05:26 AM UTC 24 |
133457000 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1324303838 |
|
|
Sep 04 10:05:04 AM UTC 24 |
Sep 04 10:05:26 AM UTC 24 |
51707300 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.1758255726 |
|
|
Sep 04 10:05:02 AM UTC 24 |
Sep 04 10:05:27 AM UTC 24 |
106268400 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.2906861826 |
|
|
Sep 04 10:05:06 AM UTC 24 |
Sep 04 10:05:28 AM UTC 24 |
25415800 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.328491549 |
|
|
Sep 04 10:05:10 AM UTC 24 |
Sep 04 10:05:28 AM UTC 24 |
31478800 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2321178769 |
|
|
Sep 04 10:05:07 AM UTC 24 |
Sep 04 10:05:30 AM UTC 24 |
71800600 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1630109192 |
|
|
Sep 04 10:05:04 AM UTC 24 |
Sep 04 10:05:30 AM UTC 24 |
221681600 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.2233515715 |
|
|
Sep 04 10:05:08 AM UTC 24 |
Sep 04 10:05:31 AM UTC 24 |
13655000 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.2967554113 |
|
|
Sep 04 10:05:08 AM UTC 24 |
Sep 04 10:05:33 AM UTC 24 |
14101100 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.2357080053 |
|
|
Sep 04 10:05:17 AM UTC 24 |
Sep 04 10:05:35 AM UTC 24 |
17329000 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1089076089 |
|
|
Sep 04 10:05:19 AM UTC 24 |
Sep 04 10:05:37 AM UTC 24 |
26715300 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.2062795550 |
|
|
Sep 04 10:05:14 AM UTC 24 |
Sep 04 10:05:37 AM UTC 24 |
300621600 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2964881368 |
|
|
Sep 04 10:05:16 AM UTC 24 |
Sep 04 10:05:37 AM UTC 24 |
42794800 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1916584113 |
|
|
Sep 04 10:05:11 AM UTC 24 |
Sep 04 10:05:37 AM UTC 24 |
49938600 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.450610652 |
|
|
Sep 04 10:05:12 AM UTC 24 |
Sep 04 10:05:38 AM UTC 24 |
187465700 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3156730545 |
|
|
Sep 04 10:05:12 AM UTC 24 |
Sep 04 10:05:39 AM UTC 24 |
68018200 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.1935863925 |
|
|
Sep 04 10:05:19 AM UTC 24 |
Sep 04 10:05:39 AM UTC 24 |
28793200 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3538157810 |
|
|
Sep 04 10:05:19 AM UTC 24 |
Sep 04 10:05:39 AM UTC 24 |
25273100 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3149653811 |
|
|
Sep 04 10:05:22 AM UTC 24 |
Sep 04 10:05:39 AM UTC 24 |
17289100 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.2072122411 |
|
|
Sep 04 10:05:18 AM UTC 24 |
Sep 04 10:05:39 AM UTC 24 |
35315400 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.477479192 |
|
|
Sep 04 10:05:22 AM UTC 24 |
Sep 04 10:05:40 AM UTC 24 |
15352800 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1013837244 |
|
|
Sep 04 10:05:18 AM UTC 24 |
Sep 04 10:05:41 AM UTC 24 |
68558100 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.624809999 |
|
|
Sep 04 10:05:17 AM UTC 24 |
Sep 04 10:05:41 AM UTC 24 |
14553200 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.760857187 |
|
|
Sep 04 10:05:22 AM UTC 24 |
Sep 04 10:05:41 AM UTC 24 |
57909000 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.3972560906 |
|
|
Sep 04 10:05:22 AM UTC 24 |
Sep 04 10:05:41 AM UTC 24 |
26942900 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.3566443384 |
|
|
Sep 04 10:05:23 AM UTC 24 |
Sep 04 10:05:41 AM UTC 24 |
78110700 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.542497550 |
|
|
Sep 04 10:05:23 AM UTC 24 |
Sep 04 10:05:43 AM UTC 24 |
17398000 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.3658301605 |
|
|
Sep 04 10:05:22 AM UTC 24 |
Sep 04 10:05:44 AM UTC 24 |
45840300 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1679692600 |
|
|
Sep 04 10:05:27 AM UTC 24 |
Sep 04 10:05:44 AM UTC 24 |
107650400 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.479844210 |
|
|
Sep 04 10:05:24 AM UTC 24 |
Sep 04 10:05:45 AM UTC 24 |
18061600 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.2108498039 |
|
|
Sep 04 10:05:23 AM UTC 24 |
Sep 04 10:05:46 AM UTC 24 |
30057300 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2602557786 |
|
|
Sep 04 10:05:18 AM UTC 24 |
Sep 04 10:05:47 AM UTC 24 |
59378400 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.171316504 |
|
|
Sep 04 10:05:24 AM UTC 24 |
Sep 04 10:05:47 AM UTC 24 |
27558900 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.618019353 |
|
|
Sep 04 10:05:25 AM UTC 24 |
Sep 04 10:05:48 AM UTC 24 |
24430200 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.2091883715 |
|
|
Sep 04 10:05:27 AM UTC 24 |
Sep 04 10:05:48 AM UTC 24 |
41490900 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2114490727 |
|
|
Sep 04 10:05:29 AM UTC 24 |
Sep 04 10:05:48 AM UTC 24 |
57570100 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.1893815355 |
|
|
Sep 04 10:05:29 AM UTC 24 |
Sep 04 10:05:49 AM UTC 24 |
15458000 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.3397349981 |
|
|
Sep 04 10:05:06 AM UTC 24 |
Sep 04 10:05:50 AM UTC 24 |
399787800 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.2646573309 |
|
|
Sep 04 10:05:29 AM UTC 24 |
Sep 04 10:05:50 AM UTC 24 |
30277700 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.3129860397 |
|
|
Sep 04 10:05:31 AM UTC 24 |
Sep 04 10:05:51 AM UTC 24 |
56155400 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2215335539 |
|
|
Sep 04 10:05:31 AM UTC 24 |
Sep 04 10:05:51 AM UTC 24 |
31680500 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.1906407958 |
|
|
Sep 04 10:05:27 AM UTC 24 |
Sep 04 10:05:51 AM UTC 24 |
43725000 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.3347781722 |
|
|
Sep 04 10:05:31 AM UTC 24 |
Sep 04 10:05:53 AM UTC 24 |
15619800 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.276895528 |
|
|
Sep 04 10:05:29 AM UTC 24 |
Sep 04 10:05:53 AM UTC 24 |
33115600 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.2373904028 |
|
|
Sep 04 10:05:34 AM UTC 24 |
Sep 04 10:05:53 AM UTC 24 |
25492800 ps |
| T1266 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.354540119 |
|
|
Sep 04 10:05:36 AM UTC 24 |
Sep 04 10:05:57 AM UTC 24 |
20311500 ps |
| T1267 |
/workspaces/repo/scratch/os_regression_2024_09_03/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.2436553410 |
|
|
Sep 04 10:05:38 AM UTC 24 |
Sep 04 10:05:57 AM UTC 24 |
20306400 ps |