FLASH_CTRL Simulation Results

Monday September 09 2024 02:20:26 UTC

GitHub Revision: `af2d1709f9`

Branch: os_regression_2024_09_08

Simulator: VCS

Build randomization enabled with --build-seed 13980492992314588037778262839223440914483141513139750793389284041724730149540

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	flash_ctrl_smoke	4.923m	33.871us	50	50	100.00
V1	smoke_hw	flash_ctrl_smoke_hw	43.910s	17.858us	5	5	100.00
V1	csr_hw_reset	flash_ctrl_csr_hw_reset	1.192m	26.120us	5	5	100.00
V1	csr_rw	flash_ctrl_csr_rw	30.650s	29.756us	20	20	100.00
V1	csr_bit_bash	flash_ctrl_csr_bit_bash	1.948m	21.000ms	5	5	100.00
V1	csr_aliasing	flash_ctrl_csr_aliasing	1.302m	25.092ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	flash_ctrl_csr_mem_rw_with_rand_reset	36.410s	318.151us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	flash_ctrl_csr_rw	30.650s	29.756us	20	20	100.00
		flash_ctrl_csr_aliasing	1.302m	25.092ms	5	5	100.00
V1	mem_walk	flash_ctrl_mem_walk	26.340s	29.243us	5	5	100.00
V1	mem_partial_access	flash_ctrl_mem_partial_access	27.460s	28.406us	5	5	100.00
V1		TOTAL			120	120	100.00
V2	sw_op	flash_ctrl_sw_op	48.040s	43.469us	5	5	100.00
V2	host_read_direct	flash_ctrl_host_dir_rd	3.239m	74.125us	5	5	100.00
V2	rma_hw_if	flash_ctrl_hw_rma	35.089m	543.581ms	3	3	100.00
		flash_ctrl_hw_rma_reset	17.533m	80.138ms	20	20	100.00
		flash_ctrl_lcmgr_intg	28.430s	47.667us	20	20	100.00
V2	host_controller_arb	flash_ctrl_host_ctrl_arb	54.457m	281.692ms	5	5	100.00
V2	erase_suspend	flash_ctrl_erase_suspend	10.760m	5.504ms	5	5	100.00
V2	program_reset	flash_ctrl_prog_reset	3.617m	3.178ms	29	30	96.67
V2	full_memory_access	flash_ctrl_full_mem_access	1.136h	203.466ms	5	5	100.00
V2	rd_buff_eviction	flash_ctrl_rd_buff_evict	4.173m	4.932ms	5	5	100.00
V2	rd_buff_eviction_w_ecc	flash_ctrl_rw_evict	1.037m	39.171us	37	40	92.50
		flash_ctrl_rw_evict_all_en	1.025m	29.268us	40	40	100.00
		flash_ctrl_re_evict	1.107m	148.356us	20	20	100.00
V2	host_arb	flash_ctrl_phy_arb	12.877m	4.057ms	20	20	100.00
V2	host_interleave	flash_ctrl_phy_arb	12.877m	4.057ms	20	20	100.00
V2	memory_protection	flash_ctrl_mp_regions	16.450m	15.561ms	20	20	100.00
V2	fetch_code	flash_ctrl_fetch_code	42.150s	1.105ms	10	10	100.00
V2	all_partitions	flash_ctrl_rand_ops	35.324m	3.317ms	20	20	100.00
V2	error_mp	flash_ctrl_error_mp	57.230m	9.526ms	10	10	100.00
V2	error_prog_win	flash_ctrl_error_prog_win	26.965m	1.943ms	10	10	100.00
V2	error_prog_type	flash_ctrl_error_prog_type	57.468m	948.457us	3	5	60.00
V2	error_read_seed	flash_ctrl_hw_read_seed_err	28.710s	206.037us	20	20	100.00
V2	read_write_overflow	flash_ctrl_oversize_error	3.139m	2.480ms	5	5	100.00
V2	flash_ctrl_disable	flash_ctrl_disable	44.430s	27.694us	50	50	100.00
V2	flash_ctrl_connect	flash_ctrl_connect	32.740s	22.640us	80	80	100.00
V2	stress_all	flash_ctrl_stress_all	24.911m	856.673us	5	5	100.00
V2	secret_partition	flash_ctrl_hw_sec_otp	4.656m	26.765ms	50	50	100.00
		flash_ctrl_otp_reset	3.903m	90.012us	80	80	100.00
V2	isolation_partition	flash_ctrl_hw_rma	35.089m	543.581ms	3	3	100.00
V2	interrupts	flash_ctrl_intr_rd	4.630m	30.201ms	40	40	100.00
		flash_ctrl_intr_wr	1.881m	15.806ms	10	10	100.00
		flash_ctrl_intr_rd_slow_flash	8.785m	199.193ms	40	40	100.00
		flash_ctrl_intr_wr_slow_flash	7.082m	344.412ms	9	10	90.00
V2	invalid_op	flash_ctrl_invalid_op	2.003m	14.298ms	20	20	100.00
V2	mid_op_rst	flash_ctrl_mid_op_rst	2.013m	7.495ms	5	5	100.00
V2	double_bit_err	flash_ctrl_read_word_sweep_derr	44.370s	18.536us	5	5	100.00
		flash_ctrl_ro_derr	3.326m	11.761ms	10	10	100.00
		flash_ctrl_rw_derr	3.857m	5.302ms	10	10	100.00
		flash_ctrl_derr_detect	4.621m	3.282ms	5	5	100.00
		flash_ctrl_integrity	10.055m	16.334ms	5	5	100.00
V2	single_bit_err	flash_ctrl_read_word_sweep_serr	41.900s	44.300us	5	5	100.00
		flash_ctrl_ro_serr	3.031m	2.889ms	10	10	100.00
		flash_ctrl_rw_serr	3.946m	1.786ms	10	10	100.00
V2	singlebit_err_counter	flash_ctrl_serr_counter	1.907m	3.365ms	5	5	100.00
V2	singlebit_err_address	flash_ctrl_serr_address	2.279m	4.484ms	5	5	100.00
V2	scramble	flash_ctrl_wo	4.552m	10.427ms	20	20	100.00
		flash_ctrl_write_word_sweep	27.650s	42.874us	1	1	100.00
		flash_ctrl_read_word_sweep	17.590s	48.526us	1	1	100.00
		flash_ctrl_ro	2.521m	1.131ms	20	20	100.00
		flash_ctrl_rw	9.161m	14.721ms	18	20	90.00
V2	filesystem_support	flash_ctrl_fs_sup	56.350s	1.758ms	5	5	100.00
V2	rma_write_process_error	flash_ctrl_rma_err	16.161m	62.830ms	3	3	100.00
		flash_ctrl_hw_prog_rma_wipe_err	4.492m	10.013ms	20	20	100.00
V2	alert_test	flash_ctrl_alert_test	29.700s	28.645us	50	50	100.00
V2	intr_test	flash_ctrl_intr_test	28.100s	91.210us	50	50	100.00
V2	tl_d_oob_addr_access	flash_ctrl_tl_errors	32.260s	226.201us	20	20	100.00
V2	tl_d_illegal_access	flash_ctrl_tl_errors	32.260s	226.201us	20	20	100.00
V2	tl_d_outstanding_access	flash_ctrl_csr_hw_reset	1.192m	26.120us	5	5	100.00
		flash_ctrl_csr_rw	30.650s	29.756us	20	20	100.00
		flash_ctrl_csr_aliasing	1.302m	25.092ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	50.290s	241.692us	20	20	100.00
V2	tl_d_partial_access	flash_ctrl_csr_hw_reset	1.192m	26.120us	5	5	100.00
		flash_ctrl_csr_rw	30.650s	29.756us	20	20	100.00
		flash_ctrl_csr_aliasing	1.302m	25.092ms	5	5	100.00
		flash_ctrl_same_csr_outstanding	50.290s	241.692us	20	20	100.00
V2		TOTAL			1004	1013	99.11
V2S	shadow_reg_update_error	flash_ctrl_shadow_reg_errors	28.310s	33.482us	20	20	100.00
V2S	shadow_reg_read_clear_staged_value	flash_ctrl_shadow_reg_errors	28.310s	33.482us	20	20	100.00
V2S	shadow_reg_storage_error	flash_ctrl_shadow_reg_errors	28.310s	33.482us	20	20	100.00
V2S	shadowed_reset_glitch	flash_ctrl_shadow_reg_errors	28.310s	33.482us	20	20	100.00
V2S	shadow_reg_update_error_with_csr_rw	flash_ctrl_shadow_reg_errors_with_csr_rw	28.080s	11.297us	20	20	100.00
V2S	tl_intg_err	flash_ctrl_sec_cm	1.908h	1.945ms	5	5	100.00
		flash_ctrl_tl_intg_err	23.147m	763.846us	20	20	100.00
V2S	sec_cm_reg_bus_integrity	flash_ctrl_tl_intg_err	23.147m	763.846us	20	20	100.00
V2S	sec_cm_host_bus_integrity	flash_ctrl_tl_intg_err	23.147m	763.846us	20	20	100.00
V2S	sec_cm_mem_bus_integrity	flash_ctrl_rd_intg	45.470s	68.948us	3	3	100.00
		flash_ctrl_wr_intg	26.390s	48.202us	3	3	100.00
V2S	sec_cm_scramble_key_sideload	flash_ctrl_smoke	4.923m	33.871us	50	50	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	flash_ctrl_otp_reset	3.903m	90.012us	80	80	100.00
		flash_ctrl_disable	44.430s	27.694us	50	50	100.00
		flash_ctrl_sec_info_access	2.102m	14.842ms	50	50	100.00
		flash_ctrl_connect	32.740s	22.640us	80	80	100.00
V2S	sec_cm_ctrl_config_regwen	flash_ctrl_config_regwen	28.330s	56.141us	5	5	100.00
V2S	sec_cm_data_regions_config_regwen	flash_ctrl_csr_rw	30.650s	29.756us	20	20	100.00
V2S	sec_cm_data_regions_config_shadow	flash_ctrl_shadow_reg_errors	28.310s	33.482us	20	20	100.00
V2S	sec_cm_info_regions_config_regwen	flash_ctrl_csr_rw	30.650s	29.756us	20	20	100.00
V2S	sec_cm_info_regions_config_shadow	flash_ctrl_shadow_reg_errors	28.310s	33.482us	20	20	100.00
V2S	sec_cm_bank_config_regwen	flash_ctrl_csr_rw	30.650s	29.756us	20	20	100.00
V2S	sec_cm_bank_config_shadow	flash_ctrl_shadow_reg_errors	28.310s	33.482us	20	20	100.00
V2S	sec_cm_mem_ctrl_global_esc	flash_ctrl_disable	44.430s	27.694us	50	50	100.00
V2S	sec_cm_mem_ctrl_local_esc	flash_ctrl_rd_intg	45.470s	68.948us	3	3	100.00
		flash_ctrl_access_after_disable	26.730s	22.940us	3	3	100.00
V2S	sec_cm_mem_addr_infection	flash_ctrl_host_addr_infection	58.520s	64.321us	3	3	100.00
V2S	sec_cm_mem_disable_config_mubi	flash_ctrl_disable	44.430s	27.694us	50	50	100.00
V2S	sec_cm_exec_config_redun	flash_ctrl_fetch_code	42.150s	1.105ms	10	10	100.00
V2S	sec_cm_mem_scramble	flash_ctrl_rw	9.161m	14.721ms	18	20	90.00
V2S	sec_cm_mem_integrity	flash_ctrl_rw_serr	3.946m	1.786ms	10	10	100.00
		flash_ctrl_rw_derr	3.857m	5.302ms	10	10	100.00
		flash_ctrl_integrity	10.055m	16.334ms	5	5	100.00
V2S	sec_cm_rma_entry_mem_sec_wipe	flash_ctrl_hw_rma	35.089m	543.581ms	3	3	100.00
V2S	sec_cm_ctrl_fsm_sparse	flash_ctrl_sec_cm	1.908h	1.945ms	5	5	100.00
V2S	sec_cm_phy_fsm_sparse	flash_ctrl_sec_cm	1.908h	1.945ms	5	5	100.00
V2S	sec_cm_phy_prog_fsm_sparse	flash_ctrl_sec_cm	1.908h	1.945ms	5	5	100.00
V2S	sec_cm_ctr_redun	flash_ctrl_sec_cm	1.908h	1.945ms	5	5	100.00
V2S	sec_cm_phy_arbiter_ctrl_redun	flash_ctrl_phy_arb_redun	38.090s	886.538us	5	5	100.00
V2S	sec_cm_phy_host_grant_ctrl_consistency	flash_ctrl_phy_host_grant_err	28.970s	15.682us	5	5	100.00
V2S	sec_cm_phy_ack_ctrl_consistency	flash_ctrl_phy_ack_consistency	29.820s	167.172us	4	5	80.00
V2S	sec_cm_fifo_ctr_redun	flash_ctrl_sec_cm	1.908h	1.945ms	5	5	100.00
V2S	sec_cm_mem_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.908h	1.945ms	5	5	100.00
V2S	sec_cm_prog_tl_lc_gate_fsm_sparse	flash_ctrl_sec_cm	1.908h	1.945ms	5	5	100.00
V2S		TOTAL			146	147	99.32
V3	asymmetric_read_path	flash_ctrl_rd_ooo	1.314m	97.676us	1	1	100.00
V3	stress_all_with_rand_reset	flash_ctrl_stress_all_with_rand_reset			0	0	--
V3		TOTAL			1	1	100.00
		TOTAL			1271	1281	99.22

Testplan Progress

Items	Total	Written	Passing	Progress
V1	9	9	9	100.00
V2	55	55	50	90.91
V2S	13	13	12	92.31
V3	2	1	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.20	95.74	94.03	98.31	91.84	98.34	96.89	98.24

Failure Buckets

Job timed out after * minutes has 4 failures:
- Test flash_ctrl_error_prog_type has 2 failures.
  - 0.flash_ctrl_error_prog_type.80601151373947740292965106975151505555109113528736520741398319155752157036346
    Log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
  - 4.flash_ctrl_error_prog_type.72006574359187180848387157282968920760737072601951247363879803724911809981486
    Log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_intr_wr_slow_flash has 1 failures.
  - 6.flash_ctrl_intr_wr_slow_flash.2870968985215153807135800700707358856157498571453918793526993045439112136969
    Log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest/run.log
```
  Job timed out after 60 minutes
```
- Test flash_ctrl_prog_reset has 1 failures.
  - 19.flash_ctrl_prog_reset.4659211897828496686803790696502907127645649728302904957150268123542636431882
    Log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest/run.log
```
  Job timed out after 60 minutes
```

UVM_ERROR (cip_base_scoreboard.sv:242) [scoreboard] Check failed expected_alert[alert_name].expected == * (* [*] vs * [*]) alert fatal_err triggered unexpectedly has 2 failures:

Test flash_ctrl_rw has 2 failures.

4.flash_ctrl_rw.6026215387099664031402063535721791721783004364543977908545355749328172566972
Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 667200.6 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 667200.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

10.flash_ctrl_rw.58192366883475189709781989343787437574714801674273454430003982960038681314749
Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest/run.log

  UVM_ERROR @ 1094058.6 ns: (cip_base_scoreboard.sv:242) [uvm_test_top.env.scoreboard] Check failed expected_alert[alert_name].expected == 1 (0 [0x0] vs 1 [0x1]) alert fatal_err triggered unexpectedly
  UVM_INFO @ 1094058.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: * has 2 failures:
- Test flash_ctrl_rw_evict has 2 failures.
  - 17.flash_ctrl_rw_evict.34271848360852847681722763977757957941690611866412859324292014466437953910286
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 52008.4 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 52008.4 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 29.flash_ctrl_rw_evict.40244170538415451010998047138618567193313442233320815972145703698288546003622
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 149699.6 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.err_code.rd_err reset value: 0x0
  UVM_INFO @ 149699.6 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (*) != exp (*) has 1 failures:
- Test flash_ctrl_phy_ack_consistency has 1 failures.
  - 4.flash_ctrl_phy_ack_consistency.87403016742160131649995991263287678376759754528612578992291786137239279098860
    Line 97, in log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest/run.log
```
  UVM_ERROR @ 30461.2 ns: (cip_tl_seq_item.sv:223) [req] d_user.data_intg act (0x2a) != exp (0x39)
  UVM_INFO @ 30461.2 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: * has 1 failures:
- Test flash_ctrl_rw_evict has 1 failures.
  - 28.flash_ctrl_rw_evict.24901582186406950205727429102827581665641754046488798646380162944362479617879
    Line 95, in log /workspaces/repo/scratch/os_regression_2024_09_08/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest/run.log
```
  UVM_ERROR @ 8705.1 ns: (csr_utils_pkg.sv:466) [csr_utils::csr_rd_check] Check failed obs == exp (0 [0x0] vs 1 [0x1]) Regname: flash_ctrl_core_reg_block.op_status.err reset value: 0x0
  UVM_INFO @ 8705.1 ns: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```