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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.24 93.99 98.31 92.52 97.18 96.99 98.21


Total test records in report: 1266
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T509 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.3957343543 Sep 18 05:16:50 PM UTC 24 Sep 18 05:18:18 PM UTC 24 3143019000 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.3721836133 Sep 18 05:15:13 PM UTC 24 Sep 18 05:18:26 PM UTC 24 67504400 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.1883657616 Sep 18 05:16:10 PM UTC 24 Sep 18 05:18:27 PM UTC 24 33807029700 ps
T321 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2868691134 Sep 18 05:16:10 PM UTC 24 Sep 18 05:18:36 PM UTC 24 37857700 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.1805394919 Sep 18 05:16:06 PM UTC 24 Sep 18 05:18:39 PM UTC 24 36907700 ps
T199 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.1302758009 Sep 18 05:05:31 PM UTC 24 Sep 18 05:18:39 PM UTC 24 40126775200 ps
T191 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.3343800890 Sep 18 05:16:12 PM UTC 24 Sep 18 05:19:15 PM UTC 24 73368800 ps
T513 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.3491937322 Sep 18 05:17:28 PM UTC 24 Sep 18 05:19:19 PM UTC 24 1971241000 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1890334292 Sep 18 05:17:06 PM UTC 24 Sep 18 05:19:25 PM UTC 24 848157500 ps
T317 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.3231188054 Sep 18 05:10:19 PM UTC 24 Sep 18 05:19:26 PM UTC 24 7568611800 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2856790079 Sep 18 04:58:01 PM UTC 24 Sep 18 05:19:35 PM UTC 24 1998750800 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.1407102874 Sep 18 05:19:16 PM UTC 24 Sep 18 05:19:44 PM UTC 24 21212900 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1098028250 Sep 18 05:18:36 PM UTC 24 Sep 18 05:19:53 PM UTC 24 8661915100 ps
T518 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.666586687 Sep 18 05:16:58 PM UTC 24 Sep 18 05:19:55 PM UTC 24 3721713400 ps
T51 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.3668916246 Sep 18 05:19:20 PM UTC 24 Sep 18 05:19:59 PM UTC 24 29515700 ps
T519 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2652436550 Sep 18 05:14:00 PM UTC 24 Sep 18 05:20:01 PM UTC 24 49935325200 ps
T299 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.1052347101 Sep 18 05:01:37 PM UTC 24 Sep 18 05:20:11 PM UTC 24 2431705900 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1032351738 Sep 18 05:19:55 PM UTC 24 Sep 18 05:20:12 PM UTC 24 26208500 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2942919956 Sep 18 05:19:26 PM UTC 24 Sep 18 05:20:15 PM UTC 24 30868200 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.3470860247 Sep 18 05:19:35 PM UTC 24 Sep 18 05:20:16 PM UTC 24 11765900 ps
T521 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.417665065 Sep 18 05:19:27 PM UTC 24 Sep 18 05:20:17 PM UTC 24 193183400 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.1358311697 Sep 18 05:20:00 PM UTC 24 Sep 18 05:20:21 PM UTC 24 27513800 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.2076266689 Sep 18 05:19:54 PM UTC 24 Sep 18 05:20:22 PM UTC 24 53748800 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.363414291 Sep 18 05:12:10 PM UTC 24 Sep 18 05:20:24 PM UTC 24 11901676200 ps
T523 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.96146775 Sep 18 05:18:19 PM UTC 24 Sep 18 05:20:36 PM UTC 24 712766200 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1527773760 Sep 18 05:20:12 PM UTC 24 Sep 18 05:20:39 PM UTC 24 168982300 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.683799947 Sep 18 05:19:44 PM UTC 24 Sep 18 05:21:03 PM UTC 24 706572200 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.843781125 Sep 18 05:18:28 PM UTC 24 Sep 18 05:21:10 PM UTC 24 840105200 ps
T87 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1956808335 Sep 18 05:16:15 PM UTC 24 Sep 18 05:21:10 PM UTC 24 37078639700 ps
T525 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1816365520 Sep 18 05:18:40 PM UTC 24 Sep 18 05:21:13 PM UTC 24 16840249200 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2894823362 Sep 18 05:20:37 PM UTC 24 Sep 18 05:21:17 PM UTC 24 823756100 ps
T147 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2423461685 Sep 18 05:05:47 PM UTC 24 Sep 18 05:21:28 PM UTC 24 10898985800 ps
T106 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2922237592 Sep 18 05:05:03 PM UTC 24 Sep 18 05:21:31 PM UTC 24 68787240500 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.574401405 Sep 18 05:18:14 PM UTC 24 Sep 18 05:21:36 PM UTC 24 5667663000 ps
T220 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2517992461 Sep 18 05:13:06 PM UTC 24 Sep 18 05:21:47 PM UTC 24 3808239400 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.17780076 Sep 18 05:18:40 PM UTC 24 Sep 18 05:21:51 PM UTC 24 52747906100 ps
T529 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.687177499 Sep 18 05:21:11 PM UTC 24 Sep 18 05:22:04 PM UTC 24 5908708600 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.4229786941 Sep 18 05:20:13 PM UTC 24 Sep 18 05:22:17 PM UTC 24 27037500 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.68997931 Sep 18 05:20:18 PM UTC 24 Sep 18 05:22:21 PM UTC 24 17806370700 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2015616690 Sep 18 05:00:56 PM UTC 24 Sep 18 05:22:41 PM UTC 24 231880623300 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3714723645 Sep 18 05:20:17 PM UTC 24 Sep 18 05:22:44 PM UTC 24 703330500 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1598285218 Sep 18 05:09:19 PM UTC 24 Sep 18 05:22:56 PM UTC 24 620078200 ps
T175 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.3779773727 Sep 18 05:10:20 PM UTC 24 Sep 18 05:23:03 PM UTC 24 40126303900 ps
T322 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3524674708 Sep 18 05:21:14 PM UTC 24 Sep 18 05:23:05 PM UTC 24 514024600 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.104467991 Sep 18 05:20:22 PM UTC 24 Sep 18 05:23:05 PM UTC 24 338468600 ps
T300 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2760067718 Sep 18 04:57:21 PM UTC 24 Sep 18 05:23:12 PM UTC 24 421214600 ps
T197 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.2519507262 Sep 18 05:23:06 PM UTC 24 Sep 18 05:23:31 PM UTC 24 10520300 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.349397433 Sep 18 05:22:05 PM UTC 24 Sep 18 05:23:32 PM UTC 24 5244939000 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.2346183303 Sep 18 05:24:48 PM UTC 24 Sep 18 05:26:22 PM UTC 24 2095185300 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1821968849 Sep 18 05:21:29 PM UTC 24 Sep 18 05:23:35 PM UTC 24 2448470800 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3441918302 Sep 18 05:22:44 PM UTC 24 Sep 18 05:23:37 PM UTC 24 57381100 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.3416716091 Sep 18 05:23:13 PM UTC 24 Sep 18 05:23:37 PM UTC 24 49437200 ps
T142 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.1953010723 Sep 18 04:58:14 PM UTC 24 Sep 18 05:26:23 PM UTC 24 337666560200 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3518917519 Sep 18 05:21:37 PM UTC 24 Sep 18 05:23:40 PM UTC 24 1457682400 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3326659876 Sep 18 05:23:32 PM UTC 24 Sep 18 05:23:51 PM UTC 24 15958700 ps
T228 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2906644036 Sep 18 05:23:04 PM UTC 24 Sep 18 05:23:59 PM UTC 24 121875500 ps
T289 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3727830254 Sep 18 05:23:33 PM UTC 24 Sep 18 05:24:01 PM UTC 24 29462800 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.1512173143 Sep 18 05:23:36 PM UTC 24 Sep 18 05:24:02 PM UTC 24 81872000 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.2646405772 Sep 18 05:20:16 PM UTC 24 Sep 18 05:24:04 PM UTC 24 64713100 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.3230340340 Sep 18 05:17:12 PM UTC 24 Sep 18 05:24:41 PM UTC 24 21707657500 ps
T69 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.1186799548 Sep 18 05:24:05 PM UTC 24 Sep 18 05:24:44 PM UTC 24 707089400 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.2945973590 Sep 18 05:21:11 PM UTC 24 Sep 18 05:24:47 PM UTC 24 38509357300 ps
T301 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.1815230574 Sep 18 04:58:24 PM UTC 24 Sep 18 05:24:52 PM UTC 24 1626740600 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.947281793 Sep 18 05:22:18 PM UTC 24 Sep 18 05:24:56 PM UTC 24 26065281000 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.2402859894 Sep 18 05:23:06 PM UTC 24 Sep 18 05:24:59 PM UTC 24 7626867200 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3479993962 Sep 18 05:23:36 PM UTC 24 Sep 18 05:25:02 PM UTC 24 10082765300 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1956025786 Sep 18 05:21:31 PM UTC 24 Sep 18 05:25:36 PM UTC 24 2686333100 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.145824831 Sep 18 05:20:02 PM UTC 24 Sep 18 05:25:42 PM UTC 24 10012007300 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.1794033113 Sep 18 05:21:52 PM UTC 24 Sep 18 05:25:54 PM UTC 24 1838821600 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.2142596170 Sep 18 05:23:52 PM UTC 24 Sep 18 05:26:02 PM UTC 24 2546013700 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.3265403931 Sep 18 05:10:04 PM UTC 24 Sep 18 05:26:10 PM UTC 24 1249897400 ps
T217 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.1385143825 Sep 18 05:21:47 PM UTC 24 Sep 18 05:26:14 PM UTC 24 8489284200 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.3685655025 Sep 18 05:26:24 PM UTC 24 Sep 18 05:26:47 PM UTC 24 30729700 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1981635296 Sep 18 05:22:22 PM UTC 24 Sep 18 05:26:41 PM UTC 24 36759391800 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.1679190520 Sep 18 05:22:42 PM UTC 24 Sep 18 05:26:51 PM UTC 24 35108625400 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.2215359596 Sep 18 05:24:52 PM UTC 24 Sep 18 05:27:01 PM UTC 24 1693856800 ps
T94 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1529042277 Sep 18 05:24:02 PM UTC 24 Sep 18 05:27:02 PM UTC 24 53701500 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.1913822715 Sep 18 05:24:57 PM UTC 24 Sep 18 05:27:16 PM UTC 24 540022200 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.2582883859 Sep 18 05:26:42 PM UTC 24 Sep 18 05:27:19 PM UTC 24 27998500 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.603866786 Sep 18 05:06:03 PM UTC 24 Sep 18 05:27:21 PM UTC 24 763003600 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.2574063365 Sep 18 05:25:04 PM UTC 24 Sep 18 05:27:28 PM UTC 24 627117100 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.4170638837 Sep 18 05:26:10 PM UTC 24 Sep 18 05:27:32 PM UTC 24 4206538200 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.2594632007 Sep 18 05:26:52 PM UTC 24 Sep 18 05:27:33 PM UTC 24 218811800 ps
T198 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.2082408633 Sep 18 05:27:01 PM UTC 24 Sep 18 05:27:38 PM UTC 24 37728900 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2315170081 Sep 18 05:27:20 PM UTC 24 Sep 18 05:27:39 PM UTC 24 15184900 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.3523072953 Sep 18 05:26:47 PM UTC 24 Sep 18 05:27:43 PM UTC 24 40368600 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2313520172 Sep 18 05:23:37 PM UTC 24 Sep 18 05:27:44 PM UTC 24 39693900 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.2790511393 Sep 18 05:27:22 PM UTC 24 Sep 18 05:27:46 PM UTC 24 211629300 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.2993598316 Sep 18 05:27:16 PM UTC 24 Sep 18 05:27:50 PM UTC 24 14861400 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.895911458 Sep 18 05:27:33 PM UTC 24 Sep 18 05:27:58 PM UTC 24 40251700 ps
T95 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.3062684202 Sep 18 04:57:20 PM UTC 24 Sep 18 05:28:05 PM UTC 24 167225161700 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.2224868692 Sep 18 05:16:08 PM UTC 24 Sep 18 05:28:09 PM UTC 24 91181800 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.4049229720 Sep 18 05:25:43 PM UTC 24 Sep 18 05:28:23 PM UTC 24 1085586600 ps
T164 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.4017370266 Sep 18 05:24:03 PM UTC 24 Sep 18 05:28:23 PM UTC 24 38841996100 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2220108217 Sep 18 05:27:03 PM UTC 24 Sep 18 05:28:28 PM UTC 24 2039848300 ps
T318 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.857427478 Sep 18 05:27:59 PM UTC 24 Sep 18 05:28:30 PM UTC 24 112005200 ps
T292 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.737370383 Sep 18 05:27:29 PM UTC 24 Sep 18 05:28:40 PM UTC 24 10081105100 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.329402179 Sep 18 05:25:37 PM UTC 24 Sep 18 05:28:53 PM UTC 24 1693052700 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1470732369 Sep 18 05:27:44 PM UTC 24 Sep 18 05:29:03 PM UTC 24 2923313500 ps
T567 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.680077797 Sep 18 05:21:17 PM UTC 24 Sep 18 05:29:04 PM UTC 24 18551996300 ps
T568 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.2751603244 Sep 18 05:28:24 PM UTC 24 Sep 18 05:29:27 PM UTC 24 3024985300 ps
T569 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.3676110359 Sep 18 05:26:02 PM UTC 24 Sep 18 05:30:05 PM UTC 24 10019788500 ps
T570 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.5778361 Sep 18 05:25:55 PM UTC 24 Sep 18 05:30:23 PM UTC 24 2424305900 ps
T571 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2990055363 Sep 18 05:26:23 PM UTC 24 Sep 18 05:30:47 PM UTC 24 81057066600 ps
T572 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3470570589 Sep 18 05:26:16 PM UTC 24 Sep 18 05:30:54 PM UTC 24 13343290300 ps
T573 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.1284562358 Sep 18 05:28:30 PM UTC 24 Sep 18 05:31:00 PM UTC 24 616144400 ps
T290 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.949505434 Sep 18 05:27:47 PM UTC 24 Sep 18 05:31:00 PM UTC 24 132975500 ps
T574 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.1216206164 Sep 18 05:28:41 PM UTC 24 Sep 18 05:31:10 PM UTC 24 998043200 ps
T328 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.3942816237 Sep 18 05:30:55 PM UTC 24 Sep 18 05:31:22 PM UTC 24 19466200 ps
T186 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.635124604 Sep 18 05:16:11 PM UTC 24 Sep 18 05:31:32 PM UTC 24 80143554500 ps
T575 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3365869035 Sep 18 05:30:06 PM UTC 24 Sep 18 05:31:36 PM UTC 24 3917717700 ps
T576 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.1816653193 Sep 18 05:29:03 PM UTC 24 Sep 18 05:31:40 PM UTC 24 1362885000 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.4164391464 Sep 18 05:31:01 PM UTC 24 Sep 18 05:31:43 PM UTC 24 36533800 ps
T577 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.564604892 Sep 18 05:25:01 PM UTC 24 Sep 18 05:31:43 PM UTC 24 29203044800 ps
T578 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.1690099452 Sep 18 05:31:01 PM UTC 24 Sep 18 05:31:51 PM UTC 24 47514400 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.2457026772 Sep 18 05:31:11 PM UTC 24 Sep 18 05:31:52 PM UTC 24 73480300 ps
T579 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1953676368 Sep 18 05:29:05 PM UTC 24 Sep 18 05:31:55 PM UTC 24 5102500300 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1688261615 Sep 18 05:31:44 PM UTC 24 Sep 18 05:32:01 PM UTC 24 15233800 ps
T46 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1527330518 Sep 18 05:29:27 PM UTC 24 Sep 18 05:32:01 PM UTC 24 2969894700 ps
T131 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.2500982 Sep 18 05:31:23 PM UTC 24 Sep 18 05:32:03 PM UTC 24 28383400 ps
T109 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.2304954528 Sep 18 05:31:37 PM UTC 24 Sep 18 05:32:05 PM UTC 24 24683600 ps
T580 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.849904192 Sep 18 05:31:41 PM UTC 24 Sep 18 05:32:06 PM UTC 24 35693600 ps
T581 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.1659284042 Sep 18 05:31:52 PM UTC 24 Sep 18 05:32:15 PM UTC 24 271870100 ps
T582 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.2819073706 Sep 18 05:28:25 PM UTC 24 Sep 18 05:32:19 PM UTC 24 9104920500 ps
T583 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.3423485191 Sep 18 05:28:54 PM UTC 24 Sep 18 05:32:22 PM UTC 24 2190869000 ps
T584 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2022315601 Sep 18 05:32:16 PM UTC 24 Sep 18 05:33:00 PM UTC 24 650020500 ps
T585 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.3733302908 Sep 18 05:31:32 PM UTC 24 Sep 18 05:33:06 PM UTC 24 1391269000 ps
T323 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.46477780 Sep 18 05:32:01 PM UTC 24 Sep 18 05:33:16 PM UTC 24 2059581100 ps
T586 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.1407121025 Sep 18 05:11:21 PM UTC 24 Sep 18 05:33:28 PM UTC 24 755206900 ps
T200 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.3851089250 Sep 18 05:20:22 PM UTC 24 Sep 18 05:33:37 PM UTC 24 80133116900 ps
T291 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2711765276 Sep 18 05:31:44 PM UTC 24 Sep 18 05:33:38 PM UTC 24 10018815100 ps
T587 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.662467565 Sep 18 05:27:34 PM UTC 24 Sep 18 05:33:42 PM UTC 24 2117898500 ps
T588 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.1205211707 Sep 18 05:32:01 PM UTC 24 Sep 18 05:34:19 PM UTC 24 248891300 ps
T589 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2290555666 Sep 18 05:33:01 PM UTC 24 Sep 18 05:34:25 PM UTC 24 6214753500 ps
T590 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1722668639 Sep 18 05:30:48 PM UTC 24 Sep 18 05:34:28 PM UTC 24 106578813600 ps
T165 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2435703009 Sep 18 05:27:51 PM UTC 24 Sep 18 05:34:47 PM UTC 24 13398752600 ps
T143 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1114044372 Sep 18 05:01:17 PM UTC 24 Sep 18 05:34:54 PM UTC 24 146248579100 ps
T591 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.2552324193 Sep 18 05:31:53 PM UTC 24 Sep 18 05:34:56 PM UTC 24 98969200 ps
T592 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3979097109 Sep 18 05:33:16 PM UTC 24 Sep 18 05:35:04 PM UTC 24 1890636100 ps
T593 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.3129095558 Sep 18 05:34:57 PM UTC 24 Sep 18 05:35:26 PM UTC 24 31167200 ps
T594 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1185012674 Sep 18 05:23:40 PM UTC 24 Sep 18 05:35:26 PM UTC 24 2377885100 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.869087937 Sep 18 05:32:06 PM UTC 24 Sep 18 05:35:49 PM UTC 24 269624100 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.1219086713 Sep 18 05:35:04 PM UTC 24 Sep 18 05:35:50 PM UTC 24 154903500 ps
T595 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3321647193 Sep 18 05:33:38 PM UTC 24 Sep 18 05:36:04 PM UTC 24 12015449700 ps
T596 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.3740713692 Sep 18 05:33:43 PM UTC 24 Sep 18 05:36:04 PM UTC 24 968489200 ps
T597 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2351105803 Sep 18 05:34:28 PM UTC 24 Sep 18 05:36:10 PM UTC 24 7990079500 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3627324092 Sep 18 05:35:28 PM UTC 24 Sep 18 05:36:21 PM UTC 24 249701600 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.303768828 Sep 18 05:30:24 PM UTC 24 Sep 18 05:36:25 PM UTC 24 54123781200 ps
T598 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.637388448 Sep 18 05:36:05 PM UTC 24 Sep 18 05:36:25 PM UTC 24 31298400 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.3691308970 Sep 18 05:35:26 PM UTC 24 Sep 18 05:36:29 PM UTC 24 252545300 ps
T129 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3578454502 Sep 18 05:35:51 PM UTC 24 Sep 18 05:36:29 PM UTC 24 16161600 ps
T288 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.712623784 Sep 18 05:36:11 PM UTC 24 Sep 18 05:36:31 PM UTC 24 48749000 ps
T599 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1050088214 Sep 18 05:33:39 PM UTC 24 Sep 18 05:36:31 PM UTC 24 1814849600 ps
T600 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.758453525 Sep 18 05:36:05 PM UTC 24 Sep 18 05:36:32 PM UTC 24 25181600 ps
T601 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.4107770709 Sep 18 05:33:07 PM UTC 24 Sep 18 05:36:39 PM UTC 24 2275101700 ps
T602 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.4266833286 Sep 18 05:27:40 PM UTC 24 Sep 18 05:36:41 PM UTC 24 81169800 ps
T603 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.238081992 Sep 18 05:36:25 PM UTC 24 Sep 18 05:36:49 PM UTC 24 172110600 ps
T604 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.4192953699 Sep 18 05:28:31 PM UTC 24 Sep 18 05:37:00 PM UTC 24 6486401300 ps
T605 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.2110975553 Sep 18 05:04:23 PM UTC 24 Sep 18 05:37:30 PM UTC 24 249009800 ps
T606 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4092028193 Sep 18 05:36:21 PM UTC 24 Sep 18 05:37:36 PM UTC 24 10023182100 ps
T607 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.3077381085 Sep 18 05:34:20 PM UTC 24 Sep 18 05:37:37 PM UTC 24 1190449600 ps
T148 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1683247958 Sep 18 05:32:07 PM UTC 24 Sep 18 05:37:46 PM UTC 24 28543003100 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.214028084 Sep 18 05:35:51 PM UTC 24 Sep 18 05:37:55 PM UTC 24 15525533100 ps
T149 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.195090649 Sep 18 05:20:24 PM UTC 24 Sep 18 05:37:56 PM UTC 24 58949891700 ps
T608 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.3219956721 Sep 18 05:36:42 PM UTC 24 Sep 18 05:38:04 PM UTC 24 2978857000 ps
T609 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.2597441296 Sep 18 05:37:47 PM UTC 24 Sep 18 05:38:08 PM UTC 24 296572300 ps
T610 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3738143183 Sep 18 05:37:55 PM UTC 24 Sep 18 05:38:35 PM UTC 24 47893300 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.1405488407 Sep 18 05:38:05 PM UTC 24 Sep 18 05:38:43 PM UTC 24 72402500 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3395648202 Sep 18 05:34:26 PM UTC 24 Sep 18 05:38:47 PM UTC 24 3811754700 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.171504950 Sep 18 05:38:08 PM UTC 24 Sep 18 05:38:49 PM UTC 24 12911000 ps
T611 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3434964478 Sep 18 05:37:58 PM UTC 24 Sep 18 05:38:51 PM UTC 24 114382400 ps
T324 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.106871495 Sep 18 05:36:32 PM UTC 24 Sep 18 05:39:03 PM UTC 24 3840347500 ps
T612 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.3822231392 Sep 18 05:38:44 PM UTC 24 Sep 18 05:39:09 PM UTC 24 24733500 ps
T613 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2576158025 Sep 18 05:34:55 PM UTC 24 Sep 18 05:39:10 PM UTC 24 77665933600 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.1676527703 Sep 18 05:38:50 PM UTC 24 Sep 18 05:39:15 PM UTC 24 31016300 ps
T614 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.1074173098 Sep 18 05:37:01 PM UTC 24 Sep 18 05:39:16 PM UTC 24 2319644400 ps
T615 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3288850494 Sep 18 05:38:48 PM UTC 24 Sep 18 05:39:17 PM UTC 24 47285000 ps
T616 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.1218413124 Sep 18 05:36:50 PM UTC 24 Sep 18 05:39:21 PM UTC 24 14911472700 ps
T617 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.447739165 Sep 18 05:36:26 PM UTC 24 Sep 18 05:39:23 PM UTC 24 76339900 ps
T618 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.3813914045 Sep 18 05:39:04 PM UTC 24 Sep 18 05:39:30 PM UTC 24 54869700 ps
T150 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.1732711657 Sep 18 04:58:20 PM UTC 24 Sep 18 05:39:35 PM UTC 24 95249889000 ps
T619 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.2538668662 Sep 18 05:20:39 PM UTC 24 Sep 18 05:39:37 PM UTC 24 1520330800 ps
T620 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2433813314 Sep 18 05:37:38 PM UTC 24 Sep 18 05:39:47 PM UTC 24 38920232000 ps
T621 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.261282807 Sep 18 05:00:19 PM UTC 24 Sep 18 05:40:13 PM UTC 24 4792700700 ps
T622 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.996058282 Sep 18 05:38:35 PM UTC 24 Sep 18 05:40:19 PM UTC 24 2740962300 ps
T623 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2986551250 Sep 18 05:36:33 PM UTC 24 Sep 18 05:40:24 PM UTC 24 43773200 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3013606123 Sep 18 05:37:38 PM UTC 24 Sep 18 05:40:37 PM UTC 24 742984400 ps
T624 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.588419541 Sep 18 05:24:00 PM UTC 24 Sep 18 05:40:49 PM UTC 24 420331160200 ps
T625 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.4196697022 Sep 18 05:40:24 PM UTC 24 Sep 18 05:40:49 PM UTC 24 19870200 ps
T626 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.326602268 Sep 18 05:39:31 PM UTC 24 Sep 18 05:40:57 PM UTC 24 1881419400 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2134732363 Sep 18 05:27:44 PM UTC 24 Sep 18 05:41:16 PM UTC 24 40126720900 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1473158935 Sep 18 05:34:48 PM UTC 24 Sep 18 05:41:25 PM UTC 24 174084234800 ps
T627 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2324431704 Sep 18 05:38:53 PM UTC 24 Sep 18 05:41:35 PM UTC 24 10012532600 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.578786202 Sep 18 05:40:37 PM UTC 24 Sep 18 05:41:35 PM UTC 24 265667100 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2585626278 Sep 18 05:40:58 PM UTC 24 Sep 18 05:41:39 PM UTC 24 16890300 ps
T628 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.3533214524 Sep 18 05:40:50 PM UTC 24 Sep 18 05:41:44 PM UTC 24 110799800 ps
T629 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.683324025 Sep 18 05:39:09 PM UTC 24 Sep 18 05:41:45 PM UTC 24 53965800 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1552359834 Sep 18 05:40:50 PM UTC 24 Sep 18 05:41:47 PM UTC 24 71619200 ps
T630 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.3008181507 Sep 18 05:41:25 PM UTC 24 Sep 18 05:41:54 PM UTC 24 13544700 ps
T631 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2722751105 Sep 18 05:39:45 PM UTC 24 Sep 18 05:41:55 PM UTC 24 2991042900 ps
T632 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3390421439 Sep 18 05:41:36 PM UTC 24 Sep 18 05:41:58 PM UTC 24 15982600 ps
T633 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.2144643560 Sep 18 05:41:36 PM UTC 24 Sep 18 05:42:00 PM UTC 24 15341300 ps
T634 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.3343089245 Sep 18 05:39:16 PM UTC 24 Sep 18 05:42:02 PM UTC 24 26750369700 ps
T188 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3656351486 Sep 18 05:39:22 PM UTC 24 Sep 18 05:42:05 PM UTC 24 42402800 ps
T635 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.3365155704 Sep 18 05:41:45 PM UTC 24 Sep 18 05:42:14 PM UTC 24 45262500 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1190059273 Sep 18 05:40:14 PM UTC 24 Sep 18 05:42:21 PM UTC 24 545201900 ps
T636 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3809499286 Sep 18 05:36:31 PM UTC 24 Sep 18 05:42:50 PM UTC 24 2708969800 ps
T637 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.902370646 Sep 18 05:41:40 PM UTC 24 Sep 18 05:43:06 PM UTC 24 10025980000 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1533861246 Sep 18 05:41:17 PM UTC 24 Sep 18 05:43:16 PM UTC 24 2116349100 ps
T638 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.2127492948 Sep 18 05:36:29 PM UTC 24 Sep 18 05:43:22 PM UTC 24 119511800 ps
T639 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.503894392 Sep 18 05:39:44 PM UTC 24 Sep 18 05:43:30 PM UTC 24 8939483200 ps
T640 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.377221679 Sep 18 05:41:56 PM UTC 24 Sep 18 05:43:35 PM UTC 24 4266793000 ps
T641 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2685179258 Sep 18 05:16:39 PM UTC 24 Sep 18 05:43:44 PM UTC 24 1135807600 ps
T642 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.1295518616 Sep 18 05:43:22 PM UTC 24 Sep 18 05:43:52 PM UTC 24 137482800 ps
T643 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.1482004920 Sep 18 05:42:07 PM UTC 24 Sep 18 05:43:54 PM UTC 24 1640702400 ps
T644 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.4244825132 Sep 18 05:23:38 PM UTC 24 Sep 18 05:44:01 PM UTC 24 160872800 ps
T645 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.1824238701 Sep 18 05:41:46 PM UTC 24 Sep 18 05:44:07 PM UTC 24 37088500 ps
T646 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1727757214 Sep 18 05:43:30 PM UTC 24 Sep 18 05:44:14 PM UTC 24 30988500 ps
T647 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.319623720 Sep 18 05:43:37 PM UTC 24 Sep 18 05:44:17 PM UTC 24 29810500 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.1383642676 Sep 18 05:43:53 PM UTC 24 Sep 18 05:44:32 PM UTC 24 10485700 ps
T151 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3255794624 Sep 18 05:39:24 PM UTC 24 Sep 18 05:44:33 PM UTC 24 39355946200 ps
T648 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.2329943998 Sep 18 05:44:08 PM UTC 24 Sep 18 05:44:35 PM UTC 24 45878300 ps
T649 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.648757472 Sep 18 05:44:02 PM UTC 24 Sep 18 05:44:35 PM UTC 24 28859600 ps
T650 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.751361492 Sep 18 05:40:19 PM UTC 24 Sep 18 05:44:39 PM UTC 24 12302196900 ps
T651 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1178036060 Sep 18 05:44:14 PM UTC 24 Sep 18 05:44:40 PM UTC 24 103640800 ps
T652 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.1831154574 Sep 18 05:42:22 PM UTC 24 Sep 18 05:44:43 PM UTC 24 10418305200 ps
T653 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2402401642 Sep 18 05:43:46 PM UTC 24 Sep 18 05:44:44 PM UTC 24 62762200 ps
T654 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.1517510543 Sep 18 05:37:31 PM UTC 24 Sep 18 05:44:52 PM UTC 24 7130175400 ps
T655 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.2117779737 Sep 18 05:41:55 PM UTC 24 Sep 18 05:44:58 PM UTC 24 99543000 ps
T656 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1854566665 Sep 18 05:44:34 PM UTC 24 Sep 18 05:44:58 PM UTC 24 84840600 ps
T296 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.100967329 Sep 18 04:57:21 PM UTC 24 Sep 18 05:45:00 PM UTC 24 18233500900 ps
T221 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.521686450 Sep 18 04:57:20 PM UTC 24 Sep 18 05:45:03 PM UTC 24 248531338900 ps
T657 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.3427490797 Sep 18 05:39:16 PM UTC 24 Sep 18 05:45:15 PM UTC 24 693480900 ps
T658 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.886155316 Sep 18 05:42:02 PM UTC 24 Sep 18 05:45:19 PM UTC 24 7628406700 ps
T96 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.674717991 Sep 18 05:42:01 PM UTC 24 Sep 18 05:45:30 PM UTC 24 146039300 ps
T659 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.938132730 Sep 18 05:43:54 PM UTC 24 Sep 18 05:45:31 PM UTC 24 568049000 ps
T660 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.1723036139 Sep 18 05:45:21 PM UTC 24 Sep 18 05:45:47 PM UTC 24 118454900 ps
T661 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2253114372 Sep 18 05:43:17 PM UTC 24 Sep 18 05:45:56 PM UTC 24 7949884100 ps
T152 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2429051151 Sep 18 05:36:40 PM UTC 24 Sep 18 05:46:10 PM UTC 24 39894989300 ps
T662 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.2136502824 Sep 18 05:45:31 PM UTC 24 Sep 18 05:46:16 PM UTC 24 28147300 ps
T663 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.1850404128 Sep 18 05:44:53 PM UTC 24 Sep 18 05:46:16 PM UTC 24 3018613900 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3542544421 Sep 18 05:45:32 PM UTC 24 Sep 18 05:46:24 PM UTC 24 78567700 ps
T208 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.3222078378 Sep 18 05:45:57 PM UTC 24 Sep 18 05:46:26 PM UTC 24 26524300 ps
T664 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.2492684917 Sep 18 05:45:47 PM UTC 24 Sep 18 05:46:27 PM UTC 24 66577200 ps
T665 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.1444029490 Sep 18 05:27:39 PM UTC 24 Sep 18 05:46:27 PM UTC 24 5193994000 ps
T666 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.1224572771 Sep 18 05:46:17 PM UTC 24 Sep 18 05:46:40 PM UTC 24 43754400 ps
T667 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3860305796 Sep 18 05:46:25 PM UTC 24 Sep 18 05:46:42 PM UTC 24 25813900 ps
T668 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.292974264 Sep 18 05:39:48 PM UTC 24 Sep 18 05:46:44 PM UTC 24 5478510400 ps
T669 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.2207181647 Sep 18 05:46:17 PM UTC 24 Sep 18 05:46:44 PM UTC 24 15457600 ps
T670 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.641972952 Sep 18 05:46:27 PM UTC 24 Sep 18 05:46:46 PM UTC 24 62208500 ps
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