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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.24 93.99 98.31 92.52 97.18 96.99 98.21


Total test records in report: 1266
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T376 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2183165434 Sep 18 04:39:47 PM UTC 24 Sep 18 04:49:58 PM UTC 24 181601800 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2346797313 Sep 18 04:41:59 PM UTC 24 Sep 18 04:50:15 PM UTC 24 430176200 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3571626834 Sep 18 04:40:52 PM UTC 24 Sep 18 04:50:25 PM UTC 24 372858700 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1789866243 Sep 18 04:39:54 PM UTC 24 Sep 18 04:51:25 PM UTC 24 699492800 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.478026917 Sep 18 04:41:31 PM UTC 24 Sep 18 04:52:01 PM UTC 24 715429500 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3653510941 Sep 18 04:41:45 PM UTC 24 Sep 18 04:52:22 PM UTC 24 695178300 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.531374201 Sep 18 04:41:18 PM UTC 24 Sep 18 04:52:31 PM UTC 24 429159100 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4008260907 Sep 18 04:42:11 PM UTC 24 Sep 18 04:53:05 PM UTC 24 1304524500 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2588836150 Sep 18 04:38:53 PM UTC 24 Sep 18 04:54:01 PM UTC 24 1670405000 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.395035490 Sep 18 04:37:08 PM UTC 24 Sep 18 04:56:41 PM UTC 24 12994645600 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2423490089 Sep 18 04:36:18 PM UTC 24 Sep 18 04:57:16 PM UTC 24 2835766300 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3632730652 Sep 18 04:40:13 PM UTC 24 Sep 18 04:57:48 PM UTC 24 2853225300 ps
T1266 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4282818541 Sep 18 04:41:09 PM UTC 24 Sep 18 04:57:57 PM UTC 24 1388365500 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3289823923 Sep 18 04:38:16 PM UTC 24 Sep 18 04:59:36 PM UTC 24 1333818600 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.174910039 Sep 18 04:40:23 PM UTC 24 Sep 18 05:00:34 PM UTC 24 582167100 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2088289047 Sep 18 04:40:40 PM UTC 24 Sep 18 05:02:53 PM UTC 24 8261479400 ps

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1744163721
Short name T8
Test name
Test status
Simulation time 904298000 ps
CPU time 28.92 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:57:51 PM UTC 24
Peak memory 273164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17
44163721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc
h_code.1744163721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.1918722090
Short name T12
Test name
Test status
Simulation time 876189600 ps
CPU time 29.52 seconds
Started Sep 18 04:57:44 PM UTC 24
Finished Sep 18 04:58:15 PM UTC 24
Peak memory 275528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1918722090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.1918722090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2767182243
Short name T250
Test name
Test status
Simulation time 66830400 ps
CPU time 30.31 seconds
Started Sep 18 04:36:50 PM UTC 24
Finished Sep 18 04:37:22 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2767182243 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.2767182243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.2631326438
Short name T28
Test name
Test status
Simulation time 17863976100 ps
CPU time 229.4 seconds
Started Sep 18 04:58:17 PM UTC 24
Finished Sep 18 05:02:10 PM UTC 24
Peak memory 283332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2631326438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_mp_regions.2631326438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.781465403
Short name T84
Test name
Test status
Simulation time 76332100 ps
CPU time 173.56 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:00:17 PM UTC 24
Peak memory 275308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=781465403 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.781465403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.2017915021
Short name T4
Test name
Test status
Simulation time 45477300 ps
CPU time 19.37 seconds
Started Sep 18 04:57:27 PM UTC 24
Finished Sep 18 04:57:48 PM UTC 24
Peak memory 271436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2017915021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_wr_intg.2017915021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2603499035
Short name T13
Test name
Test status
Simulation time 1988006100 ps
CPU time 6903.67 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 06:53:38 PM UTC 24
Peak memory 314344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2603499035 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.2603499035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.3380858598
Short name T110
Test name
Test status
Simulation time 10019047200 ps
CPU time 169.88 seconds
Started Sep 18 04:57:53 PM UTC 24
Finished Sep 18 05:00:46 PM UTC 24
Peak memory 305916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3380858598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.3380858598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1093405107
Short name T135
Test name
Test status
Simulation time 83580000 ps
CPU time 33.48 seconds
Started Sep 18 04:36:26 PM UTC 24
Finished Sep 18 04:37:01 PM UTC 24
Peak memory 286824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1093405107 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1093405107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.1263482587
Short name T33
Test name
Test status
Simulation time 3754550300 ps
CPU time 86.52 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:58:49 PM UTC 24
Peak memory 272984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263482587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.1263482587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.699888762
Short name T104
Test name
Test status
Simulation time 2031541900 ps
CPU time 99.95 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:59:03 PM UTC 24
Peak memory 291776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=699888762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_
ctrl_ro_serr.699888762
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.2108579531
Short name T126
Test name
Test status
Simulation time 2478806200 ps
CPU time 66.23 seconds
Started Sep 18 04:58:11 PM UTC 24
Finished Sep 18 04:59:19 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108579531 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.2108579531
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.585204661
Short name T34
Test name
Test status
Simulation time 2130424200 ps
CPU time 504.07 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:05:51 PM UTC 24
Peak memory 277932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585204661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.585204661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.2003446700
Short name T90
Test name
Test status
Simulation time 742482100 ps
CPU time 248.65 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 05:01:35 PM UTC 24
Peak memory 287756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2003446700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 0.flash_ctrl_derr_detect.2003446700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1831323808
Short name T268
Test name
Test status
Simulation time 338921000 ps
CPU time 48.7 seconds
Started Sep 18 04:37:35 PM UTC 24
Finished Sep 18 04:38:25 PM UTC 24
Peak memory 274468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1831323808 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.1831323808
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1999852505
Short name T25
Test name
Test status
Simulation time 106301200 ps
CPU time 44.88 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:58:10 PM UTC 24
Peak memory 287872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999852505 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.1999852505
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.3062684202
Short name T95
Test name
Test status
Simulation time 167225161700 ps
CPU time 1824.65 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:28:05 PM UTC 24
Peak memory 277828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062684202
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.3062684202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.2529458722
Short name T194
Test name
Test status
Simulation time 139546600 ps
CPU time 166.97 seconds
Started Sep 18 06:05:18 PM UTC 24
Finished Sep 18 06:08:08 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529458722 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.2529458722
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.449959285
Short name T266
Test name
Test status
Simulation time 31473100 ps
CPU time 24.66 seconds
Started Sep 18 04:36:19 PM UTC 24
Finished Sep 18 04:36:45 PM UTC 24
Peak memory 274244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449959285 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.449959285
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.659190939
Short name T375
Test name
Test status
Simulation time 1402102600 ps
CPU time 563.22 seconds
Started Sep 18 04:39:24 PM UTC 24
Finished Sep 18 04:48:54 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659190939 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.659190939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.1391671461
Short name T53
Test name
Test status
Simulation time 25643900 ps
CPU time 23.1 seconds
Started Sep 18 04:57:51 PM UTC 24
Finished Sep 18 04:58:16 PM UTC 24
Peak memory 275548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1391671461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_lcmgr_intg.1391671461
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.462035438
Short name T45
Test name
Test status
Simulation time 1738305500 ps
CPU time 216.96 seconds
Started Sep 18 04:59:36 PM UTC 24
Finished Sep 18 05:03:17 PM UTC 24
Peak memory 302024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462035438 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.462035438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1172362840
Short name T138
Test name
Test status
Simulation time 260191600 ps
CPU time 34.82 seconds
Started Sep 18 04:36:36 PM UTC 24
Finished Sep 18 04:37:13 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172362840 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.1172362840
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2035449062
Short name T54
Test name
Test status
Simulation time 1032102800 ps
CPU time 143.41 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:59:49 PM UTC 24
Peak memory 291760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2035449062 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_oversize_error.2035449062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.214028084
Short name T408
Test name
Test status
Simulation time 15525533100 ps
CPU time 121.15 seconds
Started Sep 18 05:35:51 PM UTC 24
Finished Sep 18 05:37:55 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214028084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.214028084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.1570413762
Short name T105
Test name
Test status
Simulation time 167187055600 ps
CPU time 869.79 seconds
Started Sep 18 04:57:51 PM UTC 24
Finished Sep 18 05:12:31 PM UTC 24
Peak memory 272980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=1570413762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.
flash_ctrl_rma_err.1570413762
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.674717991
Short name T96
Test name
Test status
Simulation time 146039300 ps
CPU time 205.51 seconds
Started Sep 18 05:42:01 PM UTC 24
Finished Sep 18 05:45:30 PM UTC 24
Peak memory 271456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674717991 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.674717991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.3374806323
Short name T120
Test name
Test status
Simulation time 73817700 ps
CPU time 24.61 seconds
Started Sep 18 04:57:55 PM UTC 24
Finished Sep 18 04:58:21 PM UTC 24
Peak memory 275324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374806323 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.3374806323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2953173677
Short name T302
Test name
Test status
Simulation time 1579464800 ps
CPU time 90.15 seconds
Started Sep 18 04:37:39 PM UTC 24
Finished Sep 18 04:39:11 PM UTC 24
Peak memory 274272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953173677 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.2953173677
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.887446161
Short name T64
Test name
Test status
Simulation time 2212599200 ps
CPU time 95.21 seconds
Started Sep 18 05:01:46 PM UTC 24
Finished Sep 18 05:03:23 PM UTC 24
Peak memory 272988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887446161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.887446161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1738784316
Short name T1110
Test name
Test status
Simulation time 136539300 ps
CPU time 178.99 seconds
Started Sep 18 06:13:18 PM UTC 24
Finished Sep 18 06:16:20 PM UTC 24
Peak memory 271272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1738784316 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.1738784316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.1137151106
Short name T59
Test name
Test status
Simulation time 1069089800 ps
CPU time 116.31 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:59:21 PM UTC 24
Peak memory 291752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137151106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.1137151106
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.2959607328
Short name T196
Test name
Test status
Simulation time 242334793900 ps
CPU time 3366.96 seconds
Started Sep 18 05:10:49 PM UTC 24
Finished Sep 18 06:07:32 PM UTC 24
Peak memory 275280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959607328 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.2959607328
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.4219345601
Short name T32
Test name
Test status
Simulation time 3441043600 ps
CPU time 79.6 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:58:42 PM UTC 24
Peak memory 272964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4219345601 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.4219345601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.898017281
Short name T441
Test name
Test status
Simulation time 362329500 ps
CPU time 46.78 seconds
Started Sep 18 05:09:24 PM UTC 24
Finished Sep 18 05:10:12 PM UTC 24
Peak memory 275300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=8980172
81 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fs
_sup.898017281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3800215096
Short name T244
Test name
Test status
Simulation time 628791300 ps
CPU time 32.27 seconds
Started Sep 18 04:38:49 PM UTC 24
Finished Sep 18 04:39:23 PM UTC 24
Peak memory 286620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3800215096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.3800215096
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.714609654
Short name T174
Test name
Test status
Simulation time 595207400 ps
CPU time 199.99 seconds
Started Sep 18 05:08:19 PM UTC 24
Finished Sep 18 05:11:42 PM UTC 24
Peak memory 302024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714609654 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.714609654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2423461685
Short name T147
Test name
Test status
Simulation time 10898985800 ps
CPU time 929.34 seconds
Started Sep 18 05:05:47 PM UTC 24
Finished Sep 18 05:21:28 PM UTC 24
Peak memory 283428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2423461685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_mp_regions.2423461685
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.615953232
Short name T350
Test name
Test status
Simulation time 25819700 ps
CPU time 24.02 seconds
Started Sep 18 04:39:23 PM UTC 24
Finished Sep 18 04:39:49 PM UTC 24
Peak memory 274092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615953232 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.615953232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.2949486032
Short name T6
Test name
Test status
Simulation time 13000100 ps
CPU time 27.69 seconds
Started Sep 18 04:57:38 PM UTC 24
Finished Sep 18 04:58:07 PM UTC 24
Peak memory 273280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2949486032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.2949486032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.230173543
Short name T440
Test name
Test status
Simulation time 72147600 ps
CPU time 63.97 seconds
Started Sep 18 05:09:04 PM UTC 24
Finished Sep 18 05:10:10 PM UTC 24
Peak memory 287900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230173543 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.230173543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1891352283
Short name T246
Test name
Test status
Simulation time 35852700 ps
CPU time 25.57 seconds
Started Sep 18 04:36:49 PM UTC 24
Finished Sep 18 04:37:16 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1891352283 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.1891352283
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.1413046204
Short name T140
Test name
Test status
Simulation time 10012047100 ps
CPU time 137.79 seconds
Started Sep 18 05:01:01 PM UTC 24
Finished Sep 18 05:03:21 PM UTC 24
Peak memory 394336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1413046204 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.1413046204
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.501931155
Short name T365
Test name
Test status
Simulation time 22176721200 ps
CPU time 245.9 seconds
Started Sep 18 05:08:21 PM UTC 24
Finished Sep 18 05:12:30 PM UTC 24
Peak memory 302060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=501931155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 3.flash_ctrl_intr_rd_slow_flash.501931155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4193541466
Short name T1226
Test name
Test status
Simulation time 52614300 ps
CPU time 24.46 seconds
Started Sep 18 04:42:09 PM UTC 24
Finished Sep 18 04:42:35 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193541466 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.4193541466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.3632730652
Short name T385
Test name
Test status
Simulation time 2853225300 ps
CPU time 1043.31 seconds
Started Sep 18 04:40:13 PM UTC 24
Finished Sep 18 04:57:48 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632730652 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.3632730652
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.1140163956
Short name T232
Test name
Test status
Simulation time 171482300 ps
CPU time 174.07 seconds
Started Sep 18 04:58:08 PM UTC 24
Finished Sep 18 05:01:05 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140163956 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.1140163956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.1804162642
Short name T224
Test name
Test status
Simulation time 45728600 ps
CPU time 25.91 seconds
Started Sep 18 05:15:38 PM UTC 24
Finished Sep 18 05:16:06 PM UTC 24
Peak memory 275532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1804162642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.1804162642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.1886281140
Short name T903
Test name
Test status
Simulation time 14116100 ps
CPU time 37.36 seconds
Started Sep 18 06:06:46 PM UTC 24
Finished Sep 18 06:07:25 PM UTC 24
Peak memory 285712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1886281140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_
ctrl_disable.1886281140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.1359176657
Short name T125
Test name
Test status
Simulation time 1346509100 ps
CPU time 148.63 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:59:54 PM UTC 24
Peak memory 302064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1359176657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.1359176657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.2944157395
Short name T61
Test name
Test status
Simulation time 22609800 ps
CPU time 22.35 seconds
Started Sep 18 04:57:51 PM UTC 24
Finished Sep 18 04:58:15 PM UTC 24
Peak memory 293248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944157395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.2944157395
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.3727830254
Short name T289
Test name
Test status
Simulation time 29462800 ps
CPU time 26.3 seconds
Started Sep 18 05:23:33 PM UTC 24
Finished Sep 18 05:24:01 PM UTC 24
Peak memory 275176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3727830254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_hw_read_seed_err.3727830254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.3653510941
Short name T377
Test name
Test status
Simulation time 695178300 ps
CPU time 629.65 seconds
Started Sep 18 04:41:45 PM UTC 24
Finished Sep 18 04:52:22 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653510941 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.3653510941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.4240398509
Short name T970
Test name
Test status
Simulation time 41570760900 ps
CPU time 278.6 seconds
Started Sep 18 06:05:41 PM UTC 24
Finished Sep 18 06:10:24 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4240398509 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.4240398509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.1950184425
Short name T231
Test name
Test status
Simulation time 3898796400 ps
CPU time 428.1 seconds
Started Sep 18 05:01:50 PM UTC 24
Finished Sep 18 05:09:04 PM UTC 24
Peak memory 324684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950184425 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.1950184425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.3668916246
Short name T51
Test name
Test status
Simulation time 29515700 ps
CPU time 37.65 seconds
Started Sep 18 05:19:20 PM UTC 24
Finished Sep 18 05:19:59 PM UTC 24
Peak memory 287668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668916246 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.3668916246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.773892498
Short name T17
Test name
Test status
Simulation time 17248700 ps
CPU time 26.67 seconds
Started Sep 18 04:57:27 PM UTC 24
Finished Sep 18 04:57:55 PM UTC 24
Peak memory 284940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773892498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.773892498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.1769057929
Short name T44
Test name
Test status
Simulation time 5614760100 ps
CPU time 82.01 seconds
Started Sep 18 05:00:17 PM UTC 24
Finished Sep 18 05:01:41 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769057929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.1769057929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.1408244546
Short name T446
Test name
Test status
Simulation time 49509100 ps
CPU time 52.75 seconds
Started Sep 18 05:58:28 PM UTC 24
Finished Sep 18 05:59:22 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408244546 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.1408244546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3288850494
Short name T615
Test name
Test status
Simulation time 47285000 ps
CPU time 28.25 seconds
Started Sep 18 05:38:48 PM UTC 24
Finished Sep 18 05:39:17 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3288850494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_lcmgr_intg.3288850494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.2088289047
Short name T382
Test name
Test status
Simulation time 8261479400 ps
CPU time 1318.28 seconds
Started Sep 18 04:40:40 PM UTC 24
Finished Sep 18 05:02:53 PM UTC 24
Peak memory 278508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088289047 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.2088289047
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.290374973
Short name T393
Test name
Test status
Simulation time 363655900 ps
CPU time 25.2 seconds
Started Sep 18 04:41:03 PM UTC 24
Finished Sep 18 04:41:31 PM UTC 24
Peak memory 286632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=290374973 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.290374973
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3390421439
Short name T632
Test name
Test status
Simulation time 15982600 ps
CPU time 21.47 seconds
Started Sep 18 05:41:36 PM UTC 24
Finished Sep 18 05:41:58 PM UTC 24
Peak memory 269252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3390421439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
11.flash_ctrl_hw_read_seed_err.3390421439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.4038616867
Short name T293
Test name
Test status
Simulation time 10029550900 ps
CPU time 60.13 seconds
Started Sep 18 05:55:02 PM UTC 24
Finished Sep 18 05:56:05 PM UTC 24
Peak memory 277464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4038616867 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.4038616867
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.3929946759
Short name T113
Test name
Test status
Simulation time 288248600 ps
CPU time 2961.8 seconds
Started Sep 18 04:58:22 PM UTC 24
Finished Sep 18 05:48:15 PM UTC 24
Peak memory 277940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39
29946759 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl
_error_prog_type.3929946759
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.2679221789
Short name T22
Test name
Test status
Simulation time 1090800100 ps
CPU time 44.03 seconds
Started Sep 18 04:57:27 PM UTC 24
Finished Sep 18 04:58:13 PM UTC 24
Peak memory 287552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267922178
9 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.2679221789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.2760067718
Short name T300
Test name
Test status
Simulation time 421214600 ps
CPU time 1533.22 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 05:23:12 PM UTC 24
Peak memory 288180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760067718 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.2760067718
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.4164391464
Short name T454
Test name
Test status
Simulation time 36533800 ps
CPU time 39.95 seconds
Started Sep 18 05:31:01 PM UTC 24
Finished Sep 18 05:31:43 PM UTC 24
Peak memory 287684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4164391464 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_rw_evict_all_en.4164391464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1594680349
Short name T279
Test name
Test status
Simulation time 41309700 ps
CPU time 20.06 seconds
Started Sep 18 04:40:22 PM UTC 24
Finished Sep 18 04:40:44 PM UTC 24
Peak memory 276468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594680349 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.1594680349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.2980950265
Short name T689
Test name
Test status
Simulation time 10633400 ps
CPU time 45.06 seconds
Started Sep 18 05:48:16 PM UTC 24
Finished Sep 18 05:49:02 PM UTC 24
Peak memory 285676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2980950265 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_
ctrl_disable.2980950265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.3779773727
Short name T175
Test name
Test status
Simulation time 40126303900 ps
CPU time 754.04 seconds
Started Sep 18 05:10:20 PM UTC 24
Finished Sep 18 05:23:03 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779773727
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.3779773727
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.2588836150
Short name T380
Test name
Test status
Simulation time 1670405000 ps
CPU time 897.5 seconds
Started Sep 18 04:38:53 PM UTC 24
Finished Sep 18 04:54:01 PM UTC 24
Peak memory 276392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2588836150 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.2588836150
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.3948285917
Short name T154
Test name
Test status
Simulation time 3042805600 ps
CPU time 167.92 seconds
Started Sep 18 04:59:22 PM UTC 24
Finished Sep 18 05:02:13 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3948285917 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_oversize_error.3948285917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.1244109272
Short name T179
Test name
Test status
Simulation time 4408465500 ps
CPU time 113.85 seconds
Started Sep 18 05:04:21 PM UTC 24
Finished Sep 18 05:06:17 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244109272 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.1244109272
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.2220108217
Short name T403
Test name
Test status
Simulation time 2039848300 ps
CPU time 83.21 seconds
Started Sep 18 05:27:03 PM UTC 24
Finished Sep 18 05:28:28 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220108217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.2220108217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1380072259
Short name T52
Test name
Test status
Simulation time 1545409300 ps
CPU time 31.8 seconds
Started Sep 18 04:58:19 PM UTC 24
Finished Sep 18 04:58:52 PM UTC 24
Peak memory 273232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13
80072259 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetc
h_code.1380072259
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2786365864
Short name T73
Test name
Test status
Simulation time 37436100 ps
CPU time 26.71 seconds
Started Sep 18 04:36:21 PM UTC 24
Finished Sep 18 04:36:49 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786365864 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.2786365864
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.2477797694
Short name T201
Test name
Test status
Simulation time 911235800 ps
CPU time 245.5 seconds
Started Sep 18 04:59:20 PM UTC 24
Finished Sep 18 05:03:29 PM UTC 24
Peak memory 289780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2477797694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.flash_ctrl_derr_detect.2477797694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.3678331051
Short name T117
Test name
Test status
Simulation time 48598460900 ps
CPU time 290.37 seconds
Started Sep 18 06:03:22 PM UTC 24
Finished Sep 18 06:08:16 PM UTC 24
Peak memory 303900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3678331051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.flash_ctrl_intr_rd_slow_flash.3678331051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.1101578229
Short name T101
Test name
Test status
Simulation time 755088300 ps
CPU time 37.78 seconds
Started Sep 18 05:04:38 PM UTC 24
Finished Sep 18 05:05:17 PM UTC 24
Peak memory 275532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1101578229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.1101578229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.1370899406
Short name T187
Test name
Test status
Simulation time 40123871600 ps
CPU time 786.32 seconds
Started Sep 18 05:36:32 PM UTC 24
Finished Sep 18 05:49:48 PM UTC 24
Peak memory 275236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370899406
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_res
et.1370899406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.17694469
Short name T280
Test name
Test status
Simulation time 154518500 ps
CPU time 31.49 seconds
Started Sep 18 04:40:12 PM UTC 24
Finished Sep 18 04:40:45 PM UTC 24
Peak memory 276404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17694469 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.17694469
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.2348108026
Short name T99
Test name
Test status
Simulation time 637016700 ps
CPU time 32.67 seconds
Started Sep 18 05:00:46 PM UTC 24
Finished Sep 18 05:01:20 PM UTC 24
Peak memory 275628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2348108026 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.2348108026
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.1231480408
Short name T102
Test name
Test status
Simulation time 685976900 ps
CPU time 25.03 seconds
Started Sep 18 05:09:33 PM UTC 24
Finished Sep 18 05:09:59 PM UTC 24
Peak memory 275748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1231480408 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.1231480408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.375992580
Short name T169
Test name
Test status
Simulation time 3366049100 ps
CPU time 208.22 seconds
Started Sep 18 05:07:33 PM UTC 24
Finished Sep 18 05:11:05 PM UTC 24
Peak memory 298268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=375992580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 3.flash_ctrl_rw_derr.375992580
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.674051694
Short name T177
Test name
Test status
Simulation time 15492100 ps
CPU time 16.62 seconds
Started Sep 18 05:00:58 PM UTC 24
Finished Sep 18 05:01:16 PM UTC 24
Peak memory 275268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=674051694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_lcmgr_intg.674051694
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2753161349
Short name T263
Test name
Test status
Simulation time 445456000 ps
CPU time 627.67 seconds
Started Sep 18 04:36:37 PM UTC 24
Finished Sep 18 04:47:13 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753161349 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.2753161349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2805021425
Short name T1175
Test name
Test status
Simulation time 14921200 ps
CPU time 22.6 seconds
Started Sep 18 04:40:19 PM UTC 24
Finished Sep 18 04:40:43 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2805021425 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.2805021425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.2177241631
Short name T20
Test name
Test status
Simulation time 30592100 ps
CPU time 25.93 seconds
Started Sep 18 04:57:51 PM UTC 24
Finished Sep 18 04:58:18 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2177241631 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.2177241631
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.886219588
Short name T153
Test name
Test status
Simulation time 49892366200 ps
CPU time 3353.8 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 05:53:51 PM UTC 24
Peak memory 277884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886219588 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.886219588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.3092292618
Short name T79
Test name
Test status
Simulation time 33780353200 ps
CPU time 900.77 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 05:12:32 PM UTC 24
Peak memory 286112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3092292618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_mp_regions.3092292618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.204769329
Short name T31
Test name
Test status
Simulation time 71142000 ps
CPU time 42.7 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:58:07 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204769329 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.204769329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.2585626278
Short name T428
Test name
Test status
Simulation time 16890300 ps
CPU time 39.37 seconds
Started Sep 18 05:40:58 PM UTC 24
Finished Sep 18 05:41:39 PM UTC 24
Peak memory 285648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2585626278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_
ctrl_disable.2585626278
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.2432285774
Short name T740
Test name
Test status
Simulation time 70141276500 ps
CPU time 778.9 seconds
Started Sep 18 05:41:59 PM UTC 24
Finished Sep 18 05:55:07 PM UTC 24
Peak memory 275236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432285774
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_res
et.2432285774
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.2180070168
Short name T420
Test name
Test status
Simulation time 40118536400 ps
CPU time 704.14 seconds
Started Sep 18 05:44:41 PM UTC 24
Finished Sep 18 05:56:34 PM UTC 24
Peak memory 275240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2180070168
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_res
et.2180070168
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.3378324052
Short name T449
Test name
Test status
Simulation time 22990438900 ps
CPU time 551.37 seconds
Started Sep 18 05:49:08 PM UTC 24
Finished Sep 18 05:58:27 PM UTC 24
Peak memory 320504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378324052 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.3378324052
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.4235633932
Short name T395
Test name
Test status
Simulation time 15984800 ps
CPU time 38.02 seconds
Started Sep 18 06:01:30 PM UTC 24
Finished Sep 18 06:02:09 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4235633932 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_
ctrl_disable.4235633932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.2825939710
Short name T394
Test name
Test status
Simulation time 10936000 ps
CPU time 43.19 seconds
Started Sep 18 06:02:34 PM UTC 24
Finished Sep 18 06:03:19 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2825939710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_
ctrl_disable.2825939710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.1122402547
Short name T432
Test name
Test status
Simulation time 813407000 ps
CPU time 55.24 seconds
Started Sep 18 06:06:17 PM UTC 24
Finished Sep 18 06:07:14 PM UTC 24
Peak memory 275216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122402547 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.1122402547
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.3620781786
Short name T399
Test name
Test status
Simulation time 10662100 ps
CPU time 33.64 seconds
Started Sep 18 06:10:02 PM UTC 24
Finished Sep 18 06:10:37 PM UTC 24
Peak memory 285672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3620781786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_
ctrl_disable.3620781786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.1911381444
Short name T407
Test name
Test status
Simulation time 4359653600 ps
CPU time 102.33 seconds
Started Sep 18 06:10:27 PM UTC 24
Finished Sep 18 06:12:12 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911381444 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.1911381444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.963233541
Short name T429
Test name
Test status
Simulation time 5017672000 ps
CPU time 99.87 seconds
Started Sep 18 06:11:45 PM UTC 24
Finished Sep 18 06:13:27 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=963233541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.963233541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.1663405587
Short name T37
Test name
Test status
Simulation time 5086807000 ps
CPU time 99.78 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:59:05 PM UTC 24
Peak memory 273204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663405587 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.1663405587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.541308293
Short name T19
Test name
Test status
Simulation time 15955800 ps
CPU time 23.27 seconds
Started Sep 18 05:00:50 PM UTC 24
Finished Sep 18 05:01:14 PM UTC 24
Peak memory 271080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541308293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.541308293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.1385143825
Short name T217
Test name
Test status
Simulation time 8489284200 ps
CPU time 262.86 seconds
Started Sep 18 05:21:47 PM UTC 24
Finished Sep 18 05:26:14 PM UTC 24
Peak memory 298012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1385143825 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 6.flash_ctrl_rw_derr.1385143825
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.100967329
Short name T296
Test name
Test status
Simulation time 18233500900 ps
CPU time 2830.87 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 05:45:00 PM UTC 24
Peak memory 275808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100967329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.100967329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.521686450
Short name T221
Test name
Test status
Simulation time 248531338900 ps
CPU time 2833.05 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:45:03 PM UTC 24
Peak memory 278064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521686450 -assert nop
ostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /work
spaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.521686450
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.1171881714
Short name T254
Test name
Test status
Simulation time 3698095000 ps
CPU time 515.68 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 05:06:03 PM UTC 24
Peak memory 320524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171881714 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.1171881714
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.3455718224
Short name T236
Test name
Test status
Simulation time 42875200 ps
CPU time 27.29 seconds
Started Sep 18 05:00:48 PM UTC 24
Finished Sep 18 05:01:16 PM UTC 24
Peak memory 273508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=3455718224 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.3455718224
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.2227888279
Short name T15
Test name
Test status
Simulation time 978129800 ps
CPU time 6905.37 seconds
Started Sep 18 05:00:15 PM UTC 24
Finished Sep 18 06:56:32 PM UTC 24
Peak memory 314196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227888279 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.2227888279
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.3810829143
Short name T21
Test name
Test status
Simulation time 14281900 ps
CPU time 28.87 seconds
Started Sep 18 05:04:32 PM UTC 24
Finished Sep 18 05:05:03 PM UTC 24
Peak memory 273284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3810829143 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3810829143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3163980887
Short name T14
Test name
Test status
Simulation time 1637110300 ps
CPU time 6500.67 seconds
Started Sep 18 05:04:13 PM UTC 24
Finished Sep 18 06:53:39 PM UTC 24
Peak memory 310120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163980887 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.3163980887
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.3208676928
Short name T222
Test name
Test status
Simulation time 277917377200 ps
CPU time 3549.83 seconds
Started Sep 18 05:05:43 PM UTC 24
Finished Sep 18 06:05:32 PM UTC 24
Peak memory 276240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208676928 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.3208676928
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.2517992461
Short name T220
Test name
Test status
Simulation time 3808239400 ps
CPU time 513.57 seconds
Started Sep 18 05:13:06 PM UTC 24
Finished Sep 18 05:21:47 PM UTC 24
Peak memory 330752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2517992461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integr
ity.2517992461
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3851371001
Short name T270
Test name
Test status
Simulation time 1337690600 ps
CPU time 50.4 seconds
Started Sep 18 04:36:24 PM UTC 24
Finished Sep 18 04:37:16 PM UTC 24
Peak memory 274468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851371001 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.3851371001
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2258727223
Short name T75
Test name
Test status
Simulation time 1291152600 ps
CPU time 38.03 seconds
Started Sep 18 04:36:21 PM UTC 24
Finished Sep 18 04:37:00 PM UTC 24
Peak memory 276516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258727223 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.2258727223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4003270127
Short name T267
Test name
Test status
Simulation time 37381800 ps
CPU time 39.08 seconds
Started Sep 18 04:36:21 PM UTC 24
Finished Sep 18 04:37:01 PM UTC 24
Peak memory 276580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003270127 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.4003270127
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1749698136
Short name T245
Test name
Test status
Simulation time 26222700 ps
CPU time 16.23 seconds
Started Sep 18 04:36:20 PM UTC 24
Finished Sep 18 04:36:37 PM UTC 24
Peak memory 276656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1749698136 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.1749698136
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1965556248
Short name T1136
Test name
Test status
Simulation time 54954500 ps
CPU time 21.31 seconds
Started Sep 18 04:36:19 PM UTC 24
Finished Sep 18 04:36:42 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965556248 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.1965556248
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4208692987
Short name T74
Test name
Test status
Simulation time 90664800 ps
CPU time 33.31 seconds
Started Sep 18 04:36:25 PM UTC 24
Finished Sep 18 04:37:00 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4208692987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
same_csr_outstanding.4208692987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3436977323
Short name T1135
Test name
Test status
Simulation time 12845600 ps
CPU time 19.8 seconds
Started Sep 18 04:36:18 PM UTC 24
Finished Sep 18 04:36:39 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=343
6977323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sha
dow_reg_errors.3436977323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1473609385
Short name T1137
Test name
Test status
Simulation time 128588000 ps
CPU time 29.05 seconds
Started Sep 18 04:36:18 PM UTC 24
Finished Sep 18 04:36:49 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1473609385 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1473609385
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3504514495
Short name T134
Test name
Test status
Simulation time 68151400 ps
CPU time 27.43 seconds
Started Sep 18 04:36:18 PM UTC 24
Finished Sep 18 04:36:47 PM UTC 24
Peak memory 276592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504514495 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3504514495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.2423490089
Short name T383
Test name
Test status
Simulation time 2835766300 ps
CPU time 1243.85 seconds
Started Sep 18 04:36:18 PM UTC 24
Finished Sep 18 04:57:16 PM UTC 24
Peak memory 278768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2423490089 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.2423490089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.243570265
Short name T313
Test name
Test status
Simulation time 640171600 ps
CPU time 44.39 seconds
Started Sep 18 04:37:02 PM UTC 24
Finished Sep 18 04:37:48 PM UTC 24
Peak memory 274340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243570265 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.243570265
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3291419109
Short name T271
Test name
Test status
Simulation time 1236732800 ps
CPU time 78.6 seconds
Started Sep 18 04:37:00 PM UTC 24
Finished Sep 18 04:38:21 PM UTC 24
Peak memory 276324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291419109 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.3291419109
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2031613836
Short name T269
Test name
Test status
Simulation time 124904400 ps
CPU time 55.94 seconds
Started Sep 18 04:36:49 PM UTC 24
Finished Sep 18 04:37:47 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031613836 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.2031613836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.369229044
Short name T136
Test name
Test status
Simulation time 46025800 ps
CPU time 20.27 seconds
Started Sep 18 04:37:03 PM UTC 24
Finished Sep 18 04:37:24 PM UTC 24
Peak memory 286632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=369229044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.369229044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3514828216
Short name T274
Test name
Test status
Simulation time 209715400 ps
CPU time 20.85 seconds
Started Sep 18 04:36:48 PM UTC 24
Finished Sep 18 04:37:10 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514828216 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.3514828216
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.740633049
Short name T1140
Test name
Test status
Simulation time 19934100 ps
CPU time 26.23 seconds
Started Sep 18 04:36:48 PM UTC 24
Finished Sep 18 04:37:16 PM UTC 24
Peak memory 274272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=740633049 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.740633049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2248422668
Short name T251
Test name
Test status
Simulation time 70955200 ps
CPU time 30.09 seconds
Started Sep 18 04:37:02 PM UTC 24
Finished Sep 18 04:37:33 PM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2248422668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
same_csr_outstanding.2248422668
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.105729948
Short name T1139
Test name
Test status
Simulation time 127871500 ps
CPU time 25.2 seconds
Started Sep 18 04:36:40 PM UTC 24
Finished Sep 18 04:37:07 PM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105
729948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_shad
ow_reg_errors.105729948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.16068557
Short name T1138
Test name
Test status
Simulation time 12105600 ps
CPU time 22.6 seconds
Started Sep 18 04:36:43 PM UTC 24
Finished Sep 18 04:37:06 PM UTC 24
Peak memory 274276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=16068557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_shadow_reg_errors_with_csr_rw.16068557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3176531054
Short name T1177
Test name
Test status
Simulation time 115667100 ps
CPU time 28.12 seconds
Started Sep 18 04:40:21 PM UTC 24
Finished Sep 18 04:40:51 PM UTC 24
Peak memory 276380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3176531054 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.3176531054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.256517955
Short name T1180
Test name
Test status
Simulation time 333591000 ps
CPU time 32.93 seconds
Started Sep 18 04:40:21 PM UTC 24
Finished Sep 18 04:40:56 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256517955 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.256517955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3547377630
Short name T1179
Test name
Test status
Simulation time 222064600 ps
CPU time 31.97 seconds
Started Sep 18 04:40:21 PM UTC 24
Finished Sep 18 04:40:55 PM UTC 24
Peak memory 276584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3547377630 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl
_same_csr_outstanding.3547377630
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.157797776
Short name T1174
Test name
Test status
Simulation time 33182600 ps
CPU time 24.63 seconds
Started Sep 18 04:40:13 PM UTC 24
Finished Sep 18 04:40:39 PM UTC 24
Peak memory 274416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157
797776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sha
dow_reg_errors.157797776
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2911605329
Short name T1173
Test name
Test status
Simulation time 49666800 ps
CPU time 20.15 seconds
Started Sep 18 04:40:16 PM UTC 24
Finished Sep 18 04:40:37 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2911605329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f
lash_ctrl_shadow_reg_errors_with_csr_rw.2911605329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2312824418
Short name T1183
Test name
Test status
Simulation time 294473500 ps
CPU time 23.7 seconds
Started Sep 18 04:40:37 PM UTC 24
Finished Sep 18 04:41:02 PM UTC 24
Peak memory 286624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2312824418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.2312824418
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2849518003
Short name T1181
Test name
Test status
Simulation time 52404800 ps
CPU time 23.39 seconds
Started Sep 18 04:40:32 PM UTC 24
Finished Sep 18 04:40:58 PM UTC 24
Peak memory 276332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849518003 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.2849518003
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.2453423822
Short name T353
Test name
Test status
Simulation time 151655600 ps
CPU time 20.69 seconds
Started Sep 18 04:40:29 PM UTC 24
Finished Sep 18 04:40:51 PM UTC 24
Peak memory 274548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453423822 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.2453423822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.503702178
Short name T1182
Test name
Test status
Simulation time 90777300 ps
CPU time 22.88 seconds
Started Sep 18 04:40:35 PM UTC 24
Finished Sep 18 04:41:00 PM UTC 24
Peak memory 276380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
503702178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_
same_csr_outstanding.503702178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2959325731
Short name T1176
Test name
Test status
Simulation time 62659000 ps
CPU time 25.59 seconds
Started Sep 18 04:40:24 PM UTC 24
Finished Sep 18 04:40:51 PM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295
9325731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh
adow_reg_errors.2959325731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.246360965
Short name T1178
Test name
Test status
Simulation time 13286600 ps
CPU time 24.79 seconds
Started Sep 18 04:40:28 PM UTC 24
Finished Sep 18 04:40:54 PM UTC 24
Peak memory 274404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=246360965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.246360965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.174910039
Short name T381
Test name
Test status
Simulation time 582167100 ps
CPU time 1196.93 seconds
Started Sep 18 04:40:23 PM UTC 24
Finished Sep 18 05:00:34 PM UTC 24
Peak memory 278516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174910039 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.174910039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1694924575
Short name T1192
Test name
Test status
Simulation time 197776800 ps
CPU time 29.71 seconds
Started Sep 18 04:40:52 PM UTC 24
Finished Sep 18 04:41:23 PM UTC 24
Peak memory 286620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1694924575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1694924575
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2679827749
Short name T1187
Test name
Test status
Simulation time 32007200 ps
CPU time 22.72 seconds
Started Sep 18 04:40:45 PM UTC 24
Finished Sep 18 04:41:09 PM UTC 24
Peak memory 274348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679827749 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.2679827749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.749934394
Short name T1185
Test name
Test status
Simulation time 58468600 ps
CPU time 21.43 seconds
Started Sep 18 04:40:45 PM UTC 24
Finished Sep 18 04:41:08 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749934394 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.749934394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4170269568
Short name T1190
Test name
Test status
Simulation time 38284800 ps
CPU time 30.15 seconds
Started Sep 18 04:40:46 PM UTC 24
Finished Sep 18 04:41:17 PM UTC 24
Peak memory 276384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4170269568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl
_same_csr_outstanding.4170269568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.497031524
Short name T1186
Test name
Test status
Simulation time 12494300 ps
CPU time 24.88 seconds
Started Sep 18 04:40:43 PM UTC 24
Finished Sep 18 04:41:09 PM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=497
031524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sha
dow_reg_errors.497031524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1602124740
Short name T1188
Test name
Test status
Simulation time 58387500 ps
CPU time 29.45 seconds
Started Sep 18 04:40:44 PM UTC 24
Finished Sep 18 04:41:15 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1602124740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1602124740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1796337724
Short name T1184
Test name
Test status
Simulation time 227308300 ps
CPU time 24.74 seconds
Started Sep 18 04:40:39 PM UTC 24
Finished Sep 18 04:41:05 PM UTC 24
Peak memory 276404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796337724 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.1796337724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2781522833
Short name T1194
Test name
Test status
Simulation time 59666400 ps
CPU time 25.7 seconds
Started Sep 18 04:40:58 PM UTC 24
Finished Sep 18 04:41:25 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781522833 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.2781522833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1892560610
Short name T1191
Test name
Test status
Simulation time 25338200 ps
CPU time 22.02 seconds
Started Sep 18 04:40:57 PM UTC 24
Finished Sep 18 04:41:20 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892560610 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.1892560610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1686692287
Short name T1195
Test name
Test status
Simulation time 99550900 ps
CPU time 21.91 seconds
Started Sep 18 04:41:01 PM UTC 24
Finished Sep 18 04:41:27 PM UTC 24
Peak memory 276384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1686692287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl
_same_csr_outstanding.1686692287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1928473432
Short name T1189
Test name
Test status
Simulation time 24604500 ps
CPU time 20.04 seconds
Started Sep 18 04:40:55 PM UTC 24
Finished Sep 18 04:41:16 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192
8473432 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sh
adow_reg_errors.1928473432
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1411369498
Short name T1193
Test name
Test status
Simulation time 14681200 ps
CPU time 26.47 seconds
Started Sep 18 04:40:56 PM UTC 24
Finished Sep 18 04:41:24 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1411369498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1411369498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1559094567
Short name T273
Test name
Test status
Simulation time 50031900 ps
CPU time 21.53 seconds
Started Sep 18 04:40:52 PM UTC 24
Finished Sep 18 04:41:14 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559094567 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.1559094567
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3571626834
Short name T378
Test name
Test status
Simulation time 372858700 ps
CPU time 566.52 seconds
Started Sep 18 04:40:52 PM UTC 24
Finished Sep 18 04:50:25 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571626834 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.3571626834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.949888582
Short name T1200
Test name
Test status
Simulation time 127040000 ps
CPU time 21.83 seconds
Started Sep 18 04:41:16 PM UTC 24
Finished Sep 18 04:41:39 PM UTC 24
Peak memory 286632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=949888582 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.949888582
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2077803214
Short name T1205
Test name
Test status
Simulation time 48906500 ps
CPU time 31.22 seconds
Started Sep 18 04:41:14 PM UTC 24
Finished Sep 18 04:41:46 PM UTC 24
Peak memory 276332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077803214 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.2077803214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1079223467
Short name T1196
Test name
Test status
Simulation time 116857400 ps
CPU time 16.83 seconds
Started Sep 18 04:41:10 PM UTC 24
Finished Sep 18 04:41:28 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079223467 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.1079223467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2881440459
Short name T1197
Test name
Test status
Simulation time 145349600 ps
CPU time 18.73 seconds
Started Sep 18 04:41:15 PM UTC 24
Finished Sep 18 04:41:35 PM UTC 24
Peak memory 274536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2881440459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl
_same_csr_outstanding.2881440459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.373518145
Short name T1201
Test name
Test status
Simulation time 13173400 ps
CPU time 27.51 seconds
Started Sep 18 04:41:10 PM UTC 24
Finished Sep 18 04:41:39 PM UTC 24
Peak memory 274196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373
518145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sha
dow_reg_errors.373518145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.534372136
Short name T1198
Test name
Test status
Simulation time 14670500 ps
CPU time 26.23 seconds
Started Sep 18 04:41:10 PM UTC 24
Finished Sep 18 04:41:38 PM UTC 24
Peak memory 274184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=534372136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.534372136
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1226633201
Short name T1202
Test name
Test status
Simulation time 52715500 ps
CPU time 33.37 seconds
Started Sep 18 04:41:05 PM UTC 24
Finished Sep 18 04:41:40 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226633201 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.1226633201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.4282818541
Short name T1266
Test name
Test status
Simulation time 1388365500 ps
CPU time 996.72 seconds
Started Sep 18 04:41:09 PM UTC 24
Finished Sep 18 04:57:57 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282818541 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.4282818541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3872532270
Short name T1208
Test name
Test status
Simulation time 713664200 ps
CPU time 24.61 seconds
Started Sep 18 04:41:27 PM UTC 24
Finished Sep 18 04:41:53 PM UTC 24
Peak memory 286624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3872532270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.3872532270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2009520822
Short name T1207
Test name
Test status
Simulation time 94487200 ps
CPU time 23.42 seconds
Started Sep 18 04:41:25 PM UTC 24
Finished Sep 18 04:41:50 PM UTC 24
Peak memory 274348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009520822 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.2009520822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.2524101468
Short name T1203
Test name
Test status
Simulation time 29257900 ps
CPU time 16.77 seconds
Started Sep 18 04:41:24 PM UTC 24
Finished Sep 18 04:41:42 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524101468 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.2524101468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1395169905
Short name T1209
Test name
Test status
Simulation time 267178600 ps
CPU time 30.15 seconds
Started Sep 18 04:41:26 PM UTC 24
Finished Sep 18 04:41:58 PM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1395169905 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_same_csr_outstanding.1395169905
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1791782353
Short name T1199
Test name
Test status
Simulation time 18019300 ps
CPU time 16.83 seconds
Started Sep 18 04:41:21 PM UTC 24
Finished Sep 18 04:41:39 PM UTC 24
Peak memory 274412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179
1782353 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh
adow_reg_errors.1791782353
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1026058079
Short name T1204
Test name
Test status
Simulation time 36276000 ps
CPU time 21.55 seconds
Started Sep 18 04:41:21 PM UTC 24
Finished Sep 18 04:41:44 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1026058079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1026058079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1295485171
Short name T1206
Test name
Test status
Simulation time 50405500 ps
CPU time 29.68 seconds
Started Sep 18 04:41:17 PM UTC 24
Finished Sep 18 04:41:48 PM UTC 24
Peak memory 276468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295485171 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.1295485171
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.531374201
Short name T374
Test name
Test status
Simulation time 429159100 ps
CPU time 664.86 seconds
Started Sep 18 04:41:18 PM UTC 24
Finished Sep 18 04:52:31 PM UTC 24
Peak memory 276592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531374201 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.531374201
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2709091900
Short name T1216
Test name
Test status
Simulation time 695566700 ps
CPU time 30.9 seconds
Started Sep 18 04:41:41 PM UTC 24
Finished Sep 18 04:42:13 PM UTC 24
Peak memory 286884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2709091900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.2709091900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.526030590
Short name T1211
Test name
Test status
Simulation time 92737200 ps
CPU time 22.91 seconds
Started Sep 18 04:41:40 PM UTC 24
Finished Sep 18 04:42:04 PM UTC 24
Peak memory 274468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526030590 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.526030590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2753123746
Short name T1213
Test name
Test status
Simulation time 15388500 ps
CPU time 25.39 seconds
Started Sep 18 04:41:40 PM UTC 24
Finished Sep 18 04:42:06 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753123746 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.2753123746
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1326441448
Short name T1223
Test name
Test status
Simulation time 110671600 ps
CPU time 45.64 seconds
Started Sep 18 04:41:40 PM UTC 24
Finished Sep 18 04:42:27 PM UTC 24
Peak memory 276584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1326441448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_same_csr_outstanding.1326441448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1842275882
Short name T1212
Test name
Test status
Simulation time 21437400 ps
CPU time 27.52 seconds
Started Sep 18 04:41:35 PM UTC 24
Finished Sep 18 04:42:04 PM UTC 24
Peak memory 274276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=184
2275882 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sh
adow_reg_errors.1842275882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1641088598
Short name T1210
Test name
Test status
Simulation time 30683700 ps
CPU time 21.77 seconds
Started Sep 18 04:41:39 PM UTC 24
Finished Sep 18 04:42:01 PM UTC 24
Peak memory 274200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1641088598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1641088598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4169592576
Short name T281
Test name
Test status
Simulation time 151731600 ps
CPU time 26.2 seconds
Started Sep 18 04:41:29 PM UTC 24
Finished Sep 18 04:41:57 PM UTC 24
Peak memory 276660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169592576 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.4169592576
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.478026917
Short name T373
Test name
Test status
Simulation time 715429500 ps
CPU time 622.73 seconds
Started Sep 18 04:41:31 PM UTC 24
Finished Sep 18 04:52:01 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=478026917 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.478026917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1564322446
Short name T1222
Test name
Test status
Simulation time 315664900 ps
CPU time 30.79 seconds
Started Sep 18 04:41:54 PM UTC 24
Finished Sep 18 04:42:26 PM UTC 24
Peak memory 286628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1564322446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1564322446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3656109484
Short name T1215
Test name
Test status
Simulation time 573998600 ps
CPU time 17.37 seconds
Started Sep 18 04:41:52 PM UTC 24
Finished Sep 18 04:42:10 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656109484 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.3656109484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.995968095
Short name T352
Test name
Test status
Simulation time 47381000 ps
CPU time 20.84 seconds
Started Sep 18 04:41:49 PM UTC 24
Finished Sep 18 04:42:11 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995968095 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.995968095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2225671049
Short name T1219
Test name
Test status
Simulation time 73545000 ps
CPU time 30 seconds
Started Sep 18 04:41:52 PM UTC 24
Finished Sep 18 04:42:23 PM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2225671049 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_same_csr_outstanding.2225671049
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1305218979
Short name T1214
Test name
Test status
Simulation time 22249700 ps
CPU time 20.94 seconds
Started Sep 18 04:41:46 PM UTC 24
Finished Sep 18 04:42:08 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130
5218979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sh
adow_reg_errors.1305218979
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1397523257
Short name T1218
Test name
Test status
Simulation time 39496100 ps
CPU time 29.13 seconds
Started Sep 18 04:41:47 PM UTC 24
Finished Sep 18 04:42:18 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1397523257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1397523257
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3471091702
Short name T1217
Test name
Test status
Simulation time 36253400 ps
CPU time 27.09 seconds
Started Sep 18 04:41:45 PM UTC 24
Finished Sep 18 04:42:14 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471091702 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.3471091702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3853263254
Short name T1230
Test name
Test status
Simulation time 45528300 ps
CPU time 29.09 seconds
Started Sep 18 04:42:08 PM UTC 24
Finished Sep 18 04:42:38 PM UTC 24
Peak memory 292900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3853263254 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.3853263254
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1449078889
Short name T1225
Test name
Test status
Simulation time 105166500 ps
CPU time 26.01 seconds
Started Sep 18 04:42:07 PM UTC 24
Finished Sep 18 04:42:34 PM UTC 24
Peak memory 274264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449078889 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.1449078889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3858295235
Short name T1221
Test name
Test status
Simulation time 16756500 ps
CPU time 18.18 seconds
Started Sep 18 04:42:04 PM UTC 24
Finished Sep 18 04:42:24 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858295235 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.3858295235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1095924538
Short name T1233
Test name
Test status
Simulation time 392704700 ps
CPU time 32.94 seconds
Started Sep 18 04:42:07 PM UTC 24
Finished Sep 18 04:42:41 PM UTC 24
Peak memory 274536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1095924538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_same_csr_outstanding.1095924538
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3570694159
Short name T1220
Test name
Test status
Simulation time 32756900 ps
CPU time 19 seconds
Started Sep 18 04:42:03 PM UTC 24
Finished Sep 18 04:42:23 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=357
0694159 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sh
adow_reg_errors.3570694159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.403704131
Short name T1224
Test name
Test status
Simulation time 46715000 ps
CPU time 27.37 seconds
Started Sep 18 04:42:03 PM UTC 24
Finished Sep 18 04:42:32 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=403704131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.403704131
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2401743126
Short name T1229
Test name
Test status
Simulation time 908880300 ps
CPU time 37.69 seconds
Started Sep 18 04:41:58 PM UTC 24
Finished Sep 18 04:42:37 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2401743126 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.2401743126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.2346797313
Short name T372
Test name
Test status
Simulation time 430176200 ps
CPU time 490.7 seconds
Started Sep 18 04:41:59 PM UTC 24
Finished Sep 18 04:50:15 PM UTC 24
Peak memory 276392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346797313 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.2346797313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2110815513
Short name T1238
Test name
Test status
Simulation time 63004800 ps
CPU time 26.92 seconds
Started Sep 18 04:42:24 PM UTC 24
Finished Sep 18 04:42:52 PM UTC 24
Peak memory 286320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2110815513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.2110815513
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1089403439
Short name T1231
Test name
Test status
Simulation time 185720500 ps
CPU time 18.75 seconds
Started Sep 18 04:42:18 PM UTC 24
Finished Sep 18 04:42:38 PM UTC 24
Peak memory 274476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089403439 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.1089403439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3049046702
Short name T1232
Test name
Test status
Simulation time 26099600 ps
CPU time 25.84 seconds
Started Sep 18 04:42:14 PM UTC 24
Finished Sep 18 04:42:41 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049046702 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.3049046702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1694476768
Short name T1235
Test name
Test status
Simulation time 816614100 ps
CPU time 23.12 seconds
Started Sep 18 04:42:24 PM UTC 24
Finished Sep 18 04:42:48 PM UTC 24
Peak memory 276072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1694476768 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_same_csr_outstanding.1694476768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1676205364
Short name T1227
Test name
Test status
Simulation time 62831700 ps
CPU time 23 seconds
Started Sep 18 04:42:11 PM UTC 24
Finished Sep 18 04:42:36 PM UTC 24
Peak memory 274340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167
6205364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh
adow_reg_errors.1676205364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.138939817
Short name T1228
Test name
Test status
Simulation time 20795700 ps
CPU time 21.15 seconds
Started Sep 18 04:42:14 PM UTC 24
Finished Sep 18 04:42:37 PM UTC 24
Peak memory 274136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=138939817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.138939817
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.4008260907
Short name T384
Test name
Test status
Simulation time 1304524500 ps
CPU time 646.4 seconds
Started Sep 18 04:42:11 PM UTC 24
Finished Sep 18 04:53:05 PM UTC 24
Peak memory 276652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008260907 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.4008260907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1597757355
Short name T1144
Test name
Test status
Simulation time 195888800 ps
CPU time 40.75 seconds
Started Sep 18 04:37:23 PM UTC 24
Finished Sep 18 04:38:06 PM UTC 24
Peak memory 274468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597757355 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.1597757355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1241457757
Short name T137
Test name
Test status
Simulation time 725251300 ps
CPU time 33.82 seconds
Started Sep 18 04:37:42 PM UTC 24
Finished Sep 18 04:38:17 PM UTC 24
Peak memory 286692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1241457757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.1241457757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4075898804
Short name T252
Test name
Test status
Simulation time 39462200 ps
CPU time 24.84 seconds
Started Sep 18 04:37:25 PM UTC 24
Finished Sep 18 04:37:52 PM UTC 24
Peak memory 274276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4075898804 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.4075898804
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.1589102203
Short name T347
Test name
Test status
Simulation time 15727200 ps
CPU time 24.92 seconds
Started Sep 18 04:37:16 PM UTC 24
Finished Sep 18 04:37:42 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589102203 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.1589102203
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1409628823
Short name T247
Test name
Test status
Simulation time 29433400 ps
CPU time 18.94 seconds
Started Sep 18 04:37:17 PM UTC 24
Finished Sep 18 04:37:37 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409628823 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.1409628823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.146896386
Short name T1142
Test name
Test status
Simulation time 55961800 ps
CPU time 25.41 seconds
Started Sep 18 04:37:16 PM UTC 24
Finished Sep 18 04:37:43 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146896386 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.146896386
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.404791437
Short name T253
Test name
Test status
Simulation time 608226600 ps
CPU time 29.24 seconds
Started Sep 18 04:37:42 PM UTC 24
Finished Sep 18 04:38:12 PM UTC 24
Peak memory 276644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
404791437 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_s
ame_csr_outstanding.404791437
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2027767095
Short name T1141
Test name
Test status
Simulation time 81300200 ps
CPU time 28.05 seconds
Started Sep 18 04:37:11 PM UTC 24
Finished Sep 18 04:37:40 PM UTC 24
Peak memory 274408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202
7767095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha
dow_reg_errors.2027767095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2679051962
Short name T1143
Test name
Test status
Simulation time 13297400 ps
CPU time 29.52 seconds
Started Sep 18 04:37:14 PM UTC 24
Finished Sep 18 04:37:45 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2679051962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2679051962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3557662709
Short name T214
Test name
Test status
Simulation time 722421400 ps
CPU time 33 seconds
Started Sep 18 04:37:07 PM UTC 24
Finished Sep 18 04:37:41 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3557662709 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3557662709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.395035490
Short name T386
Test name
Test status
Simulation time 12994645600 ps
CPU time 1160.38 seconds
Started Sep 18 04:37:08 PM UTC 24
Finished Sep 18 04:56:41 PM UTC 24
Peak memory 286868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395035490 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.395035490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.387552749
Short name T1237
Test name
Test status
Simulation time 28541700 ps
CPU time 25.18 seconds
Started Sep 18 04:42:25 PM UTC 24
Finished Sep 18 04:42:51 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387552749 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.387552749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1233599061
Short name T1236
Test name
Test status
Simulation time 17991900 ps
CPU time 24.18 seconds
Started Sep 18 04:42:25 PM UTC 24
Finished Sep 18 04:42:50 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233599061 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.1233599061
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.610748903
Short name T1234
Test name
Test status
Simulation time 50101900 ps
CPU time 18.73 seconds
Started Sep 18 04:42:27 PM UTC 24
Finished Sep 18 04:42:47 PM UTC 24
Peak memory 274480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610748903 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.610748903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2727414446
Short name T1241
Test name
Test status
Simulation time 15356500 ps
CPU time 25.52 seconds
Started Sep 18 04:42:28 PM UTC 24
Finished Sep 18 04:42:55 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727414446 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.2727414446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.3188693331
Short name T1240
Test name
Test status
Simulation time 189936800 ps
CPU time 18.93 seconds
Started Sep 18 04:42:33 PM UTC 24
Finished Sep 18 04:42:54 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188693331 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.3188693331
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.4040626264
Short name T1242
Test name
Test status
Simulation time 27008100 ps
CPU time 19.92 seconds
Started Sep 18 04:42:35 PM UTC 24
Finished Sep 18 04:42:56 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040626264 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.4040626264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2587251325
Short name T1239
Test name
Test status
Simulation time 22130200 ps
CPU time 16.77 seconds
Started Sep 18 04:42:35 PM UTC 24
Finished Sep 18 04:42:53 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587251325 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.2587251325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3857007089
Short name T1243
Test name
Test status
Simulation time 32113700 ps
CPU time 21.4 seconds
Started Sep 18 04:42:36 PM UTC 24
Finished Sep 18 04:42:59 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857007089 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.3857007089
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.895261767
Short name T1245
Test name
Test status
Simulation time 15628200 ps
CPU time 20.67 seconds
Started Sep 18 04:42:37 PM UTC 24
Finished Sep 18 04:42:59 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895261767 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.895261767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.4215443632
Short name T1249
Test name
Test status
Simulation time 17470600 ps
CPU time 24.81 seconds
Started Sep 18 04:42:39 PM UTC 24
Finished Sep 18 04:43:05 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4215443632 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.4215443632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.437433446
Short name T308
Test name
Test status
Simulation time 3238189100 ps
CPU time 95.65 seconds
Started Sep 18 04:38:12 PM UTC 24
Finished Sep 18 04:39:50 PM UTC 24
Peak memory 274276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437433446 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.437433446
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1279730761
Short name T390
Test name
Test status
Simulation time 2208729400 ps
CPU time 59.56 seconds
Started Sep 18 04:38:11 PM UTC 24
Finished Sep 18 04:39:12 PM UTC 24
Peak memory 276324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279730761 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.1279730761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2357967130
Short name T1150
Test name
Test status
Simulation time 19259300 ps
CPU time 37.55 seconds
Started Sep 18 04:38:07 PM UTC 24
Finished Sep 18 04:38:45 PM UTC 24
Peak memory 274468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357967130 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.2357967130
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3918158666
Short name T242
Test name
Test status
Simulation time 42424600 ps
CPU time 33.28 seconds
Started Sep 18 04:38:14 PM UTC 24
Finished Sep 18 04:38:49 PM UTC 24
Peak memory 286820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3918158666 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.3918158666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.811460792
Short name T314
Test name
Test status
Simulation time 205809500 ps
CPU time 27.28 seconds
Started Sep 18 04:38:07 PM UTC 24
Finished Sep 18 04:38:35 PM UTC 24
Peak memory 274476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=811460792 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.811460792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.475001113
Short name T348
Test name
Test status
Simulation time 80544700 ps
CPU time 15.92 seconds
Started Sep 18 04:37:48 PM UTC 24
Finished Sep 18 04:38:05 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475001113 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.475001113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4096242792
Short name T248
Test name
Test status
Simulation time 28544700 ps
CPU time 23.8 seconds
Started Sep 18 04:37:52 PM UTC 24
Finished Sep 18 04:38:18 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096242792 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.4096242792
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2942216095
Short name T1145
Test name
Test status
Simulation time 48709600 ps
CPU time 17.45 seconds
Started Sep 18 04:37:51 PM UTC 24
Finished Sep 18 04:38:10 PM UTC 24
Peak memory 274352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942216095 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.2942216095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1858975800
Short name T1152
Test name
Test status
Simulation time 233589500 ps
CPU time 39.92 seconds
Started Sep 18 04:38:13 PM UTC 24
Finished Sep 18 04:38:54 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1858975800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
same_csr_outstanding.1858975800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2781453610
Short name T1147
Test name
Test status
Simulation time 23036000 ps
CPU time 28.31 seconds
Started Sep 18 04:37:46 PM UTC 24
Finished Sep 18 04:38:16 PM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278
1453610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha
dow_reg_errors.2781453610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2673368094
Short name T1146
Test name
Test status
Simulation time 25435700 ps
CPU time 21.82 seconds
Started Sep 18 04:37:48 PM UTC 24
Finished Sep 18 04:38:11 PM UTC 24
Peak memory 274464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2673368094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2673368094
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1251663451
Short name T215
Test name
Test status
Simulation time 77717400 ps
CPU time 29.56 seconds
Started Sep 18 04:37:43 PM UTC 24
Finished Sep 18 04:38:14 PM UTC 24
Peak memory 276464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251663451 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.1251663451
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1665425398
Short name T265
Test name
Test status
Simulation time 726985600 ps
CPU time 652.04 seconds
Started Sep 18 04:37:44 PM UTC 24
Finished Sep 18 04:48:44 PM UTC 24
Peak memory 276460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1665425398 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.1665425398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.128559070
Short name T1246
Test name
Test status
Simulation time 38746800 ps
CPU time 19.65 seconds
Started Sep 18 04:42:39 PM UTC 24
Finished Sep 18 04:43:00 PM UTC 24
Peak memory 274544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=128559070 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.128559070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.1687455416
Short name T1248
Test name
Test status
Simulation time 14689000 ps
CPU time 24.12 seconds
Started Sep 18 04:42:39 PM UTC 24
Finished Sep 18 04:43:05 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687455416 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.1687455416
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.942823162
Short name T1244
Test name
Test status
Simulation time 58660000 ps
CPU time 18.16 seconds
Started Sep 18 04:42:40 PM UTC 24
Finished Sep 18 04:42:59 PM UTC 24
Peak memory 274352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=942823162 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.942823162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.3797946311
Short name T1247
Test name
Test status
Simulation time 48931100 ps
CPU time 19.04 seconds
Started Sep 18 04:42:43 PM UTC 24
Finished Sep 18 04:43:03 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3797946311 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.3797946311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1773801789
Short name T1252
Test name
Test status
Simulation time 15353100 ps
CPU time 26.33 seconds
Started Sep 18 04:42:43 PM UTC 24
Finished Sep 18 04:43:10 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773801789 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.1773801789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.1617003705
Short name T1251
Test name
Test status
Simulation time 133737300 ps
CPU time 18.39 seconds
Started Sep 18 04:42:48 PM UTC 24
Finished Sep 18 04:43:07 PM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617003705 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.1617003705
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.1231051325
Short name T1250
Test name
Test status
Simulation time 21114600 ps
CPU time 17.2 seconds
Started Sep 18 04:42:49 PM UTC 24
Finished Sep 18 04:43:07 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231051325 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.1231051325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.1273774913
Short name T1253
Test name
Test status
Simulation time 30287200 ps
CPU time 18.91 seconds
Started Sep 18 04:42:51 PM UTC 24
Finished Sep 18 04:43:11 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273774913 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.1273774913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2552466077
Short name T1258
Test name
Test status
Simulation time 88132700 ps
CPU time 23.33 seconds
Started Sep 18 04:42:52 PM UTC 24
Finished Sep 18 04:43:17 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552466077 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.2552466077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.3780720520
Short name T1257
Test name
Test status
Simulation time 56262600 ps
CPU time 21.79 seconds
Started Sep 18 04:42:53 PM UTC 24
Finished Sep 18 04:43:16 PM UTC 24
Peak memory 274292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780720520 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.3780720520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1366975913
Short name T1154
Test name
Test status
Simulation time 920989700 ps
CPU time 34.91 seconds
Started Sep 18 04:38:46 PM UTC 24
Finished Sep 18 04:39:22 PM UTC 24
Peak memory 274276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366975913 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.1366975913
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.172499990
Short name T305
Test name
Test status
Simulation time 6183513200 ps
CPU time 54.11 seconds
Started Sep 18 04:38:45 PM UTC 24
Finished Sep 18 04:39:41 PM UTC 24
Peak memory 276328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172499990 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.172499990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1240102307
Short name T306
Test name
Test status
Simulation time 56382900 ps
CPU time 62.69 seconds
Started Sep 18 04:38:41 PM UTC 24
Finished Sep 18 04:39:45 PM UTC 24
Peak memory 276452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240102307 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.1240102307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3349044358
Short name T307
Test name
Test status
Simulation time 68423200 ps
CPU time 29.73 seconds
Started Sep 18 04:38:44 PM UTC 24
Finished Sep 18 04:39:15 PM UTC 24
Peak memory 274276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349044358 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.3349044358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.1687398411
Short name T349
Test name
Test status
Simulation time 163102600 ps
CPU time 25.55 seconds
Started Sep 18 04:38:22 PM UTC 24
Finished Sep 18 04:38:48 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687398411 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.1687398411
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3829116506
Short name T249
Test name
Test status
Simulation time 218808100 ps
CPU time 26.31 seconds
Started Sep 18 04:38:36 PM UTC 24
Finished Sep 18 04:39:03 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829116506 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.3829116506
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.989229161
Short name T1151
Test name
Test status
Simulation time 17370500 ps
CPU time 26.99 seconds
Started Sep 18 04:38:26 PM UTC 24
Finished Sep 18 04:38:54 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989229161 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.989229161
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1083590502
Short name T303
Test name
Test status
Simulation time 238345400 ps
CPU time 31.73 seconds
Started Sep 18 04:38:48 PM UTC 24
Finished Sep 18 04:39:21 PM UTC 24
Peak memory 274340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1083590502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
same_csr_outstanding.1083590502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1853399296
Short name T1148
Test name
Test status
Simulation time 12447200 ps
CPU time 23.22 seconds
Started Sep 18 04:38:18 PM UTC 24
Finished Sep 18 04:38:43 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185
3399296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sha
dow_reg_errors.1853399296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1962131121
Short name T1149
Test name
Test status
Simulation time 26334900 ps
CPU time 25.1 seconds
Started Sep 18 04:38:18 PM UTC 24
Finished Sep 18 04:38:45 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1962131121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1962131121
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.762727809
Short name T216
Test name
Test status
Simulation time 187010100 ps
CPU time 30.76 seconds
Started Sep 18 04:38:15 PM UTC 24
Finished Sep 18 04:38:47 PM UTC 24
Peak memory 276596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762727809 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.762727809
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.3289823923
Short name T387
Test name
Test status
Simulation time 1333818600 ps
CPU time 1265.08 seconds
Started Sep 18 04:38:16 PM UTC 24
Finished Sep 18 04:59:36 PM UTC 24
Peak memory 278508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289823923 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.3289823923
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.2843655168
Short name T1259
Test name
Test status
Simulation time 15127000 ps
CPU time 22.7 seconds
Started Sep 18 04:42:54 PM UTC 24
Finished Sep 18 04:43:18 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843655168 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.2843655168
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.3018439891
Short name T1256
Test name
Test status
Simulation time 25152800 ps
CPU time 19.72 seconds
Started Sep 18 04:42:54 PM UTC 24
Finished Sep 18 04:43:15 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3018439891 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.3018439891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.4259787442
Short name T1254
Test name
Test status
Simulation time 30220400 ps
CPU time 18.2 seconds
Started Sep 18 04:42:55 PM UTC 24
Finished Sep 18 04:43:15 PM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259787442 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.4259787442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.269009796
Short name T1255
Test name
Test status
Simulation time 53512500 ps
CPU time 16.5 seconds
Started Sep 18 04:42:57 PM UTC 24
Finished Sep 18 04:43:15 PM UTC 24
Peak memory 274480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=269009796 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.269009796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.4064784772
Short name T1260
Test name
Test status
Simulation time 25084400 ps
CPU time 18.07 seconds
Started Sep 18 04:42:59 PM UTC 24
Finished Sep 18 04:43:19 PM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064784772 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.4064784772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.280988261
Short name T1264
Test name
Test status
Simulation time 42684800 ps
CPU time 25.63 seconds
Started Sep 18 04:43:00 PM UTC 24
Finished Sep 18 04:43:26 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280988261 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.280988261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1628236548
Short name T1265
Test name
Test status
Simulation time 16130100 ps
CPU time 25.51 seconds
Started Sep 18 04:43:01 PM UTC 24
Finished Sep 18 04:43:27 PM UTC 24
Peak memory 274292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628236548 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.1628236548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2524437218
Short name T1261
Test name
Test status
Simulation time 26896400 ps
CPU time 18.1 seconds
Started Sep 18 04:43:02 PM UTC 24
Finished Sep 18 04:43:21 PM UTC 24
Peak memory 274292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524437218 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.2524437218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.76901626
Short name T1262
Test name
Test status
Simulation time 16413900 ps
CPU time 21.06 seconds
Started Sep 18 04:43:04 PM UTC 24
Finished Sep 18 04:43:26 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76901626 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.76901626
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.990135471
Short name T1263
Test name
Test status
Simulation time 128976700 ps
CPU time 19.27 seconds
Started Sep 18 04:43:06 PM UTC 24
Finished Sep 18 04:43:26 PM UTC 24
Peak memory 274480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990135471 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.990135471
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1748720032
Short name T1159
Test name
Test status
Simulation time 158951100 ps
CPU time 34.35 seconds
Started Sep 18 04:39:11 PM UTC 24
Finished Sep 18 04:39:47 PM UTC 24
Peak memory 286624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1748720032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.1748720032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1977107819
Short name T304
Test name
Test status
Simulation time 38130400 ps
CPU time 26.18 seconds
Started Sep 18 04:38:58 PM UTC 24
Finished Sep 18 04:39:26 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977107819 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.1977107819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.598469444
Short name T351
Test name
Test status
Simulation time 16190200 ps
CPU time 23.91 seconds
Started Sep 18 04:38:58 PM UTC 24
Finished Sep 18 04:39:23 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=598469444 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.598469444
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3925504557
Short name T1156
Test name
Test status
Simulation time 84999000 ps
CPU time 32.31 seconds
Started Sep 18 04:39:04 PM UTC 24
Finished Sep 18 04:39:38 PM UTC 24
Peak memory 276524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3925504557 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_
same_csr_outstanding.3925504557
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4106474064
Short name T1153
Test name
Test status
Simulation time 17350200 ps
CPU time 25.17 seconds
Started Sep 18 04:38:55 PM UTC 24
Finished Sep 18 04:39:22 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410
6474064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha
dow_reg_errors.4106474064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1029941228
Short name T1155
Test name
Test status
Simulation time 25408900 ps
CPU time 25.5 seconds
Started Sep 18 04:38:58 PM UTC 24
Finished Sep 18 04:39:25 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1029941228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1029941228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3487127749
Short name T243
Test name
Test status
Simulation time 128479900 ps
CPU time 20.33 seconds
Started Sep 18 04:38:49 PM UTC 24
Finished Sep 18 04:39:11 PM UTC 24
Peak memory 276656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487127749 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.3487127749
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.312915908
Short name T1160
Test name
Test status
Simulation time 49847900 ps
CPU time 27.01 seconds
Started Sep 18 04:39:23 PM UTC 24
Finished Sep 18 04:39:52 PM UTC 24
Peak memory 286412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=312915908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.312915908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3038710309
Short name T388
Test name
Test status
Simulation time 112914600 ps
CPU time 28.48 seconds
Started Sep 18 04:39:23 PM UTC 24
Finished Sep 18 04:39:53 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038710309 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.3038710309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1822507969
Short name T309
Test name
Test status
Simulation time 109333300 ps
CPU time 26.62 seconds
Started Sep 18 04:39:23 PM UTC 24
Finished Sep 18 04:39:51 PM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1822507969 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
same_csr_outstanding.1822507969
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2367727943
Short name T1157
Test name
Test status
Simulation time 77887300 ps
CPU time 23.73 seconds
Started Sep 18 04:39:16 PM UTC 24
Finished Sep 18 04:39:41 PM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236
7727943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sha
dow_reg_errors.2367727943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1297244730
Short name T1158
Test name
Test status
Simulation time 14013000 ps
CPU time 19.33 seconds
Started Sep 18 04:39:21 PM UTC 24
Finished Sep 18 04:39:42 PM UTC 24
Peak memory 274464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1297244730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1297244730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3154681698
Short name T275
Test name
Test status
Simulation time 91659400 ps
CPU time 31.71 seconds
Started Sep 18 04:39:12 PM UTC 24
Finished Sep 18 04:39:46 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154681698 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.3154681698
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.147157063
Short name T264
Test name
Test status
Simulation time 492046700 ps
CPU time 525.82 seconds
Started Sep 18 04:39:13 PM UTC 24
Finished Sep 18 04:48:05 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147157063 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.147157063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1957822448
Short name T310
Test name
Test status
Simulation time 60884400 ps
CPU time 25.26 seconds
Started Sep 18 04:39:43 PM UTC 24
Finished Sep 18 04:40:09 PM UTC 24
Peak memory 286760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1957822448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.1957822448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4262820148
Short name T391
Test name
Test status
Simulation time 59704300 ps
CPU time 28.14 seconds
Started Sep 18 04:39:42 PM UTC 24
Finished Sep 18 04:40:11 PM UTC 24
Peak memory 274284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4262820148 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.4262820148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1662676470
Short name T355
Test name
Test status
Simulation time 18111500 ps
CPU time 23.26 seconds
Started Sep 18 04:39:39 PM UTC 24
Finished Sep 18 04:40:03 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662676470 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1662676470
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1808317823
Short name T1165
Test name
Test status
Simulation time 197505900 ps
CPU time 31.55 seconds
Started Sep 18 04:39:42 PM UTC 24
Finished Sep 18 04:40:15 PM UTC 24
Peak memory 276388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1808317823 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
same_csr_outstanding.1808317823
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.4003019162
Short name T1162
Test name
Test status
Simulation time 23530500 ps
CPU time 28.79 seconds
Started Sep 18 04:39:25 PM UTC 24
Finished Sep 18 04:39:55 PM UTC 24
Peak memory 274472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=400
3019162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sha
dow_reg_errors.4003019162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.976173230
Short name T1161
Test name
Test status
Simulation time 24655400 ps
CPU time 26.76 seconds
Started Sep 18 04:39:26 PM UTC 24
Finished Sep 18 04:39:55 PM UTC 24
Peak memory 274208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=976173230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.976173230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.340006605
Short name T277
Test name
Test status
Simulation time 38792300 ps
CPU time 25.12 seconds
Started Sep 18 04:39:24 PM UTC 24
Finished Sep 18 04:39:51 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340006605 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.340006605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2347554297
Short name T1167
Test name
Test status
Simulation time 51166700 ps
CPU time 28.81 seconds
Started Sep 18 04:39:52 PM UTC 24
Finished Sep 18 04:40:22 PM UTC 24
Peak memory 286628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2347554297 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.2347554297
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3381400341
Short name T389
Test name
Test status
Simulation time 45408300 ps
CPU time 25.82 seconds
Started Sep 18 04:39:51 PM UTC 24
Finished Sep 18 04:40:18 PM UTC 24
Peak memory 274540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381400341 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.3381400341
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1119299382
Short name T354
Test name
Test status
Simulation time 17672900 ps
CPU time 20.82 seconds
Started Sep 18 04:39:50 PM UTC 24
Finished Sep 18 04:40:12 PM UTC 24
Peak memory 274288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119299382 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.1119299382
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1275099972
Short name T1169
Test name
Test status
Simulation time 65050300 ps
CPU time 29.44 seconds
Started Sep 18 04:39:52 PM UTC 24
Finished Sep 18 04:40:23 PM UTC 24
Peak memory 276388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1275099972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_
same_csr_outstanding.1275099972
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1014777702
Short name T1163
Test name
Test status
Simulation time 24775100 ps
CPU time 20.82 seconds
Started Sep 18 04:39:47 PM UTC 24
Finished Sep 18 04:40:09 PM UTC 24
Peak memory 274408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=101
4777702 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sha
dow_reg_errors.1014777702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3926400696
Short name T1164
Test name
Test status
Simulation time 18307000 ps
CPU time 23.24 seconds
Started Sep 18 04:39:48 PM UTC 24
Finished Sep 18 04:40:12 PM UTC 24
Peak memory 274272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3926400696 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.3926400696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.446995223
Short name T278
Test name
Test status
Simulation time 64948500 ps
CPU time 31.49 seconds
Started Sep 18 04:39:46 PM UTC 24
Finished Sep 18 04:40:19 PM UTC 24
Peak memory 276596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446995223 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.446995223
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2183165434
Short name T376
Test name
Test status
Simulation time 181601800 ps
CPU time 604.3 seconds
Started Sep 18 04:39:47 PM UTC 24
Finished Sep 18 04:49:58 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183165434 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.2183165434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2629707655
Short name T1171
Test name
Test status
Simulation time 114731600 ps
CPU time 23.15 seconds
Started Sep 18 04:40:11 PM UTC 24
Finished Sep 18 04:40:35 PM UTC 24
Peak memory 286620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2629707655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.2629707655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2818990664
Short name T392
Test name
Test status
Simulation time 151751800 ps
CPU time 30.69 seconds
Started Sep 18 04:40:09 PM UTC 24
Finished Sep 18 04:40:42 PM UTC 24
Peak memory 274280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2818990664 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.2818990664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.3595560158
Short name T1170
Test name
Test status
Simulation time 100654300 ps
CPU time 25.58 seconds
Started Sep 18 04:40:04 PM UTC 24
Finished Sep 18 04:40:31 PM UTC 24
Peak memory 274348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595560158 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.3595560158
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4217316831
Short name T1172
Test name
Test status
Simulation time 245391800 ps
CPU time 25.1 seconds
Started Sep 18 04:40:10 PM UTC 24
Finished Sep 18 04:40:36 PM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4217316831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
same_csr_outstanding.4217316831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3061885014
Short name T1168
Test name
Test status
Simulation time 30806800 ps
CPU time 26.16 seconds
Started Sep 18 04:39:55 PM UTC 24
Finished Sep 18 04:40:23 PM UTC 24
Peak memory 274408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306
1885014 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha
dow_reg_errors.3061885014
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4107034724
Short name T1166
Test name
Test status
Simulation time 37835000 ps
CPU time 22.93 seconds
Started Sep 18 04:39:56 PM UTC 24
Finished Sep 18 04:40:20 PM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4107034724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.4107034724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.779634092
Short name T272
Test name
Test status
Simulation time 55718300 ps
CPU time 34.2 seconds
Started Sep 18 04:39:53 PM UTC 24
Finished Sep 18 04:40:29 PM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779634092 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.779634092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.1789866243
Short name T379
Test name
Test status
Simulation time 699492800 ps
CPU time 682.59 seconds
Started Sep 18 04:39:54 PM UTC 24
Finished Sep 18 04:51:25 PM UTC 24
Peak memory 276588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1789866243 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.1789866243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.642702920
Short name T5
Test name
Test status
Simulation time 27176100 ps
CPU time 24.81 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:57:50 PM UTC 24
Peak memory 285612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=642702920 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_disable.642702920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.2017818190
Short name T48
Test name
Test status
Simulation time 645929400 ps
CPU time 53.47 seconds
Started Sep 18 04:57:44 PM UTC 24
Finished Sep 18 04:58:39 PM UTC 24
Peak memory 273288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017818
190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f
s_sup.2017818190
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.2965265070
Short name T132
Test name
Test status
Simulation time 64691800 ps
CPU time 49.17 seconds
Started Sep 18 04:57:53 PM UTC 24
Finished Sep 18 04:58:44 PM UTC 24
Peak memory 287616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=296526507
0 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho
st_addr_infection.2965265070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.4079727336
Short name T107
Test name
Test status
Simulation time 59060600 ps
CPU time 165.88 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:00:09 PM UTC 24
Peak memory 275216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079727336 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.4079727336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.3262841158
Short name T62
Test name
Test status
Simulation time 71638900 ps
CPU time 15.88 seconds
Started Sep 18 04:57:51 PM UTC 24
Finished Sep 18 04:58:08 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3262841158 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_hw_read_seed_err.3262841158
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.2864506056
Short name T141
Test name
Test status
Simulation time 160169098300 ps
CPU time 901.42 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:12:33 PM UTC 24
Peak memory 277816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864506056
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.2864506056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.2341517620
Short name T55
Test name
Test status
Simulation time 4164097300 ps
CPU time 77.31 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 04:58:40 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2341517620 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.2341517620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.3202604373
Short name T319
Test name
Test status
Simulation time 15836259200 ps
CPU time 582.44 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 05:07:13 PM UTC 24
Peak memory 343240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3202604373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integr
ity.3202604373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.2996597524
Short name T43
Test name
Test status
Simulation time 754079900 ps
CPU time 168.58 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 05:00:15 PM UTC 24
Peak memory 306096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996597524 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.2996597524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.517174168
Short name T76
Test name
Test status
Simulation time 56925287200 ps
CPU time 228.75 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 05:01:16 PM UTC 24
Peak memory 303916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=517174168 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_intr_rd_slow_flash.517174168
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.512538108
Short name T41
Test name
Test status
Simulation time 62774053300 ps
CPU time 244.87 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 05:01:32 PM UTC 24
Peak memory 271432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=512538108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.512538108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.1291367831
Short name T468
Test name
Test status
Simulation time 184224100 ps
CPU time 586.18 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:07:14 PM UTC 24
Peak memory 278004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291367831 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.1291367831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.333492468
Short name T11
Test name
Test status
Simulation time 24329000 ps
CPU time 24.84 seconds
Started Sep 18 04:57:44 PM UTC 24
Finished Sep 18 04:58:10 PM UTC 24
Peak memory 275552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=333492468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.333492468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.1589413993
Short name T159
Test name
Test status
Simulation time 5509889200 ps
CPU time 158.24 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 05:00:04 PM UTC 24
Peak memory 275516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589413993 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.1589413993
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.3874493568
Short name T163
Test name
Test status
Simulation time 797244600 ps
CPU time 747.75 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:09:56 PM UTC 24
Peak memory 296364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874493568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.3874493568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.2154575473
Short name T71
Test name
Test status
Simulation time 297265600 ps
CPU time 168.84 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:00:12 PM UTC 24
Peak memory 273416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154575473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.2154575473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.2349901453
Short name T103
Test name
Test status
Simulation time 277636300 ps
CPU time 64.96 seconds
Started Sep 18 04:57:53 PM UTC 24
Finished Sep 18 04:59:00 PM UTC 24
Peak memory 285632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349901453 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.2349901453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.35424103
Short name T1
Test name
Test status
Simulation time 42251200 ps
CPU time 18.41 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:57:41 PM UTC 24
Peak memory 275332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35424103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_ba
se_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.35424103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.3068649695
Short name T16
Test name
Test status
Simulation time 31467600 ps
CPU time 29.97 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:57:54 PM UTC 24
Peak memory 275248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3068649695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_read_word_sweep_derr.3068649695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.908069296
Short name T3
Test name
Test status
Simulation time 75546300 ps
CPU time 25.47 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:57:48 PM UTC 24
Peak memory 275348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908069296 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.908069296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.3113852221
Short name T68
Test name
Test status
Simulation time 2622402200 ps
CPU time 110.5 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:59:14 PM UTC 24
Peak memory 292116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3113852221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.3113852221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.3884120809
Short name T60
Test name
Test status
Simulation time 7428130700 ps
CPU time 179.67 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 05:00:25 PM UTC 24
Peak memory 293896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3884120809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rw_derr.3884120809
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.2267951939
Short name T42
Test name
Test status
Simulation time 2871890700 ps
CPU time 87.43 seconds
Started Sep 18 04:57:27 PM UTC 24
Finished Sep 18 04:58:56 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267951939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.2267951939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.2038766948
Short name T67
Test name
Test status
Simulation time 1083581900 ps
CPU time 58.14 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:58:23 PM UTC 24
Peak memory 275388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=203
8766948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser
r_address.2038766948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.2474303351
Short name T30
Test name
Test status
Simulation time 834671800 ps
CPU time 53.6 seconds
Started Sep 18 04:57:23 PM UTC 24
Finished Sep 18 04:58:18 PM UTC 24
Peak memory 285712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24
74303351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_se
rr_counter.2474303351
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.1408526664
Short name T56
Test name
Test status
Simulation time 78880100 ps
CPU time 200.2 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 05:00:43 PM UTC 24
Peak memory 287508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408526664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.1408526664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.4039152013
Short name T9
Test name
Test status
Simulation time 28154200 ps
CPU time 30.52 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 04:57:52 PM UTC 24
Peak memory 271048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4039152013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.4039152013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.1014858400
Short name T410
Test name
Test status
Simulation time 365329300 ps
CPU time 506.46 seconds
Started Sep 18 04:57:27 PM UTC 24
Finished Sep 18 05:06:00 PM UTC 24
Peak memory 287688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014858400 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.1014858400
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.2592672781
Short name T10
Test name
Test status
Simulation time 177358000 ps
CPU time 40.08 seconds
Started Sep 18 04:57:20 PM UTC 24
Finished Sep 18 04:58:02 PM UTC 24
Peak memory 270804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2592672781 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.2592672781
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.3806431010
Short name T241
Test name
Test status
Simulation time 2139989800 ps
CPU time 155.13 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:59:59 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3806431010 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.3806431010
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.2051054430
Short name T2
Test name
Test status
Simulation time 268032200 ps
CPU time 21.09 seconds
Started Sep 18 04:57:21 PM UTC 24
Finished Sep 18 04:57:43 PM UTC 24
Peak memory 269108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051054430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.2051054430
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.1331250738
Short name T7
Test name
Test status
Simulation time 12903900 ps
CPU time 19.09 seconds
Started Sep 18 05:00:35 PM UTC 24
Finished Sep 18 05:00:56 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1331250738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.1331250738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.490718363
Short name T121
Test name
Test status
Simulation time 66821100 ps
CPU time 27.47 seconds
Started Sep 18 05:01:05 PM UTC 24
Finished Sep 18 05:01:34 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490718363 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.490718363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3469633330
Short name T227
Test name
Test status
Simulation time 53266600 ps
CPU time 17.96 seconds
Started Sep 18 05:00:50 PM UTC 24
Finished Sep 18 05:01:09 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469633330 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.3469633330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.1411140396
Short name T23
Test name
Test status
Simulation time 29584500 ps
CPU time 27.22 seconds
Started Sep 18 05:00:25 PM UTC 24
Finished Sep 18 05:00:54 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411140396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.1411140396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.3772151943
Short name T283
Test name
Test status
Simulation time 30311900 ps
CPU time 40.39 seconds
Started Sep 18 05:00:15 PM UTC 24
Finished Sep 18 05:00:57 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3772151943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_disable.3772151943
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.3889857142
Short name T35
Test name
Test status
Simulation time 2784069400 ps
CPU time 464.84 seconds
Started Sep 18 04:58:11 PM UTC 24
Finished Sep 18 05:06:02 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3889857142 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.3889857142
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.11510356
Short name T713
Test name
Test status
Simulation time 12924196000 ps
CPU time 3158.59 seconds
Started Sep 18 04:58:31 PM UTC 24
Finished Sep 18 05:51:42 PM UTC 24
Peak memory 275912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11510356 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/co
verage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.11510356
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.1815230574
Short name T301
Test name
Test status
Simulation time 1626740600 ps
CPU time 1571.11 seconds
Started Sep 18 04:58:24 PM UTC 24
Finished Sep 18 05:24:52 PM UTC 24
Peak memory 288172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1815230574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.1815230574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.3342596689
Short name T262
Test name
Test status
Simulation time 1394566300 ps
CPU time 62.17 seconds
Started Sep 18 05:00:45 PM UTC 24
Finished Sep 18 05:01:49 PM UTC 24
Peak memory 273292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342596
689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f
s_sup.3342596689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.1732711657
Short name T150
Test name
Test status
Simulation time 95249889000 ps
CPU time 2448.75 seconds
Started Sep 18 04:58:20 PM UTC 24
Finished Sep 18 05:39:35 PM UTC 24
Peak memory 278164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1732711657 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.1732711657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.2553374475
Short name T259
Test name
Test status
Simulation time 65733300 ps
CPU time 35.03 seconds
Started Sep 18 05:01:05 PM UTC 24
Finished Sep 18 05:01:42 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255337447
5 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho
st_addr_infection.2553374475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.3165578835
Short name T707
Test name
Test status
Simulation time 289282069400 ps
CPU time 3123.59 seconds
Started Sep 18 04:58:17 PM UTC 24
Finished Sep 18 05:50:51 PM UTC 24
Peak memory 278324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165578835 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.3165578835
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.3675241430
Short name T85
Test name
Test status
Simulation time 17953400 ps
CPU time 23.77 seconds
Started Sep 18 05:00:58 PM UTC 24
Finished Sep 18 05:01:23 PM UTC 24
Peak memory 275372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3675241430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.flash_ctrl_hw_read_seed_err.3675241430
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.1953010723
Short name T142
Test name
Test status
Simulation time 337666560200 ps
CPU time 1670.93 seconds
Started Sep 18 04:58:14 PM UTC 24
Finished Sep 18 05:26:23 PM UTC 24
Peak memory 277928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1953010723
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.1953010723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.549055822
Short name T144
Test name
Test status
Simulation time 160172113900 ps
CPU time 825.54 seconds
Started Sep 18 04:58:15 PM UTC 24
Finished Sep 18 05:12:10 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549055822 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.549055822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.238130045
Short name T172
Test name
Test status
Simulation time 4237645600 ps
CPU time 708.59 seconds
Started Sep 18 04:59:28 PM UTC 24
Finished Sep 18 05:11:26 PM UTC 24
Peak memory 340988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=238130045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integrity.238130045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.714620678
Short name T77
Test name
Test status
Simulation time 6043761400 ps
CPU time 169.45 seconds
Started Sep 18 04:59:52 PM UTC 24
Finished Sep 18 05:02:45 PM UTC 24
Peak memory 303916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=714620678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_intr_rd_slow_flash.714620678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.1612068364
Short name T40
Test name
Test status
Simulation time 9329251900 ps
CPU time 80.81 seconds
Started Sep 18 04:59:50 PM UTC 24
Finished Sep 18 05:01:13 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1612068364 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.1612068364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1620106361
Short name T475
Test name
Test status
Simulation time 201363824100 ps
CPU time 401.06 seconds
Started Sep 18 04:59:56 PM UTC 24
Finished Sep 18 05:06:42 PM UTC 24
Peak memory 275468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620106361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1620106361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.2026065745
Short name T82
Test name
Test status
Simulation time 4227577900 ps
CPU time 90.77 seconds
Started Sep 18 04:58:40 PM UTC 24
Finished Sep 18 05:00:12 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026065745 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.2026065745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.1332847274
Short name T63
Test name
Test status
Simulation time 11808499700 ps
CPU time 141.17 seconds
Started Sep 18 04:58:40 PM UTC 24
Finished Sep 18 05:01:04 PM UTC 24
Peak memory 270936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332847274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.1332847274
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.1269743053
Short name T155
Test name
Test status
Simulation time 55492900 ps
CPU time 236.71 seconds
Started Sep 18 04:58:17 PM UTC 24
Finished Sep 18 05:02:18 PM UTC 24
Peak memory 271460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269743053 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.1269743053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2078378159
Short name T218
Test name
Test status
Simulation time 130356000 ps
CPU time 195.99 seconds
Started Sep 18 04:58:09 PM UTC 24
Finished Sep 18 05:01:28 PM UTC 24
Peak memory 275216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078378159 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2078378159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.4253453448
Short name T133
Test name
Test status
Simulation time 27380400 ps
CPU time 18.1 seconds
Started Sep 18 05:00:00 PM UTC 24
Finished Sep 18 05:00:24 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253453448 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.4253453448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.2856790079
Short name T515
Test name
Test status
Simulation time 1998750800 ps
CPU time 1279.06 seconds
Started Sep 18 04:58:01 PM UTC 24
Finished Sep 18 05:19:35 PM UTC 24
Peak memory 296364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856790079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.2856790079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.2839440618
Short name T27
Test name
Test status
Simulation time 2522327100 ps
CPU time 203.69 seconds
Started Sep 18 04:58:08 PM UTC 24
Finished Sep 18 05:01:35 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839440618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.2839440618
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.1334453831
Short name T367
Test name
Test status
Simulation time 89533200 ps
CPU time 39.72 seconds
Started Sep 18 05:00:27 PM UTC 24
Finished Sep 18 05:01:09 PM UTC 24
Peak memory 285496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=133445383
1 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.1334453831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.1782773072
Short name T414
Test name
Test status
Simulation time 433640600 ps
CPU time 60.76 seconds
Started Sep 18 05:00:15 PM UTC 24
Finished Sep 18 05:01:18 PM UTC 24
Peak memory 287932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782773072 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.1782773072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.3956116240
Short name T72
Test name
Test status
Simulation time 59713200 ps
CPU time 45.02 seconds
Started Sep 18 04:59:04 PM UTC 24
Finished Sep 18 04:59:50 PM UTC 24
Peak memory 275372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3956116240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_read_word_sweep_derr.3956116240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.413879614
Short name T234
Test name
Test status
Simulation time 40546000 ps
CPU time 40.68 seconds
Started Sep 18 04:58:44 PM UTC 24
Finished Sep 18 04:59:27 PM UTC 24
Peak memory 275384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413879614 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.413879614
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2015616690
Short name T184
Test name
Test status
Simulation time 231880623300 ps
CPU time 1289.67 seconds
Started Sep 18 05:00:56 PM UTC 24
Finished Sep 18 05:22:41 PM UTC 24
Peak memory 273108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2015616690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.
flash_ctrl_rma_err.2015616690
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.3900975125
Short name T80
Test name
Test status
Simulation time 1035504400 ps
CPU time 124.95 seconds
Started Sep 18 04:58:41 PM UTC 24
Finished Sep 18 05:00:48 PM UTC 24
Peak memory 302304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3900975125 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.3900975125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.2569375250
Short name T211
Test name
Test status
Simulation time 572658900 ps
CPU time 158.75 seconds
Started Sep 18 04:59:06 PM UTC 24
Finished Sep 18 05:01:47 PM UTC 24
Peak memory 291844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569375250 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2569375250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.1020148175
Short name T81
Test name
Test status
Simulation time 2737201700 ps
CPU time 138.89 seconds
Started Sep 18 04:58:50 PM UTC 24
Finished Sep 18 05:01:12 PM UTC 24
Peak memory 306176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1020148175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_ro_serr.1020148175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.2335057007
Short name T255
Test name
Test status
Simulation time 4111129800 ps
CPU time 436.45 seconds
Started Sep 18 04:58:43 PM UTC 24
Finished Sep 18 05:06:06 PM UTC 24
Peak memory 320572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2335057007 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.2335057007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.512065529
Short name T157
Test name
Test status
Simulation time 2457809500 ps
CPU time 207.68 seconds
Started Sep 18 04:59:15 PM UTC 24
Finished Sep 18 05:02:46 PM UTC 24
Peak memory 295940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=512065529 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 1.flash_ctrl_rw_derr.512065529
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.2340989880
Short name T39
Test name
Test status
Simulation time 80325600 ps
CPU time 56.07 seconds
Started Sep 18 05:00:08 PM UTC 24
Finished Sep 18 05:01:07 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340989880 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.2340989880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3725470498
Short name T38
Test name
Test status
Simulation time 28395400 ps
CPU time 36.12 seconds
Started Sep 18 05:00:10 PM UTC 24
Finished Sep 18 05:00:49 PM UTC 24
Peak memory 285636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3725470498 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw_evict_all_en.3725470498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_serr.1710528820
Short name T223
Test name
Test status
Simulation time 2830041800 ps
CPU time 182.02 seconds
Started Sep 18 04:58:52 PM UTC 24
Finished Sep 18 05:01:57 PM UTC 24
Peak memory 292020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1710528820 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_serr.1710528820
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.1567766389
Short name T282
Test name
Test status
Simulation time 1285318600 ps
CPU time 70.09 seconds
Started Sep 18 04:59:01 PM UTC 24
Finished Sep 18 05:00:13 PM UTC 24
Peak memory 275644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156
7766389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser
r_address.1567766389
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.2193297405
Short name T240
Test name
Test status
Simulation time 727789500 ps
CPU time 95.09 seconds
Started Sep 18 04:58:58 PM UTC 24
Finished Sep 18 05:00:35 PM UTC 24
Peak memory 285692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21
93297405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_se
rr_counter.2193297405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.1441735128
Short name T235
Test name
Test status
Simulation time 55876900 ps
CPU time 164.68 seconds
Started Sep 18 04:57:56 PM UTC 24
Finished Sep 18 05:00:44 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441735128 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.1441735128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.3613869881
Short name T219
Test name
Test status
Simulation time 17541800 ps
CPU time 36.59 seconds
Started Sep 18 04:57:58 PM UTC 24
Finished Sep 18 04:58:36 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613869881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.3613869881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.261282807
Short name T621
Test name
Test status
Simulation time 4792700700 ps
CPU time 2369.94 seconds
Started Sep 18 05:00:19 PM UTC 24
Finished Sep 18 05:40:13 PM UTC 24
Peak memory 304612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261282807 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.261282807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.1703259018
Short name T26
Test name
Test status
Simulation time 33349700 ps
CPU time 35.47 seconds
Started Sep 18 04:58:03 PM UTC 24
Finished Sep 18 04:58:39 PM UTC 24
Peak memory 272972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703259018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.1703259018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.4294006071
Short name T261
Test name
Test status
Simulation time 2426638100 ps
CPU time 183.39 seconds
Started Sep 18 04:58:41 PM UTC 24
Finished Sep 18 05:01:47 PM UTC 24
Peak memory 271120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4294006071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.4294006071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.529839108
Short name T18
Test name
Test status
Simulation time 47367500 ps
CPU time 24.1 seconds
Started Sep 18 05:00:35 PM UTC 24
Finished Sep 18 05:01:01 PM UTC 24
Peak memory 275604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=529839108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 1.flash_ctrl_wr_intg.529839108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.3813914045
Short name T618
Test name
Test status
Simulation time 54869700 ps
CPU time 24.87 seconds
Started Sep 18 05:39:04 PM UTC 24
Finished Sep 18 05:39:30 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3813914045 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.3813914045
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.3822231392
Short name T612
Test name
Test status
Simulation time 24733500 ps
CPU time 23.56 seconds
Started Sep 18 05:38:44 PM UTC 24
Finished Sep 18 05:39:09 PM UTC 24
Peak memory 294988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822231392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.3822231392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.171504950
Short name T396
Test name
Test status
Simulation time 12911000 ps
CPU time 39.38 seconds
Started Sep 18 05:38:08 PM UTC 24
Finished Sep 18 05:38:49 PM UTC 24
Peak memory 285496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=171504950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_disable.171504950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.2324431704
Short name T627
Test name
Test status
Simulation time 10012532600 ps
CPU time 159.07 seconds
Started Sep 18 05:38:53 PM UTC 24
Finished Sep 18 05:41:35 PM UTC 24
Peak memory 330580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2324431704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.2324431704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.1676527703
Short name T370
Test name
Test status
Simulation time 31016300 ps
CPU time 23.9 seconds
Started Sep 18 05:38:50 PM UTC 24
Finished Sep 18 05:39:15 PM UTC 24
Peak memory 275508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1676527703 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
10.flash_ctrl_hw_read_seed_err.1676527703
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.106871495
Short name T324
Test name
Test status
Simulation time 3840347500 ps
CPU time 148.29 seconds
Started Sep 18 05:36:32 PM UTC 24
Finished Sep 18 05:39:03 PM UTC 24
Peak memory 275212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106871495 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.106871495
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.3013606123
Short name T359
Test name
Test status
Simulation time 742984400 ps
CPU time 176.37 seconds
Started Sep 18 05:37:38 PM UTC 24
Finished Sep 18 05:40:37 PM UTC 24
Peak memory 306096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013606123 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.3013606123
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.2433813314
Short name T620
Test name
Test status
Simulation time 38920232000 ps
CPU time 127.3 seconds
Started Sep 18 05:37:38 PM UTC 24
Finished Sep 18 05:39:47 PM UTC 24
Peak memory 303904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2433813314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_intr_rd_slow_flash.2433813314
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.3219956721
Short name T608
Test name
Test status
Simulation time 2978857000 ps
CPU time 79.84 seconds
Started Sep 18 05:36:42 PM UTC 24
Finished Sep 18 05:38:04 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219956721 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.3219956721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.2429051151
Short name T152
Test name
Test status
Simulation time 39894989300 ps
CPU time 563.36 seconds
Started Sep 18 05:36:40 PM UTC 24
Finished Sep 18 05:46:10 PM UTC 24
Peak memory 283524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2429051151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.flash_ctrl_mp_regions.2429051151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.2986551250
Short name T623
Test name
Test status
Simulation time 43773200 ps
CPU time 227.35 seconds
Started Sep 18 05:36:33 PM UTC 24
Finished Sep 18 05:40:24 PM UTC 24
Peak memory 271528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986551250 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.2986551250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3809499286
Short name T636
Test name
Test status
Simulation time 2708969800 ps
CPU time 374.72 seconds
Started Sep 18 05:36:31 PM UTC 24
Finished Sep 18 05:42:50 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809499286 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3809499286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.2597441296
Short name T609
Test name
Test status
Simulation time 296572300 ps
CPU time 19.52 seconds
Started Sep 18 05:37:47 PM UTC 24
Finished Sep 18 05:38:08 PM UTC 24
Peak memory 271116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597441296 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.2597441296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.2127492948
Short name T638
Test name
Test status
Simulation time 119511800 ps
CPU time 406.77 seconds
Started Sep 18 05:36:29 PM UTC 24
Finished Sep 18 05:43:22 PM UTC 24
Peak memory 291532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127492948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.2127492948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.1405488407
Short name T456
Test name
Test status
Simulation time 72402500 ps
CPU time 36.23 seconds
Started Sep 18 05:38:05 PM UTC 24
Finished Sep 18 05:38:43 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405488407 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.1405488407
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.1074173098
Short name T614
Test name
Test status
Simulation time 2319644400 ps
CPU time 131.81 seconds
Started Sep 18 05:37:01 PM UTC 24
Finished Sep 18 05:39:16 PM UTC 24
Peak memory 304052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1074173098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.1074173098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.1517510543
Short name T654
Test name
Test status
Simulation time 7130175400 ps
CPU time 434.35 seconds
Started Sep 18 05:37:31 PM UTC 24
Finished Sep 18 05:44:52 PM UTC 24
Peak memory 320528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1517510543 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.1517510543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.3738143183
Short name T610
Test name
Test status
Simulation time 47893300 ps
CPU time 38.23 seconds
Started Sep 18 05:37:55 PM UTC 24
Finished Sep 18 05:38:35 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3738143183 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.3738143183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.3434964478
Short name T611
Test name
Test status
Simulation time 114382400 ps
CPU time 52.12 seconds
Started Sep 18 05:37:58 PM UTC 24
Finished Sep 18 05:38:51 PM UTC 24
Peak memory 287936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3434964478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw_evict_all_en.3434964478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.996058282
Short name T622
Test name
Test status
Simulation time 2740962300 ps
CPU time 100.97 seconds
Started Sep 18 05:38:35 PM UTC 24
Finished Sep 18 05:40:19 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996058282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.996058282
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.447739165
Short name T617
Test name
Test status
Simulation time 76339900 ps
CPU time 174.04 seconds
Started Sep 18 05:36:26 PM UTC 24
Finished Sep 18 05:39:23 PM UTC 24
Peak memory 289484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447739165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.447739165
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.1218413124
Short name T616
Test name
Test status
Simulation time 14911472700 ps
CPU time 148.02 seconds
Started Sep 18 05:36:50 PM UTC 24
Finished Sep 18 05:39:21 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1218413124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.1218413124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.3365155704
Short name T635
Test name
Test status
Simulation time 45262500 ps
CPU time 27.49 seconds
Started Sep 18 05:41:45 PM UTC 24
Finished Sep 18 05:42:14 PM UTC 24
Peak memory 275196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365155704 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.3365155704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.3008181507
Short name T630
Test name
Test status
Simulation time 13544700 ps
CPU time 27.67 seconds
Started Sep 18 05:41:25 PM UTC 24
Finished Sep 18 05:41:54 PM UTC 24
Peak memory 284872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008181507 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.3008181507
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.902370646
Short name T637
Test name
Test status
Simulation time 10025980000 ps
CPU time 84.72 seconds
Started Sep 18 05:41:40 PM UTC 24
Finished Sep 18 05:43:06 PM UTC 24
Peak memory 308276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=902370646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.902370646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1277412831
Short name T423
Test name
Test status
Simulation time 160181365100 ps
CPU time 821.88 seconds
Started Sep 18 05:39:18 PM UTC 24
Finished Sep 18 05:53:10 PM UTC 24
Peak memory 275236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1277412831
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res
et.1277412831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.3343089245
Short name T634
Test name
Test status
Simulation time 26750369700 ps
CPU time 162.99 seconds
Started Sep 18 05:39:16 PM UTC 24
Finished Sep 18 05:42:02 PM UTC 24
Peak memory 273292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343089245 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.3343089245
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.1190059273
Short name T364
Test name
Test status
Simulation time 545201900 ps
CPU time 124.58 seconds
Started Sep 18 05:40:14 PM UTC 24
Finished Sep 18 05:42:21 PM UTC 24
Peak memory 306096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190059273 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.1190059273
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.751361492
Short name T650
Test name
Test status
Simulation time 12302196900 ps
CPU time 256.06 seconds
Started Sep 18 05:40:19 PM UTC 24
Finished Sep 18 05:44:39 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=751361492 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 11.flash_ctrl_intr_rd_slow_flash.751361492
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.326602268
Short name T626
Test name
Test status
Simulation time 1881419400 ps
CPU time 84.36 seconds
Started Sep 18 05:39:31 PM UTC 24
Finished Sep 18 05:40:57 PM UTC 24
Peak memory 270924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326602268 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.326602268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.2144643560
Short name T633
Test name
Test status
Simulation time 15341300 ps
CPU time 23.14 seconds
Started Sep 18 05:41:36 PM UTC 24
Finished Sep 18 05:42:00 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2144643560 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_lcmgr_intg.2144643560
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.3255794624
Short name T151
Test name
Test status
Simulation time 39355946200 ps
CPU time 305.62 seconds
Started Sep 18 05:39:24 PM UTC 24
Finished Sep 18 05:44:33 PM UTC 24
Peak memory 283564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3255794624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 11.flash_ctrl_mp_regions.3255794624
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.3656351486
Short name T188
Test name
Test status
Simulation time 42402800 ps
CPU time 161.19 seconds
Started Sep 18 05:39:22 PM UTC 24
Finished Sep 18 05:42:05 PM UTC 24
Peak memory 275700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3656351486 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.3656351486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.3427490797
Short name T657
Test name
Test status
Simulation time 693480900 ps
CPU time 353.35 seconds
Started Sep 18 05:39:16 PM UTC 24
Finished Sep 18 05:45:15 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427490797 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3427490797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_prog_reset.4196697022
Short name T625
Test name
Test status
Simulation time 19870200 ps
CPU time 23.45 seconds
Started Sep 18 05:40:24 PM UTC 24
Finished Sep 18 05:40:49 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196697022 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_prog_reset.4196697022
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1127628151
Short name T734
Test name
Test status
Simulation time 97906300 ps
CPU time 908.1 seconds
Started Sep 18 05:39:11 PM UTC 24
Finished Sep 18 05:54:30 PM UTC 24
Peak memory 293580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127628151 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.1127628151
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1552359834
Short name T344
Test name
Test status
Simulation time 71619200 ps
CPU time 55.66 seconds
Started Sep 18 05:40:50 PM UTC 24
Finished Sep 18 05:41:47 PM UTC 24
Peak memory 287608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1552359834 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.1552359834
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.2722751105
Short name T631
Test name
Test status
Simulation time 2991042900 ps
CPU time 127.54 seconds
Started Sep 18 05:39:45 PM UTC 24
Finished Sep 18 05:41:55 PM UTC 24
Peak memory 291864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2722751105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.2722751105
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.292974264
Short name T668
Test name
Test status
Simulation time 5478510400 ps
CPU time 410.01 seconds
Started Sep 18 05:39:48 PM UTC 24
Finished Sep 18 05:46:44 PM UTC 24
Peak memory 320524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292974264 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.292974264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.578786202
Short name T461
Test name
Test status
Simulation time 265667100 ps
CPU time 55.69 seconds
Started Sep 18 05:40:37 PM UTC 24
Finished Sep 18 05:41:35 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578786202 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.578786202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict_all_en.3533214524
Short name T628
Test name
Test status
Simulation time 110799800 ps
CPU time 52.16 seconds
Started Sep 18 05:40:50 PM UTC 24
Finished Sep 18 05:41:44 PM UTC 24
Peak memory 281532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3533214524 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_c
trl_rw_evict_all_en.3533214524
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.1533861246
Short name T409
Test name
Test status
Simulation time 2116349100 ps
CPU time 116.52 seconds
Started Sep 18 05:41:17 PM UTC 24
Finished Sep 18 05:43:16 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533861246 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.1533861246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.683324025
Short name T629
Test name
Test status
Simulation time 53965800 ps
CPU time 153.9 seconds
Started Sep 18 05:39:09 PM UTC 24
Finished Sep 18 05:41:45 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683324025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.683324025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_wo.503894392
Short name T639
Test name
Test status
Simulation time 8939483200 ps
CPU time 222.13 seconds
Started Sep 18 05:39:44 PM UTC 24
Finished Sep 18 05:43:30 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=503894392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_wo.503894392
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/11.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.1854566665
Short name T656
Test name
Test status
Simulation time 84840600 ps
CPU time 23.02 seconds
Started Sep 18 05:44:34 PM UTC 24
Finished Sep 18 05:44:58 PM UTC 24
Peak memory 275196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854566665 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.1854566665
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.648757472
Short name T649
Test name
Test status
Simulation time 28859600 ps
CPU time 31.18 seconds
Started Sep 18 05:44:02 PM UTC 24
Finished Sep 18 05:44:35 PM UTC 24
Peak memory 294924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648757472 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.648757472
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.1383642676
Short name T397
Test name
Test status
Simulation time 10485700 ps
CPU time 38.16 seconds
Started Sep 18 05:43:53 PM UTC 24
Finished Sep 18 05:44:32 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1383642676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_
ctrl_disable.1383642676
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.883524922
Short name T674
Test name
Test status
Simulation time 10011752800 ps
CPU time 168.87 seconds
Started Sep 18 05:44:18 PM UTC 24
Finished Sep 18 05:47:09 PM UTC 24
Peak memory 316272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=883524922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.883524922
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.1178036060
Short name T651
Test name
Test status
Simulation time 103640800 ps
CPU time 24.31 seconds
Started Sep 18 05:44:14 PM UTC 24
Finished Sep 18 05:44:40 PM UTC 24
Peak memory 269512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1178036060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
12.flash_ctrl_hw_read_seed_err.1178036060
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.377221679
Short name T640
Test name
Test status
Simulation time 4266793000 ps
CPU time 97.16 seconds
Started Sep 18 05:41:56 PM UTC 24
Finished Sep 18 05:43:35 PM UTC 24
Peak memory 273288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=377221679 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.377221679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3795248462
Short name T676
Test name
Test status
Simulation time 4964997200 ps
CPU time 264.76 seconds
Started Sep 18 05:43:07 PM UTC 24
Finished Sep 18 05:47:36 PM UTC 24
Peak memory 302004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795248462 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.3795248462
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.2253114372
Short name T661
Test name
Test status
Simulation time 7949884100 ps
CPU time 156.35 seconds
Started Sep 18 05:43:17 PM UTC 24
Finished Sep 18 05:45:56 PM UTC 24
Peak memory 304160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2253114372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_intr_rd_slow_flash.2253114372
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.1482004920
Short name T643
Test name
Test status
Simulation time 1640702400 ps
CPU time 104.71 seconds
Started Sep 18 05:42:07 PM UTC 24
Finished Sep 18 05:43:54 PM UTC 24
Peak memory 270916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482004920 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.1482004920
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.2329943998
Short name T648
Test name
Test status
Simulation time 45878300 ps
CPU time 25.06 seconds
Started Sep 18 05:44:08 PM UTC 24
Finished Sep 18 05:44:35 PM UTC 24
Peak memory 273220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2329943998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_lcmgr_intg.2329943998
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.886155316
Short name T658
Test name
Test status
Simulation time 7628406700 ps
CPU time 193.39 seconds
Started Sep 18 05:42:02 PM UTC 24
Finished Sep 18 05:45:19 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=886155316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 12.flash_ctrl_mp_regions.886155316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.2117779737
Short name T655
Test name
Test status
Simulation time 99543000 ps
CPU time 180.05 seconds
Started Sep 18 05:41:55 PM UTC 24
Finished Sep 18 05:44:58 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117779737 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.2117779737
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.1295518616
Short name T642
Test name
Test status
Simulation time 137482800 ps
CPU time 28.56 seconds
Started Sep 18 05:43:22 PM UTC 24
Finished Sep 18 05:43:52 PM UTC 24
Peak memory 275236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295518616 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.1295518616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.3983014044
Short name T1023
Test name
Test status
Simulation time 956606700 ps
CPU time 1824.11 seconds
Started Sep 18 05:41:48 PM UTC 24
Finished Sep 18 06:12:31 PM UTC 24
Peak memory 293836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983014044 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.3983014044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.2402401642
Short name T653
Test name
Test status
Simulation time 62762200 ps
CPU time 56.87 seconds
Started Sep 18 05:43:46 PM UTC 24
Finished Sep 18 05:44:44 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402401642 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.2402401642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.1831154574
Short name T652
Test name
Test status
Simulation time 10418305200 ps
CPU time 138.73 seconds
Started Sep 18 05:42:22 PM UTC 24
Finished Sep 18 05:44:43 PM UTC 24
Peak memory 291872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1831154574 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.1831154574
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.1023209633
Short name T699
Test name
Test status
Simulation time 3141227700 ps
CPU time 424.19 seconds
Started Sep 18 05:42:51 PM UTC 24
Finished Sep 18 05:50:01 PM UTC 24
Peak memory 332812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023209633 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.1023209633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.1727757214
Short name T646
Test name
Test status
Simulation time 30988500 ps
CPU time 42.07 seconds
Started Sep 18 05:43:30 PM UTC 24
Finished Sep 18 05:44:14 PM UTC 24
Peak memory 287704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1727757214 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.1727757214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.319623720
Short name T647
Test name
Test status
Simulation time 29810500 ps
CPU time 38.9 seconds
Started Sep 18 05:43:37 PM UTC 24
Finished Sep 18 05:44:17 PM UTC 24
Peak memory 285856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=319623720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ct
rl_rw_evict_all_en.319623720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.938132730
Short name T659
Test name
Test status
Simulation time 568049000 ps
CPU time 94.98 seconds
Started Sep 18 05:43:54 PM UTC 24
Finished Sep 18 05:45:31 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938132730 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.938132730
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.1824238701
Short name T645
Test name
Test status
Simulation time 37088500 ps
CPU time 138.74 seconds
Started Sep 18 05:41:46 PM UTC 24
Finished Sep 18 05:44:07 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824238701 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1824238701
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.641972952
Short name T670
Test name
Test status
Simulation time 62208500 ps
CPU time 17.55 seconds
Started Sep 18 05:46:27 PM UTC 24
Finished Sep 18 05:46:46 PM UTC 24
Peak memory 269192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641972952 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.641972952
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.1224572771
Short name T666
Test name
Test status
Simulation time 43754400 ps
CPU time 21.44 seconds
Started Sep 18 05:46:17 PM UTC 24
Finished Sep 18 05:46:40 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224572771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.1224572771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.3222078378
Short name T208
Test name
Test status
Simulation time 26524300 ps
CPU time 27.41 seconds
Started Sep 18 05:45:57 PM UTC 24
Finished Sep 18 05:46:26 PM UTC 24
Peak memory 285608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3222078378 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_
ctrl_disable.3222078378
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.104066025
Short name T695
Test name
Test status
Simulation time 10012225600 ps
CPU time 182.23 seconds
Started Sep 18 05:46:27 PM UTC 24
Finished Sep 18 05:49:32 PM UTC 24
Peak memory 394072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=104066025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.104066025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.3860305796
Short name T667
Test name
Test status
Simulation time 25813900 ps
CPU time 15.51 seconds
Started Sep 18 05:46:25 PM UTC 24
Finished Sep 18 05:46:42 PM UTC 24
Peak memory 275508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3860305796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
13.flash_ctrl_hw_read_seed_err.3860305796
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.3269308608
Short name T671
Test name
Test status
Simulation time 4594647300 ps
CPU time 142.19 seconds
Started Sep 18 05:44:39 PM UTC 24
Finished Sep 18 05:47:04 PM UTC 24
Peak memory 271244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269308608 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.3269308608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.1799542793
Short name T684
Test name
Test status
Simulation time 1687711800 ps
CPU time 222.53 seconds
Started Sep 18 05:45:03 PM UTC 24
Finished Sep 18 05:48:49 PM UTC 24
Peak memory 302004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1799542793 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.1799542793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1679926420
Short name T337
Test name
Test status
Simulation time 43732060100 ps
CPU time 209.47 seconds
Started Sep 18 05:45:15 PM UTC 24
Finished Sep 18 05:48:48 PM UTC 24
Peak memory 303904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1679926420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_intr_rd_slow_flash.1679926420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.1850404128
Short name T663
Test name
Test status
Simulation time 3018613900 ps
CPU time 81.33 seconds
Started Sep 18 05:44:53 PM UTC 24
Finished Sep 18 05:46:16 PM UTC 24
Peak memory 270916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850404128 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.1850404128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.2207181647
Short name T669
Test name
Test status
Simulation time 15457600 ps
CPU time 25.84 seconds
Started Sep 18 05:46:17 PM UTC 24
Finished Sep 18 05:46:44 PM UTC 24
Peak memory 271204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2207181647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_lcmgr_intg.2207181647
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.4098096235
Short name T672
Test name
Test status
Simulation time 3700811100 ps
CPU time 137.55 seconds
Started Sep 18 05:44:46 PM UTC 24
Finished Sep 18 05:47:06 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4098096235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_mp_regions.4098096235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.1063191000
Short name T98
Test name
Test status
Simulation time 79462700 ps
CPU time 206.26 seconds
Started Sep 18 05:44:43 PM UTC 24
Finished Sep 18 05:48:13 PM UTC 24
Peak memory 271272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063191000 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.1063191000
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.2495024349
Short name T721
Test name
Test status
Simulation time 712983400 ps
CPU time 491.86 seconds
Started Sep 18 05:44:36 PM UTC 24
Finished Sep 18 05:52:55 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495024349 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.2495024349
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.1723036139
Short name T660
Test name
Test status
Simulation time 118454900 ps
CPU time 24.52 seconds
Started Sep 18 05:45:21 PM UTC 24
Finished Sep 18 05:45:47 PM UTC 24
Peak memory 275272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723036139 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.1723036139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.2284075876
Short name T770
Test name
Test status
Simulation time 253994800 ps
CPU time 820.95 seconds
Started Sep 18 05:44:36 PM UTC 24
Finished Sep 18 05:58:27 PM UTC 24
Peak memory 291532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284075876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.2284075876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.2492684917
Short name T664
Test name
Test status
Simulation time 66577200 ps
CPU time 38.32 seconds
Started Sep 18 05:45:47 PM UTC 24
Finished Sep 18 05:46:27 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2492684917 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.2492684917
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1904503963
Short name T116
Test name
Test status
Simulation time 1168854300 ps
CPU time 132.66 seconds
Started Sep 18 05:44:59 PM UTC 24
Finished Sep 18 05:47:14 PM UTC 24
Peak memory 304352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1904503963 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.1904503963
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.994161608
Short name T730
Test name
Test status
Simulation time 10568118500 ps
CPU time 539.81 seconds
Started Sep 18 05:45:01 PM UTC 24
Finished Sep 18 05:54:08 PM UTC 24
Peak memory 330808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994161608 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.994161608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.2136502824
Short name T662
Test name
Test status
Simulation time 28147300 ps
CPU time 43.49 seconds
Started Sep 18 05:45:31 PM UTC 24
Finished Sep 18 05:46:16 PM UTC 24
Peak memory 287772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136502824 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.2136502824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.3542544421
Short name T451
Test name
Test status
Simulation time 78567700 ps
CPU time 50.53 seconds
Started Sep 18 05:45:32 PM UTC 24
Finished Sep 18 05:46:24 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3542544421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw_evict_all_en.3542544421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.55913793
Short name T437
Test name
Test status
Simulation time 2053827200 ps
CPU time 80.86 seconds
Started Sep 18 05:46:11 PM UTC 24
Finished Sep 18 05:47:33 PM UTC 24
Peak memory 273104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55913793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.55913793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.3552195671
Short name T692
Test name
Test status
Simulation time 78228200 ps
CPU time 267.4 seconds
Started Sep 18 05:44:35 PM UTC 24
Finished Sep 18 05:49:07 PM UTC 24
Peak memory 289480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552195671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.3552195671
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.2275299861
Short name T683
Test name
Test status
Simulation time 2555268300 ps
CPU time 225.65 seconds
Started Sep 18 05:44:59 PM UTC 24
Finished Sep 18 05:48:48 PM UTC 24
Peak memory 270828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2275299861 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.2275299861
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.2486430121
Short name T694
Test name
Test status
Simulation time 94027400 ps
CPU time 22.89 seconds
Started Sep 18 05:48:48 PM UTC 24
Finished Sep 18 05:49:13 PM UTC 24
Peak memory 269048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486430121 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.2486430121
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.3482365090
Short name T685
Test name
Test status
Simulation time 50837100 ps
CPU time 25.21 seconds
Started Sep 18 05:48:23 PM UTC 24
Finished Sep 18 05:48:49 PM UTC 24
Peak memory 294988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482365090 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.3482365090
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1257362176
Short name T749
Test name
Test status
Simulation time 10012374300 ps
CPU time 405.02 seconds
Started Sep 18 05:48:41 PM UTC 24
Finished Sep 18 05:55:32 PM UTC 24
Peak memory 344844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1257362176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1257362176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.2495245473
Short name T687
Test name
Test status
Simulation time 15294100 ps
CPU time 18.76 seconds
Started Sep 18 05:48:39 PM UTC 24
Finished Sep 18 05:48:59 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2495245473 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
14.flash_ctrl_hw_read_seed_err.2495245473
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.226411594
Short name T788
Test name
Test status
Simulation time 40120031100 ps
CPU time 802.96 seconds
Started Sep 18 05:46:45 PM UTC 24
Finished Sep 18 06:00:17 PM UTC 24
Peak memory 275236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226411594 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_reset.226411594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.3269468512
Short name T693
Test name
Test status
Simulation time 6958860500 ps
CPU time 144.94 seconds
Started Sep 18 05:46:45 PM UTC 24
Finished Sep 18 05:49:12 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3269468512 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.3269468512
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.2778773325
Short name T371
Test name
Test status
Simulation time 4048731000 ps
CPU time 188.03 seconds
Started Sep 18 05:47:34 PM UTC 24
Finished Sep 18 05:50:45 PM UTC 24
Peak memory 301996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778773325 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.2778773325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.964407798
Short name T697
Test name
Test status
Simulation time 116085568000 ps
CPU time 137.24 seconds
Started Sep 18 05:47:36 PM UTC 24
Finished Sep 18 05:49:56 PM UTC 24
Peak memory 303936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=964407798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 14.flash_ctrl_intr_rd_slow_flash.964407798
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.3447016743
Short name T681
Test name
Test status
Simulation time 3385377000 ps
CPU time 89.79 seconds
Started Sep 18 05:47:07 PM UTC 24
Finished Sep 18 05:48:38 PM UTC 24
Peak memory 272960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447016743 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.3447016743
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.1951378344
Short name T688
Test name
Test status
Simulation time 15106500 ps
CPU time 22.75 seconds
Started Sep 18 05:48:38 PM UTC 24
Finished Sep 18 05:49:02 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1951378344 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_lcmgr_intg.1951378344
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.1258768348
Short name T166
Test name
Test status
Simulation time 82800807100 ps
CPU time 593.78 seconds
Started Sep 18 05:47:05 PM UTC 24
Finished Sep 18 05:57:06 PM UTC 24
Peak memory 283336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1258768348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_mp_regions.1258768348
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.2260028935
Short name T705
Test name
Test status
Simulation time 45853700 ps
CPU time 232.68 seconds
Started Sep 18 05:46:47 PM UTC 24
Finished Sep 18 05:50:43 PM UTC 24
Peak memory 271464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260028935 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.2260028935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.440645510
Short name T682
Test name
Test status
Simulation time 26751900 ps
CPU time 115.75 seconds
Started Sep 18 05:46:43 PM UTC 24
Finished Sep 18 05:48:41 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440645510 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.440645510
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.1575994994
Short name T677
Test name
Test status
Simulation time 19772800 ps
CPU time 16.75 seconds
Started Sep 18 05:47:37 PM UTC 24
Finished Sep 18 05:47:55 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575994994 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.1575994994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.3194036072
Short name T858
Test name
Test status
Simulation time 9299361900 ps
CPU time 1094.7 seconds
Started Sep 18 05:46:41 PM UTC 24
Finished Sep 18 06:05:07 PM UTC 24
Peak memory 293772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3194036072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.3194036072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.3676641831
Short name T691
Test name
Test status
Simulation time 364128400 ps
CPU time 52.09 seconds
Started Sep 18 05:48:14 PM UTC 24
Finished Sep 18 05:49:07 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676641831 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.3676641831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.2949780206
Short name T690
Test name
Test status
Simulation time 571636900 ps
CPU time 113.02 seconds
Started Sep 18 05:47:10 PM UTC 24
Finished Sep 18 05:49:05 PM UTC 24
Peak memory 291724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2949780206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.2949780206
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.2626668491
Short name T737
Test name
Test status
Simulation time 36668055900 ps
CPU time 444.05 seconds
Started Sep 18 05:47:15 PM UTC 24
Finished Sep 18 05:54:45 PM UTC 24
Peak memory 330952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626668491 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw.2626668491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.1659899062
Short name T686
Test name
Test status
Simulation time 77905000 ps
CPU time 52.02 seconds
Started Sep 18 05:47:56 PM UTC 24
Finished Sep 18 05:48:50 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659899062 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.1659899062
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.448100381
Short name T680
Test name
Test status
Simulation time 50872500 ps
CPU time 38.33 seconds
Started Sep 18 05:47:57 PM UTC 24
Finished Sep 18 05:48:37 PM UTC 24
Peak memory 287612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=448100381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ct
rl_rw_evict_all_en.448100381
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.2290617260
Short name T696
Test name
Test status
Simulation time 1579118300 ps
CPU time 90.17 seconds
Started Sep 18 05:48:17 PM UTC 24
Finished Sep 18 05:49:49 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290617260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.2290617260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.1842212059
Short name T679
Test name
Test status
Simulation time 68353600 ps
CPU time 111.9 seconds
Started Sep 18 05:46:28 PM UTC 24
Finished Sep 18 05:48:23 PM UTC 24
Peak memory 287488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842212059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.1842212059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.414252916
Short name T711
Test name
Test status
Simulation time 4000542300 ps
CPU time 268.52 seconds
Started Sep 18 05:47:08 PM UTC 24
Finished Sep 18 05:51:40 PM UTC 24
Peak memory 271180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=414252916 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.414252916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.2511939138
Short name T709
Test name
Test status
Simulation time 44644600 ps
CPU time 22.02 seconds
Started Sep 18 05:50:32 PM UTC 24
Finished Sep 18 05:50:55 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511939138 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.2511939138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.1994714889
Short name T700
Test name
Test status
Simulation time 26968700 ps
CPU time 19.5 seconds
Started Sep 18 05:50:02 PM UTC 24
Finished Sep 18 05:50:23 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994714889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1994714889
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.2581303108
Short name T209
Test name
Test status
Simulation time 11655300 ps
CPU time 25.82 seconds
Started Sep 18 05:49:56 PM UTC 24
Finished Sep 18 05:50:23 PM UTC 24
Peak memory 285672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2581303108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_
ctrl_disable.2581303108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2102827072
Short name T325
Test name
Test status
Simulation time 10012810600 ps
CPU time 212.01 seconds
Started Sep 18 05:50:24 PM UTC 24
Finished Sep 18 05:54:00 PM UTC 24
Peak memory 369564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2102827072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.2102827072
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.3182217907
Short name T704
Test name
Test status
Simulation time 15168200 ps
CPU time 17.43 seconds
Started Sep 18 05:50:24 PM UTC 24
Finished Sep 18 05:50:43 PM UTC 24
Peak memory 269300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3182217907 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
15.flash_ctrl_hw_read_seed_err.3182217907
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.26683044
Short name T176
Test name
Test status
Simulation time 40127954700 ps
CPU time 743.91 seconds
Started Sep 18 05:48:51 PM UTC 24
Finished Sep 18 06:01:23 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26683044 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_reset.26683044
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.1131974598
Short name T701
Test name
Test status
Simulation time 2881557700 ps
CPU time 97.7 seconds
Started Sep 18 05:48:51 PM UTC 24
Finished Sep 18 05:50:31 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131974598 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.1131974598
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.4119132708
Short name T715
Test name
Test status
Simulation time 674466700 ps
CPU time 172.26 seconds
Started Sep 18 05:49:14 PM UTC 24
Finished Sep 18 05:52:09 PM UTC 24
Peak memory 302028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119132708 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.4119132708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2601691712
Short name T718
Test name
Test status
Simulation time 100780138100 ps
CPU time 206.63 seconds
Started Sep 18 05:49:14 PM UTC 24
Finished Sep 18 05:52:44 PM UTC 24
Peak memory 303900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2601691712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_intr_rd_slow_flash.2601691712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1928264546
Short name T229
Test name
Test status
Simulation time 10589600700 ps
CPU time 70.37 seconds
Started Sep 18 05:49:03 PM UTC 24
Finished Sep 18 05:50:15 PM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928264546 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.1928264546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.2545190754
Short name T703
Test name
Test status
Simulation time 27882700 ps
CPU time 17.98 seconds
Started Sep 18 05:50:17 PM UTC 24
Finished Sep 18 05:50:36 PM UTC 24
Peak memory 275292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2545190754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.fla
sh_ctrl_lcmgr_intg.2545190754
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.643806831
Short name T865
Test name
Test status
Simulation time 39493753600 ps
CPU time 974.57 seconds
Started Sep 18 05:49:03 PM UTC 24
Finished Sep 18 06:05:29 PM UTC 24
Peak memory 283320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=643806831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 15.flash_ctrl_mp_regions.643806831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.1609207170
Short name T183
Test name
Test status
Simulation time 144387200 ps
CPU time 222.51 seconds
Started Sep 18 05:49:00 PM UTC 24
Finished Sep 18 05:52:47 PM UTC 24
Peak memory 271272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609207170 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.1609207170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.4290444876
Short name T772
Test name
Test status
Simulation time 2106005300 ps
CPU time 578.23 seconds
Started Sep 18 05:48:50 PM UTC 24
Finished Sep 18 05:58:35 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290444876 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.4290444876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.2487426345
Short name T698
Test name
Test status
Simulation time 31189400 ps
CPU time 21.55 seconds
Started Sep 18 05:49:34 PM UTC 24
Finished Sep 18 05:49:56 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487426345 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.2487426345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.2006502181
Short name T793
Test name
Test status
Simulation time 1530477000 ps
CPU time 693.55 seconds
Started Sep 18 05:48:50 PM UTC 24
Finished Sep 18 06:00:32 PM UTC 24
Peak memory 289676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006502181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.2006502181
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.1621550145
Short name T443
Test name
Test status
Simulation time 70697000 ps
CPU time 54.3 seconds
Started Sep 18 05:49:50 PM UTC 24
Finished Sep 18 05:50:46 PM UTC 24
Peak memory 285916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621550145 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.1621550145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.454294688
Short name T708
Test name
Test status
Simulation time 1103190500 ps
CPU time 102.78 seconds
Started Sep 18 05:49:08 PM UTC 24
Finished Sep 18 05:50:53 PM UTC 24
Peak memory 302056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=454294688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.454294688
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.3704445951
Short name T702
Test name
Test status
Simulation time 71893000 ps
CPU time 47.89 seconds
Started Sep 18 05:49:44 PM UTC 24
Finished Sep 18 05:50:33 PM UTC 24
Peak memory 287608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704445951 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.3704445951
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.1735369648
Short name T706
Test name
Test status
Simulation time 40184900 ps
CPU time 59.54 seconds
Started Sep 18 05:49:49 PM UTC 24
Finished Sep 18 05:50:50 PM UTC 24
Peak memory 279680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1735369648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw_evict_all_en.1735369648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.2535944756
Short name T710
Test name
Test status
Simulation time 17793107800 ps
CPU time 83.18 seconds
Started Sep 18 05:49:57 PM UTC 24
Finished Sep 18 05:51:22 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535944756 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.2535944756
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.2360711345
Short name T729
Test name
Test status
Simulation time 37325200 ps
CPU time 300.26 seconds
Started Sep 18 05:48:49 PM UTC 24
Finished Sep 18 05:53:53 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360711345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.2360711345
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.1374386710
Short name T720
Test name
Test status
Simulation time 4329174600 ps
CPU time 223.16 seconds
Started Sep 18 05:49:05 PM UTC 24
Finished Sep 18 05:52:53 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1374386710 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.1374386710
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.917180573
Short name T726
Test name
Test status
Simulation time 100867400 ps
CPU time 19.43 seconds
Started Sep 18 05:52:56 PM UTC 24
Finished Sep 18 05:53:17 PM UTC 24
Peak memory 268992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917180573 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.917180573
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.3591645116
Short name T724
Test name
Test status
Simulation time 51277500 ps
CPU time 20.83 seconds
Started Sep 18 05:52:48 PM UTC 24
Finished Sep 18 05:53:10 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3591645116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.3591645116
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.3982060590
Short name T728
Test name
Test status
Simulation time 58816600 ps
CPU time 38.89 seconds
Started Sep 18 05:52:41 PM UTC 24
Finished Sep 18 05:53:21 PM UTC 24
Peak memory 285712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3982060590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_
ctrl_disable.3982060590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.880156358
Short name T744
Test name
Test status
Simulation time 10011950300 ps
CPU time 136.81 seconds
Started Sep 18 05:52:56 PM UTC 24
Finished Sep 18 05:55:15 PM UTC 24
Peak memory 340776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=880156358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.880156358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3991147111
Short name T727
Test name
Test status
Simulation time 25632200 ps
CPU time 24.07 seconds
Started Sep 18 05:52:54 PM UTC 24
Finished Sep 18 05:53:19 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3991147111 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
16.flash_ctrl_hw_read_seed_err.3991147111
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.2997729200
Short name T863
Test name
Test status
Simulation time 40127026200 ps
CPU time 867.01 seconds
Started Sep 18 05:50:46 PM UTC 24
Finished Sep 18 06:05:23 PM UTC 24
Peak memory 275036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997729200
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res
et.2997729200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.2825805008
Short name T712
Test name
Test status
Simulation time 1723725700 ps
CPU time 54.02 seconds
Started Sep 18 05:50:44 PM UTC 24
Finished Sep 18 05:51:40 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825805008 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.2825805008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.4121393752
Short name T358
Test name
Test status
Simulation time 549024700 ps
CPU time 124.98 seconds
Started Sep 18 05:51:42 PM UTC 24
Finished Sep 18 05:53:49 PM UTC 24
Peak memory 306092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121393752 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.4121393752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.243017639
Short name T741
Test name
Test status
Simulation time 11905356900 ps
CPU time 204.81 seconds
Started Sep 18 05:51:42 PM UTC 24
Finished Sep 18 05:55:10 PM UTC 24
Peak memory 301896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=243017639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 16.flash_ctrl_intr_rd_slow_flash.243017639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.2831673641
Short name T719
Test name
Test status
Simulation time 865252600 ps
CPU time 112.13 seconds
Started Sep 18 05:50:52 PM UTC 24
Finished Sep 18 05:52:46 PM UTC 24
Peak memory 270912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831673641 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2831673641
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.290277922
Short name T725
Test name
Test status
Simulation time 25363700 ps
CPU time 23.74 seconds
Started Sep 18 05:52:48 PM UTC 24
Finished Sep 18 05:53:13 PM UTC 24
Peak memory 271204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=290277922 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flas
h_ctrl_lcmgr_intg.290277922
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.3912536603
Short name T439
Test name
Test status
Simulation time 16425557500 ps
CPU time 631.25 seconds
Started Sep 18 05:50:51 PM UTC 24
Finished Sep 18 06:01:30 PM UTC 24
Peak memory 283372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3912536603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 16.flash_ctrl_mp_regions.3912536603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.3685139721
Short name T189
Test name
Test status
Simulation time 75200000 ps
CPU time 131.2 seconds
Started Sep 18 05:50:47 PM UTC 24
Finished Sep 18 05:53:00 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685139721 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.3685139721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.3838932865
Short name T765
Test name
Test status
Simulation time 72099800 ps
CPU time 399.14 seconds
Started Sep 18 05:50:43 PM UTC 24
Finished Sep 18 05:57:28 PM UTC 24
Peak memory 275464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838932865 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.3838932865
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.948605554
Short name T716
Test name
Test status
Simulation time 59924200 ps
CPU time 30.53 seconds
Started Sep 18 05:51:43 PM UTC 24
Finished Sep 18 05:52:15 PM UTC 24
Peak memory 275452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948605554 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.948605554
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.3793981980
Short name T806
Test name
Test status
Simulation time 83030000 ps
CPU time 665.52 seconds
Started Sep 18 05:50:36 PM UTC 24
Finished Sep 18 06:01:50 PM UTC 24
Peak memory 289480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793981980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.3793981980
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.3305670885
Short name T723
Test name
Test status
Simulation time 61475700 ps
CPU time 47.96 seconds
Started Sep 18 05:52:15 PM UTC 24
Finished Sep 18 05:53:05 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305670885 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.3305670885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.587451646
Short name T722
Test name
Test status
Simulation time 798699100 ps
CPU time 117.12 seconds
Started Sep 18 05:50:56 PM UTC 24
Finished Sep 18 05:52:55 PM UTC 24
Peak memory 291748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=587451646 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.587451646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.1206103200
Short name T785
Test name
Test status
Simulation time 7839328000 ps
CPU time 493.93 seconds
Started Sep 18 05:51:23 PM UTC 24
Finished Sep 18 05:59:43 PM UTC 24
Peak memory 320532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206103200 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.1206103200
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.3073815220
Short name T717
Test name
Test status
Simulation time 40947200 ps
CPU time 51.93 seconds
Started Sep 18 05:51:47 PM UTC 24
Finished Sep 18 05:52:40 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073815220 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.3073815220
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.2748406994
Short name T457
Test name
Test status
Simulation time 73524600 ps
CPU time 58.32 seconds
Started Sep 18 05:52:10 PM UTC 24
Finished Sep 18 05:53:10 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2748406994 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw_evict_all_en.2748406994
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3747223615
Short name T731
Test name
Test status
Simulation time 1347023600 ps
CPU time 88.95 seconds
Started Sep 18 05:52:44 PM UTC 24
Finished Sep 18 05:54:15 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3747223615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3747223615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.4232684653
Short name T714
Test name
Test status
Simulation time 136121700 ps
CPU time 69.76 seconds
Started Sep 18 05:50:34 PM UTC 24
Finished Sep 18 05:51:46 PM UTC 24
Peak memory 277192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232684653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.4232684653
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.1172340571
Short name T736
Test name
Test status
Simulation time 5354003300 ps
CPU time 219.15 seconds
Started Sep 18 05:50:54 PM UTC 24
Finished Sep 18 05:54:36 PM UTC 24
Peak memory 273204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1172340571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.1172340571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.2683885422
Short name T746
Test name
Test status
Simulation time 31026100 ps
CPU time 17.4 seconds
Started Sep 18 05:55:07 PM UTC 24
Finished Sep 18 05:55:26 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683885422 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.2683885422
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.2320572661
Short name T739
Test name
Test status
Simulation time 23970200 ps
CPU time 22.81 seconds
Started Sep 18 05:54:37 PM UTC 24
Finished Sep 18 05:55:01 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320572661 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2320572661
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.4105745596
Short name T398
Test name
Test status
Simulation time 41009000 ps
CPU time 43.96 seconds
Started Sep 18 05:54:31 PM UTC 24
Finished Sep 18 05:55:16 PM UTC 24
Peak memory 285744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4105745596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_
ctrl_disable.4105745596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.2994916822
Short name T745
Test name
Test status
Simulation time 15730700 ps
CPU time 16.81 seconds
Started Sep 18 05:55:00 PM UTC 24
Finished Sep 18 05:55:18 PM UTC 24
Peak memory 275248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2994916822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
17.flash_ctrl_hw_read_seed_err.2994916822
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.661899696
Short name T913
Test name
Test status
Simulation time 40121562800 ps
CPU time 881.13 seconds
Started Sep 18 05:53:11 PM UTC 24
Finished Sep 18 06:08:03 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=661899696 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_reset.661899696
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.1703548253
Short name T733
Test name
Test status
Simulation time 1603788100 ps
CPU time 72.39 seconds
Started Sep 18 05:53:11 PM UTC 24
Finished Sep 18 05:54:25 PM UTC 24
Peak memory 271052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703548253 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.1703548253
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1276337108
Short name T752
Test name
Test status
Simulation time 564386000 ps
CPU time 121.7 seconds
Started Sep 18 05:54:01 PM UTC 24
Finished Sep 18 05:56:05 PM UTC 24
Peak memory 306132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276337108 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.1276337108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1427795876
Short name T769
Test name
Test status
Simulation time 26874538900 ps
CPU time 242.19 seconds
Started Sep 18 05:54:01 PM UTC 24
Finished Sep 18 05:58:07 PM UTC 24
Peak memory 305952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1427795876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 17.flash_ctrl_intr_rd_slow_flash.1427795876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.722325662
Short name T732
Test name
Test status
Simulation time 6305849200 ps
CPU time 59.5 seconds
Started Sep 18 05:53:20 PM UTC 24
Finished Sep 18 05:54:21 PM UTC 24
Peak memory 270924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722325662 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.722325662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.37282650
Short name T743
Test name
Test status
Simulation time 15787300 ps
CPU time 25.04 seconds
Started Sep 18 05:54:45 PM UTC 24
Finished Sep 18 05:55:11 PM UTC 24
Peak memory 271136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=37282650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash
_ctrl_lcmgr_intg.37282650
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.2371124139
Short name T753
Test name
Test status
Simulation time 7525037500 ps
CPU time 184.12 seconds
Started Sep 18 05:53:18 PM UTC 24
Finished Sep 18 05:56:25 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2371124139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_mp_regions.2371124139
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.1020207621
Short name T190
Test name
Test status
Simulation time 75152100 ps
CPU time 235.07 seconds
Started Sep 18 05:53:13 PM UTC 24
Finished Sep 18 05:57:12 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020207621 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.1020207621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.1598912910
Short name T755
Test name
Test status
Simulation time 40891300 ps
CPU time 207.86 seconds
Started Sep 18 05:53:10 PM UTC 24
Finished Sep 18 05:56:41 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598912910 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.1598912910
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.3381740108
Short name T735
Test name
Test status
Simulation time 21518900 ps
CPU time 20.56 seconds
Started Sep 18 05:54:09 PM UTC 24
Finished Sep 18 05:54:31 PM UTC 24
Peak memory 271432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3381740108 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.3381740108
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.3082436337
Short name T1042
Test name
Test status
Simulation time 3090866000 ps
CPU time 1192.47 seconds
Started Sep 18 05:53:05 PM UTC 24
Finished Sep 18 06:13:10 PM UTC 24
Peak memory 293576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082436337 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.3082436337
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.1095060228
Short name T748
Test name
Test status
Simulation time 305132500 ps
CPU time 63.36 seconds
Started Sep 18 05:54:27 PM UTC 24
Finished Sep 18 05:55:32 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095060228 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.1095060228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.3491965369
Short name T750
Test name
Test status
Simulation time 1899362800 ps
CPU time 104.88 seconds
Started Sep 18 05:53:50 PM UTC 24
Finished Sep 18 05:55:37 PM UTC 24
Peak memory 301964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3491965369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.3491965369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.3207695948
Short name T800
Test name
Test status
Simulation time 8131453600 ps
CPU time 429.02 seconds
Started Sep 18 05:54:00 PM UTC 24
Finished Sep 18 06:01:14 PM UTC 24
Peak memory 330748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207695948 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.3207695948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.1762262269
Short name T738
Test name
Test status
Simulation time 68065900 ps
CPU time 41.84 seconds
Started Sep 18 05:54:16 PM UTC 24
Finished Sep 18 05:55:00 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1762262269 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.1762262269
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.1269480484
Short name T742
Test name
Test status
Simulation time 62192900 ps
CPU time 47.66 seconds
Started Sep 18 05:54:22 PM UTC 24
Finished Sep 18 05:55:11 PM UTC 24
Peak memory 285856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1269480484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_c
trl_rw_evict_all_en.1269480484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.818305388
Short name T430
Test name
Test status
Simulation time 6731091700 ps
CPU time 97.03 seconds
Started Sep 18 05:54:32 PM UTC 24
Finished Sep 18 05:56:11 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=818305388 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.818305388
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.4194305105
Short name T767
Test name
Test status
Simulation time 3059755800 ps
CPU time 285.12 seconds
Started Sep 18 05:53:01 PM UTC 24
Finished Sep 18 05:57:50 PM UTC 24
Peak memory 291520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194305105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.4194305105
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.3996269396
Short name T756
Test name
Test status
Simulation time 8851527600 ps
CPU time 209.35 seconds
Started Sep 18 05:53:23 PM UTC 24
Finished Sep 18 05:56:56 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3996269396 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_wo.3996269396
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/17.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1717603159
Short name T766
Test name
Test status
Simulation time 260012200 ps
CPU time 25.21 seconds
Started Sep 18 05:57:10 PM UTC 24
Finished Sep 18 05:57:36 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717603159 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.1717603159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.2237060219
Short name T763
Test name
Test status
Simulation time 25862800 ps
CPU time 24.98 seconds
Started Sep 18 05:56:56 PM UTC 24
Finished Sep 18 05:57:22 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237060219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.2237060219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.1994776117
Short name T760
Test name
Test status
Simulation time 138000600 ps
CPU time 40.04 seconds
Started Sep 18 05:56:35 PM UTC 24
Finished Sep 18 05:57:16 PM UTC 24
Peak memory 285484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1994776117 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_
ctrl_disable.1994776117
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2340603144
Short name T810
Test name
Test status
Simulation time 10012850600 ps
CPU time 290.2 seconds
Started Sep 18 05:57:08 PM UTC 24
Finished Sep 18 06:02:02 PM UTC 24
Peak memory 289572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2340603144 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.2340603144
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.298920871
Short name T764
Test name
Test status
Simulation time 26139900 ps
CPU time 20.81 seconds
Started Sep 18 05:57:03 PM UTC 24
Finished Sep 18 05:57:25 PM UTC 24
Peak memory 269252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=298920871 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
8.flash_ctrl_hw_read_seed_err.298920871
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.3101006644
Short name T1029
Test name
Test status
Simulation time 40123582200 ps
CPU time 1035.13 seconds
Started Sep 18 05:55:17 PM UTC 24
Finished Sep 18 06:12:45 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101006644
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_res
et.3101006644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.966952355
Short name T751
Test name
Test status
Simulation time 850491900 ps
CPU time 47.3 seconds
Started Sep 18 05:55:16 PM UTC 24
Finished Sep 18 05:56:05 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=966952355 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.966952355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.2272374921
Short name T356
Test name
Test status
Simulation time 1757195500 ps
CPU time 234.7 seconds
Started Sep 18 05:56:06 PM UTC 24
Finished Sep 18 06:00:04 PM UTC 24
Peak memory 293876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272374921 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.2272374921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1815891119
Short name T357
Test name
Test status
Simulation time 24547096500 ps
CPU time 517.46 seconds
Started Sep 18 05:56:06 PM UTC 24
Finished Sep 18 06:04:50 PM UTC 24
Peak memory 293696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1815891119 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_intr_rd_slow_flash.1815891119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.1100062034
Short name T757
Test name
Test status
Simulation time 3943048300 ps
CPU time 89.89 seconds
Started Sep 18 05:55:27 PM UTC 24
Finished Sep 18 05:56:59 PM UTC 24
Peak memory 272960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100062034 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.1100062034
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.2105876800
Short name T761
Test name
Test status
Simulation time 26507500 ps
CPU time 19.46 seconds
Started Sep 18 05:57:00 PM UTC 24
Finished Sep 18 05:57:21 PM UTC 24
Peak memory 275528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2105876800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_lcmgr_intg.2105876800
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.3942314292
Short name T956
Test name
Test status
Simulation time 11829224200 ps
CPU time 856.38 seconds
Started Sep 18 05:55:27 PM UTC 24
Finished Sep 18 06:09:54 PM UTC 24
Peak memory 283332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3942314292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 18.flash_ctrl_mp_regions.3942314292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.3029234230
Short name T97
Test name
Test status
Simulation time 454117500 ps
CPU time 166.89 seconds
Started Sep 18 05:55:19 PM UTC 24
Finished Sep 18 05:58:08 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029234230 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.3029234230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.1574483753
Short name T824
Test name
Test status
Simulation time 1426851400 ps
CPU time 445.2 seconds
Started Sep 18 05:55:13 PM UTC 24
Finished Sep 18 06:02:43 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574483753 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.1574483753
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.1608319217
Short name T754
Test name
Test status
Simulation time 24398100 ps
CPU time 26.72 seconds
Started Sep 18 05:56:06 PM UTC 24
Finished Sep 18 05:56:34 PM UTC 24
Peak memory 271348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1608319217 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.1608319217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.3301751103
Short name T803
Test name
Test status
Simulation time 102522900 ps
CPU time 374.75 seconds
Started Sep 18 05:55:12 PM UTC 24
Finished Sep 18 06:01:31 PM UTC 24
Peak memory 283596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301751103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.3301751103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.1372021824
Short name T762
Test name
Test status
Simulation time 191539900 ps
CPU time 44.74 seconds
Started Sep 18 05:56:35 PM UTC 24
Finished Sep 18 05:57:21 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372021824 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.1372021824
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.2144954217
Short name T768
Test name
Test status
Simulation time 977137300 ps
CPU time 136.06 seconds
Started Sep 18 05:55:33 PM UTC 24
Finished Sep 18 05:57:52 PM UTC 24
Peak memory 303916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2144954217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.2144954217
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.3947481007
Short name T832
Test name
Test status
Simulation time 7483383300 ps
CPU time 453.02 seconds
Started Sep 18 05:55:37 PM UTC 24
Finished Sep 18 06:03:17 PM UTC 24
Peak memory 320540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947481007 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.3947481007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.459895467
Short name T758
Test name
Test status
Simulation time 36811900 ps
CPU time 49.12 seconds
Started Sep 18 05:56:12 PM UTC 24
Finished Sep 18 05:57:02 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459895467 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.459895467
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.4083493660
Short name T759
Test name
Test status
Simulation time 28530700 ps
CPU time 41.6 seconds
Started Sep 18 05:56:27 PM UTC 24
Finished Sep 18 05:57:10 PM UTC 24
Peak memory 287612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4083493660 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_c
trl_rw_evict_all_en.4083493660
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.4166481761
Short name T775
Test name
Test status
Simulation time 30469044400 ps
CPU time 139.79 seconds
Started Sep 18 05:56:42 PM UTC 24
Finished Sep 18 05:59:04 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166481761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.4166481761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.3768503541
Short name T781
Test name
Test status
Simulation time 105738800 ps
CPU time 252.17 seconds
Started Sep 18 05:55:11 PM UTC 24
Finished Sep 18 05:59:27 PM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768503541 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.3768503541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.999041477
Short name T783
Test name
Test status
Simulation time 2736821800 ps
CPU time 240.77 seconds
Started Sep 18 05:55:33 PM UTC 24
Finished Sep 18 05:59:38 PM UTC 24
Peak memory 275088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=999041477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.999041477
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.1556800235
Short name T786
Test name
Test status
Simulation time 38905200 ps
CPU time 27.02 seconds
Started Sep 18 05:59:19 PM UTC 24
Finished Sep 18 05:59:48 PM UTC 24
Peak memory 268996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556800235 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.1556800235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.1271826691
Short name T778
Test name
Test status
Simulation time 16926300 ps
CPU time 25.55 seconds
Started Sep 18 05:58:52 PM UTC 24
Finished Sep 18 05:59:18 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271826691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.1271826691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.256767452
Short name T779
Test name
Test status
Simulation time 10800200 ps
CPU time 44.53 seconds
Started Sep 18 05:58:35 PM UTC 24
Finished Sep 18 05:59:21 PM UTC 24
Peak memory 285692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=256767452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_disable.256767452
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3679655883
Short name T852
Test name
Test status
Simulation time 10012541700 ps
CPU time 327.76 seconds
Started Sep 18 05:59:09 PM UTC 24
Finished Sep 18 06:04:42 PM UTC 24
Peak memory 324356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3679655883 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.3679655883
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.3265476810
Short name T339
Test name
Test status
Simulation time 23421700 ps
CPU time 26.49 seconds
Started Sep 18 05:59:07 PM UTC 24
Finished Sep 18 05:59:35 PM UTC 24
Peak memory 271376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3265476810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
19.flash_ctrl_hw_read_seed_err.3265476810
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.639023590
Short name T1014
Test name
Test status
Simulation time 40130571300 ps
CPU time 869.53 seconds
Started Sep 18 05:57:23 PM UTC 24
Finished Sep 18 06:12:02 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639023590 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_reset.639023590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1162868307
Short name T771
Test name
Test status
Simulation time 4621663000 ps
CPU time 65.53 seconds
Started Sep 18 05:57:21 PM UTC 24
Finished Sep 18 05:58:29 PM UTC 24
Peak memory 271052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162868307 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.1162868307
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.688018838
Short name T805
Test name
Test status
Simulation time 28525165300 ps
CPU time 211.79 seconds
Started Sep 18 05:58:07 PM UTC 24
Finished Sep 18 06:01:43 PM UTC 24
Peak memory 302188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688018838 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.688018838
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2386366038
Short name T797
Test name
Test status
Simulation time 18148550900 ps
CPU time 152.48 seconds
Started Sep 18 05:58:10 PM UTC 24
Finished Sep 18 06:00:45 PM UTC 24
Peak memory 303908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2386366038 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 19.flash_ctrl_intr_rd_slow_flash.2386366038
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3563454465
Short name T776
Test name
Test status
Simulation time 3047993400 ps
CPU time 94.09 seconds
Started Sep 18 05:57:29 PM UTC 24
Finished Sep 18 05:59:05 PM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563454465 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.3563454465
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.354627664
Short name T780
Test name
Test status
Simulation time 48738100 ps
CPU time 16.81 seconds
Started Sep 18 05:59:06 PM UTC 24
Finished Sep 18 05:59:24 PM UTC 24
Peak memory 275296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=354627664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_lcmgr_intg.354627664
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1550009247
Short name T787
Test name
Test status
Simulation time 1589801700 ps
CPU time 159.63 seconds
Started Sep 18 05:57:26 PM UTC 24
Finished Sep 18 06:00:09 PM UTC 24
Peak memory 275332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1550009247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 19.flash_ctrl_mp_regions.1550009247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.2014769532
Short name T789
Test name
Test status
Simulation time 292528000 ps
CPU time 178.63 seconds
Started Sep 18 05:57:23 PM UTC 24
Finished Sep 18 06:00:24 PM UTC 24
Peak memory 270952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014769532 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.2014769532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.3543411340
Short name T924
Test name
Test status
Simulation time 1411754700 ps
CPU time 667.69 seconds
Started Sep 18 05:57:21 PM UTC 24
Finished Sep 18 06:08:37 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543411340 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.3543411340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.644348031
Short name T773
Test name
Test status
Simulation time 60286000 ps
CPU time 20.42 seconds
Started Sep 18 05:58:19 PM UTC 24
Finished Sep 18 05:58:40 PM UTC 24
Peak memory 271420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644348031 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.644348031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.2505632877
Short name T791
Test name
Test status
Simulation time 57251700 ps
CPU time 187.02 seconds
Started Sep 18 05:57:17 PM UTC 24
Finished Sep 18 06:00:27 PM UTC 24
Peak memory 281292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505632877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.2505632877
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.4079610233
Short name T782
Test name
Test status
Simulation time 65227100 ps
CPU time 56.57 seconds
Started Sep 18 05:58:29 PM UTC 24
Finished Sep 18 05:59:27 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079610233 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.4079610233
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1374134837
Short name T784
Test name
Test status
Simulation time 625990300 ps
CPU time 104.65 seconds
Started Sep 18 05:57:51 PM UTC 24
Finished Sep 18 05:59:38 PM UTC 24
Peak memory 302088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1374134837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.1374134837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw.2503380656
Short name T907
Test name
Test status
Simulation time 4680543700 ps
CPU time 578.96 seconds
Started Sep 18 05:57:53 PM UTC 24
Finished Sep 18 06:07:40 PM UTC 24
Peak memory 330740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2503380656 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw.2503380656
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.600385313
Short name T777
Test name
Test status
Simulation time 28770800 ps
CPU time 38.67 seconds
Started Sep 18 05:58:28 PM UTC 24
Finished Sep 18 05:59:08 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=600385313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ct
rl_rw_evict_all_en.600385313
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.3250204981
Short name T436
Test name
Test status
Simulation time 1165802300 ps
CPU time 88.5 seconds
Started Sep 18 05:58:41 PM UTC 24
Finished Sep 18 06:00:12 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250204981 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.3250204981
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.1938870237
Short name T774
Test name
Test status
Simulation time 39576200 ps
CPU time 96.02 seconds
Started Sep 18 05:57:13 PM UTC 24
Finished Sep 18 05:58:51 PM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938870237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.1938870237
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.1264838681
Short name T799
Test name
Test status
Simulation time 2236150300 ps
CPU time 209.11 seconds
Started Sep 18 05:57:37 PM UTC 24
Finished Sep 18 06:01:10 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1264838681 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.1264838681
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.1818746445
Short name T122
Test name
Test status
Simulation time 65564000 ps
CPU time 28.55 seconds
Started Sep 18 05:05:12 PM UTC 24
Finished Sep 18 05:05:42 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818746445 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.1818746445
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.317720401
Short name T119
Test name
Test status
Simulation time 20305700 ps
CPU time 22.12 seconds
Started Sep 18 05:04:52 PM UTC 24
Finished Sep 18 05:05:15 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317720401 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.317720401
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.2896874833
Short name T24
Test name
Test status
Simulation time 26604500 ps
CPU time 23.3 seconds
Started Sep 18 05:04:26 PM UTC 24
Finished Sep 18 05:04:51 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2896874833 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.2896874833
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.3897893284
Short name T91
Test name
Test status
Simulation time 1207914500 ps
CPU time 199.3 seconds
Started Sep 18 05:02:47 PM UTC 24
Finished Sep 18 05:06:09 PM UTC 24
Peak memory 291828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3897893284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.flash_ctrl_derr_detect.3897893284
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.3175015998
Short name T130
Test name
Test status
Simulation time 21150100 ps
CPU time 34.31 seconds
Started Sep 18 05:04:00 PM UTC 24
Finished Sep 18 05:04:36 PM UTC 24
Peak memory 285692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3175015998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_c
trl_disable.3175015998
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.88402075
Short name T36
Test name
Test status
Simulation time 1426480600 ps
CPU time 475.04 seconds
Started Sep 18 05:01:17 PM UTC 24
Finished Sep 18 05:09:18 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88402075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_b
ase_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.88402075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.2183893985
Short name T297
Test name
Test status
Simulation time 9054652200 ps
CPU time 2748.27 seconds
Started Sep 18 05:01:42 PM UTC 24
Finished Sep 18 05:47:57 PM UTC 24
Peak memory 277928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183893985 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.2183893985
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.535170299
Short name T114
Test name
Test status
Simulation time 1520828300 ps
CPU time 2804.14 seconds
Started Sep 18 05:01:36 PM UTC 24
Finished Sep 18 05:48:49 PM UTC 24
Peak memory 277936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53
5170299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
error_prog_type.535170299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.1052347101
Short name T299
Test name
Test status
Simulation time 2431705900 ps
CPU time 1102.24 seconds
Started Sep 18 05:01:37 PM UTC 24
Finished Sep 18 05:20:11 PM UTC 24
Peak memory 285388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052347101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.1052347101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.587339260
Short name T57
Test name
Test status
Simulation time 566087800 ps
CPU time 24.9 seconds
Started Sep 18 05:01:32 PM UTC 24
Finished Sep 18 05:01:59 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58
7339260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetch
_code.587339260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.3756131806
Short name T465
Test name
Test status
Simulation time 334771700 ps
CPU time 46.1 seconds
Started Sep 18 05:04:37 PM UTC 24
Finished Sep 18 05:05:24 PM UTC 24
Peak memory 275504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756131
806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_f
s_sup.3756131806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.3942042157
Short name T1119
Test name
Test status
Simulation time 445096375300 ps
CPU time 4456.35 seconds
Started Sep 18 05:01:36 PM UTC 24
Finished Sep 18 06:16:41 PM UTC 24
Peak memory 277896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942042157 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.3942042157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.918379324
Short name T471
Test name
Test status
Simulation time 62071700 ps
CPU time 37.39 seconds
Started Sep 18 05:05:08 PM UTC 24
Finished Sep 18 05:05:47 PM UTC 24
Peak memory 279552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918379324
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hos
t_addr_infection.918379324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.2598790438
Short name T204
Test name
Test status
Simulation time 55583000 ps
CPU time 162.68 seconds
Started Sep 18 05:01:14 PM UTC 24
Finished Sep 18 05:03:59 PM UTC 24
Peak memory 273164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2598790438 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.2598790438
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.532159778
Short name T181
Test name
Test status
Simulation time 10016935000 ps
CPU time 111.79 seconds
Started Sep 18 05:05:04 PM UTC 24
Finished Sep 18 05:06:58 PM UTC 24
Peak memory 289748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=532159778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.532159778
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.2607746064
Short name T286
Test name
Test status
Simulation time 204567900 ps
CPU time 24.64 seconds
Started Sep 18 05:05:04 PM UTC 24
Finished Sep 18 05:05:30 PM UTC 24
Peak memory 269176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2607746064 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_hw_read_seed_err.2607746064
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1114044372
Short name T143
Test name
Test status
Simulation time 146248579100 ps
CPU time 1995.89 seconds
Started Sep 18 05:01:17 PM UTC 24
Finished Sep 18 05:34:54 PM UTC 24
Peak memory 277828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114044372
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.1114044372
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.2925395581
Short name T145
Test name
Test status
Simulation time 160168006700 ps
CPU time 958.62 seconds
Started Sep 18 05:01:18 PM UTC 24
Finished Sep 18 05:17:28 PM UTC 24
Peak memory 275292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925395581
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.2925395581
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.3665188508
Short name T127
Test name
Test status
Simulation time 8998873100 ps
CPU time 97.17 seconds
Started Sep 18 05:01:17 PM UTC 24
Finished Sep 18 05:02:56 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665188508 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.3665188508
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2639109258
Short name T47
Test name
Test status
Simulation time 5841217100 ps
CPU time 207.72 seconds
Started Sep 18 05:03:05 PM UTC 24
Finished Sep 18 05:06:36 PM UTC 24
Peak memory 302000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639109258 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.2639109258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2068519930
Short name T474
Test name
Test status
Simulation time 5892686300 ps
CPU time 163.79 seconds
Started Sep 18 05:03:22 PM UTC 24
Finished Sep 18 05:06:09 PM UTC 24
Peak memory 303932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2068519930 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_intr_rd_slow_flash.2068519930
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.4176280622
Short name T315
Test name
Test status
Simulation time 8762731000 ps
CPU time 72.05 seconds
Started Sep 18 05:03:17 PM UTC 24
Finished Sep 18 05:04:31 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176280622 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.4176280622
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.68559561
Short name T481
Test name
Test status
Simulation time 44086129200 ps
CPU time 363.67 seconds
Started Sep 18 05:03:23 PM UTC 24
Finished Sep 18 05:09:32 PM UTC 24
Peak memory 271352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68559561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.68559561
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.2162789607
Short name T89
Test name
Test status
Simulation time 8266557300 ps
CPU time 97.27 seconds
Started Sep 18 05:01:43 PM UTC 24
Finished Sep 18 05:03:22 PM UTC 24
Peak memory 271172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2162789607 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.2162789607
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.3556472868
Short name T178
Test name
Test status
Simulation time 15562900 ps
CPU time 25.36 seconds
Started Sep 18 05:05:03 PM UTC 24
Finished Sep 18 05:05:30 PM UTC 24
Peak memory 271188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3556472868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_lcmgr_intg.3556472868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.1806911212
Short name T78
Test name
Test status
Simulation time 30915521400 ps
CPU time 559.53 seconds
Started Sep 18 05:01:28 PM UTC 24
Finished Sep 18 05:10:55 PM UTC 24
Peak memory 283328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1806911212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_mp_regions.1806911212
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.828913171
Short name T93
Test name
Test status
Simulation time 38282000 ps
CPU time 218.24 seconds
Started Sep 18 05:01:20 PM UTC 24
Finished Sep 18 05:05:02 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828913171 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.828913171
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.3621339590
Short name T213
Test name
Test status
Simulation time 877138400 ps
CPU time 149.54 seconds
Started Sep 18 05:02:54 PM UTC 24
Finished Sep 18 05:05:26 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=3621339590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_oversize_error.3621339590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.2013976740
Short name T66
Test name
Test status
Simulation time 45189900 ps
CPU time 25.96 seconds
Started Sep 18 05:04:44 PM UTC 24
Finished Sep 18 05:05:11 PM UTC 24
Peak memory 293056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013976740 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.2013976740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.2082410212
Short name T29
Test name
Test status
Simulation time 9756355100 ps
CPU time 248.96 seconds
Started Sep 18 05:01:15 PM UTC 24
Finished Sep 18 05:05:27 PM UTC 24
Peak memory 275216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082410212 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.2082410212
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.4229985088
Short name T203
Test name
Test status
Simulation time 121361900 ps
CPU time 20.71 seconds
Started Sep 18 05:03:24 PM UTC 24
Finished Sep 18 05:03:47 PM UTC 24
Peak memory 271224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229985088 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.4229985088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.3990976686
Short name T160
Test name
Test status
Simulation time 151074400 ps
CPU time 210.73 seconds
Started Sep 18 05:01:10 PM UTC 24
Finished Sep 18 05:04:43 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3990976686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.3990976686
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.4196459457
Short name T205
Test name
Test status
Simulation time 347380900 ps
CPU time 174.51 seconds
Started Sep 18 05:01:15 PM UTC 24
Finished Sep 18 05:04:12 PM UTC 24
Peak memory 273348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196459457 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.4196459457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.907119487
Short name T368
Test name
Test status
Simulation time 216491700 ps
CPU time 35.12 seconds
Started Sep 18 05:04:30 PM UTC 24
Finished Sep 18 05:05:07 PM UTC 24
Peak memory 285724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907119487
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.907119487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.1754949572
Short name T161
Test name
Test status
Simulation time 243930200 ps
CPU time 53.91 seconds
Started Sep 18 05:03:48 PM UTC 24
Finished Sep 18 05:04:43 PM UTC 24
Peak memory 285852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1754949572 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.1754949572
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2937187851
Short name T158
Test name
Test status
Simulation time 197766500 ps
CPU time 43.7 seconds
Started Sep 18 05:02:18 PM UTC 24
Finished Sep 18 05:03:03 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2937187851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_read_word_sweep_derr.2937187851
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.875005747
Short name T156
Test name
Test status
Simulation time 26100200 ps
CPU time 40.68 seconds
Started Sep 18 05:01:58 PM UTC 24
Finished Sep 18 05:02:40 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875005747 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.875005747
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.2922237592
Short name T106
Test name
Test status
Simulation time 68787240500 ps
CPU time 976.49 seconds
Started Sep 18 05:05:03 PM UTC 24
Finished Sep 18 05:21:31 PM UTC 24
Peak memory 272752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2922237592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.
flash_ctrl_rma_err.2922237592
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.2388090589
Short name T285
Test name
Test status
Simulation time 5215609600 ps
CPU time 154.54 seconds
Started Sep 18 05:01:48 PM UTC 24
Finished Sep 18 05:04:26 PM UTC 24
Peak memory 304176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2388090589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.2388090589
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.3248293706
Short name T470
Test name
Test status
Simulation time 2401673500 ps
CPU time 152.7 seconds
Started Sep 18 05:02:41 PM UTC 24
Finished Sep 18 05:05:17 PM UTC 24
Peak memory 292024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248293706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.3248293706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.794169475
Short name T206
Test name
Test status
Simulation time 1129630500 ps
CPU time 138.2 seconds
Started Sep 18 05:01:59 PM UTC 24
Finished Sep 18 05:04:20 PM UTC 24
Peak memory 306360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=794169475 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_
ctrl_ro_serr.794169475
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.1838062409
Short name T417
Test name
Test status
Simulation time 6038914000 ps
CPU time 173.89 seconds
Started Sep 18 05:02:45 PM UTC 24
Finished Sep 18 05:05:42 PM UTC 24
Peak memory 297968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1838062409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rw_derr.1838062409
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.4083454725
Short name T124
Test name
Test status
Simulation time 29892500 ps
CPU time 55.38 seconds
Started Sep 18 05:03:33 PM UTC 24
Finished Sep 18 05:04:30 PM UTC 24
Peak memory 287612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4083454725 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw_evict_all_en.4083454725
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.610026103
Short name T464
Test name
Test status
Simulation time 1841575100 ps
CPU time 171.55 seconds
Started Sep 18 05:02:07 PM UTC 24
Finished Sep 18 05:05:02 PM UTC 24
Peak memory 306184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=610026103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.610026103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.2207190866
Short name T207
Test name
Test status
Simulation time 3601419200 ps
CPU time 126.91 seconds
Started Sep 18 05:02:13 PM UTC 24
Finished Sep 18 05:04:23 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=220
7190866 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ser
r_address.2207190866
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3876458235
Short name T202
Test name
Test status
Simulation time 396000400 ps
CPU time 77.99 seconds
Started Sep 18 05:02:12 PM UTC 24
Finished Sep 18 05:03:32 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38
76458235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se
rr_counter.3876458235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3768244806
Short name T412
Test name
Test status
Simulation time 46913300 ps
CPU time 242.68 seconds
Started Sep 18 05:01:07 PM UTC 24
Finished Sep 18 05:05:13 PM UTC 24
Peak memory 289732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768244806 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3768244806
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.3098920990
Short name T260
Test name
Test status
Simulation time 142119000 ps
CPU time 34.39 seconds
Started Sep 18 05:01:09 PM UTC 24
Finished Sep 18 05:01:45 PM UTC 24
Peak memory 271180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3098920990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.3098920990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.2110975553
Short name T605
Test name
Test status
Simulation time 249009800 ps
CPU time 1965.62 seconds
Started Sep 18 05:04:23 PM UTC 24
Finished Sep 18 05:37:30 PM UTC 24
Peak memory 297928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110975553 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.2110975553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.1230390235
Short name T311
Test name
Test status
Simulation time 42106700 ps
CPU time 51.7 seconds
Started Sep 18 05:01:14 PM UTC 24
Finished Sep 18 05:02:07 PM UTC 24
Peak memory 273164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1230390235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.1230390235
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.3161250836
Short name T469
Test name
Test status
Simulation time 4208625000 ps
CPU time 165.67 seconds
Started Sep 18 05:01:48 PM UTC 24
Finished Sep 18 05:04:37 PM UTC 24
Peak memory 275520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3161250836 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.3161250836
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.3595420406
Short name T123
Test name
Test status
Simulation time 161875800 ps
CPU time 30.58 seconds
Started Sep 18 05:04:31 PM UTC 24
Finished Sep 18 05:05:04 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=3595420406 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_wr_intg.3595420406
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.1401664684
Short name T795
Test name
Test status
Simulation time 60029100 ps
CPU time 23.22 seconds
Started Sep 18 06:00:10 PM UTC 24
Finished Sep 18 06:00:35 PM UTC 24
Peak memory 269244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401664684 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.1401664684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.2163951263
Short name T792
Test name
Test status
Simulation time 80740600 ps
CPU time 23.48 seconds
Started Sep 18 06:00:07 PM UTC 24
Finished Sep 18 06:00:31 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2163951263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2163951263
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.4119919739
Short name T790
Test name
Test status
Simulation time 23622000 ps
CPU time 38.41 seconds
Started Sep 18 05:59:44 PM UTC 24
Finished Sep 18 06:00:24 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4119919739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_
ctrl_disable.4119919739
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.1672069421
Short name T808
Test name
Test status
Simulation time 5220783400 ps
CPU time 153 seconds
Started Sep 18 05:59:24 PM UTC 24
Finished Sep 18 06:02:00 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672069421 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.1672069421
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.338239442
Short name T814
Test name
Test status
Simulation time 3465116300 ps
CPU time 154.43 seconds
Started Sep 18 05:59:28 PM UTC 24
Finished Sep 18 06:02:05 PM UTC 24
Peak memory 306284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=338239442 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.338239442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.754496553
Short name T854
Test name
Test status
Simulation time 15129287800 ps
CPU time 318.48 seconds
Started Sep 18 05:59:28 PM UTC 24
Finished Sep 18 06:04:51 PM UTC 24
Peak memory 301892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=754496553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 20.flash_ctrl_intr_rd_slow_flash.754496553
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.2309406566
Short name T345
Test name
Test status
Simulation time 70648200 ps
CPU time 159.06 seconds
Started Sep 18 05:59:25 PM UTC 24
Finished Sep 18 06:02:06 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309406566 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.2309406566
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.4188664723
Short name T819
Test name
Test status
Simulation time 9356148800 ps
CPU time 171.01 seconds
Started Sep 18 05:59:36 PM UTC 24
Finished Sep 18 06:02:30 PM UTC 24
Peak memory 271152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188664723 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.4188664723
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.3495873290
Short name T796
Test name
Test status
Simulation time 101153000 ps
CPU time 54.16 seconds
Started Sep 18 05:59:39 PM UTC 24
Finished Sep 18 06:00:35 PM UTC 24
Peak memory 279420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3495873290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_c
trl_rw_evict_all_en.3495873290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.48151839
Short name T404
Test name
Test status
Simulation time 4492066900 ps
CPU time 87.45 seconds
Started Sep 18 05:59:48 PM UTC 24
Finished Sep 18 06:01:18 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48151839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.48151839
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.2284650528
Short name T835
Test name
Test status
Simulation time 30630100 ps
CPU time 234.48 seconds
Started Sep 18 05:59:22 PM UTC 24
Finished Sep 18 06:03:20 PM UTC 24
Peak memory 287420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284650528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.2284650528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.3926760669
Short name T802
Test name
Test status
Simulation time 167291700 ps
CPU time 24.2 seconds
Started Sep 18 06:01:00 PM UTC 24
Finished Sep 18 06:01:25 PM UTC 24
Peak memory 269052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926760669 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.3926760669
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.1163389984
Short name T801
Test name
Test status
Simulation time 13552600 ps
CPU time 29.98 seconds
Started Sep 18 06:00:46 PM UTC 24
Finished Sep 18 06:01:17 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163389984 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.1163389984
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1494582673
Short name T210
Test name
Test status
Simulation time 17373100 ps
CPU time 43.68 seconds
Started Sep 18 06:00:35 PM UTC 24
Finished Sep 18 06:01:21 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1494582673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_
ctrl_disable.1494582673
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.4004958075
Short name T821
Test name
Test status
Simulation time 4176932500 ps
CPU time 133.56 seconds
Started Sep 18 06:00:17 PM UTC 24
Finished Sep 18 06:02:34 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4004958075 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.4004958075
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.3527658768
Short name T823
Test name
Test status
Simulation time 2275023900 ps
CPU time 134.38 seconds
Started Sep 18 06:00:25 PM UTC 24
Finished Sep 18 06:02:41 PM UTC 24
Peak memory 306100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527658768 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.3527658768
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2544373347
Short name T826
Test name
Test status
Simulation time 41395178800 ps
CPU time 139.66 seconds
Started Sep 18 06:00:28 PM UTC 24
Finished Sep 18 06:02:50 PM UTC 24
Peak memory 303904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2544373347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 21.flash_ctrl_intr_rd_slow_flash.2544373347
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.89238180
Short name T195
Test name
Test status
Simulation time 40215900 ps
CPU time 171.04 seconds
Started Sep 18 06:00:25 PM UTC 24
Finished Sep 18 06:03:18 PM UTC 24
Peak memory 275504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89238180 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.89238180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.3091858520
Short name T798
Test name
Test status
Simulation time 276073800 ps
CPU time 25.22 seconds
Started Sep 18 06:00:32 PM UTC 24
Finished Sep 18 06:00:59 PM UTC 24
Peak memory 271088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091858520 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.3091858520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.1111608543
Short name T450
Test name
Test status
Simulation time 96083300 ps
CPU time 54.08 seconds
Started Sep 18 06:00:33 PM UTC 24
Finished Sep 18 06:01:29 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111608543 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.1111608543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.2345901760
Short name T804
Test name
Test status
Simulation time 49923100 ps
CPU time 55.41 seconds
Started Sep 18 06:00:35 PM UTC 24
Finished Sep 18 06:01:32 PM UTC 24
Peak memory 279680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2345901760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_c
trl_rw_evict_all_en.2345901760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.2429304818
Short name T401
Test name
Test status
Simulation time 7983603700 ps
CPU time 85.26 seconds
Started Sep 18 06:00:35 PM UTC 24
Finished Sep 18 06:02:03 PM UTC 24
Peak memory 275348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429304818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.2429304818
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.298097851
Short name T834
Test name
Test status
Simulation time 8439105500 ps
CPU time 184.94 seconds
Started Sep 18 06:00:12 PM UTC 24
Finished Sep 18 06:03:20 PM UTC 24
Peak memory 291532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298097851 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.298097851
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3926534043
Short name T812
Test name
Test status
Simulation time 41222100 ps
CPU time 28.45 seconds
Started Sep 18 06:01:34 PM UTC 24
Finished Sep 18 06:02:03 PM UTC 24
Peak memory 275400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926534043 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.3926534043
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.1485561919
Short name T809
Test name
Test status
Simulation time 31783200 ps
CPU time 27.47 seconds
Started Sep 18 06:01:33 PM UTC 24
Finished Sep 18 06:02:02 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485561919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.1485561919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.3493020147
Short name T340
Test name
Test status
Simulation time 3202645300 ps
CPU time 264.12 seconds
Started Sep 18 06:01:15 PM UTC 24
Finished Sep 18 06:05:43 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493020147 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.3493020147
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.2394878601
Short name T833
Test name
Test status
Simulation time 527818100 ps
CPU time 117.9 seconds
Started Sep 18 06:01:18 PM UTC 24
Finished Sep 18 06:03:18 PM UTC 24
Peak memory 306324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394878601 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.2394878601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.197108537
Short name T880
Test name
Test status
Simulation time 41839512700 ps
CPU time 286.33 seconds
Started Sep 18 06:01:21 PM UTC 24
Finished Sep 18 06:06:12 PM UTC 24
Peak memory 293676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=197108537 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 22.flash_ctrl_intr_rd_slow_flash.197108537
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.3410484700
Short name T846
Test name
Test status
Simulation time 69340700 ps
CPU time 181.11 seconds
Started Sep 18 06:01:18 PM UTC 24
Finished Sep 18 06:04:22 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410484700 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.3410484700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.2443289088
Short name T807
Test name
Test status
Simulation time 304924800 ps
CPU time 28.89 seconds
Started Sep 18 06:01:25 PM UTC 24
Finished Sep 18 06:01:55 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443289088 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.2443289088
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.3176151305
Short name T816
Test name
Test status
Simulation time 32164700 ps
CPU time 53.92 seconds
Started Sep 18 06:01:25 PM UTC 24
Finished Sep 18 06:02:20 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176151305 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.3176151305
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.2425563018
Short name T811
Test name
Test status
Simulation time 61392900 ps
CPU time 36.03 seconds
Started Sep 18 06:01:26 PM UTC 24
Finished Sep 18 06:02:03 PM UTC 24
Peak memory 287940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2425563018 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_c
trl_rw_evict_all_en.2425563018
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.3658333116
Short name T825
Test name
Test status
Simulation time 2322786100 ps
CPU time 73.81 seconds
Started Sep 18 06:01:31 PM UTC 24
Finished Sep 18 06:02:47 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3658333116 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.3658333116
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.1266242583
Short name T815
Test name
Test status
Simulation time 75973500 ps
CPU time 65.79 seconds
Started Sep 18 06:01:11 PM UTC 24
Finished Sep 18 06:02:19 PM UTC 24
Peak memory 285576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266242583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.1266242583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.1033319336
Short name T822
Test name
Test status
Simulation time 186241500 ps
CPU time 26.98 seconds
Started Sep 18 06:02:07 PM UTC 24
Finished Sep 18 06:02:35 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033319336 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.1033319336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.2904426436
Short name T818
Test name
Test status
Simulation time 16874600 ps
CPU time 20.78 seconds
Started Sep 18 06:02:06 PM UTC 24
Finished Sep 18 06:02:28 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904426436 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.2904426436
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.4177766691
Short name T820
Test name
Test status
Simulation time 35700000 ps
CPU time 25.82 seconds
Started Sep 18 06:02:05 PM UTC 24
Finished Sep 18 06:02:32 PM UTC 24
Peak memory 285744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4177766691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_
ctrl_disable.4177766691
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3016793655
Short name T327
Test name
Test status
Simulation time 2928799400 ps
CPU time 80.8 seconds
Started Sep 18 06:01:51 PM UTC 24
Finished Sep 18 06:03:14 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016793655 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.3016793655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd.3365634464
Short name T872
Test name
Test status
Simulation time 10195723700 ps
CPU time 220.97 seconds
Started Sep 18 06:02:00 PM UTC 24
Finished Sep 18 06:05:45 PM UTC 24
Peak memory 302028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365634464 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_rd.3365634464
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1248534844
Short name T853
Test name
Test status
Simulation time 5717651500 ps
CPU time 161.36 seconds
Started Sep 18 06:02:02 PM UTC 24
Finished Sep 18 06:04:47 PM UTC 24
Peak memory 303904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1248534844 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.flash_ctrl_intr_rd_slow_flash.1248534844
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.3191447526
Short name T851
Test name
Test status
Simulation time 72366500 ps
CPU time 162.05 seconds
Started Sep 18 06:01:56 PM UTC 24
Finished Sep 18 06:04:41 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3191447526 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.3191447526
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.393968621
Short name T817
Test name
Test status
Simulation time 18142000 ps
CPU time 18.4 seconds
Started Sep 18 06:02:03 PM UTC 24
Finished Sep 18 06:02:22 PM UTC 24
Peak memory 275448 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393968621 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.393968621
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.3898332491
Short name T828
Test name
Test status
Simulation time 47083200 ps
CPU time 60.41 seconds
Started Sep 18 06:02:04 PM UTC 24
Finished Sep 18 06:03:06 PM UTC 24
Peak memory 287608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898332491 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.3898332491
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.1736968997
Short name T827
Test name
Test status
Simulation time 38268800 ps
CPU time 51.5 seconds
Started Sep 18 06:02:04 PM UTC 24
Finished Sep 18 06:02:57 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1736968997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c
trl_rw_evict_all_en.1736968997
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.2146760950
Short name T839
Test name
Test status
Simulation time 2774544900 ps
CPU time 109.49 seconds
Started Sep 18 06:02:05 PM UTC 24
Finished Sep 18 06:03:57 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146760950 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.2146760950
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.538952936
Short name T860
Test name
Test status
Simulation time 236183200 ps
CPU time 205.18 seconds
Started Sep 18 06:01:44 PM UTC 24
Finished Sep 18 06:05:12 PM UTC 24
Peak memory 289480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=538952936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.538952936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.324727992
Short name T829
Test name
Test status
Simulation time 65632100 ps
CPU time 21.35 seconds
Started Sep 18 06:02:44 PM UTC 24
Finished Sep 18 06:03:06 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=324727992 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.324727992
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.1916571101
Short name T831
Test name
Test status
Simulation time 26799800 ps
CPU time 28.62 seconds
Started Sep 18 06:02:42 PM UTC 24
Finished Sep 18 06:03:12 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916571101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.1916571101
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.1035721107
Short name T841
Test name
Test status
Simulation time 3232688700 ps
CPU time 103.27 seconds
Started Sep 18 06:02:19 PM UTC 24
Finished Sep 18 06:04:05 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035721107 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.1035721107
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.2843138135
Short name T914
Test name
Test status
Simulation time 29385383700 ps
CPU time 338.79 seconds
Started Sep 18 06:02:23 PM UTC 24
Finished Sep 18 06:08:06 PM UTC 24
Peak memory 301856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2843138135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 24.flash_ctrl_intr_rd_slow_flash.2843138135
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.1396204569
Short name T868
Test name
Test status
Simulation time 44083000 ps
CPU time 191.2 seconds
Started Sep 18 06:02:22 PM UTC 24
Finished Sep 18 06:05:36 PM UTC 24
Peak memory 270952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396204569 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.1396204569
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.2061955588
Short name T326
Test name
Test status
Simulation time 19815200 ps
CPU time 15.88 seconds
Started Sep 18 06:02:29 PM UTC 24
Finished Sep 18 06:02:46 PM UTC 24
Peak memory 275184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061955588 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.2061955588
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.51450057
Short name T341
Test name
Test status
Simulation time 42939600 ps
CPU time 47.99 seconds
Started Sep 18 06:02:31 PM UTC 24
Finished Sep 18 06:03:21 PM UTC 24
Peak memory 287604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=51450057 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.51450057
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.1833524594
Short name T830
Test name
Test status
Simulation time 30709500 ps
CPU time 37.83 seconds
Started Sep 18 06:02:33 PM UTC 24
Finished Sep 18 06:03:12 PM UTC 24
Peak memory 279420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1833524594 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c
trl_rw_evict_all_en.1833524594
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.2671088425
Short name T838
Test name
Test status
Simulation time 7413328500 ps
CPU time 73.16 seconds
Started Sep 18 06:02:36 PM UTC 24
Finished Sep 18 06:03:52 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671088425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.2671088425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.2937476192
Short name T875
Test name
Test status
Simulation time 20271800 ps
CPU time 212.72 seconds
Started Sep 18 06:02:10 PM UTC 24
Finished Sep 18 06:05:46 PM UTC 24
Peak memory 289480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937476192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.2937476192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.2059620721
Short name T836
Test name
Test status
Simulation time 76885000 ps
CPU time 16.28 seconds
Started Sep 18 06:03:19 PM UTC 24
Finished Sep 18 06:03:36 PM UTC 24
Peak memory 275388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059620721 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.2059620721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.445713624
Short name T837
Test name
Test status
Simulation time 100935100 ps
CPU time 21.42 seconds
Started Sep 18 06:03:17 PM UTC 24
Finished Sep 18 06:03:40 PM UTC 24
Peak memory 284684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445713624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.445713624
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.911315022
Short name T424
Test name
Test status
Simulation time 25851800 ps
CPU time 24.96 seconds
Started Sep 18 06:03:14 PM UTC 24
Finished Sep 18 06:03:40 PM UTC 24
Peak memory 285884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=911315022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c
trl_disable.911315022
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.1082063868
Short name T335
Test name
Test status
Simulation time 2147851600 ps
CPU time 76.51 seconds
Started Sep 18 06:02:48 PM UTC 24
Finished Sep 18 06:04:06 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082063868 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.1082063868
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.130358955
Short name T859
Test name
Test status
Simulation time 747398300 ps
CPU time 129.7 seconds
Started Sep 18 06:02:57 PM UTC 24
Finished Sep 18 06:05:09 PM UTC 24
Peak memory 308140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130358955 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.130358955
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.925861779
Short name T904
Test name
Test status
Simulation time 12027644100 ps
CPU time 268.13 seconds
Started Sep 18 06:02:57 PM UTC 24
Finished Sep 18 06:07:29 PM UTC 24
Peak memory 303912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=925861779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 25.flash_ctrl_intr_rd_slow_flash.925861779
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.3513833146
Short name T877
Test name
Test status
Simulation time 149475400 ps
CPU time 177.96 seconds
Started Sep 18 06:02:51 PM UTC 24
Finished Sep 18 06:05:52 PM UTC 24
Peak memory 273320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3513833146 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.3513833146
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.1110751586
Short name T92
Test name
Test status
Simulation time 69296100 ps
CPU time 20.02 seconds
Started Sep 18 06:03:06 PM UTC 24
Finished Sep 18 06:03:28 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110751586 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.1110751586
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.484608729
Short name T842
Test name
Test status
Simulation time 68611500 ps
CPU time 57.15 seconds
Started Sep 18 06:03:07 PM UTC 24
Finished Sep 18 06:04:06 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484608729 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.484608729
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.3933664191
Short name T447
Test name
Test status
Simulation time 144177200 ps
CPU time 52.36 seconds
Started Sep 18 06:03:14 PM UTC 24
Finished Sep 18 06:04:08 PM UTC 24
Peak memory 287680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3933664191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c
trl_rw_evict_all_en.3933664191
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1169916957
Short name T850
Test name
Test status
Simulation time 456231200 ps
CPU time 77.95 seconds
Started Sep 18 06:03:15 PM UTC 24
Finished Sep 18 06:04:35 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1169916957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.1169916957
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.1029539336
Short name T849
Test name
Test status
Simulation time 27847600 ps
CPU time 101.81 seconds
Started Sep 18 06:02:47 PM UTC 24
Finished Sep 18 06:04:31 PM UTC 24
Peak memory 285376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029539336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.1029539336
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.2596608819
Short name T844
Test name
Test status
Simulation time 179453500 ps
CPU time 17.22 seconds
Started Sep 18 06:04:03 PM UTC 24
Finished Sep 18 06:04:21 PM UTC 24
Peak memory 269052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596608819 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.2596608819
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.2840629068
Short name T848
Test name
Test status
Simulation time 55453700 ps
CPU time 27.92 seconds
Started Sep 18 06:03:57 PM UTC 24
Finished Sep 18 06:04:27 PM UTC 24
Peak memory 295052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840629068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.2840629068
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.4160265113
Short name T843
Test name
Test status
Simulation time 11297700 ps
CPU time 29.51 seconds
Started Sep 18 06:03:41 PM UTC 24
Finished Sep 18 06:04:12 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4160265113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_
ctrl_disable.4160265113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.519736183
Short name T899
Test name
Test status
Simulation time 5593213600 ps
CPU time 227.9 seconds
Started Sep 18 06:03:20 PM UTC 24
Finished Sep 18 06:07:12 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=519736183 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.519736183
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.246584343
Short name T867
Test name
Test status
Simulation time 1422064500 ps
CPU time 128.42 seconds
Started Sep 18 06:03:22 PM UTC 24
Finished Sep 18 06:05:32 PM UTC 24
Peak memory 306120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246584343 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.246584343
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.4167109074
Short name T890
Test name
Test status
Simulation time 140280700 ps
CPU time 183.42 seconds
Started Sep 18 06:03:21 PM UTC 24
Finished Sep 18 06:06:28 PM UTC 24
Peak memory 271416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167109074 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.4167109074
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.1242442046
Short name T840
Test name
Test status
Simulation time 64290800 ps
CPU time 31.94 seconds
Started Sep 18 06:03:29 PM UTC 24
Finished Sep 18 06:04:02 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242442046 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.1242442046
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.722985634
Short name T845
Test name
Test status
Simulation time 76925600 ps
CPU time 41.64 seconds
Started Sep 18 06:03:38 PM UTC 24
Finished Sep 18 06:04:21 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722985634 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.722985634
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.440472299
Short name T847
Test name
Test status
Simulation time 28013500 ps
CPU time 44.03 seconds
Started Sep 18 06:03:40 PM UTC 24
Finished Sep 18 06:04:26 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=440472299 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ct
rl_rw_evict_all_en.440472299
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.3774088766
Short name T864
Test name
Test status
Simulation time 1490284400 ps
CPU time 90.04 seconds
Started Sep 18 06:03:52 PM UTC 24
Finished Sep 18 06:05:24 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3774088766 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.3774088766
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.2797664771
Short name T884
Test name
Test status
Simulation time 55909600 ps
CPU time 173.2 seconds
Started Sep 18 06:03:19 PM UTC 24
Finished Sep 18 06:06:15 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797664771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.2797664771
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.2862443603
Short name T857
Test name
Test status
Simulation time 193271700 ps
CPU time 23.86 seconds
Started Sep 18 06:04:32 PM UTC 24
Finished Sep 18 06:04:57 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862443603 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.2862443603
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.1548772903
Short name T856
Test name
Test status
Simulation time 14131400 ps
CPU time 21.7 seconds
Started Sep 18 06:04:31 PM UTC 24
Finished Sep 18 06:04:54 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548772903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.1548772903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.3187498706
Short name T422
Test name
Test status
Simulation time 30506500 ps
CPU time 32.59 seconds
Started Sep 18 06:04:27 PM UTC 24
Finished Sep 18 06:05:01 PM UTC 24
Peak memory 285676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3187498706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_
ctrl_disable.3187498706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.3394108041
Short name T333
Test name
Test status
Simulation time 11843916900 ps
CPU time 252.37 seconds
Started Sep 18 06:04:07 PM UTC 24
Finished Sep 18 06:08:23 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394108041 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.3394108041
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.1302600782
Short name T901
Test name
Test status
Simulation time 1891267000 ps
CPU time 184.34 seconds
Started Sep 18 06:04:08 PM UTC 24
Finished Sep 18 06:07:15 PM UTC 24
Peak memory 302028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302600782 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.1302600782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.463959362
Short name T917
Test name
Test status
Simulation time 8704685800 ps
CPU time 236.15 seconds
Started Sep 18 06:04:13 PM UTC 24
Finished Sep 18 06:08:13 PM UTC 24
Peak memory 305964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=463959362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 27.flash_ctrl_intr_rd_slow_flash.463959362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.865083752
Short name T905
Test name
Test status
Simulation time 203644700 ps
CPU time 202.46 seconds
Started Sep 18 06:04:07 PM UTC 24
Finished Sep 18 06:07:33 PM UTC 24
Peak memory 271608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865083752 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.865083752
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.3068255162
Short name T855
Test name
Test status
Simulation time 19268400 ps
CPU time 29.39 seconds
Started Sep 18 06:04:22 PM UTC 24
Finished Sep 18 06:04:53 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068255162 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.3068255162
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.2878783906
Short name T445
Test name
Test status
Simulation time 49229600 ps
CPU time 47.53 seconds
Started Sep 18 06:04:22 PM UTC 24
Finished Sep 18 06:05:11 PM UTC 24
Peak memory 287932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878783906 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.2878783906
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.397681958
Short name T861
Test name
Test status
Simulation time 29406000 ps
CPU time 51.57 seconds
Started Sep 18 06:04:23 PM UTC 24
Finished Sep 18 06:05:17 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=397681958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ct
rl_rw_evict_all_en.397681958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.4106865785
Short name T871
Test name
Test status
Simulation time 1639240000 ps
CPU time 71.14 seconds
Started Sep 18 06:04:28 PM UTC 24
Finished Sep 18 06:05:41 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106865785 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.4106865785
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.1908452364
Short name T876
Test name
Test status
Simulation time 225535200 ps
CPU time 99.79 seconds
Started Sep 18 06:04:06 PM UTC 24
Finished Sep 18 06:05:48 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908452364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.1908452364
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.63733734
Short name T870
Test name
Test status
Simulation time 46481500 ps
CPU time 28.98 seconds
Started Sep 18 06:05:10 PM UTC 24
Finished Sep 18 06:05:40 PM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63733734 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.63733734
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.1654607150
Short name T869
Test name
Test status
Simulation time 28032900 ps
CPU time 27.5 seconds
Started Sep 18 06:05:08 PM UTC 24
Finished Sep 18 06:05:36 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1654607150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.1654607150
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.3356044571
Short name T336
Test name
Test status
Simulation time 27882300 ps
CPU time 39.16 seconds
Started Sep 18 06:04:58 PM UTC 24
Finished Sep 18 06:05:39 PM UTC 24
Peak memory 285808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3356044571 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_
ctrl_disable.3356044571
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.2318865213
Short name T885
Test name
Test status
Simulation time 6110358000 ps
CPU time 92.65 seconds
Started Sep 18 06:04:41 PM UTC 24
Finished Sep 18 06:06:16 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318865213 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.2318865213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.2928864113
Short name T794
Test name
Test status
Simulation time 6765621500 ps
CPU time 196.35 seconds
Started Sep 18 06:04:48 PM UTC 24
Finished Sep 18 06:08:07 PM UTC 24
Peak memory 302004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928864113 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.2928864113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.1850504077
Short name T1006
Test name
Test status
Simulation time 47024193200 ps
CPU time 408.2 seconds
Started Sep 18 06:04:51 PM UTC 24
Finished Sep 18 06:11:44 PM UTC 24
Peak memory 302144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1850504077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.flash_ctrl_intr_rd_slow_flash.1850504077
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.4252578296
Short name T182
Test name
Test status
Simulation time 78606200 ps
CPU time 186.29 seconds
Started Sep 18 06:04:44 PM UTC 24
Finished Sep 18 06:07:53 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252578296 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.4252578296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.383047454
Short name T862
Test name
Test status
Simulation time 36787600 ps
CPU time 25.8 seconds
Started Sep 18 06:04:52 PM UTC 24
Finished Sep 18 06:05:19 PM UTC 24
Peak memory 275252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383047454 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.383047454
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.22066358
Short name T866
Test name
Test status
Simulation time 28017700 ps
CPU time 36.43 seconds
Started Sep 18 06:04:54 PM UTC 24
Finished Sep 18 06:05:32 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22066358 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.22066358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.994076398
Short name T874
Test name
Test status
Simulation time 26099100 ps
CPU time 48.98 seconds
Started Sep 18 06:04:55 PM UTC 24
Finished Sep 18 06:05:46 PM UTC 24
Peak memory 285624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=994076398 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ct
rl_rw_evict_all_en.994076398
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.5829043
Short name T431
Test name
Test status
Simulation time 2598287800 ps
CPU time 73.31 seconds
Started Sep 18 06:05:01 PM UTC 24
Finished Sep 18 06:06:16 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5829043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/fl
ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.5829043
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.1472052084
Short name T941
Test name
Test status
Simulation time 82614900 ps
CPU time 282.67 seconds
Started Sep 18 06:04:35 PM UTC 24
Finished Sep 18 06:09:22 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1472052084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.1472052084
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.1914811767
Short name T878
Test name
Test status
Simulation time 74944200 ps
CPU time 19.02 seconds
Started Sep 18 06:05:38 PM UTC 24
Finished Sep 18 06:05:58 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1914811767 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.1914811767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.1395303821
Short name T879
Test name
Test status
Simulation time 43833500 ps
CPU time 30.05 seconds
Started Sep 18 06:05:36 PM UTC 24
Finished Sep 18 06:06:08 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395303821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.1395303821
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.2336580124
Short name T881
Test name
Test status
Simulation time 31679200 ps
CPU time 37.06 seconds
Started Sep 18 06:05:33 PM UTC 24
Finished Sep 18 06:06:12 PM UTC 24
Peak memory 285680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2336580124 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_
ctrl_disable.2336580124
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.3606398996
Short name T887
Test name
Test status
Simulation time 9050184900 ps
CPU time 67.61 seconds
Started Sep 18 06:05:13 PM UTC 24
Finished Sep 18 06:06:22 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606398996 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.3606398996
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.2406089946
Short name T906
Test name
Test status
Simulation time 2157436900 ps
CPU time 132.55 seconds
Started Sep 18 06:05:20 PM UTC 24
Finished Sep 18 06:07:35 PM UTC 24
Peak memory 306100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406089946 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.2406089946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2195371956
Short name T915
Test name
Test status
Simulation time 5642001400 ps
CPU time 162.92 seconds
Started Sep 18 06:05:23 PM UTC 24
Finished Sep 18 06:08:09 PM UTC 24
Peak memory 304132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2195371956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.flash_ctrl_intr_rd_slow_flash.2195371956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.307408324
Short name T873
Test name
Test status
Simulation time 19392100 ps
CPU time 18.34 seconds
Started Sep 18 06:05:25 PM UTC 24
Finished Sep 18 06:05:45 PM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307408324 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.307408324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.1298970504
Short name T883
Test name
Test status
Simulation time 67588900 ps
CPU time 42.42 seconds
Started Sep 18 06:05:30 PM UTC 24
Finished Sep 18 06:06:14 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1298970504 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.1298970504
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.2963012230
Short name T882
Test name
Test status
Simulation time 30140900 ps
CPU time 38.5 seconds
Started Sep 18 06:05:33 PM UTC 24
Finished Sep 18 06:06:13 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2963012230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c
trl_rw_evict_all_en.2963012230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.3977288095
Short name T894
Test name
Test status
Simulation time 7439825100 ps
CPU time 75.81 seconds
Started Sep 18 06:05:33 PM UTC 24
Finished Sep 18 06:06:51 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3977288095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3977288095
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.4251911148
Short name T896
Test name
Test status
Simulation time 25217100 ps
CPU time 101.14 seconds
Started Sep 18 06:05:13 PM UTC 24
Finished Sep 18 06:06:56 PM UTC 24
Peak memory 287572 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251911148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.4251911148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.198321408
Short name T484
Test name
Test status
Simulation time 47620600 ps
CPU time 20.2 seconds
Started Sep 18 05:09:58 PM UTC 24
Finished Sep 18 05:10:19 PM UTC 24
Peak memory 269244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=198321408 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.198321408
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.1339507103
Short name T482
Test name
Test status
Simulation time 35094400 ps
CPU time 20.3 seconds
Started Sep 18 05:09:41 PM UTC 24
Finished Sep 18 05:10:03 PM UTC 24
Peak memory 273312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1339507103 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.1339507103
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.891184140
Short name T108
Test name
Test status
Simulation time 21261400 ps
CPU time 22.97 seconds
Started Sep 18 05:09:19 PM UTC 24
Finished Sep 18 05:09:43 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891184140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.891184140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.360685276
Short name T173
Test name
Test status
Simulation time 1281506100 ps
CPU time 221.86 seconds
Started Sep 18 05:07:47 PM UTC 24
Finished Sep 18 05:11:33 PM UTC 24
Peak memory 289784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=360685276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 3.flash_ctrl_derr_detect.360685276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.2070089724
Short name T128
Test name
Test status
Simulation time 30598100 ps
CPU time 25.27 seconds
Started Sep 18 05:09:06 PM UTC 24
Finished Sep 18 05:09:33 PM UTC 24
Peak memory 285560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2070089724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_disable.2070089724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.2195822229
Short name T257
Test name
Test status
Simulation time 5560535600 ps
CPU time 460.68 seconds
Started Sep 18 05:05:30 PM UTC 24
Finished Sep 18 05:13:17 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195822229 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.2195822229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.3785079568
Short name T298
Test name
Test status
Simulation time 9853881900 ps
CPU time 2594.58 seconds
Started Sep 18 05:06:03 PM UTC 24
Finished Sep 18 05:49:43 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785079568 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.3785079568
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.603866786
Short name T555
Test name
Test status
Simulation time 763003600 ps
CPU time 1264.66 seconds
Started Sep 18 05:06:03 PM UTC 24
Finished Sep 18 05:27:21 PM UTC 24
Peak memory 283404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603866786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/fl
ash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.603866786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.2493259236
Short name T70
Test name
Test status
Simulation time 1679320400 ps
CPU time 42.38 seconds
Started Sep 18 05:05:53 PM UTC 24
Finished Sep 18 05:06:36 PM UTC 24
Peak memory 273232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24
93259236 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc
h_code.2493259236
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.1056837232
Short name T438
Test name
Test status
Simulation time 48915463600 ps
CPU time 3556.08 seconds
Started Sep 18 05:05:59 PM UTC 24
Finished Sep 18 06:05:55 PM UTC 24
Peak memory 275452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056837232 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.1056837232
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.3914977359
Short name T284
Test name
Test status
Simulation time 430139700 ps
CPU time 236.05 seconds
Started Sep 18 05:05:18 PM UTC 24
Finished Sep 18 05:09:18 PM UTC 24
Peak memory 275212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3914977359 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.3914977359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.886312494
Short name T111
Test name
Test status
Simulation time 10027867500 ps
CPU time 114.55 seconds
Started Sep 18 05:09:55 PM UTC 24
Finished Sep 18 05:11:52 PM UTC 24
Peak memory 287492 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=886312494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.886312494
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.2605021555
Short name T483
Test name
Test status
Simulation time 27048600 ps
CPU time 19.26 seconds
Started Sep 18 05:09:45 PM UTC 24
Finished Sep 18 05:10:06 PM UTC 24
Peak memory 268968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2605021555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_hw_read_seed_err.2605021555
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.1302758009
Short name T199
Test name
Test status
Simulation time 40126775200 ps
CPU time 779.41 seconds
Started Sep 18 05:05:31 PM UTC 24
Finished Sep 18 05:18:39 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302758009
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.1302758009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.3227048036
Short name T480
Test name
Test status
Simulation time 2231399000 ps
CPU time 187.74 seconds
Started Sep 18 05:05:28 PM UTC 24
Finished Sep 18 05:08:39 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227048036 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.3227048036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.474243316
Short name T499
Test name
Test status
Simulation time 21366143600 ps
CPU time 439.73 seconds
Started Sep 18 05:08:15 PM UTC 24
Finished Sep 18 05:15:40 PM UTC 24
Peak memory 336932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=474243316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integrity.474243316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.1669505670
Short name T418
Test name
Test status
Simulation time 5279926100 ps
CPU time 78.29 seconds
Started Sep 18 05:08:21 PM UTC 24
Finished Sep 18 05:09:41 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669505670 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.1669505670
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.1113811373
Short name T498
Test name
Test status
Simulation time 144471805500 ps
CPU time 428.41 seconds
Started Sep 18 05:08:24 PM UTC 24
Finished Sep 18 05:15:38 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113811373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.1113811373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.523646137
Short name T162
Test name
Test status
Simulation time 3916820500 ps
CPU time 99.99 seconds
Started Sep 18 05:06:04 PM UTC 24
Finished Sep 18 05:07:46 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523646137 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.523646137
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.310418939
Short name T295
Test name
Test status
Simulation time 48546000 ps
CPU time 24.65 seconds
Started Sep 18 05:09:43 PM UTC 24
Finished Sep 18 05:10:09 PM UTC 24
Peak memory 275264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=310418939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_lcmgr_intg.310418939
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.2565449762
Short name T83
Test name
Test status
Simulation time 3293388400 ps
CPU time 130.36 seconds
Started Sep 18 05:06:07 PM UTC 24
Finished Sep 18 05:08:20 PM UTC 24
Peak memory 272984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565449762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.2565449762
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.3692057801
Short name T139
Test name
Test status
Simulation time 429678800 ps
CPU time 202.33 seconds
Started Sep 18 05:05:43 PM UTC 24
Finished Sep 18 05:09:09 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692057801 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.3692057801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.135848136
Short name T226
Test name
Test status
Simulation time 3857681200 ps
CPU time 150.75 seconds
Started Sep 18 05:07:56 PM UTC 24
Finished Sep 18 05:10:30 PM UTC 24
Peak memory 306168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=135848136 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 3.flash_ctrl_oversize_error.135848136
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1299027362
Short name T238
Test name
Test status
Simulation time 27176500 ps
CPU time 21.51 seconds
Started Sep 18 05:09:40 PM UTC 24
Finished Sep 18 05:10:03 PM UTC 24
Peak memory 271452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1299027362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1299027362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.3076119261
Short name T258
Test name
Test status
Simulation time 2720809300 ps
CPU time 696.39 seconds
Started Sep 18 05:05:27 PM UTC 24
Finished Sep 18 05:17:11 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3076119261 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.3076119261
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.1536559270
Short name T237
Test name
Test status
Simulation time 23822400 ps
CPU time 19.12 seconds
Started Sep 18 05:09:34 PM UTC 24
Finished Sep 18 05:09:55 PM UTC 24
Peak memory 273412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1536559270 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.1536559270
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.161955412
Short name T416
Test name
Test status
Simulation time 54958600 ps
CPU time 26.37 seconds
Started Sep 18 05:08:38 PM UTC 24
Finished Sep 18 05:09:06 PM UTC 24
Peak memory 271092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=161955412 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.161955412
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.1013389742
Short name T233
Test name
Test status
Simulation time 95673700 ps
CPU time 183.46 seconds
Started Sep 18 05:05:17 PM UTC 24
Finished Sep 18 05:08:23 PM UTC 24
Peak memory 291784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013389742 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.1013389742
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.552281008
Short name T476
Test name
Test status
Simulation time 93891300 ps
CPU time 125.14 seconds
Started Sep 18 05:05:25 PM UTC 24
Finished Sep 18 05:07:32 PM UTC 24
Peak memory 273152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=552281008 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.552281008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.1260248949
Short name T477
Test name
Test status
Simulation time 18576400 ps
CPU time 39.91 seconds
Started Sep 18 05:07:14 PM UTC 24
Finished Sep 18 05:07:55 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1260248949 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_read_word_sweep_derr.1260248949
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.3208430080
Short name T415
Test name
Test status
Simulation time 194964000 ps
CPU time 28.47 seconds
Started Sep 18 05:06:37 PM UTC 24
Finished Sep 18 05:07:07 PM UTC 24
Peak memory 275384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3208430080 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.3208430080
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.3168397441
Short name T230
Test name
Test status
Simulation time 3335897300 ps
CPU time 125.65 seconds
Started Sep 18 05:06:10 PM UTC 24
Finished Sep 18 05:08:18 PM UTC 24
Peak memory 302112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3168397441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.3168397441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.1021196039
Short name T316
Test name
Test status
Simulation time 2379544200 ps
CPU time 167.67 seconds
Started Sep 18 05:07:14 PM UTC 24
Finished Sep 18 05:10:04 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1021196039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.1021196039
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2911409903
Short name T413
Test name
Test status
Simulation time 2664528000 ps
CPU time 145.57 seconds
Started Sep 18 05:06:37 PM UTC 24
Finished Sep 18 05:09:05 PM UTC 24
Peak memory 308468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2911409903 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_ro_serr.2911409903
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.1275793097
Short name T492
Test name
Test status
Simulation time 80060432200 ps
CPU time 465.18 seconds
Started Sep 18 05:06:18 PM UTC 24
Finished Sep 18 05:14:09 PM UTC 24
Peak memory 337108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275793097 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.1275793097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.250299286
Short name T49
Test name
Test status
Simulation time 31949400 ps
CPU time 57.76 seconds
Started Sep 18 05:08:40 PM UTC 24
Finished Sep 18 05:09:39 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250299286 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.250299286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.3532787318
Short name T459
Test name
Test status
Simulation time 63042000 ps
CPU time 47.23 seconds
Started Sep 18 05:08:55 PM UTC 24
Finished Sep 18 05:09:44 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3532787318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw_evict_all_en.3532787318
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.1017059533
Short name T225
Test name
Test status
Simulation time 2388930000 ps
CPU time 156.35 seconds
Started Sep 18 05:06:44 PM UTC 24
Finished Sep 18 05:09:23 PM UTC 24
Peak memory 292024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1017059533 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.1017059533
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.758347702
Short name T146
Test name
Test status
Simulation time 17176102600 ps
CPU time 6945.53 seconds
Started Sep 18 05:09:06 PM UTC 24
Finished Sep 18 07:06:05 PM UTC 24
Peak memory 316240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758347702 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.758347702
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.2248666790
Short name T346
Test name
Test status
Simulation time 903242800 ps
CPU time 68.21 seconds
Started Sep 18 05:09:10 PM UTC 24
Finished Sep 18 05:10:20 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248666790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.2248666790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.3786356837
Short name T479
Test name
Test status
Simulation time 1447079200 ps
CPU time 70.35 seconds
Started Sep 18 05:07:08 PM UTC 24
Finished Sep 18 05:08:20 PM UTC 24
Peak memory 275384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378
6356837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser
r_address.3786356837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.1105539312
Short name T478
Test name
Test status
Simulation time 6712265000 ps
CPU time 73.5 seconds
Started Sep 18 05:06:59 PM UTC 24
Finished Sep 18 05:08:14 PM UTC 24
Peak memory 285684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11
05539312 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_se
rr_counter.1105539312
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.3398149826
Short name T411
Test name
Test status
Simulation time 35670500 ps
CPU time 200.3 seconds
Started Sep 18 05:05:13 PM UTC 24
Finished Sep 18 05:08:37 PM UTC 24
Peak memory 289484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398149826 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.3398149826
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.2391772554
Short name T472
Test name
Test status
Simulation time 37447500 ps
CPU time 42.06 seconds
Started Sep 18 05:05:15 PM UTC 24
Finished Sep 18 05:05:58 PM UTC 24
Peak memory 270912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391772554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.2391772554
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.1598285218
Short name T533
Test name
Test status
Simulation time 620078200 ps
CPU time 807.92 seconds
Started Sep 18 05:09:19 PM UTC 24
Finished Sep 18 05:22:56 PM UTC 24
Peak memory 287496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598285218 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.1598285218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.708722330
Short name T473
Test name
Test status
Simulation time 91981500 ps
CPU time 43.21 seconds
Started Sep 18 05:05:18 PM UTC 24
Finished Sep 18 05:06:02 PM UTC 24
Peak memory 272968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=708722330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.708722330
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.3603970231
Short name T419
Test name
Test status
Simulation time 8229776400 ps
CPU time 161.85 seconds
Started Sep 18 05:06:10 PM UTC 24
Finished Sep 18 05:08:55 PM UTC 24
Peak memory 271360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3603970231 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.3603970231
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.1061513208
Short name T888
Test name
Test status
Simulation time 105800300 ps
CPU time 20.36 seconds
Started Sep 18 06:06:03 PM UTC 24
Finished Sep 18 06:06:25 PM UTC 24
Peak memory 269308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061513208 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.1061513208
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.2858526166
Short name T886
Test name
Test status
Simulation time 17427000 ps
CPU time 26.56 seconds
Started Sep 18 06:05:54 PM UTC 24
Finished Sep 18 06:06:22 PM UTC 24
Peak memory 294920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2858526166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.2858526166
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.903870484
Short name T889
Test name
Test status
Simulation time 26931900 ps
CPU time 36.08 seconds
Started Sep 18 06:05:47 PM UTC 24
Finished Sep 18 06:06:26 PM UTC 24
Peak memory 285820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=903870484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c
trl_disable.903870484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.4031720964
Short name T928
Test name
Test status
Simulation time 2879928700 ps
CPU time 179.02 seconds
Started Sep 18 06:05:44 PM UTC 24
Finished Sep 18 06:08:46 PM UTC 24
Peak memory 302004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031720964 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.4031720964
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.1417684921
Short name T975
Test name
Test status
Simulation time 28314849800 ps
CPU time 280.14 seconds
Started Sep 18 06:05:45 PM UTC 24
Finished Sep 18 06:10:30 PM UTC 24
Peak memory 302080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1417684921 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 30.flash_ctrl_intr_rd_slow_flash.1417684921
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.2618958645
Short name T934
Test name
Test status
Simulation time 74200600 ps
CPU time 194.64 seconds
Started Sep 18 06:05:42 PM UTC 24
Finished Sep 18 06:09:00 PM UTC 24
Peak memory 271272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618958645 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.2618958645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.466282874
Short name T891
Test name
Test status
Simulation time 60705100 ps
CPU time 51.34 seconds
Started Sep 18 06:05:45 PM UTC 24
Finished Sep 18 06:06:38 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466282874 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.466282874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.906668700
Short name T462
Test name
Test status
Simulation time 123871900 ps
CPU time 50.87 seconds
Started Sep 18 06:05:46 PM UTC 24
Finished Sep 18 06:06:40 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=906668700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ct
rl_rw_evict_all_en.906668700
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.3812487654
Short name T897
Test name
Test status
Simulation time 1682241000 ps
CPU time 70.29 seconds
Started Sep 18 06:05:49 PM UTC 24
Finished Sep 18 06:07:01 PM UTC 24
Peak memory 273108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812487654 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.3812487654
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.3681614728
Short name T919
Test name
Test status
Simulation time 86297900 ps
CPU time 153.03 seconds
Started Sep 18 06:05:40 PM UTC 24
Finished Sep 18 06:08:15 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681614728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.3681614728
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.3693408704
Short name T893
Test name
Test status
Simulation time 157297500 ps
CPU time 24.26 seconds
Started Sep 18 06:06:22 PM UTC 24
Finished Sep 18 06:06:48 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3693408704 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.3693408704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.1144432991
Short name T892
Test name
Test status
Simulation time 64948700 ps
CPU time 27.33 seconds
Started Sep 18 06:06:17 PM UTC 24
Finished Sep 18 06:06:46 PM UTC 24
Peak memory 294920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144432991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.1144432991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.3830874715
Short name T421
Test name
Test status
Simulation time 15523200 ps
CPU time 25.2 seconds
Started Sep 18 06:06:16 PM UTC 24
Finished Sep 18 06:06:42 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3830874715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_
ctrl_disable.3830874715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.1722880863
Short name T967
Test name
Test status
Simulation time 3271549000 ps
CPU time 251.52 seconds
Started Sep 18 06:06:03 PM UTC 24
Finished Sep 18 06:10:19 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722880863 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.1722880863
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.423263063
Short name T926
Test name
Test status
Simulation time 2607156300 ps
CPU time 145.75 seconds
Started Sep 18 06:06:13 PM UTC 24
Finished Sep 18 06:08:41 PM UTC 24
Peak memory 306124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423263063 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.423263063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.4138515148
Short name T961
Test name
Test status
Simulation time 10308292000 ps
CPU time 227.55 seconds
Started Sep 18 06:06:13 PM UTC 24
Finished Sep 18 06:10:04 PM UTC 24
Peak memory 301884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=4138515148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 31.flash_ctrl_intr_rd_slow_flash.4138515148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.2011315735
Short name T936
Test name
Test status
Simulation time 68016900 ps
CPU time 177.07 seconds
Started Sep 18 06:06:09 PM UTC 24
Finished Sep 18 06:09:09 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2011315735 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.2011315735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.1880459301
Short name T895
Test name
Test status
Simulation time 67740700 ps
CPU time 37.4 seconds
Started Sep 18 06:06:14 PM UTC 24
Finished Sep 18 06:06:53 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880459301 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.1880459301
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.1957982339
Short name T898
Test name
Test status
Simulation time 129704200 ps
CPU time 51.4 seconds
Started Sep 18 06:06:15 PM UTC 24
Finished Sep 18 06:07:08 PM UTC 24
Peak memory 285664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1957982339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c
trl_rw_evict_all_en.1957982339
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.3005719172
Short name T938
Test name
Test status
Simulation time 35473800 ps
CPU time 187.19 seconds
Started Sep 18 06:06:03 PM UTC 24
Finished Sep 18 06:09:14 PM UTC 24
Peak memory 277376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005719172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3005719172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.1807623268
Short name T902
Test name
Test status
Simulation time 131272700 ps
CPU time 25.1 seconds
Started Sep 18 06:06:54 PM UTC 24
Finished Sep 18 06:07:20 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807623268 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.1807623268
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.422985466
Short name T900
Test name
Test status
Simulation time 14936400 ps
CPU time 22.35 seconds
Started Sep 18 06:06:52 PM UTC 24
Finished Sep 18 06:07:15 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422985466 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.422985466
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.402144070
Short name T955
Test name
Test status
Simulation time 12095989900 ps
CPU time 200.64 seconds
Started Sep 18 06:06:26 PM UTC 24
Finished Sep 18 06:09:50 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402144070 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.402144070
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.641113056
Short name T969
Test name
Test status
Simulation time 6577505600 ps
CPU time 230.3 seconds
Started Sep 18 06:06:29 PM UTC 24
Finished Sep 18 06:10:23 PM UTC 24
Peak memory 302188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641113056 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.641113056
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.1545775178
Short name T960
Test name
Test status
Simulation time 30966935300 ps
CPU time 200.29 seconds
Started Sep 18 06:06:39 PM UTC 24
Finished Sep 18 06:10:02 PM UTC 24
Peak memory 301848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1545775178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 32.flash_ctrl_intr_rd_slow_flash.1545775178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.1144554890
Short name T964
Test name
Test status
Simulation time 42321500 ps
CPU time 219.64 seconds
Started Sep 18 06:06:27 PM UTC 24
Finished Sep 18 06:10:10 PM UTC 24
Peak memory 275516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1144554890 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.1144554890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.1049527196
Short name T452
Test name
Test status
Simulation time 107419600 ps
CPU time 51.9 seconds
Started Sep 18 06:06:40 PM UTC 24
Finished Sep 18 06:07:34 PM UTC 24
Peak memory 287608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1049527196 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.1049527196
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.290443357
Short name T460
Test name
Test status
Simulation time 33777100 ps
CPU time 32.79 seconds
Started Sep 18 06:06:43 PM UTC 24
Finished Sep 18 06:07:17 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=290443357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ct
rl_rw_evict_all_en.290443357
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.1650299608
Short name T433
Test name
Test status
Simulation time 1593288700 ps
CPU time 79.22 seconds
Started Sep 18 06:06:49 PM UTC 24
Finished Sep 18 06:08:10 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650299608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.1650299608
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.816882843
Short name T944
Test name
Test status
Simulation time 117921600 ps
CPU time 180.13 seconds
Started Sep 18 06:06:24 PM UTC 24
Finished Sep 18 06:09:27 PM UTC 24
Peak memory 289676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=816882843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.816882843
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.1563068148
Short name T910
Test name
Test status
Simulation time 161633000 ps
CPU time 22.81 seconds
Started Sep 18 06:07:30 PM UTC 24
Finished Sep 18 06:07:54 PM UTC 24
Peak memory 269308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1563068148 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.1563068148
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.3089772900
Short name T909
Test name
Test status
Simulation time 26157500 ps
CPU time 23.34 seconds
Started Sep 18 06:07:26 PM UTC 24
Finished Sep 18 06:07:51 PM UTC 24
Peak memory 284740 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089772900 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3089772900
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.876274081
Short name T908
Test name
Test status
Simulation time 23282900 ps
CPU time 29.39 seconds
Started Sep 18 06:07:19 PM UTC 24
Finished Sep 18 06:07:50 PM UTC 24
Peak memory 285884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=876274081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c
trl_disable.876274081
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.1521208344
Short name T912
Test name
Test status
Simulation time 599677500 ps
CPU time 58.79 seconds
Started Sep 18 06:07:02 PM UTC 24
Finished Sep 18 06:08:02 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521208344 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.1521208344
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.3234786
Short name T992
Test name
Test status
Simulation time 24522343100 ps
CPU time 238.39 seconds
Started Sep 18 06:07:12 PM UTC 24
Finished Sep 18 06:11:15 PM UTC 24
Peak memory 302036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234786 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.3234786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.2563958929
Short name T1028
Test name
Test status
Simulation time 24408080900 ps
CPU time 323.46 seconds
Started Sep 18 06:07:15 PM UTC 24
Finished Sep 18 06:12:44 PM UTC 24
Peak memory 306208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2563958929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.flash_ctrl_intr_rd_slow_flash.2563958929
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.1607153309
Short name T962
Test name
Test status
Simulation time 78443000 ps
CPU time 175.56 seconds
Started Sep 18 06:07:09 PM UTC 24
Finished Sep 18 06:10:08 PM UTC 24
Peak memory 271416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607153309 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.1607153309
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.3755018213
Short name T911
Test name
Test status
Simulation time 26752800 ps
CPU time 42.91 seconds
Started Sep 18 06:07:17 PM UTC 24
Finished Sep 18 06:08:01 PM UTC 24
Peak memory 287932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3755018213 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.3755018213
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.2669540478
Short name T918
Test name
Test status
Simulation time 71205800 ps
CPU time 56.07 seconds
Started Sep 18 06:07:17 PM UTC 24
Finished Sep 18 06:08:14 PM UTC 24
Peak memory 285920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2669540478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_c
trl_rw_evict_all_en.2669540478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.1958609987
Short name T935
Test name
Test status
Simulation time 2844586100 ps
CPU time 100.46 seconds
Started Sep 18 06:07:21 PM UTC 24
Finished Sep 18 06:09:04 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958609987 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1958609987
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.3922455645
Short name T951
Test name
Test status
Simulation time 75072300 ps
CPU time 164.55 seconds
Started Sep 18 06:06:57 PM UTC 24
Finished Sep 18 06:09:44 PM UTC 24
Peak memory 287616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922455645 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.3922455645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.3553217324
Short name T922
Test name
Test status
Simulation time 64176000 ps
CPU time 24.38 seconds
Started Sep 18 06:08:03 PM UTC 24
Finished Sep 18 06:08:29 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553217324 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.3553217324
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.3360858933
Short name T921
Test name
Test status
Simulation time 53583600 ps
CPU time 25.15 seconds
Started Sep 18 06:08:02 PM UTC 24
Finished Sep 18 06:08:29 PM UTC 24
Peak memory 294984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360858933 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.3360858933
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.336948145
Short name T920
Test name
Test status
Simulation time 83351900 ps
CPU time 30.67 seconds
Started Sep 18 06:07:53 PM UTC 24
Finished Sep 18 06:08:25 PM UTC 24
Peak memory 285692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=336948145 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c
trl_disable.336948145
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.1449230066
Short name T945
Test name
Test status
Simulation time 4344800100 ps
CPU time 112.68 seconds
Started Sep 18 06:07:33 PM UTC 24
Finished Sep 18 06:09:28 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1449230066 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.1449230066
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.1111435405
Short name T950
Test name
Test status
Simulation time 3111762300 ps
CPU time 126.19 seconds
Started Sep 18 06:07:36 PM UTC 24
Finished Sep 18 06:09:44 PM UTC 24
Peak memory 306100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1111435405 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.1111435405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.3089451712
Short name T118
Test name
Test status
Simulation time 12247295800 ps
CPU time 311.6 seconds
Started Sep 18 06:07:41 PM UTC 24
Finished Sep 18 06:12:57 PM UTC 24
Peak memory 305956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3089451712 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.flash_ctrl_intr_rd_slow_flash.3089451712
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.2230676646
Short name T974
Test name
Test status
Simulation time 75642300 ps
CPU time 170.42 seconds
Started Sep 18 06:07:34 PM UTC 24
Finished Sep 18 06:10:28 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230676646 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.2230676646
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.1811106896
Short name T927
Test name
Test status
Simulation time 52402100 ps
CPU time 52.83 seconds
Started Sep 18 06:07:51 PM UTC 24
Finished Sep 18 06:08:45 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811106896 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.1811106896
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.155236761
Short name T923
Test name
Test status
Simulation time 31969000 ps
CPU time 38.79 seconds
Started Sep 18 06:07:52 PM UTC 24
Finished Sep 18 06:08:32 PM UTC 24
Peak memory 285564 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=155236761 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ct
rl_rw_evict_all_en.155236761
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.3028515778
Short name T947
Test name
Test status
Simulation time 2699780300 ps
CPU time 101.34 seconds
Started Sep 18 06:07:55 PM UTC 24
Finished Sep 18 06:09:39 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028515778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3028515778
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.4058946623
Short name T997
Test name
Test status
Simulation time 38649500 ps
CPU time 223.64 seconds
Started Sep 18 06:07:32 PM UTC 24
Finished Sep 18 06:11:19 PM UTC 24
Peak memory 289484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4058946623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.4058946623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.3496318697
Short name T932
Test name
Test status
Simulation time 53721500 ps
CPU time 25.4 seconds
Started Sep 18 06:08:24 PM UTC 24
Finished Sep 18 06:08:50 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496318697 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.3496318697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.388838620
Short name T925
Test name
Test status
Simulation time 46741400 ps
CPU time 20.12 seconds
Started Sep 18 06:08:17 PM UTC 24
Finished Sep 18 06:08:38 PM UTC 24
Peak memory 295120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388838620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.388838620
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.728616934
Short name T931
Test name
Test status
Simulation time 32314600 ps
CPU time 33.12 seconds
Started Sep 18 06:08:15 PM UTC 24
Finished Sep 18 06:08:50 PM UTC 24
Peak memory 285716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=728616934 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c
trl_disable.728616934
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.4246056509
Short name T929
Test name
Test status
Simulation time 2469010200 ps
CPU time 37.72 seconds
Started Sep 18 06:08:08 PM UTC 24
Finished Sep 18 06:08:47 PM UTC 24
Peak memory 271052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246056509 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.4246056509
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.446570016
Short name T966
Test name
Test status
Simulation time 1585091400 ps
CPU time 127.67 seconds
Started Sep 18 06:08:09 PM UTC 24
Finished Sep 18 06:10:19 PM UTC 24
Peak memory 302188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=446570016 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.446570016
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.3097094186
Short name T1083
Test name
Test status
Simulation time 13623869800 ps
CPU time 370.16 seconds
Started Sep 18 06:08:10 PM UTC 24
Finished Sep 18 06:14:25 PM UTC 24
Peak memory 301860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3097094186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.flash_ctrl_intr_rd_slow_flash.3097094186
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.2251727097
Short name T990
Test name
Test status
Simulation time 36440300 ps
CPU time 177.84 seconds
Started Sep 18 06:08:08 PM UTC 24
Finished Sep 18 06:11:08 PM UTC 24
Peak memory 271208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2251727097 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.2251727097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.2051255175
Short name T930
Test name
Test status
Simulation time 277105100 ps
CPU time 38.25 seconds
Started Sep 18 06:08:10 PM UTC 24
Finished Sep 18 06:08:50 PM UTC 24
Peak memory 287868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051255175 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.2051255175
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.1862808371
Short name T933
Test name
Test status
Simulation time 73314300 ps
CPU time 40.71 seconds
Started Sep 18 06:08:14 PM UTC 24
Finished Sep 18 06:08:56 PM UTC 24
Peak memory 285632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1862808371 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c
trl_rw_evict_all_en.1862808371
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.453783170
Short name T434
Test name
Test status
Simulation time 506588600 ps
CPU time 97.22 seconds
Started Sep 18 06:08:16 PM UTC 24
Finished Sep 18 06:09:56 PM UTC 24
Peak memory 275352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=453783170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.453783170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.1089606983
Short name T958
Test name
Test status
Simulation time 40743900 ps
CPU time 113.34 seconds
Started Sep 18 06:08:05 PM UTC 24
Finished Sep 18 06:10:00 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1089606983 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.1089606983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.2276327587
Short name T937
Test name
Test status
Simulation time 190678700 ps
CPU time 19.34 seconds
Started Sep 18 06:08:51 PM UTC 24
Finished Sep 18 06:09:12 PM UTC 24
Peak memory 275188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276327587 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.2276327587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.2452899486
Short name T939
Test name
Test status
Simulation time 20896700 ps
CPU time 28.63 seconds
Started Sep 18 06:08:48 PM UTC 24
Finished Sep 18 06:09:18 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2452899486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.2452899486
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.1498620258
Short name T942
Test name
Test status
Simulation time 108610200 ps
CPU time 35.73 seconds
Started Sep 18 06:08:47 PM UTC 24
Finished Sep 18 06:09:24 PM UTC 24
Peak memory 285640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1498620258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_
ctrl_disable.1498620258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.1099393965
Short name T957
Test name
Test status
Simulation time 4145342100 ps
CPU time 81.71 seconds
Started Sep 18 06:08:30 PM UTC 24
Finished Sep 18 06:09:54 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1099393965 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.1099393965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.1188823325
Short name T996
Test name
Test status
Simulation time 3636101300 ps
CPU time 162.51 seconds
Started Sep 18 06:08:33 PM UTC 24
Finished Sep 18 06:11:19 PM UTC 24
Peak memory 301992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188823325 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.1188823325
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.779049076
Short name T983
Test name
Test status
Simulation time 11833814900 ps
CPU time 129.58 seconds
Started Sep 18 06:08:38 PM UTC 24
Finished Sep 18 06:10:50 PM UTC 24
Peak memory 303944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=779049076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 36.flash_ctrl_intr_rd_slow_flash.779049076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.1285740456
Short name T1004
Test name
Test status
Simulation time 65702900 ps
CPU time 183.8 seconds
Started Sep 18 06:08:30 PM UTC 24
Finished Sep 18 06:11:38 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285740456 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.1285740456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.2733844657
Short name T943
Test name
Test status
Simulation time 30484000 ps
CPU time 44.94 seconds
Started Sep 18 06:08:38 PM UTC 24
Finished Sep 18 06:09:25 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733844657 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.2733844657
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.2157691546
Short name T946
Test name
Test status
Simulation time 28231000 ps
CPU time 49.22 seconds
Started Sep 18 06:08:41 PM UTC 24
Finished Sep 18 06:09:32 PM UTC 24
Peak memory 279420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2157691546 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c
trl_rw_evict_all_en.2157691546
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.2695561099
Short name T954
Test name
Test status
Simulation time 684098700 ps
CPU time 59.84 seconds
Started Sep 18 06:08:47 PM UTC 24
Finished Sep 18 06:09:48 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2695561099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.2695561099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.2208017156
Short name T998
Test name
Test status
Simulation time 33336500 ps
CPU time 175.9 seconds
Started Sep 18 06:08:26 PM UTC 24
Finished Sep 18 06:11:25 PM UTC 24
Peak memory 289472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2208017156 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.2208017156
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.623631932
Short name T948
Test name
Test status
Simulation time 40965500 ps
CPU time 15.93 seconds
Started Sep 18 06:09:23 PM UTC 24
Finished Sep 18 06:09:40 PM UTC 24
Peak memory 269256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623631932 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.623631932
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.693821609
Short name T953
Test name
Test status
Simulation time 22360700 ps
CPU time 23.68 seconds
Started Sep 18 06:09:20 PM UTC 24
Finished Sep 18 06:09:45 PM UTC 24
Peak memory 284752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693821609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.693821609
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.1157209138
Short name T949
Test name
Test status
Simulation time 61016400 ps
CPU time 26.89 seconds
Started Sep 18 06:09:15 PM UTC 24
Finished Sep 18 06:09:43 PM UTC 24
Peak memory 285616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1157209138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_
ctrl_disable.1157209138
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.1972208880
Short name T952
Test name
Test status
Simulation time 1530139800 ps
CPU time 51.35 seconds
Started Sep 18 06:08:51 PM UTC 24
Finished Sep 18 06:09:44 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972208880 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.1972208880
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.4293001459
Short name T985
Test name
Test status
Simulation time 1638365100 ps
CPU time 111.07 seconds
Started Sep 18 06:09:01 PM UTC 24
Finished Sep 18 06:10:55 PM UTC 24
Peak memory 306124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293001459 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.4293001459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.1273793678
Short name T1039
Test name
Test status
Simulation time 12158531900 ps
CPU time 237.91 seconds
Started Sep 18 06:09:04 PM UTC 24
Finished Sep 18 06:13:06 PM UTC 24
Peak memory 304004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1273793678 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 37.flash_ctrl_intr_rd_slow_flash.1273793678
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.915254289
Short name T994
Test name
Test status
Simulation time 314085300 ps
CPU time 136.37 seconds
Started Sep 18 06:08:57 PM UTC 24
Finished Sep 18 06:11:16 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=915254289 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.915254289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.1197315916
Short name T959
Test name
Test status
Simulation time 104007200 ps
CPU time 50.81 seconds
Started Sep 18 06:09:10 PM UTC 24
Finished Sep 18 06:10:02 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1197315916 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.1197315916
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.2512432264
Short name T973
Test name
Test status
Simulation time 1168760600 ps
CPU time 66.04 seconds
Started Sep 18 06:09:19 PM UTC 24
Finished Sep 18 06:10:27 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2512432264 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.2512432264
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.1259467441
Short name T984
Test name
Test status
Simulation time 53224600 ps
CPU time 118.32 seconds
Started Sep 18 06:08:51 PM UTC 24
Finished Sep 18 06:10:52 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259467441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.1259467441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.2481965
Short name T965
Test name
Test status
Simulation time 51295500 ps
CPU time 28.17 seconds
Started Sep 18 06:09:46 PM UTC 24
Finished Sep 18 06:10:15 PM UTC 24
Peak memory 269240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481965 -assert nopostproc +UVM_TESTNAME=fl
ash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.2481965
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.2690722377
Short name T963
Test name
Test status
Simulation time 47288600 ps
CPU time 22.89 seconds
Started Sep 18 06:09:46 PM UTC 24
Finished Sep 18 06:10:10 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690722377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.2690722377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.226840387
Short name T971
Test name
Test status
Simulation time 46139700 ps
CPU time 38.52 seconds
Started Sep 18 06:09:44 PM UTC 24
Finished Sep 18 06:10:24 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=226840387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c
trl_disable.226840387
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.1980808315
Short name T1007
Test name
Test status
Simulation time 28979350200 ps
CPU time 138.86 seconds
Started Sep 18 06:09:25 PM UTC 24
Finished Sep 18 06:11:47 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980808315 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.1980808315
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.4278989882
Short name T1056
Test name
Test status
Simulation time 1481242900 ps
CPU time 237.99 seconds
Started Sep 18 06:09:30 PM UTC 24
Finished Sep 18 06:13:32 PM UTC 24
Peak memory 301996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278989882 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.4278989882
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.549691659
Short name T1104
Test name
Test status
Simulation time 109422335700 ps
CPU time 375.75 seconds
Started Sep 18 06:09:33 PM UTC 24
Finished Sep 18 06:15:54 PM UTC 24
Peak memory 304196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=549691659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 38.flash_ctrl_intr_rd_slow_flash.549691659
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.2383337735
Short name T192
Test name
Test status
Simulation time 34280100 ps
CPU time 151.18 seconds
Started Sep 18 06:09:28 PM UTC 24
Finished Sep 18 06:12:01 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383337735 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.2383337735
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict.2361988442
Short name T968
Test name
Test status
Simulation time 29923800 ps
CPU time 41.01 seconds
Started Sep 18 06:09:39 PM UTC 24
Finished Sep 18 06:10:22 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361988442 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_rw_evict.2361988442
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.3013020790
Short name T972
Test name
Test status
Simulation time 28715100 ps
CPU time 42.79 seconds
Started Sep 18 06:09:41 PM UTC 24
Finished Sep 18 06:10:25 PM UTC 24
Peak memory 281536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3013020790 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c
trl_rw_evict_all_en.3013020790
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.246895832
Short name T980
Test name
Test status
Simulation time 885663000 ps
CPU time 57.38 seconds
Started Sep 18 06:09:46 PM UTC 24
Finished Sep 18 06:10:44 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=246895832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.246895832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.3305356140
Short name T1000
Test name
Test status
Simulation time 18359600 ps
CPU time 124.08 seconds
Started Sep 18 06:09:24 PM UTC 24
Finished Sep 18 06:11:31 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305356140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.3305356140
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.2723122102
Short name T976
Test name
Test status
Simulation time 226349400 ps
CPU time 24.13 seconds
Started Sep 18 06:10:05 PM UTC 24
Finished Sep 18 06:10:30 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723122102 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.2723122102
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.2645481724
Short name T977
Test name
Test status
Simulation time 23730100 ps
CPU time 25.84 seconds
Started Sep 18 06:10:03 PM UTC 24
Finished Sep 18 06:10:31 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2645481724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.2645481724
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.2957331373
Short name T1003
Test name
Test status
Simulation time 2365886900 ps
CPU time 106.21 seconds
Started Sep 18 06:09:49 PM UTC 24
Finished Sep 18 06:11:38 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957331373 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.2957331373
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.1733234350
Short name T1037
Test name
Test status
Simulation time 11790557200 ps
CPU time 180.32 seconds
Started Sep 18 06:09:56 PM UTC 24
Finished Sep 18 06:13:00 PM UTC 24
Peak memory 303900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1733234350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.flash_ctrl_intr_rd_slow_flash.1733234350
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.2238538644
Short name T1031
Test name
Test status
Simulation time 37787600 ps
CPU time 174.74 seconds
Started Sep 18 06:09:51 PM UTC 24
Finished Sep 18 06:12:49 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238538644 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.2238538644
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.2967612518
Short name T978
Test name
Test status
Simulation time 28896700 ps
CPU time 36.36 seconds
Started Sep 18 06:09:57 PM UTC 24
Finished Sep 18 06:10:35 PM UTC 24
Peak memory 287608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967612518 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.2967612518
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.2438736229
Short name T981
Test name
Test status
Simulation time 43285700 ps
CPU time 45.74 seconds
Started Sep 18 06:10:01 PM UTC 24
Finished Sep 18 06:10:48 PM UTC 24
Peak memory 279420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2438736229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c
trl_rw_evict_all_en.2438736229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.2005588176
Short name T402
Test name
Test status
Simulation time 5442667600 ps
CPU time 110.87 seconds
Started Sep 18 06:10:03 PM UTC 24
Finished Sep 18 06:11:57 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005588176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2005588176
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.590407376
Short name T1093
Test name
Test status
Simulation time 692241600 ps
CPU time 303.12 seconds
Started Sep 18 06:09:46 PM UTC 24
Finished Sep 18 06:14:53 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590407376 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.590407376
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.1496438280
Short name T505
Test name
Test status
Simulation time 279220900 ps
CPU time 19.83 seconds
Started Sep 18 05:16:00 PM UTC 24
Finished Sep 18 05:16:21 PM UTC 24
Peak memory 269068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496438280 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.1496438280
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.3090266605
Short name T502
Test name
Test status
Simulation time 29801400 ps
CPU time 24.36 seconds
Started Sep 18 05:15:42 PM UTC 24
Finished Sep 18 05:16:07 PM UTC 24
Peak memory 275164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090266605 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.3090266605
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.793251439
Short name T320
Test name
Test status
Simulation time 14900400 ps
CPU time 26.71 seconds
Started Sep 18 05:15:13 PM UTC 24
Finished Sep 18 05:15:41 PM UTC 24
Peak memory 284724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793251439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.793251439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.247205218
Short name T507
Test name
Test status
Simulation time 2309515000 ps
CPU time 224.3 seconds
Started Sep 18 05:13:02 PM UTC 24
Finished Sep 18 05:16:49 PM UTC 24
Peak memory 291824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=247205218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 4.flash_ctrl_derr_detect.247205218
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.339749585
Short name T276
Test name
Test status
Simulation time 35050000 ps
CPU time 43.05 seconds
Started Sep 18 05:14:42 PM UTC 24
Finished Sep 18 05:15:27 PM UTC 24
Peak memory 285620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=339749585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_disable.339749585
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.3231188054
Short name T317
Test name
Test status
Simulation time 7568611800 ps
CPU time 539.63 seconds
Started Sep 18 05:10:19 PM UTC 24
Finished Sep 18 05:19:26 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231188054 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.3231188054
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.255399425
Short name T813
Test name
Test status
Simulation time 43622589300 ps
CPU time 3007.22 seconds
Started Sep 18 05:11:27 PM UTC 24
Finished Sep 18 06:02:04 PM UTC 24
Peak memory 273352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255399425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.255399425
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.252501990
Short name T115
Test name
Test status
Simulation time 718567800 ps
CPU time 3035.89 seconds
Started Sep 18 05:11:13 PM UTC 24
Finished Sep 18 06:02:22 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25
2501990 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
error_prog_type.252501990
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.1407121025
Short name T586
Test name
Test status
Simulation time 755206900 ps
CPU time 1312.71 seconds
Started Sep 18 05:11:21 PM UTC 24
Finished Sep 18 05:33:28 PM UTC 24
Peak memory 285388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407121025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.1407121025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.2412489013
Short name T58
Test name
Test status
Simulation time 611078200 ps
CPU time 34.06 seconds
Started Sep 18 05:10:57 PM UTC 24
Finished Sep 18 05:11:33 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24
12489013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc
h_code.2412489013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.2191128914
Short name T503
Test name
Test status
Simulation time 337689700 ps
CPU time 45.34 seconds
Started Sep 18 05:15:22 PM UTC 24
Finished Sep 18 05:16:09 PM UTC 24
Peak memory 273264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191128
914 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_f
s_sup.2191128914
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.718245812
Short name T1132
Test name
Test status
Simulation time 195646602700 ps
CPU time 4103.21 seconds
Started Sep 18 05:11:06 PM UTC 24
Finished Sep 18 06:20:13 PM UTC 24
Peak memory 288124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718245812 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.718245812
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.3852561358
Short name T171
Test name
Test status
Simulation time 123539200 ps
CPU time 70.82 seconds
Started Sep 18 05:10:07 PM UTC 24
Finished Sep 18 05:11:20 PM UTC 24
Peak memory 275468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3852561358 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.3852561358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.956495155
Short name T212
Test name
Test status
Simulation time 10017103200 ps
CPU time 136.73 seconds
Started Sep 18 05:15:53 PM UTC 24
Finished Sep 18 05:18:12 PM UTC 24
Peak memory 310124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=956495155 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.956495155
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.79284797
Short name T287
Test name
Test status
Simulation time 46925900 ps
CPU time 16.29 seconds
Started Sep 18 05:15:52 PM UTC 24
Finished Sep 18 05:16:09 PM UTC 24
Peak memory 271320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=79284797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.
flash_ctrl_hw_read_seed_err.79284797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.536154915
Short name T170
Test name
Test status
Simulation time 4708327100 ps
CPU time 56.92 seconds
Started Sep 18 05:10:13 PM UTC 24
Finished Sep 18 05:11:12 PM UTC 24
Peak memory 273104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536154915 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.536154915
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.2007866487
Short name T361
Test name
Test status
Simulation time 614061500 ps
CPU time 151.54 seconds
Started Sep 18 05:13:17 PM UTC 24
Finished Sep 18 05:15:52 PM UTC 24
Peak memory 306352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007866487 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.2007866487
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.3619835801
Short name T504
Test name
Test status
Simulation time 5833824900 ps
CPU time 146.31 seconds
Started Sep 18 05:13:46 PM UTC 24
Finished Sep 18 05:16:14 PM UTC 24
Peak memory 303904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3619835801 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_intr_rd_slow_flash.3619835801
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.3507519159
Short name T496
Test name
Test status
Simulation time 2539140500 ps
CPU time 75.05 seconds
Started Sep 18 05:13:24 PM UTC 24
Finished Sep 18 05:14:42 PM UTC 24
Peak memory 275516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507519159 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.3507519159
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.2652436550
Short name T519
Test name
Test status
Simulation time 49935325200 ps
CPU time 356.48 seconds
Started Sep 18 05:14:00 PM UTC 24
Finished Sep 18 05:20:01 PM UTC 24
Peak memory 271172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652436550 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.2652436550
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.1704815599
Short name T488
Test name
Test status
Simulation time 2031996100 ps
CPU time 90.53 seconds
Started Sep 18 05:11:33 PM UTC 24
Finished Sep 18 05:13:06 PM UTC 24
Peak memory 275016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704815599 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1704815599
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.509557642
Short name T294
Test name
Test status
Simulation time 25197000 ps
CPU time 19.64 seconds
Started Sep 18 05:15:51 PM UTC 24
Finished Sep 18 05:16:12 PM UTC 24
Peak memory 271104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=509557642 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_lcmgr_intg.509557642
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.4120651448
Short name T86
Test name
Test status
Simulation time 2517171100 ps
CPU time 85.12 seconds
Started Sep 18 05:11:34 PM UTC 24
Finished Sep 18 05:13:01 PM UTC 24
Peak memory 270936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120651448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.4120651448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.2862826767
Short name T88
Test name
Test status
Simulation time 7663608100 ps
CPU time 251.15 seconds
Started Sep 18 05:10:56 PM UTC 24
Finished Sep 18 05:15:11 PM UTC 24
Peak memory 283332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2862826767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_mp_regions.2862826767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.882035535
Short name T185
Test name
Test status
Simulation time 44823300 ps
CPU time 147.64 seconds
Started Sep 18 05:10:31 PM UTC 24
Finished Sep 18 05:13:01 PM UTC 24
Peak memory 275372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=882035535 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.882035535
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.2866673459
Short name T500
Test name
Test status
Simulation time 1479533300 ps
CPU time 165.99 seconds
Started Sep 18 05:13:02 PM UTC 24
Finished Sep 18 05:15:51 PM UTC 24
Peak memory 291844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2866673459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_oversize_error.2866673459
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3282575782
Short name T239
Test name
Test status
Simulation time 110876700 ps
CPU time 28.42 seconds
Started Sep 18 05:15:40 PM UTC 24
Finished Sep 18 05:16:10 PM UTC 24
Peak memory 275552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282575782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3282575782
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.1607606329
Short name T256
Test name
Test status
Simulation time 679497600 ps
CPU time 160.61 seconds
Started Sep 18 05:10:11 PM UTC 24
Finished Sep 18 05:12:54 PM UTC 24
Peak memory 275212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607606329 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.1607606329
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.657272460
Short name T100
Test name
Test status
Simulation time 775965800 ps
CPU time 21.7 seconds
Started Sep 18 05:15:27 PM UTC 24
Finished Sep 18 05:15:50 PM UTC 24
Peak memory 275524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=657272460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.657272460
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.2156519228
Short name T312
Test name
Test status
Simulation time 22149600 ps
CPU time 23.51 seconds
Started Sep 18 05:14:10 PM UTC 24
Finished Sep 18 05:14:34 PM UTC 24
Peak memory 271408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2156519228 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.2156519228
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.3265403931
Short name T549
Test name
Test status
Simulation time 1249897400 ps
CPU time 955.26 seconds
Started Sep 18 05:10:04 PM UTC 24
Finished Sep 18 05:26:10 PM UTC 24
Peak memory 291720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265403931 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.3265403931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.530303679
Short name T466
Test name
Test status
Simulation time 279199200 ps
CPU time 127.43 seconds
Started Sep 18 05:10:10 PM UTC 24
Finished Sep 18 05:12:20 PM UTC 24
Peak memory 273156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530303679 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.530303679
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.208065457
Short name T497
Test name
Test status
Simulation time 118779700 ps
CPU time 44.64 seconds
Started Sep 18 05:14:35 PM UTC 24
Finished Sep 18 05:15:21 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=208065457 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.208065457
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.4269545751
Short name T489
Test name
Test status
Simulation time 34525700 ps
CPU time 27.35 seconds
Started Sep 18 05:12:55 PM UTC 24
Finished Sep 18 05:13:23 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4269545751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_read_word_sweep_derr.4269545751
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3893744125
Short name T487
Test name
Test status
Simulation time 68355300 ps
CPU time 38.51 seconds
Started Sep 18 05:12:21 PM UTC 24
Finished Sep 18 05:13:00 PM UTC 24
Peak memory 275328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893744125 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.3893744125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.1308158048
Short name T490
Test name
Test status
Simulation time 2258394200 ps
CPU time 108.87 seconds
Started Sep 18 05:11:53 PM UTC 24
Finished Sep 18 05:13:44 PM UTC 24
Peak memory 291840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1308158048 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.1308158048
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.1016194253
Short name T501
Test name
Test status
Simulation time 1102276400 ps
CPU time 180.4 seconds
Started Sep 18 05:12:56 PM UTC 24
Finished Sep 18 05:15:59 PM UTC 24
Peak memory 292024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016194253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.1016194253
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.3261918377
Short name T495
Test name
Test status
Simulation time 1718099600 ps
CPU time 127.2 seconds
Started Sep 18 05:12:31 PM UTC 24
Finished Sep 18 05:14:40 PM UTC 24
Peak memory 291960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3261918377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_ro_serr.3261918377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.363414291
Short name T467
Test name
Test status
Simulation time 11901676200 ps
CPU time 487.32 seconds
Started Sep 18 05:12:10 PM UTC 24
Finished Sep 18 05:20:24 PM UTC 24
Peak memory 330976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363414291 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.363414291
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2899455439
Short name T506
Test name
Test status
Simulation time 1301139300 ps
CPU time 219.11 seconds
Started Sep 18 05:13:02 PM UTC 24
Finished Sep 18 05:16:44 PM UTC 24
Peak memory 292020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2899455439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_rw_derr.2899455439
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.3713046587
Short name T458
Test name
Test status
Simulation time 30813800 ps
CPU time 45.92 seconds
Started Sep 18 05:14:14 PM UTC 24
Finished Sep 18 05:15:01 PM UTC 24
Peak memory 285632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3713046587 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.3713046587
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.2266830838
Short name T50
Test name
Test status
Simulation time 124462600 ps
CPU time 37.89 seconds
Started Sep 18 05:14:33 PM UTC 24
Finished Sep 18 05:15:12 PM UTC 24
Peak memory 285628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2266830838 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw_evict_all_en.2266830838
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.569510126
Short name T329
Test name
Test status
Simulation time 1631466800 ps
CPU time 269.82 seconds
Started Sep 18 05:12:32 PM UTC 24
Finished Sep 18 05:17:06 PM UTC 24
Peak memory 291852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=569510126 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.569510126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.317160740
Short name T65
Test name
Test status
Simulation time 6030021700 ps
CPU time 7019.52 seconds
Started Sep 18 05:14:42 PM UTC 24
Finished Sep 18 07:12:54 PM UTC 24
Peak memory 314196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317160740 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.317160740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.2111899031
Short name T180
Test name
Test status
Simulation time 6850768200 ps
CPU time 93.26 seconds
Started Sep 18 05:15:02 PM UTC 24
Finished Sep 18 05:16:38 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111899031 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.2111899031
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.2063951558
Short name T493
Test name
Test status
Simulation time 1431426400 ps
CPU time 96.01 seconds
Started Sep 18 05:12:34 PM UTC 24
Finished Sep 18 05:14:13 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206
3951558 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser
r_address.2063951558
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.4265112097
Short name T491
Test name
Test status
Simulation time 693973700 ps
CPU time 83.5 seconds
Started Sep 18 05:12:33 PM UTC 24
Finished Sep 18 05:13:59 PM UTC 24
Peak memory 285704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42
65112097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_se
rr_counter.4265112097
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.1597563936
Short name T486
Test name
Test status
Simulation time 61372200 ps
CPU time 170.53 seconds
Started Sep 18 05:10:01 PM UTC 24
Finished Sep 18 05:12:54 PM UTC 24
Peak memory 289668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597563936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.1597563936
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.41930606
Short name T485
Test name
Test status
Simulation time 13819500 ps
CPU time 42.64 seconds
Started Sep 18 05:10:04 PM UTC 24
Finished Sep 18 05:10:48 PM UTC 24
Peak memory 270972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41930606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.41930606
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.3721836133
Short name T510
Test name
Test status
Simulation time 67504400 ps
CPU time 189.81 seconds
Started Sep 18 05:15:13 PM UTC 24
Finished Sep 18 05:18:26 PM UTC 24
Peak memory 272864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721836133 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.3721836133
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.3893097902
Short name T168
Test name
Test status
Simulation time 70393600 ps
CPU time 49.8 seconds
Started Sep 18 05:10:05 PM UTC 24
Finished Sep 18 05:10:56 PM UTC 24
Peak memory 273164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893097902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.3893097902
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.2568962672
Short name T494
Test name
Test status
Simulation time 5906215600 ps
CPU time 166.37 seconds
Started Sep 18 05:11:43 PM UTC 24
Finished Sep 18 05:14:32 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2568962672 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.2568962672
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.1263554071
Short name T979
Test name
Test status
Simulation time 49082300 ps
CPU time 18.85 seconds
Started Sep 18 06:10:22 PM UTC 24
Finished Sep 18 06:10:43 PM UTC 24
Peak memory 269060 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1263554071 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.1263554071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.206267695
Short name T982
Test name
Test status
Simulation time 38543500 ps
CPU time 28.01 seconds
Started Sep 18 06:10:20 PM UTC 24
Finished Sep 18 06:10:50 PM UTC 24
Peak memory 284944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206267695 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.206267695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.3882388662
Short name T988
Test name
Test status
Simulation time 34919500 ps
CPU time 45.07 seconds
Started Sep 18 06:10:16 PM UTC 24
Finished Sep 18 06:11:03 PM UTC 24
Peak memory 285644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3882388662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_
ctrl_disable.3882388662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.2217131503
Short name T1010
Test name
Test status
Simulation time 3739310200 ps
CPU time 100.7 seconds
Started Sep 18 06:10:11 PM UTC 24
Finished Sep 18 06:11:54 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217131503 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.2217131503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.3554760375
Short name T1055
Test name
Test status
Simulation time 81138900 ps
CPU time 195.85 seconds
Started Sep 18 06:10:11 PM UTC 24
Finished Sep 18 06:13:30 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554760375 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.3554760375
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.3278136610
Short name T405
Test name
Test status
Simulation time 30082778400 ps
CPU time 131.86 seconds
Started Sep 18 06:10:20 PM UTC 24
Finished Sep 18 06:12:35 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278136610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.3278136610
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.3487592441
Short name T1046
Test name
Test status
Simulation time 39442900 ps
CPU time 184.79 seconds
Started Sep 18 06:10:09 PM UTC 24
Finished Sep 18 06:13:17 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487592441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.3487592441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.3131161731
Short name T986
Test name
Test status
Simulation time 67511100 ps
CPU time 24.21 seconds
Started Sep 18 06:10:30 PM UTC 24
Finished Sep 18 06:10:56 PM UTC 24
Peak memory 275196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131161731 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.3131161731
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.764460767
Short name T987
Test name
Test status
Simulation time 48777300 ps
CPU time 27.68 seconds
Started Sep 18 06:10:29 PM UTC 24
Finished Sep 18 06:10:58 PM UTC 24
Peak memory 284752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764460767 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.764460767
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.1556575497
Short name T991
Test name
Test status
Simulation time 15207900 ps
CPU time 45.49 seconds
Started Sep 18 06:10:26 PM UTC 24
Finished Sep 18 06:11:13 PM UTC 24
Peak memory 285720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1556575497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_
ctrl_disable.1556575497
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.3835564619
Short name T1068
Test name
Test status
Simulation time 32761322300 ps
CPU time 206.96 seconds
Started Sep 18 06:10:25 PM UTC 24
Finished Sep 18 06:13:55 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835564619 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.3835564619
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.1616630807
Short name T1053
Test name
Test status
Simulation time 74311200 ps
CPU time 178.04 seconds
Started Sep 18 06:10:25 PM UTC 24
Finished Sep 18 06:13:26 PM UTC 24
Peak memory 271272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616630807 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.1616630807
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.2854116441
Short name T1069
Test name
Test status
Simulation time 49999900 ps
CPU time 209.03 seconds
Started Sep 18 06:10:24 PM UTC 24
Finished Sep 18 06:13:56 PM UTC 24
Peak memory 289480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2854116441 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.2854116441
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.1447415745
Short name T993
Test name
Test status
Simulation time 62047600 ps
CPU time 24.86 seconds
Started Sep 18 06:10:49 PM UTC 24
Finished Sep 18 06:11:15 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1447415745 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.1447415745
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.2451931449
Short name T989
Test name
Test status
Simulation time 69985200 ps
CPU time 18.46 seconds
Started Sep 18 06:10:45 PM UTC 24
Finished Sep 18 06:11:05 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451931449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.2451931449
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.2150884946
Short name T916
Test name
Test status
Simulation time 11647300 ps
CPU time 29.43 seconds
Started Sep 18 06:10:38 PM UTC 24
Finished Sep 18 06:11:08 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2150884946 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_
ctrl_disable.2150884946
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.190393113
Short name T1026
Test name
Test status
Simulation time 3705655800 ps
CPU time 122.78 seconds
Started Sep 18 06:10:32 PM UTC 24
Finished Sep 18 06:12:37 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190393113 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.190393113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.1881947287
Short name T193
Test name
Test status
Simulation time 145423500 ps
CPU time 196.26 seconds
Started Sep 18 06:10:36 PM UTC 24
Finished Sep 18 06:13:55 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1881947287 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.1881947287
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.3538359924
Short name T1012
Test name
Test status
Simulation time 1688630200 ps
CPU time 74.95 seconds
Started Sep 18 06:10:44 PM UTC 24
Finished Sep 18 06:12:01 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538359924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.3538359924
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.650034079
Short name T1020
Test name
Test status
Simulation time 101282300 ps
CPU time 108.8 seconds
Started Sep 18 06:10:30 PM UTC 24
Finished Sep 18 06:12:21 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650034079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.650034079
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.1623499128
Short name T999
Test name
Test status
Simulation time 98122500 ps
CPU time 24.53 seconds
Started Sep 18 06:11:04 PM UTC 24
Finished Sep 18 06:11:30 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623499128 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.1623499128
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.1432001757
Short name T995
Test name
Test status
Simulation time 48561700 ps
CPU time 18.47 seconds
Started Sep 18 06:10:59 PM UTC 24
Finished Sep 18 06:11:18 PM UTC 24
Peak memory 294988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432001757 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.1432001757
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.3072658530
Short name T1001
Test name
Test status
Simulation time 17524600 ps
CPU time 36.62 seconds
Started Sep 18 06:10:56 PM UTC 24
Finished Sep 18 06:11:34 PM UTC 24
Peak memory 285616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3072658530 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_
ctrl_disable.3072658530
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.2884759256
Short name T1015
Test name
Test status
Simulation time 9397530500 ps
CPU time 69.88 seconds
Started Sep 18 06:10:51 PM UTC 24
Finished Sep 18 06:12:03 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884759256 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.2884759256
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.3495989875
Short name T1072
Test name
Test status
Simulation time 74525300 ps
CPU time 184.58 seconds
Started Sep 18 06:10:53 PM UTC 24
Finished Sep 18 06:14:00 PM UTC 24
Peak memory 275708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495989875 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.3495989875
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.1562251431
Short name T1025
Test name
Test status
Simulation time 2717709500 ps
CPU time 93.1 seconds
Started Sep 18 06:10:57 PM UTC 24
Finished Sep 18 06:12:32 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562251431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.1562251431
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.2514689687
Short name T1022
Test name
Test status
Simulation time 207518700 ps
CPU time 92.97 seconds
Started Sep 18 06:10:50 PM UTC 24
Finished Sep 18 06:12:25 PM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2514689687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2514689687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.173423881
Short name T1005
Test name
Test status
Simulation time 71802200 ps
CPU time 20.28 seconds
Started Sep 18 06:11:17 PM UTC 24
Finished Sep 18 06:11:38 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=173423881 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.173423881
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.3534407150
Short name T1002
Test name
Test status
Simulation time 19931300 ps
CPU time 18.71 seconds
Started Sep 18 06:11:17 PM UTC 24
Finished Sep 18 06:11:37 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534407150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.3534407150
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.1074884648
Short name T1008
Test name
Test status
Simulation time 48604000 ps
CPU time 34.02 seconds
Started Sep 18 06:11:13 PM UTC 24
Finished Sep 18 06:11:49 PM UTC 24
Peak memory 285488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1074884648 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_
ctrl_disable.1074884648
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.619461695
Short name T342
Test name
Test status
Simulation time 8831159200 ps
CPU time 181.18 seconds
Started Sep 18 06:11:09 PM UTC 24
Finished Sep 18 06:14:13 PM UTC 24
Peak memory 275340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619461695 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.619461695
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.359853189
Short name T1062
Test name
Test status
Simulation time 38624300 ps
CPU time 146.71 seconds
Started Sep 18 06:11:09 PM UTC 24
Finished Sep 18 06:13:38 PM UTC 24
Peak memory 271416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359853189 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.359853189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.3810894799
Short name T1032
Test name
Test status
Simulation time 9410030900 ps
CPU time 92.05 seconds
Started Sep 18 06:11:16 PM UTC 24
Finished Sep 18 06:12:50 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3810894799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.3810894799
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.3328756721
Short name T1033
Test name
Test status
Simulation time 30283000 ps
CPU time 103.44 seconds
Started Sep 18 06:11:05 PM UTC 24
Finished Sep 18 06:12:51 PM UTC 24
Peak memory 287620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3328756721 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3328756721
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.1458422604
Short name T1009
Test name
Test status
Simulation time 29930400 ps
CPU time 16.7 seconds
Started Sep 18 06:11:35 PM UTC 24
Finished Sep 18 06:11:53 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458422604 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.1458422604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.2570025114
Short name T1011
Test name
Test status
Simulation time 21501400 ps
CPU time 24.08 seconds
Started Sep 18 06:11:31 PM UTC 24
Finished Sep 18 06:11:57 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570025114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.2570025114
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.2789754289
Short name T1013
Test name
Test status
Simulation time 10810700 ps
CPU time 33.62 seconds
Started Sep 18 06:11:26 PM UTC 24
Finished Sep 18 06:12:01 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2789754289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_
ctrl_disable.2789754289
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.768435855
Short name T1050
Test name
Test status
Simulation time 2677824400 ps
CPU time 120.88 seconds
Started Sep 18 06:11:20 PM UTC 24
Finished Sep 18 06:13:24 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768435855 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.768435855
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.1016296178
Short name T1085
Test name
Test status
Simulation time 77722800 ps
CPU time 184.23 seconds
Started Sep 18 06:11:20 PM UTC 24
Finished Sep 18 06:14:28 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1016296178 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.1016296178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.870377058
Short name T1027
Test name
Test status
Simulation time 1682594000 ps
CPU time 71.55 seconds
Started Sep 18 06:11:30 PM UTC 24
Finished Sep 18 06:12:44 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=870377058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.870377058
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.2928196899
Short name T1090
Test name
Test status
Simulation time 29824100 ps
CPU time 203.42 seconds
Started Sep 18 06:11:19 PM UTC 24
Finished Sep 18 06:14:46 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928196899 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2928196899
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.3580552891
Short name T1018
Test name
Test status
Simulation time 134910000 ps
CPU time 27.38 seconds
Started Sep 18 06:11:50 PM UTC 24
Finished Sep 18 06:12:18 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3580552891 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.3580552891
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.4040778189
Short name T1016
Test name
Test status
Simulation time 14692400 ps
CPU time 22.82 seconds
Started Sep 18 06:11:47 PM UTC 24
Finished Sep 18 06:12:11 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040778189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.4040778189
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.2697222458
Short name T1017
Test name
Test status
Simulation time 57319600 ps
CPU time 35.96 seconds
Started Sep 18 06:11:39 PM UTC 24
Finished Sep 18 06:12:17 PM UTC 24
Peak memory 285484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2697222458 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_
ctrl_disable.2697222458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.197498740
Short name T343
Test name
Test status
Simulation time 2294228900 ps
CPU time 157.47 seconds
Started Sep 18 06:11:39 PM UTC 24
Finished Sep 18 06:14:19 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197498740 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.197498740
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1070557632
Short name T1078
Test name
Test status
Simulation time 163165500 ps
CPU time 155.05 seconds
Started Sep 18 06:11:39 PM UTC 24
Finished Sep 18 06:14:17 PM UTC 24
Peak memory 270952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070557632 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.1070557632
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.1985405230
Short name T1095
Test name
Test status
Simulation time 52586000 ps
CPU time 211.86 seconds
Started Sep 18 06:11:38 PM UTC 24
Finished Sep 18 06:15:13 PM UTC 24
Peak memory 291520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1985405230 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.1985405230
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.574918635
Short name T1019
Test name
Test status
Simulation time 34392200 ps
CPU time 15.9 seconds
Started Sep 18 06:12:02 PM UTC 24
Finished Sep 18 06:12:19 PM UTC 24
Peak memory 269040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=574918635 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.574918635
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.1817933944
Short name T1024
Test name
Test status
Simulation time 14673600 ps
CPU time 27.06 seconds
Started Sep 18 06:12:02 PM UTC 24
Finished Sep 18 06:12:31 PM UTC 24
Peak memory 294920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817933944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.1817933944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.496057776
Short name T1021
Test name
Test status
Simulation time 42986100 ps
CPU time 25.72 seconds
Started Sep 18 06:11:58 PM UTC 24
Finished Sep 18 06:12:25 PM UTC 24
Peak memory 285692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=496057776 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_c
trl_disable.496057776
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.523284832
Short name T1088
Test name
Test status
Simulation time 7915301600 ps
CPU time 164.17 seconds
Started Sep 18 06:11:55 PM UTC 24
Finished Sep 18 06:14:42 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=523284832 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.523284832
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.2364578334
Short name T1091
Test name
Test status
Simulation time 468571100 ps
CPU time 166.97 seconds
Started Sep 18 06:11:57 PM UTC 24
Finished Sep 18 06:14:47 PM UTC 24
Peak memory 271016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364578334 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.2364578334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.1158081854
Short name T1057
Test name
Test status
Simulation time 2297506100 ps
CPU time 88.9 seconds
Started Sep 18 06:12:01 PM UTC 24
Finished Sep 18 06:13:32 PM UTC 24
Peak memory 275348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158081854 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.1158081854
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.2067936229
Short name T1092
Test name
Test status
Simulation time 55861400 ps
CPU time 174.73 seconds
Started Sep 18 06:11:54 PM UTC 24
Finished Sep 18 06:14:51 PM UTC 24
Peak memory 287424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067936229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.2067936229
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.1369478164
Short name T1034
Test name
Test status
Simulation time 84641500 ps
CPU time 29.75 seconds
Started Sep 18 06:12:20 PM UTC 24
Finished Sep 18 06:12:51 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369478164 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.1369478164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.2331242944
Short name T1035
Test name
Test status
Simulation time 27089300 ps
CPU time 31.75 seconds
Started Sep 18 06:12:19 PM UTC 24
Finished Sep 18 06:12:52 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2331242944 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.2331242944
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.3162477260
Short name T1030
Test name
Test status
Simulation time 11235100 ps
CPU time 31.1 seconds
Started Sep 18 06:12:13 PM UTC 24
Finished Sep 18 06:12:46 PM UTC 24
Peak memory 285680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3162477260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_
ctrl_disable.3162477260
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.2871613511
Short name T1051
Test name
Test status
Simulation time 5514846900 ps
CPU time 78.51 seconds
Started Sep 18 06:12:04 PM UTC 24
Finished Sep 18 06:13:24 PM UTC 24
Peak memory 273292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2871613511 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.2871613511
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.3375059456
Short name T1096
Test name
Test status
Simulation time 162850700 ps
CPU time 179.26 seconds
Started Sep 18 06:12:12 PM UTC 24
Finished Sep 18 06:15:14 PM UTC 24
Peak memory 273468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375059456 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.3375059456
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.1266109059
Short name T1063
Test name
Test status
Simulation time 10772537400 ps
CPU time 80.21 seconds
Started Sep 18 06:12:17 PM UTC 24
Finished Sep 18 06:13:39 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266109059 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.1266109059
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.3471126901
Short name T1040
Test name
Test status
Simulation time 53099600 ps
CPU time 64.79 seconds
Started Sep 18 06:12:04 PM UTC 24
Finished Sep 18 06:13:10 PM UTC 24
Peak memory 285376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471126901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.3471126901
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.1900301355
Short name T1038
Test name
Test status
Simulation time 33025100 ps
CPU time 24.39 seconds
Started Sep 18 06:12:35 PM UTC 24
Finished Sep 18 06:13:01 PM UTC 24
Peak memory 269044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1900301355 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.1900301355
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.1637119085
Short name T1036
Test name
Test status
Simulation time 21323900 ps
CPU time 23.36 seconds
Started Sep 18 06:12:33 PM UTC 24
Finished Sep 18 06:12:58 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637119085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.1637119085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.720514099
Short name T1043
Test name
Test status
Simulation time 37231900 ps
CPU time 38.75 seconds
Started Sep 18 06:12:32 PM UTC 24
Finished Sep 18 06:13:12 PM UTC 24
Peak memory 285500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=720514099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_c
trl_disable.720514099
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.3879789750
Short name T334
Test name
Test status
Simulation time 2486956700 ps
CPU time 89.93 seconds
Started Sep 18 06:12:26 PM UTC 24
Finished Sep 18 06:13:57 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879789750 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.3879789750
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2517875391
Short name T1103
Test name
Test status
Simulation time 65591900 ps
CPU time 202.93 seconds
Started Sep 18 06:12:27 PM UTC 24
Finished Sep 18 06:15:53 PM UTC 24
Peak memory 273312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2517875391 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.2517875391
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.4210520870
Short name T1061
Test name
Test status
Simulation time 470970000 ps
CPU time 63.75 seconds
Started Sep 18 06:12:32 PM UTC 24
Finished Sep 18 06:13:37 PM UTC 24
Peak memory 275280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210520870 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.4210520870
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.591214706
Short name T1111
Test name
Test status
Simulation time 37291700 ps
CPU time 236.53 seconds
Started Sep 18 06:12:22 PM UTC 24
Finished Sep 18 06:16:22 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591214706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.591214706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1527773760
Short name T524
Test name
Test status
Simulation time 168982300 ps
CPU time 25.46 seconds
Started Sep 18 05:20:12 PM UTC 24
Finished Sep 18 05:20:39 PM UTC 24
Peak memory 269036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527773760 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1527773760
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.2076266689
Short name T522
Test name
Test status
Simulation time 53748800 ps
CPU time 25.98 seconds
Started Sep 18 05:19:54 PM UTC 24
Finished Sep 18 05:20:22 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076266689 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.2076266689
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.3470860247
Short name T427
Test name
Test status
Simulation time 11765900 ps
CPU time 39.76 seconds
Started Sep 18 05:19:35 PM UTC 24
Finished Sep 18 05:20:16 PM UTC 24
Peak memory 285652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3470860247 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_c
trl_disable.3470860247
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.1936271243
Short name T940
Test name
Test status
Simulation time 21102009300 ps
CPU time 3120.5 seconds
Started Sep 18 05:16:46 PM UTC 24
Finished Sep 18 06:09:19 PM UTC 24
Peak memory 275132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936271243 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.1936271243
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2685179258
Short name T641
Test name
Test status
Simulation time 1135807600 ps
CPU time 1607.67 seconds
Started Sep 18 05:16:39 PM UTC 24
Finished Sep 18 05:43:44 PM UTC 24
Peak memory 285588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2685179258 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2685179258
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2821771480
Short name T508
Test name
Test status
Simulation time 412679900 ps
CPU time 33.16 seconds
Started Sep 18 05:16:22 PM UTC 24
Finished Sep 18 05:16:57 PM UTC 24
Peak memory 275404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28
21771480 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetc
h_code.2821771480
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.145824831
Short name T546
Test name
Test status
Simulation time 10012007300 ps
CPU time 335.92 seconds
Started Sep 18 05:20:02 PM UTC 24
Finished Sep 18 05:25:42 PM UTC 24
Peak memory 338696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=145824831 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.145824831
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.1358311697
Short name T338
Test name
Test status
Simulation time 27513800 ps
CPU time 20.32 seconds
Started Sep 18 05:20:00 PM UTC 24
Finished Sep 18 05:20:21 PM UTC 24
Peak memory 269292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1358311697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_hw_read_seed_err.1358311697
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.635124604
Short name T186
Test name
Test status
Simulation time 80143554500 ps
CPU time 909.85 seconds
Started Sep 18 05:16:11 PM UTC 24
Finished Sep 18 05:31:32 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635124604 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.635124604
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.1883657616
Short name T511
Test name
Test status
Simulation time 33807029700 ps
CPU time 134.58 seconds
Started Sep 18 05:16:10 PM UTC 24
Finished Sep 18 05:18:27 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883657616 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.1883657616
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.843781125
Short name T362
Test name
Test status
Simulation time 840105200 ps
CPU time 158.63 seconds
Started Sep 18 05:18:28 PM UTC 24
Finished Sep 18 05:21:10 PM UTC 24
Peak memory 306312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843781125 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.843781125
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.17780076
Short name T528
Test name
Test status
Simulation time 52747906100 ps
CPU time 187.78 seconds
Started Sep 18 05:18:40 PM UTC 24
Finished Sep 18 05:21:51 PM UTC 24
Peak memory 303948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=17780076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_n
ame 5.flash_ctrl_intr_rd_slow_flash.17780076
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.1098028250
Short name T517
Test name
Test status
Simulation time 8661915100 ps
CPU time 75.2 seconds
Started Sep 18 05:18:36 PM UTC 24
Finished Sep 18 05:19:53 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098028250 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.1098028250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1816365520
Short name T525
Test name
Test status
Simulation time 16840249200 ps
CPU time 150.42 seconds
Started Sep 18 05:18:40 PM UTC 24
Finished Sep 18 05:21:13 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816365520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.1816365520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.3957343543
Short name T509
Test name
Test status
Simulation time 3143019000 ps
CPU time 86.43 seconds
Started Sep 18 05:16:50 PM UTC 24
Finished Sep 18 05:18:18 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3957343543 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.3957343543
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.1032351738
Short name T520
Test name
Test status
Simulation time 26208500 ps
CPU time 15.72 seconds
Started Sep 18 05:19:55 PM UTC 24
Finished Sep 18 05:20:12 PM UTC 24
Peak memory 275264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1032351738 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_lcmgr_intg.1032351738
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1956808335
Short name T87
Test name
Test status
Simulation time 37078639700 ps
CPU time 289.88 seconds
Started Sep 18 05:16:15 PM UTC 24
Finished Sep 18 05:21:10 PM UTC 24
Peak memory 283324 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1956808335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_mp_regions.1956808335
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.3343800890
Short name T191
Test name
Test status
Simulation time 73368800 ps
CPU time 179.75 seconds
Started Sep 18 05:16:12 PM UTC 24
Finished Sep 18 05:19:15 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343800890 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.3343800890
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.2868691134
Short name T321
Test name
Test status
Simulation time 37857700 ps
CPU time 142.95 seconds
Started Sep 18 05:16:10 PM UTC 24
Finished Sep 18 05:18:36 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868691134 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.2868691134
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.1407102874
Short name T516
Test name
Test status
Simulation time 21212900 ps
CPU time 26.68 seconds
Started Sep 18 05:19:16 PM UTC 24
Finished Sep 18 05:19:44 PM UTC 24
Peak memory 271112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407102874 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.1407102874
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.2224868692
Short name T563
Test name
Test status
Simulation time 91181800 ps
CPU time 712.35 seconds
Started Sep 18 05:16:08 PM UTC 24
Finished Sep 18 05:28:09 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224868692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.2224868692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.417665065
Short name T521
Test name
Test status
Simulation time 193183400 ps
CPU time 48.43 seconds
Started Sep 18 05:19:27 PM UTC 24
Finished Sep 18 05:20:17 PM UTC 24
Peak memory 287612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417665065 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.417665065
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1890334292
Short name T514
Test name
Test status
Simulation time 848157500 ps
CPU time 136.72 seconds
Started Sep 18 05:17:06 PM UTC 24
Finished Sep 18 05:19:25 PM UTC 24
Peak memory 304224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1890334292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.1890334292
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.96146775
Short name T523
Test name
Test status
Simulation time 712766200 ps
CPU time 135.11 seconds
Started Sep 18 05:18:19 PM UTC 24
Finished Sep 18 05:20:36 PM UTC 24
Peak memory 292100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96146775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.96146775
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.3491937322
Short name T513
Test name
Test status
Simulation time 1971241000 ps
CPU time 108.69 seconds
Started Sep 18 05:17:28 PM UTC 24
Finished Sep 18 05:19:19 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3491937322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_ro_serr.3491937322
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.3230340340
Short name T542
Test name
Test status
Simulation time 21707657500 ps
CPU time 443.44 seconds
Started Sep 18 05:17:12 PM UTC 24
Finished Sep 18 05:24:41 PM UTC 24
Peak memory 324648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230340340 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.3230340340
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2942919956
Short name T453
Test name
Test status
Simulation time 30868200 ps
CPU time 47.47 seconds
Started Sep 18 05:19:26 PM UTC 24
Finished Sep 18 05:20:15 PM UTC 24
Peak memory 285668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2942919956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw_evict_all_en.2942919956
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.574401405
Short name T527
Test name
Test status
Simulation time 5667663000 ps
CPU time 199.35 seconds
Started Sep 18 05:18:14 PM UTC 24
Finished Sep 18 05:21:36 PM UTC 24
Peak memory 306168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=574401405 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.574401405
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.683799947
Short name T435
Test name
Test status
Simulation time 706572200 ps
CPU time 77.01 seconds
Started Sep 18 05:19:44 PM UTC 24
Finished Sep 18 05:21:03 PM UTC 24
Peak memory 275160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683799947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.683799947
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.1805394919
Short name T512
Test name
Test status
Simulation time 36907700 ps
CPU time 150.72 seconds
Started Sep 18 05:16:06 PM UTC 24
Finished Sep 18 05:18:39 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805394919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.1805394919
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.666586687
Short name T518
Test name
Test status
Simulation time 3721713400 ps
CPU time 174 seconds
Started Sep 18 05:16:58 PM UTC 24
Finished Sep 18 05:19:55 PM UTC 24
Peak memory 271432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=666586687 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.666586687
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.991911704
Short name T1041
Test name
Test status
Simulation time 14901500 ps
CPU time 23.66 seconds
Started Sep 18 06:12:45 PM UTC 24
Finished Sep 18 06:13:10 PM UTC 24
Peak memory 284236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991911704 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.991911704
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.3183986983
Short name T1099
Test name
Test status
Simulation time 279821000 ps
CPU time 170.89 seconds
Started Sep 18 06:12:37 PM UTC 24
Finished Sep 18 06:15:31 PM UTC 24
Peak memory 271356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183986983 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.3183986983
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.4003360053
Short name T1044
Test name
Test status
Simulation time 234717200 ps
CPU time 25.59 seconds
Started Sep 18 06:12:46 PM UTC 24
Finished Sep 18 06:13:13 PM UTC 24
Peak memory 294984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4003360053 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.4003360053
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.3266733503
Short name T1098
Test name
Test status
Simulation time 41128000 ps
CPU time 162.39 seconds
Started Sep 18 06:12:45 PM UTC 24
Finished Sep 18 06:15:30 PM UTC 24
Peak memory 275508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266733503 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.3266733503
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.278663394
Short name T1049
Test name
Test status
Simulation time 15642600 ps
CPU time 30.31 seconds
Started Sep 18 06:12:50 PM UTC 24
Finished Sep 18 06:13:22 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278663394 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.278663394
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3702555787
Short name T1102
Test name
Test status
Simulation time 45321300 ps
CPU time 174.52 seconds
Started Sep 18 06:12:47 PM UTC 24
Finished Sep 18 06:15:45 PM UTC 24
Peak memory 275516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3702555787 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.3702555787
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.734723552
Short name T1045
Test name
Test status
Simulation time 16476400 ps
CPU time 21.47 seconds
Started Sep 18 06:12:51 PM UTC 24
Finished Sep 18 06:13:14 PM UTC 24
Peak memory 284752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734723552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.734723552
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.549386051
Short name T1107
Test name
Test status
Simulation time 42108500 ps
CPU time 202.19 seconds
Started Sep 18 06:12:51 PM UTC 24
Finished Sep 18 06:16:17 PM UTC 24
Peak memory 271256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549386051 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.549386051
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.2563517293
Short name T1047
Test name
Test status
Simulation time 23646800 ps
CPU time 24.61 seconds
Started Sep 18 06:12:53 PM UTC 24
Finished Sep 18 06:13:19 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563517293 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.2563517293
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.632571623
Short name T1101
Test name
Test status
Simulation time 51838000 ps
CPU time 163.78 seconds
Started Sep 18 06:12:52 PM UTC 24
Finished Sep 18 06:15:39 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632571623 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.632571623
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.957890281
Short name T1048
Test name
Test status
Simulation time 28665500 ps
CPU time 20.87 seconds
Started Sep 18 06:12:58 PM UTC 24
Finished Sep 18 06:13:20 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957890281 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.957890281
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.4062556326
Short name T1100
Test name
Test status
Simulation time 260444300 ps
CPU time 157.71 seconds
Started Sep 18 06:12:55 PM UTC 24
Finished Sep 18 06:15:35 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062556326 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.4062556326
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.3597556032
Short name T1054
Test name
Test status
Simulation time 17300400 ps
CPU time 25.58 seconds
Started Sep 18 06:13:01 PM UTC 24
Finished Sep 18 06:13:28 PM UTC 24
Peak memory 294988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597556032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.3597556032
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.1613129290
Short name T1097
Test name
Test status
Simulation time 41003600 ps
CPU time 134.64 seconds
Started Sep 18 06:12:59 PM UTC 24
Finished Sep 18 06:15:16 PM UTC 24
Peak memory 271228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1613129290 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.1613129290
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.3103296380
Short name T1052
Test name
Test status
Simulation time 31265200 ps
CPU time 17.44 seconds
Started Sep 18 06:13:06 PM UTC 24
Finished Sep 18 06:13:25 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103296380 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.3103296380
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1828786911
Short name T1105
Test name
Test status
Simulation time 36699200 ps
CPU time 171.18 seconds
Started Sep 18 06:13:02 PM UTC 24
Finished Sep 18 06:15:56 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828786911 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.1828786911
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.2888509709
Short name T1060
Test name
Test status
Simulation time 54244800 ps
CPU time 23.89 seconds
Started Sep 18 06:13:11 PM UTC 24
Finished Sep 18 06:13:37 PM UTC 24
Peak memory 294984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888509709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.2888509709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2797255246
Short name T1114
Test name
Test status
Simulation time 143968300 ps
CPU time 194.1 seconds
Started Sep 18 06:13:11 PM UTC 24
Finished Sep 18 06:16:29 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797255246 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.2797255246
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.2392548684
Short name T1058
Test name
Test status
Simulation time 31418500 ps
CPU time 19.97 seconds
Started Sep 18 06:13:13 PM UTC 24
Finished Sep 18 06:13:34 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2392548684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2392548684
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3541793119
Short name T1121
Test name
Test status
Simulation time 71562300 ps
CPU time 212.56 seconds
Started Sep 18 06:13:12 PM UTC 24
Finished Sep 18 06:16:47 PM UTC 24
Peak memory 271400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3541793119 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.3541793119
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.1512173143
Short name T540
Test name
Test status
Simulation time 81872000 ps
CPU time 24.29 seconds
Started Sep 18 05:23:36 PM UTC 24
Finished Sep 18 05:24:02 PM UTC 24
Peak memory 275120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512173143 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1512173143
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.3416716091
Short name T400
Test name
Test status
Simulation time 49437200 ps
CPU time 23.33 seconds
Started Sep 18 05:23:13 PM UTC 24
Finished Sep 18 05:23:37 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3416716091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.3416716091
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.2519507262
Short name T197
Test name
Test status
Simulation time 10520300 ps
CPU time 23.83 seconds
Started Sep 18 05:23:06 PM UTC 24
Finished Sep 18 05:23:31 PM UTC 24
Peak memory 285712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2519507262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c
trl_disable.2519507262
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.1287483323
Short name T1094
Test name
Test status
Simulation time 33109223300 ps
CPU time 3206.35 seconds
Started Sep 18 05:21:04 PM UTC 24
Finished Sep 18 06:15:02 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287483323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.1287483323
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.2538668662
Short name T619
Test name
Test status
Simulation time 1520330800 ps
CPU time 1125.63 seconds
Started Sep 18 05:20:39 PM UTC 24
Finished Sep 18 05:39:37 PM UTC 24
Peak memory 285396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538668662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.2538668662
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2894823362
Short name T526
Test name
Test status
Simulation time 823756100 ps
CPU time 38.27 seconds
Started Sep 18 05:20:37 PM UTC 24
Finished Sep 18 05:21:17 PM UTC 24
Peak memory 275216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28
94823362 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetc
h_code.2894823362
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.3479993962
Short name T112
Test name
Test status
Simulation time 10082765300 ps
CPU time 83.83 seconds
Started Sep 18 05:23:36 PM UTC 24
Finished Sep 18 05:25:02 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3479993962 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.3479993962
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.3851089250
Short name T200
Test name
Test status
Simulation time 80133116900 ps
CPU time 785.91 seconds
Started Sep 18 05:20:22 PM UTC 24
Finished Sep 18 05:33:37 PM UTC 24
Peak memory 275036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851089250
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.3851089250
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.68997931
Short name T531
Test name
Test status
Simulation time 17806370700 ps
CPU time 121.11 seconds
Started Sep 18 05:20:18 PM UTC 24
Finished Sep 18 05:22:21 PM UTC 24
Peak memory 273104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=68997931 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.68997931
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.1794033113
Short name T547
Test name
Test status
Simulation time 1838821600 ps
CPU time 239.11 seconds
Started Sep 18 05:21:52 PM UTC 24
Finished Sep 18 05:25:54 PM UTC 24
Peak memory 302128 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794033113 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.1794033113
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.947281793
Short name T544
Test name
Test status
Simulation time 26065281000 ps
CPU time 155.46 seconds
Started Sep 18 05:22:18 PM UTC 24
Finished Sep 18 05:24:56 PM UTC 24
Peak memory 303916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=947281793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 6.flash_ctrl_intr_rd_slow_flash.947281793
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.349397433
Short name T535
Test name
Test status
Simulation time 5244939000 ps
CPU time 85.46 seconds
Started Sep 18 05:22:05 PM UTC 24
Finished Sep 18 05:23:32 PM UTC 24
Peak memory 271156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=349397433 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.349397433
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.1981635296
Short name T551
Test name
Test status
Simulation time 36759391800 ps
CPU time 255.44 seconds
Started Sep 18 05:22:22 PM UTC 24
Finished Sep 18 05:26:41 PM UTC 24
Peak memory 271344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981635296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.1981635296
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.687177499
Short name T529
Test name
Test status
Simulation time 5908708600 ps
CPU time 51.47 seconds
Started Sep 18 05:21:11 PM UTC 24
Finished Sep 18 05:22:04 PM UTC 24
Peak memory 272972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687177499 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.687177499
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.3326659876
Short name T539
Test name
Test status
Simulation time 15958700 ps
CPU time 17.49 seconds
Started Sep 18 05:23:32 PM UTC 24
Finished Sep 18 05:23:51 PM UTC 24
Peak memory 275196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3326659876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_lcmgr_intg.3326659876
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.195090649
Short name T149
Test name
Test status
Simulation time 58949891700 ps
CPU time 1040.09 seconds
Started Sep 18 05:20:24 PM UTC 24
Finished Sep 18 05:37:56 PM UTC 24
Peak memory 283328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=195090649 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 6.flash_ctrl_mp_regions.195090649
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.104467991
Short name T534
Test name
Test status
Simulation time 338468600 ps
CPU time 160.36 seconds
Started Sep 18 05:20:22 PM UTC 24
Finished Sep 18 05:23:05 PM UTC 24
Peak memory 275372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104467991 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.104467991
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3714723645
Short name T532
Test name
Test status
Simulation time 703330500 ps
CPU time 144.08 seconds
Started Sep 18 05:20:17 PM UTC 24
Finished Sep 18 05:22:44 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3714723645 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3714723645
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.1679190520
Short name T552
Test name
Test status
Simulation time 35108625400 ps
CPU time 245.35 seconds
Started Sep 18 05:22:42 PM UTC 24
Finished Sep 18 05:26:51 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1679190520 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.1679190520
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.2646405772
Short name T541
Test name
Test status
Simulation time 64713100 ps
CPU time 223.71 seconds
Started Sep 18 05:20:16 PM UTC 24
Finished Sep 18 05:24:04 PM UTC 24
Peak memory 291528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646405772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.2646405772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.2906644036
Short name T228
Test name
Test status
Simulation time 121875500 ps
CPU time 53.59 seconds
Started Sep 18 05:23:04 PM UTC 24
Finished Sep 18 05:23:59 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906644036 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.2906644036
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3524674708
Short name T322
Test name
Test status
Simulation time 514024600 ps
CPU time 108.39 seconds
Started Sep 18 05:21:14 PM UTC 24
Finished Sep 18 05:23:05 PM UTC 24
Peak memory 302004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3524674708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.3524674708
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.3518917519
Short name T538
Test name
Test status
Simulation time 1457682400 ps
CPU time 120.49 seconds
Started Sep 18 05:21:37 PM UTC 24
Finished Sep 18 05:23:40 PM UTC 24
Peak memory 291832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518917519 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.3518917519
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1821968849
Short name T537
Test name
Test status
Simulation time 2448470800 ps
CPU time 123.98 seconds
Started Sep 18 05:21:29 PM UTC 24
Finished Sep 18 05:23:35 PM UTC 24
Peak memory 291844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1821968849 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_ro_serr.1821968849
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.680077797
Short name T567
Test name
Test status
Simulation time 18551996300 ps
CPU time 460.79 seconds
Started Sep 18 05:21:17 PM UTC 24
Finished Sep 18 05:29:04 PM UTC 24
Peak memory 324604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680077797 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.680077797
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3441918302
Short name T332
Test name
Test status
Simulation time 57381100 ps
CPU time 50.82 seconds
Started Sep 18 05:22:44 PM UTC 24
Finished Sep 18 05:23:37 PM UTC 24
Peak memory 285660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441918302 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.3441918302
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1956025786
Short name T545
Test name
Test status
Simulation time 2686333100 ps
CPU time 241.29 seconds
Started Sep 18 05:21:31 PM UTC 24
Finished Sep 18 05:25:36 PM UTC 24
Peak memory 306160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1956025786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.1956025786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.2402859894
Short name T406
Test name
Test status
Simulation time 7626867200 ps
CPU time 111.52 seconds
Started Sep 18 05:23:06 PM UTC 24
Finished Sep 18 05:24:59 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402859894 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.2402859894
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.4229786941
Short name T530
Test name
Test status
Simulation time 27037500 ps
CPU time 121.28 seconds
Started Sep 18 05:20:13 PM UTC 24
Finished Sep 18 05:22:17 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229786941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.4229786941
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.2945973590
Short name T543
Test name
Test status
Simulation time 38509357300 ps
CPU time 212.78 seconds
Started Sep 18 05:21:11 PM UTC 24
Finished Sep 18 05:24:47 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2945973590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.2945973590
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.863687240
Short name T1059
Test name
Test status
Simulation time 45446700 ps
CPU time 18.27 seconds
Started Sep 18 06:13:15 PM UTC 24
Finished Sep 18 06:13:34 PM UTC 24
Peak memory 294992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863687240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.863687240
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1880577008
Short name T1106
Test name
Test status
Simulation time 158565100 ps
CPU time 170.21 seconds
Started Sep 18 06:13:15 PM UTC 24
Finished Sep 18 06:16:08 PM UTC 24
Peak memory 275560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880577008 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.1880577008
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.3469429178
Short name T1064
Test name
Test status
Simulation time 24906200 ps
CPU time 20.99 seconds
Started Sep 18 06:13:20 PM UTC 24
Finished Sep 18 06:13:42 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3469429178 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.3469429178
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.3140494699
Short name T1066
Test name
Test status
Simulation time 45449400 ps
CPU time 23.63 seconds
Started Sep 18 06:13:22 PM UTC 24
Finished Sep 18 06:13:47 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140494699 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.3140494699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.678626453
Short name T1113
Test name
Test status
Simulation time 586578700 ps
CPU time 184.3 seconds
Started Sep 18 06:13:20 PM UTC 24
Finished Sep 18 06:16:27 PM UTC 24
Peak memory 271460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678626453 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.678626453
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.1156898786
Short name T1070
Test name
Test status
Simulation time 17134000 ps
CPU time 31.52 seconds
Started Sep 18 06:13:25 PM UTC 24
Finished Sep 18 06:13:57 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156898786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1156898786
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1721182384
Short name T1109
Test name
Test status
Simulation time 38916200 ps
CPU time 170.68 seconds
Started Sep 18 06:13:24 PM UTC 24
Finished Sep 18 06:16:18 PM UTC 24
Peak memory 271208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721182384 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.1721182384
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.2408523600
Short name T1065
Test name
Test status
Simulation time 71369200 ps
CPU time 17.77 seconds
Started Sep 18 06:13:27 PM UTC 24
Finished Sep 18 06:13:46 PM UTC 24
Peak memory 284940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408523600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.2408523600
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1833476063
Short name T1115
Test name
Test status
Simulation time 703187600 ps
CPU time 181.08 seconds
Started Sep 18 06:13:26 PM UTC 24
Finished Sep 18 06:16:30 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833476063 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.1833476063
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.968085468
Short name T1073
Test name
Test status
Simulation time 13455100 ps
CPU time 32.12 seconds
Started Sep 18 06:13:29 PM UTC 24
Finished Sep 18 06:14:03 PM UTC 24
Peak memory 294988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968085468 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.968085468
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3019498885
Short name T1108
Test name
Test status
Simulation time 39574000 ps
CPU time 166.96 seconds
Started Sep 18 06:13:28 PM UTC 24
Finished Sep 18 06:16:18 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019498885 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.3019498885
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.4236947403
Short name T1071
Test name
Test status
Simulation time 16887000 ps
CPU time 25.27 seconds
Started Sep 18 06:13:32 PM UTC 24
Finished Sep 18 06:13:59 PM UTC 24
Peak memory 294920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236947403 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.4236947403
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1851295126
Short name T1118
Test name
Test status
Simulation time 40725800 ps
CPU time 185.91 seconds
Started Sep 18 06:13:31 PM UTC 24
Finished Sep 18 06:16:40 PM UTC 24
Peak memory 270952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1851295126 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.1851295126
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.1309166021
Short name T1067
Test name
Test status
Simulation time 15316600 ps
CPU time 19.29 seconds
Started Sep 18 06:13:34 PM UTC 24
Finished Sep 18 06:13:55 PM UTC 24
Peak memory 294920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309166021 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.1309166021
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.719302033
Short name T1117
Test name
Test status
Simulation time 149658300 ps
CPU time 177.17 seconds
Started Sep 18 06:13:33 PM UTC 24
Finished Sep 18 06:16:33 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719302033 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.719302033
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.3010865071
Short name T1074
Test name
Test status
Simulation time 24297700 ps
CPU time 24.74 seconds
Started Sep 18 06:13:38 PM UTC 24
Finished Sep 18 06:14:04 PM UTC 24
Peak memory 294988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010865071 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3010865071
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.3630774221
Short name T1112
Test name
Test status
Simulation time 42952300 ps
CPU time 167.58 seconds
Started Sep 18 06:13:35 PM UTC 24
Finished Sep 18 06:16:26 PM UTC 24
Peak memory 271612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3630774221 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.3630774221
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.2552473514
Short name T1075
Test name
Test status
Simulation time 35267500 ps
CPU time 24.27 seconds
Started Sep 18 06:13:39 PM UTC 24
Finished Sep 18 06:14:04 PM UTC 24
Peak memory 284936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552473514 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2552473514
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.2524132762
Short name T1120
Test name
Test status
Simulation time 275954800 ps
CPU time 181.93 seconds
Started Sep 18 06:13:39 PM UTC 24
Finished Sep 18 06:16:44 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524132762 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.2524132762
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.895911458
Short name T562
Test name
Test status
Simulation time 40251700 ps
CPU time 24.31 seconds
Started Sep 18 05:27:33 PM UTC 24
Finished Sep 18 05:27:58 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895911458 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.895911458
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.2993598316
Short name T561
Test name
Test status
Simulation time 14861400 ps
CPU time 32.6 seconds
Started Sep 18 05:27:16 PM UTC 24
Finished Sep 18 05:27:50 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993598316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.2993598316
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.2082408633
Short name T198
Test name
Test status
Simulation time 37728900 ps
CPU time 35.45 seconds
Started Sep 18 05:27:01 PM UTC 24
Finished Sep 18 05:27:38 PM UTC 24
Peak memory 285524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2082408633 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c
trl_disable.2082408633
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.887638719
Short name T1133
Test name
Test status
Simulation time 5202038400 ps
CPU time 3301.52 seconds
Started Sep 18 05:24:45 PM UTC 24
Finished Sep 18 06:20:21 PM UTC 24
Peak memory 275876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887638719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.887638719
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.1385033578
Short name T675
Test name
Test status
Simulation time 771013000 ps
CPU time 1357.89 seconds
Started Sep 18 05:24:42 PM UTC 24
Finished Sep 18 05:47:35 PM UTC 24
Peak memory 285588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385033578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.1385033578
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.1186799548
Short name T69
Test name
Test status
Simulation time 707089400 ps
CPU time 37.82 seconds
Started Sep 18 05:24:05 PM UTC 24
Finished Sep 18 05:24:44 PM UTC 24
Peak memory 273360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11
86799548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc
h_code.1186799548
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.737370383
Short name T292
Test name
Test status
Simulation time 10081105100 ps
CPU time 69.68 seconds
Started Sep 18 05:27:29 PM UTC 24
Finished Sep 18 05:28:40 PM UTC 24
Peak memory 275412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=737370383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.737370383
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.2790511393
Short name T560
Test name
Test status
Simulation time 211629300 ps
CPU time 23.14 seconds
Started Sep 18 05:27:22 PM UTC 24
Finished Sep 18 05:27:46 PM UTC 24
Peak memory 269032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2790511393 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_hw_read_seed_err.2790511393
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.588419541
Short name T624
Test name
Test status
Simulation time 420331160200 ps
CPU time 997.19 seconds
Started Sep 18 05:24:00 PM UTC 24
Finished Sep 18 05:40:49 PM UTC 24
Peak memory 275180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588419541 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.588419541
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.2142596170
Short name T548
Test name
Test status
Simulation time 2546013700 ps
CPU time 127.84 seconds
Started Sep 18 05:23:52 PM UTC 24
Finished Sep 18 05:26:02 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142596170 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.2142596170
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.3676110359
Short name T569
Test name
Test status
Simulation time 10019788500 ps
CPU time 238.8 seconds
Started Sep 18 05:26:02 PM UTC 24
Finished Sep 18 05:30:05 PM UTC 24
Peak memory 302220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3676110359 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.3676110359
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.3470570589
Short name T572
Test name
Test status
Simulation time 13343290300 ps
CPU time 274.54 seconds
Started Sep 18 05:26:16 PM UTC 24
Finished Sep 18 05:30:54 PM UTC 24
Peak memory 303940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3470570589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_intr_rd_slow_flash.3470570589
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.4170638837
Short name T557
Test name
Test status
Simulation time 4206538200 ps
CPU time 79.67 seconds
Started Sep 18 05:26:10 PM UTC 24
Finished Sep 18 05:27:32 PM UTC 24
Peak memory 273416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170638837 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.4170638837
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.2990055363
Short name T571
Test name
Test status
Simulation time 81057066600 ps
CPU time 260.26 seconds
Started Sep 18 05:26:23 PM UTC 24
Finished Sep 18 05:30:47 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2990055363 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.2990055363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.2346183303
Short name T536
Test name
Test status
Simulation time 2095185300 ps
CPU time 91.42 seconds
Started Sep 18 05:24:48 PM UTC 24
Finished Sep 18 05:26:22 PM UTC 24
Peak memory 275268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2346183303 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.2346183303
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.2315170081
Short name T331
Test name
Test status
Simulation time 15184900 ps
CPU time 18.53 seconds
Started Sep 18 05:27:20 PM UTC 24
Finished Sep 18 05:27:39 PM UTC 24
Peak memory 275548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2315170081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_lcmgr_intg.2315170081
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.4017370266
Short name T164
Test name
Test status
Simulation time 38841996100 ps
CPU time 256.63 seconds
Started Sep 18 05:24:03 PM UTC 24
Finished Sep 18 05:28:23 PM UTC 24
Peak memory 283372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4017370266 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_mp_regions.4017370266
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.1529042277
Short name T94
Test name
Test status
Simulation time 53701500 ps
CPU time 177.27 seconds
Started Sep 18 05:24:02 PM UTC 24
Finished Sep 18 05:27:02 PM UTC 24
Peak memory 271264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529042277 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.1529042277
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1185012674
Short name T594
Test name
Test status
Simulation time 2377885100 ps
CPU time 697.59 seconds
Started Sep 18 05:23:40 PM UTC 24
Finished Sep 18 05:35:26 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1185012674 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1185012674
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.3685655025
Short name T550
Test name
Test status
Simulation time 30729700 ps
CPU time 21.61 seconds
Started Sep 18 05:26:24 PM UTC 24
Finished Sep 18 05:26:47 PM UTC 24
Peak memory 271412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3685655025 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.3685655025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.4244825132
Short name T644
Test name
Test status
Simulation time 160872800 ps
CPU time 1209.18 seconds
Started Sep 18 05:23:38 PM UTC 24
Finished Sep 18 05:44:01 PM UTC 24
Peak memory 293768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244825132 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.4244825132
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.2594632007
Short name T444
Test name
Test status
Simulation time 218811800 ps
CPU time 39.59 seconds
Started Sep 18 05:26:52 PM UTC 24
Finished Sep 18 05:27:33 PM UTC 24
Peak memory 287668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594632007 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.2594632007
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.1913822715
Short name T554
Test name
Test status
Simulation time 540022200 ps
CPU time 136.86 seconds
Started Sep 18 05:24:57 PM UTC 24
Finished Sep 18 05:27:16 PM UTC 24
Peak memory 291728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1913822715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.1913822715
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.4049229720
Short name T564
Test name
Test status
Simulation time 1085586600 ps
CPU time 157.56 seconds
Started Sep 18 05:25:43 PM UTC 24
Finished Sep 18 05:28:23 PM UTC 24
Peak memory 291848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049229720 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.4049229720
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.2574063365
Short name T556
Test name
Test status
Simulation time 627117100 ps
CPU time 141.09 seconds
Started Sep 18 05:25:04 PM UTC 24
Finished Sep 18 05:27:28 PM UTC 24
Peak memory 291832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2574063365 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_ro_serr.2574063365
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.564604892
Short name T577
Test name
Test status
Simulation time 29203044800 ps
CPU time 397.67 seconds
Started Sep 18 05:25:01 PM UTC 24
Finished Sep 18 05:31:43 PM UTC 24
Peak memory 330788 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=564604892 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.564604892
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.5778361
Short name T570
Test name
Test status
Simulation time 2424305900 ps
CPU time 263.72 seconds
Started Sep 18 05:25:55 PM UTC 24
Finished Sep 18 05:30:23 PM UTC 24
Peak memory 296140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=5778361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/nul
l -cm_name 7.flash_ctrl_rw_derr.5778361
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.2582883859
Short name T448
Test name
Test status
Simulation time 27998500 ps
CPU time 35.3 seconds
Started Sep 18 05:26:42 PM UTC 24
Finished Sep 18 05:27:19 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582883859 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.2582883859
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.3523072953
Short name T558
Test name
Test status
Simulation time 40368600 ps
CPU time 54.58 seconds
Started Sep 18 05:26:47 PM UTC 24
Finished Sep 18 05:27:43 PM UTC 24
Peak memory 285632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3523072953 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw_evict_all_en.3523072953
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.329402179
Short name T565
Test name
Test status
Simulation time 1693052700 ps
CPU time 193.45 seconds
Started Sep 18 05:25:37 PM UTC 24
Finished Sep 18 05:28:53 PM UTC 24
Peak memory 306168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=329402179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.329402179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.2313520172
Short name T559
Test name
Test status
Simulation time 39693900 ps
CPU time 242.32 seconds
Started Sep 18 05:23:37 PM UTC 24
Finished Sep 18 05:27:44 PM UTC 24
Peak memory 289484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313520172 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.2313520172
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.2215359596
Short name T553
Test name
Test status
Simulation time 1693856800 ps
CPU time 126.2 seconds
Started Sep 18 05:24:52 PM UTC 24
Finished Sep 18 05:27:01 PM UTC 24
Peak memory 271176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2215359596 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.2215359596
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.1344104321
Short name T1076
Test name
Test status
Simulation time 16686600 ps
CPU time 21.46 seconds
Started Sep 18 06:13:43 PM UTC 24
Finished Sep 18 06:14:06 PM UTC 24
Peak memory 294920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344104321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.1344104321
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2074017122
Short name T1116
Test name
Test status
Simulation time 101918700 ps
CPU time 168.97 seconds
Started Sep 18 06:13:40 PM UTC 24
Finished Sep 18 06:16:31 PM UTC 24
Peak memory 275260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2074017122 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.2074017122
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.1961037583
Short name T1077
Test name
Test status
Simulation time 16767000 ps
CPU time 18.57 seconds
Started Sep 18 06:13:48 PM UTC 24
Finished Sep 18 06:14:08 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961037583 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.1961037583
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3849587219
Short name T1127
Test name
Test status
Simulation time 202738700 ps
CPU time 217.42 seconds
Started Sep 18 06:13:46 PM UTC 24
Finished Sep 18 06:17:27 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849587219 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.3849587219
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.3197681013
Short name T1079
Test name
Test status
Simulation time 25645000 ps
CPU time 24.44 seconds
Started Sep 18 06:13:55 PM UTC 24
Finished Sep 18 06:14:21 PM UTC 24
Peak memory 294920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197681013 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.3197681013
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.800494773
Short name T1122
Test name
Test status
Simulation time 50443200 ps
CPU time 173.42 seconds
Started Sep 18 06:13:55 PM UTC 24
Finished Sep 18 06:16:52 PM UTC 24
Peak memory 271268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800494773 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.800494773
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.4139597311
Short name T1080
Test name
Test status
Simulation time 23755700 ps
CPU time 24.95 seconds
Started Sep 18 06:13:57 PM UTC 24
Finished Sep 18 06:14:23 PM UTC 24
Peak memory 284936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4139597311 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.4139597311
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.93111377
Short name T1124
Test name
Test status
Simulation time 41925500 ps
CPU time 174.78 seconds
Started Sep 18 06:13:57 PM UTC 24
Finished Sep 18 06:16:54 PM UTC 24
Peak memory 275256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93111377 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.93111377
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.1756707180
Short name T1082
Test name
Test status
Simulation time 16474700 ps
CPU time 25.54 seconds
Started Sep 18 06:13:58 PM UTC 24
Finished Sep 18 06:14:25 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756707180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1756707180
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.2247513483
Short name T1129
Test name
Test status
Simulation time 170213700 ps
CPU time 227.77 seconds
Started Sep 18 06:13:58 PM UTC 24
Finished Sep 18 06:17:49 PM UTC 24
Peak memory 270948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247513483 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.2247513483
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.2166831276
Short name T1084
Test name
Test status
Simulation time 23755800 ps
CPU time 24.89 seconds
Started Sep 18 06:14:01 PM UTC 24
Finished Sep 18 06:14:27 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2166831276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.2166831276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.599130334
Short name T1125
Test name
Test status
Simulation time 276058100 ps
CPU time 182.83 seconds
Started Sep 18 06:14:00 PM UTC 24
Finished Sep 18 06:17:06 PM UTC 24
Peak memory 271348 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599130334 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.599130334
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.1575095549
Short name T1081
Test name
Test status
Simulation time 24248000 ps
CPU time 18.77 seconds
Started Sep 18 06:14:04 PM UTC 24
Finished Sep 18 06:14:24 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575095549 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1575095549
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3692992532
Short name T1126
Test name
Test status
Simulation time 41258700 ps
CPU time 182.84 seconds
Started Sep 18 06:14:03 PM UTC 24
Finished Sep 18 06:17:09 PM UTC 24
Peak memory 271420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3692992532 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.3692992532
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.2506860098
Short name T1086
Test name
Test status
Simulation time 23464100 ps
CPU time 26.25 seconds
Started Sep 18 06:14:07 PM UTC 24
Finished Sep 18 06:14:34 PM UTC 24
Peak memory 284744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2506860098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.2506860098
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.4280871157
Short name T1123
Test name
Test status
Simulation time 40798600 ps
CPU time 164.66 seconds
Started Sep 18 06:14:06 PM UTC 24
Finished Sep 18 06:16:53 PM UTC 24
Peak memory 271612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280871157 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.4280871157
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.1560408655
Short name T1087
Test name
Test status
Simulation time 14518100 ps
CPU time 21.47 seconds
Started Sep 18 06:14:14 PM UTC 24
Finished Sep 18 06:14:37 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560408655 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1560408655
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.686676498
Short name T1130
Test name
Test status
Simulation time 39227100 ps
CPU time 223.53 seconds
Started Sep 18 06:14:09 PM UTC 24
Finished Sep 18 06:17:56 PM UTC 24
Peak memory 275036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686676498 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.686676498
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2711372484
Short name T1089
Test name
Test status
Simulation time 47457600 ps
CPU time 23.01 seconds
Started Sep 18 06:14:20 PM UTC 24
Finished Sep 18 06:14:45 PM UTC 24
Peak memory 284876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2711372484 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.2711372484
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.2932486776
Short name T1128
Test name
Test status
Simulation time 173693400 ps
CPU time 192.4 seconds
Started Sep 18 06:14:18 PM UTC 24
Finished Sep 18 06:17:34 PM UTC 24
Peak memory 271612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932486776 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.2932486776
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.1659284042
Short name T581
Test name
Test status
Simulation time 271870100 ps
CPU time 21.55 seconds
Started Sep 18 05:31:52 PM UTC 24
Finished Sep 18 05:32:15 PM UTC 24
Peak memory 269068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659284042 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.1659284042
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.2304954528
Short name T109
Test name
Test status
Simulation time 24683600 ps
CPU time 27.54 seconds
Started Sep 18 05:31:37 PM UTC 24
Finished Sep 18 05:32:05 PM UTC 24
Peak memory 284748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2304954528 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.2304954528
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.2500982
Short name T131
Test name
Test status
Simulation time 28383400 ps
CPU time 38.59 seconds
Started Sep 18 05:31:23 PM UTC 24
Finished Sep 18 05:32:03 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2500982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_disable.2500982
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.730050986
Short name T1131
Test name
Test status
Simulation time 10581708000 ps
CPU time 3036.84 seconds
Started Sep 18 05:28:10 PM UTC 24
Finished Sep 18 06:19:18 PM UTC 24
Peak memory 273096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=730050986 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.730050986
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.2127944167
Short name T673
Test name
Test status
Simulation time 348763400 ps
CPU time 1128.06 seconds
Started Sep 18 05:28:07 PM UTC 24
Finished Sep 18 05:47:07 PM UTC 24
Peak memory 285396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127944167 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.2127944167
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.857427478
Short name T318
Test name
Test status
Simulation time 112005200 ps
CPU time 29.33 seconds
Started Sep 18 05:27:59 PM UTC 24
Finished Sep 18 05:28:30 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=85
7427478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asse
rt -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetch
_code.857427478
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.2711765276
Short name T291
Test name
Test status
Simulation time 10018815100 ps
CPU time 112.1 seconds
Started Sep 18 05:31:44 PM UTC 24
Finished Sep 18 05:33:38 PM UTC 24
Peak memory 338796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2711765276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.2711765276
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.1688261615
Short name T369
Test name
Test status
Simulation time 15233800 ps
CPU time 15.75 seconds
Started Sep 18 05:31:44 PM UTC 24
Finished Sep 18 05:32:01 PM UTC 24
Peak memory 271172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1688261615 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_hw_read_seed_err.1688261615
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.2134732363
Short name T426
Test name
Test status
Simulation time 40126720900 ps
CPU time 803.07 seconds
Started Sep 18 05:27:44 PM UTC 24
Finished Sep 18 05:41:16 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134732363
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.2134732363
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.1470732369
Short name T566
Test name
Test status
Simulation time 2923313500 ps
CPU time 76.46 seconds
Started Sep 18 05:27:44 PM UTC 24
Finished Sep 18 05:29:03 PM UTC 24
Peak memory 272528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1470732369 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.1470732369
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.1527330518
Short name T46
Test name
Test status
Simulation time 2969894700 ps
CPU time 150.69 seconds
Started Sep 18 05:29:27 PM UTC 24
Finished Sep 18 05:32:01 PM UTC 24
Peak memory 304076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527330518 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.1527330518
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.303768828
Short name T360
Test name
Test status
Simulation time 54123781200 ps
CPU time 356.26 seconds
Started Sep 18 05:30:24 PM UTC 24
Finished Sep 18 05:36:25 PM UTC 24
Peak memory 302124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=303768828 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 8.flash_ctrl_intr_rd_slow_flash.303768828
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.3365869035
Short name T575
Test name
Test status
Simulation time 3917717700 ps
CPU time 88.35 seconds
Started Sep 18 05:30:06 PM UTC 24
Finished Sep 18 05:31:36 PM UTC 24
Peak memory 275452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365869035 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.3365869035
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.1722668639
Short name T590
Test name
Test status
Simulation time 106578813600 ps
CPU time 216.21 seconds
Started Sep 18 05:30:48 PM UTC 24
Finished Sep 18 05:34:28 PM UTC 24
Peak memory 271160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722668639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.1722668639
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.2751603244
Short name T568
Test name
Test status
Simulation time 3024985300 ps
CPU time 60.91 seconds
Started Sep 18 05:28:24 PM UTC 24
Finished Sep 18 05:29:27 PM UTC 24
Peak memory 275012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751603244 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.2751603244
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.849904192
Short name T580
Test name
Test status
Simulation time 35693600 ps
CPU time 24.01 seconds
Started Sep 18 05:31:41 PM UTC 24
Finished Sep 18 05:32:06 PM UTC 24
Peak memory 275200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=849904192 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_lcmgr_intg.849904192
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.2435703009
Short name T165
Test name
Test status
Simulation time 13398752600 ps
CPU time 410.05 seconds
Started Sep 18 05:27:51 PM UTC 24
Finished Sep 18 05:34:47 PM UTC 24
Peak memory 283332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2435703009 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_mp_regions.2435703009
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.949505434
Short name T290
Test name
Test status
Simulation time 132975500 ps
CPU time 189.77 seconds
Started Sep 18 05:27:47 PM UTC 24
Finished Sep 18 05:31:00 PM UTC 24
Peak memory 270948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949505434 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.949505434
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.4266833286
Short name T602
Test name
Test status
Simulation time 81169800 ps
CPU time 534.79 seconds
Started Sep 18 05:27:40 PM UTC 24
Finished Sep 18 05:36:41 PM UTC 24
Peak memory 275216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266833286 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.4266833286
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.3942816237
Short name T328
Test name
Test status
Simulation time 19466200 ps
CPU time 25.97 seconds
Started Sep 18 05:30:55 PM UTC 24
Finished Sep 18 05:31:22 PM UTC 24
Peak memory 271088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942816237 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.3942816237
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.1444029490
Short name T665
Test name
Test status
Simulation time 5193994000 ps
CPU time 1115.99 seconds
Started Sep 18 05:27:39 PM UTC 24
Finished Sep 18 05:46:27 PM UTC 24
Peak memory 295624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444029490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.1444029490
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.2457026772
Short name T442
Test name
Test status
Simulation time 73480300 ps
CPU time 39.02 seconds
Started Sep 18 05:31:11 PM UTC 24
Finished Sep 18 05:31:52 PM UTC 24
Peak memory 289916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457026772 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.2457026772
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.1284562358
Short name T573
Test name
Test status
Simulation time 616144400 ps
CPU time 147.55 seconds
Started Sep 18 05:28:30 PM UTC 24
Finished Sep 18 05:31:00 PM UTC 24
Peak memory 302312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1284562358 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.1284562358
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.1816653193
Short name T576
Test name
Test status
Simulation time 1362885000 ps
CPU time 154.67 seconds
Started Sep 18 05:29:03 PM UTC 24
Finished Sep 18 05:31:40 PM UTC 24
Peak memory 291824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816653193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.1816653193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.1216206164
Short name T574
Test name
Test status
Simulation time 998043200 ps
CPU time 146.69 seconds
Started Sep 18 05:28:41 PM UTC 24
Finished Sep 18 05:31:10 PM UTC 24
Peak memory 291832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1216206164 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_ro_serr.1216206164
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.4192953699
Short name T604
Test name
Test status
Simulation time 6486401300 ps
CPU time 503.3 seconds
Started Sep 18 05:28:31 PM UTC 24
Finished Sep 18 05:37:00 PM UTC 24
Peak memory 324640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4192953699 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.4192953699
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.1953676368
Short name T579
Test name
Test status
Simulation time 5102500300 ps
CPU time 166.6 seconds
Started Sep 18 05:29:05 PM UTC 24
Finished Sep 18 05:31:55 PM UTC 24
Peak memory 296028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1953676368 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 8.flash_ctrl_rw_derr.1953676368
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.1690099452
Short name T578
Test name
Test status
Simulation time 47514400 ps
CPU time 48.09 seconds
Started Sep 18 05:31:01 PM UTC 24
Finished Sep 18 05:31:51 PM UTC 24
Peak memory 287676 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1690099452 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.1690099452
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.3423485191
Short name T583
Test name
Test status
Simulation time 2190869000 ps
CPU time 204.64 seconds
Started Sep 18 05:28:54 PM UTC 24
Finished Sep 18 05:32:22 PM UTC 24
Peak memory 306164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3423485191 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.3423485191
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.3733302908
Short name T585
Test name
Test status
Simulation time 1391269000 ps
CPU time 91.67 seconds
Started Sep 18 05:31:32 PM UTC 24
Finished Sep 18 05:33:06 PM UTC 24
Peak memory 275344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733302908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.3733302908
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.662467565
Short name T587
Test name
Test status
Simulation time 2117898500 ps
CPU time 363.01 seconds
Started Sep 18 05:27:34 PM UTC 24
Finished Sep 18 05:33:42 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662467565 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.662467565
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.2819073706
Short name T582
Test name
Test status
Simulation time 9104920500 ps
CPU time 229.75 seconds
Started Sep 18 05:28:25 PM UTC 24
Finished Sep 18 05:32:19 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=2819073706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.2819073706
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.238081992
Short name T603
Test name
Test status
Simulation time 172110600 ps
CPU time 22.54 seconds
Started Sep 18 05:36:25 PM UTC 24
Finished Sep 18 05:36:49 PM UTC 24
Peak memory 269048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238081992 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.238081992
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.758453525
Short name T600
Test name
Test status
Simulation time 25181600 ps
CPU time 25.65 seconds
Started Sep 18 05:36:05 PM UTC 24
Finished Sep 18 05:36:32 PM UTC 24
Peak memory 284680 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758453525 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.758453525
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3578454502
Short name T129
Test name
Test status
Simulation time 16161600 ps
CPU time 36.91 seconds
Started Sep 18 05:35:51 PM UTC 24
Finished Sep 18 05:36:29 PM UTC 24
Peak memory 285688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3578454502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c
trl_disable.3578454502
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3647514948
Short name T1134
Test name
Test status
Simulation time 11512477100 ps
CPU time 3050.34 seconds
Started Sep 18 05:32:23 PM UTC 24
Finished Sep 18 06:23:44 PM UTC 24
Peak memory 277932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647514948 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.3647514948
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.4061313789
Short name T747
Test name
Test status
Simulation time 12629122400 ps
CPU time 1371.37 seconds
Started Sep 18 05:32:20 PM UTC 24
Finished Sep 18 05:55:26 PM UTC 24
Peak memory 285396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4061313789 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.4061313789
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.2022315601
Short name T584
Test name
Test status
Simulation time 650020500 ps
CPU time 42.25 seconds
Started Sep 18 05:32:16 PM UTC 24
Finished Sep 18 05:33:00 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20
22315601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc
h_code.2022315601
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.4092028193
Short name T606
Test name
Test status
Simulation time 10023182100 ps
CPU time 73.35 seconds
Started Sep 18 05:36:21 PM UTC 24
Finished Sep 18 05:37:36 PM UTC 24
Peak memory 314204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4092028193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.4092028193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.712623784
Short name T288
Test name
Test status
Simulation time 48749000 ps
CPU time 18.76 seconds
Started Sep 18 05:36:11 PM UTC 24
Finished Sep 18 05:36:31 PM UTC 24
Peak memory 275468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=712623784 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9
.flash_ctrl_hw_read_seed_err.712623784
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.3405686420
Short name T678
Test name
Test status
Simulation time 80152005300 ps
CPU time 960.24 seconds
Started Sep 18 05:32:04 PM UTC 24
Finished Sep 18 05:48:16 PM UTC 24
Peak memory 275228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405686420
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.3405686420
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.46477780
Short name T323
Test name
Test status
Simulation time 2059581100 ps
CPU time 72.68 seconds
Started Sep 18 05:32:01 PM UTC 24
Finished Sep 18 05:33:16 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46477780 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.46477780
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3395648202
Short name T363
Test name
Test status
Simulation time 3811754700 ps
CPU time 256.34 seconds
Started Sep 18 05:34:26 PM UTC 24
Finished Sep 18 05:38:47 PM UTC 24
Peak memory 302284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395648202 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.3395648202
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.1473158935
Short name T366
Test name
Test status
Simulation time 174084234800 ps
CPU time 391.74 seconds
Started Sep 18 05:34:48 PM UTC 24
Finished Sep 18 05:41:25 PM UTC 24
Peak memory 303932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1473158935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 9.flash_ctrl_intr_rd_slow_flash.1473158935
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.2351105803
Short name T597
Test name
Test status
Simulation time 7990079500 ps
CPU time 99.75 seconds
Started Sep 18 05:34:28 PM UTC 24
Finished Sep 18 05:36:10 PM UTC 24
Peak memory 271368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351105803 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.2351105803
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2576158025
Short name T613
Test name
Test status
Simulation time 77665933600 ps
CPU time 251.22 seconds
Started Sep 18 05:34:55 PM UTC 24
Finished Sep 18 05:39:10 PM UTC 24
Peak memory 271172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576158025 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2576158025
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.2290555666
Short name T589
Test name
Test status
Simulation time 6214753500 ps
CPU time 82.58 seconds
Started Sep 18 05:33:01 PM UTC 24
Finished Sep 18 05:34:25 PM UTC 24
Peak memory 271044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290555666 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.2290555666
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.637388448
Short name T598
Test name
Test status
Simulation time 31298400 ps
CPU time 19.08 seconds
Started Sep 18 05:36:05 PM UTC 24
Finished Sep 18 05:36:25 PM UTC 24
Peak memory 275296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=637388448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_lcmgr_intg.637388448
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.1683247958
Short name T148
Test name
Test status
Simulation time 28543003100 ps
CPU time 334.86 seconds
Started Sep 18 05:32:07 PM UTC 24
Finished Sep 18 05:37:46 PM UTC 24
Peak memory 283524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1683247958 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 9.flash_ctrl_mp_regions.1683247958
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.869087937
Short name T425
Test name
Test status
Simulation time 269624100 ps
CPU time 219.52 seconds
Started Sep 18 05:32:06 PM UTC 24
Finished Sep 18 05:35:49 PM UTC 24
Peak memory 271148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=869087937 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.869087937
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.1205211707
Short name T588
Test name
Test status
Simulation time 248891300 ps
CPU time 135.05 seconds
Started Sep 18 05:32:01 PM UTC 24
Finished Sep 18 05:34:19 PM UTC 24
Peak memory 275472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205211707 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.1205211707
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.3129095558
Short name T593
Test name
Test status
Simulation time 31167200 ps
CPU time 26.97 seconds
Started Sep 18 05:34:57 PM UTC 24
Finished Sep 18 05:35:26 PM UTC 24
Peak memory 271088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129095558 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.3129095558
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.3345447179
Short name T167
Test name
Test status
Simulation time 2172731200 ps
CPU time 1565.74 seconds
Started Sep 18 05:31:55 PM UTC 24
Finished Sep 18 05:58:18 PM UTC 24
Peak memory 295624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345447179 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3345447179
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.3627324092
Short name T330
Test name
Test status
Simulation time 249701600 ps
CPU time 51.66 seconds
Started Sep 18 05:35:28 PM UTC 24
Finished Sep 18 05:36:21 PM UTC 24
Peak memory 285656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627324092 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.3627324092
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.3979097109
Short name T592
Test name
Test status
Simulation time 1890636100 ps
CPU time 105.31 seconds
Started Sep 18 05:33:16 PM UTC 24
Finished Sep 18 05:35:04 PM UTC 24
Peak memory 304104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3979097109 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.3979097109
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.3740713692
Short name T596
Test name
Test status
Simulation time 968489200 ps
CPU time 138.8 seconds
Started Sep 18 05:33:43 PM UTC 24
Finished Sep 18 05:36:04 PM UTC 24
Peak memory 292088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740713692 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.3740713692
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.3321647193
Short name T595
Test name
Test status
Simulation time 12015449700 ps
CPU time 143.66 seconds
Started Sep 18 05:33:38 PM UTC 24
Finished Sep 18 05:36:04 PM UTC 24
Peak memory 291828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3321647193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_ro_serr.3321647193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.3077381085
Short name T607
Test name
Test status
Simulation time 1190449600 ps
CPU time 193.29 seconds
Started Sep 18 05:34:20 PM UTC 24
Finished Sep 18 05:37:37 PM UTC 24
Peak memory 293876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3077381085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 9.flash_ctrl_rw_derr.3077381085
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.1219086713
Short name T463
Test name
Test status
Simulation time 154903500 ps
CPU time 43.93 seconds
Started Sep 18 05:35:04 PM UTC 24
Finished Sep 18 05:35:50 PM UTC 24
Peak memory 287640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219086713 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.1219086713
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.3691308970
Short name T455
Test name
Test status
Simulation time 252545300 ps
CPU time 60.53 seconds
Started Sep 18 05:35:26 PM UTC 24
Finished Sep 18 05:36:29 PM UTC 24
Peak memory 287672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3691308970 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw_evict_all_en.3691308970
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.1050088214
Short name T599
Test name
Test status
Simulation time 1814849600 ps
CPU time 169.52 seconds
Started Sep 18 05:33:39 PM UTC 24
Finished Sep 18 05:36:31 PM UTC 24
Peak memory 302280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1050088214 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.1050088214
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.2552324193
Short name T591
Test name
Test status
Simulation time 98969200 ps
CPU time 180.37 seconds
Started Sep 18 05:31:53 PM UTC 24
Finished Sep 18 05:34:56 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552324193 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2552324193
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.4107770709
Short name T601
Test name
Test status
Simulation time 2275101700 ps
CPU time 208.91 seconds
Started Sep 18 05:33:07 PM UTC 24
Finished Sep 18 05:36:39 PM UTC 24
Peak memory 271164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4107770709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.4107770709
Directory /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest
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