| T1089 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.2711372484 |
|
|
Sep 18 06:14:20 PM UTC 24 |
Sep 18 06:14:45 PM UTC 24 |
47457600 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.2928196899 |
|
|
Sep 18 06:11:19 PM UTC 24 |
Sep 18 06:14:46 PM UTC 24 |
29824100 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.2364578334 |
|
|
Sep 18 06:11:57 PM UTC 24 |
Sep 18 06:14:47 PM UTC 24 |
468571100 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.2067936229 |
|
|
Sep 18 06:11:54 PM UTC 24 |
Sep 18 06:14:51 PM UTC 24 |
55861400 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.590407376 |
|
|
Sep 18 06:09:46 PM UTC 24 |
Sep 18 06:14:53 PM UTC 24 |
692241600 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.1287483323 |
|
|
Sep 18 05:21:04 PM UTC 24 |
Sep 18 06:15:02 PM UTC 24 |
33109223300 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.1985405230 |
|
|
Sep 18 06:11:38 PM UTC 24 |
Sep 18 06:15:13 PM UTC 24 |
52586000 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.3375059456 |
|
|
Sep 18 06:12:12 PM UTC 24 |
Sep 18 06:15:14 PM UTC 24 |
162850700 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.1613129290 |
|
|
Sep 18 06:12:59 PM UTC 24 |
Sep 18 06:15:16 PM UTC 24 |
41003600 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.3266733503 |
|
|
Sep 18 06:12:45 PM UTC 24 |
Sep 18 06:15:30 PM UTC 24 |
41128000 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.3183986983 |
|
|
Sep 18 06:12:37 PM UTC 24 |
Sep 18 06:15:31 PM UTC 24 |
279821000 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.4062556326 |
|
|
Sep 18 06:12:55 PM UTC 24 |
Sep 18 06:15:35 PM UTC 24 |
260444300 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.632571623 |
|
|
Sep 18 06:12:52 PM UTC 24 |
Sep 18 06:15:39 PM UTC 24 |
51838000 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3702555787 |
|
|
Sep 18 06:12:47 PM UTC 24 |
Sep 18 06:15:45 PM UTC 24 |
45321300 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.2517875391 |
|
|
Sep 18 06:12:27 PM UTC 24 |
Sep 18 06:15:53 PM UTC 24 |
65591900 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.549691659 |
|
|
Sep 18 06:09:33 PM UTC 24 |
Sep 18 06:15:54 PM UTC 24 |
109422335700 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.1828786911 |
|
|
Sep 18 06:13:02 PM UTC 24 |
Sep 18 06:15:56 PM UTC 24 |
36699200 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.1880577008 |
|
|
Sep 18 06:13:15 PM UTC 24 |
Sep 18 06:16:08 PM UTC 24 |
158565100 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.549386051 |
|
|
Sep 18 06:12:51 PM UTC 24 |
Sep 18 06:16:17 PM UTC 24 |
42108500 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3019498885 |
|
|
Sep 18 06:13:28 PM UTC 24 |
Sep 18 06:16:18 PM UTC 24 |
39574000 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1721182384 |
|
|
Sep 18 06:13:24 PM UTC 24 |
Sep 18 06:16:18 PM UTC 24 |
38916200 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.1738784316 |
|
|
Sep 18 06:13:18 PM UTC 24 |
Sep 18 06:16:20 PM UTC 24 |
136539300 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.591214706 |
|
|
Sep 18 06:12:22 PM UTC 24 |
Sep 18 06:16:22 PM UTC 24 |
37291700 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.3630774221 |
|
|
Sep 18 06:13:35 PM UTC 24 |
Sep 18 06:16:26 PM UTC 24 |
42952300 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.678626453 |
|
|
Sep 18 06:13:20 PM UTC 24 |
Sep 18 06:16:27 PM UTC 24 |
586578700 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.2797255246 |
|
|
Sep 18 06:13:11 PM UTC 24 |
Sep 18 06:16:29 PM UTC 24 |
143968300 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.1833476063 |
|
|
Sep 18 06:13:26 PM UTC 24 |
Sep 18 06:16:30 PM UTC 24 |
703187600 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.2074017122 |
|
|
Sep 18 06:13:40 PM UTC 24 |
Sep 18 06:16:31 PM UTC 24 |
101918700 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.719302033 |
|
|
Sep 18 06:13:33 PM UTC 24 |
Sep 18 06:16:33 PM UTC 24 |
149658300 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.1851295126 |
|
|
Sep 18 06:13:31 PM UTC 24 |
Sep 18 06:16:40 PM UTC 24 |
40725800 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.3942042157 |
|
|
Sep 18 05:01:36 PM UTC 24 |
Sep 18 06:16:41 PM UTC 24 |
445096375300 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.2524132762 |
|
|
Sep 18 06:13:39 PM UTC 24 |
Sep 18 06:16:44 PM UTC 24 |
275954800 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.3541793119 |
|
|
Sep 18 06:13:12 PM UTC 24 |
Sep 18 06:16:47 PM UTC 24 |
71562300 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.800494773 |
|
|
Sep 18 06:13:55 PM UTC 24 |
Sep 18 06:16:52 PM UTC 24 |
50443200 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.4280871157 |
|
|
Sep 18 06:14:06 PM UTC 24 |
Sep 18 06:16:53 PM UTC 24 |
40798600 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.93111377 |
|
|
Sep 18 06:13:57 PM UTC 24 |
Sep 18 06:16:54 PM UTC 24 |
41925500 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.599130334 |
|
|
Sep 18 06:14:00 PM UTC 24 |
Sep 18 06:17:06 PM UTC 24 |
276058100 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3692992532 |
|
|
Sep 18 06:14:03 PM UTC 24 |
Sep 18 06:17:09 PM UTC 24 |
41258700 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3849587219 |
|
|
Sep 18 06:13:46 PM UTC 24 |
Sep 18 06:17:27 PM UTC 24 |
202738700 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.2932486776 |
|
|
Sep 18 06:14:18 PM UTC 24 |
Sep 18 06:17:34 PM UTC 24 |
173693400 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.2247513483 |
|
|
Sep 18 06:13:58 PM UTC 24 |
Sep 18 06:17:49 PM UTC 24 |
170213700 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.686676498 |
|
|
Sep 18 06:14:09 PM UTC 24 |
Sep 18 06:17:56 PM UTC 24 |
39227100 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.730050986 |
|
|
Sep 18 05:28:10 PM UTC 24 |
Sep 18 06:19:18 PM UTC 24 |
10581708000 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.718245812 |
|
|
Sep 18 05:11:06 PM UTC 24 |
Sep 18 06:20:13 PM UTC 24 |
195646602700 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.887638719 |
|
|
Sep 18 05:24:45 PM UTC 24 |
Sep 18 06:20:21 PM UTC 24 |
5202038400 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3647514948 |
|
|
Sep 18 05:32:23 PM UTC 24 |
Sep 18 06:23:44 PM UTC 24 |
11512477100 ps |
| T13 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.2603499035 |
|
|
Sep 18 04:57:23 PM UTC 24 |
Sep 18 06:53:38 PM UTC 24 |
1988006100 ps |
| T14 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3163980887 |
|
|
Sep 18 05:04:13 PM UTC 24 |
Sep 18 06:53:39 PM UTC 24 |
1637110300 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.2227888279 |
|
|
Sep 18 05:00:15 PM UTC 24 |
Sep 18 06:56:32 PM UTC 24 |
978129800 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.758347702 |
|
|
Sep 18 05:09:06 PM UTC 24 |
Sep 18 07:06:05 PM UTC 24 |
17176102600 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.317160740 |
|
|
Sep 18 05:14:42 PM UTC 24 |
Sep 18 07:12:54 PM UTC 24 |
6030021700 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.1749698136 |
|
|
Sep 18 04:36:20 PM UTC 24 |
Sep 18 04:36:37 PM UTC 24 |
26222700 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.3436977323 |
|
|
Sep 18 04:36:18 PM UTC 24 |
Sep 18 04:36:39 PM UTC 24 |
12845600 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.1965556248 |
|
|
Sep 18 04:36:19 PM UTC 24 |
Sep 18 04:36:42 PM UTC 24 |
54954500 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.449959285 |
|
|
Sep 18 04:36:19 PM UTC 24 |
Sep 18 04:36:45 PM UTC 24 |
31473100 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3504514495 |
|
|
Sep 18 04:36:18 PM UTC 24 |
Sep 18 04:36:47 PM UTC 24 |
68151400 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.1473609385 |
|
|
Sep 18 04:36:18 PM UTC 24 |
Sep 18 04:36:49 PM UTC 24 |
128588000 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.2786365864 |
|
|
Sep 18 04:36:21 PM UTC 24 |
Sep 18 04:36:49 PM UTC 24 |
37436100 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.4208692987 |
|
|
Sep 18 04:36:25 PM UTC 24 |
Sep 18 04:37:00 PM UTC 24 |
90664800 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2258727223 |
|
|
Sep 18 04:36:21 PM UTC 24 |
Sep 18 04:37:00 PM UTC 24 |
1291152600 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1093405107 |
|
|
Sep 18 04:36:26 PM UTC 24 |
Sep 18 04:37:01 PM UTC 24 |
83580000 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.4003270127 |
|
|
Sep 18 04:36:21 PM UTC 24 |
Sep 18 04:37:01 PM UTC 24 |
37381800 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.16068557 |
|
|
Sep 18 04:36:43 PM UTC 24 |
Sep 18 04:37:06 PM UTC 24 |
12105600 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.105729948 |
|
|
Sep 18 04:36:40 PM UTC 24 |
Sep 18 04:37:07 PM UTC 24 |
127871500 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.3514828216 |
|
|
Sep 18 04:36:48 PM UTC 24 |
Sep 18 04:37:10 PM UTC 24 |
209715400 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.1172362840 |
|
|
Sep 18 04:36:36 PM UTC 24 |
Sep 18 04:37:13 PM UTC 24 |
260191600 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.3851371001 |
|
|
Sep 18 04:36:24 PM UTC 24 |
Sep 18 04:37:16 PM UTC 24 |
1337690600 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.740633049 |
|
|
Sep 18 04:36:48 PM UTC 24 |
Sep 18 04:37:16 PM UTC 24 |
19934100 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1891352283 |
|
|
Sep 18 04:36:49 PM UTC 24 |
Sep 18 04:37:16 PM UTC 24 |
35852700 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2767182243 |
|
|
Sep 18 04:36:50 PM UTC 24 |
Sep 18 04:37:22 PM UTC 24 |
66830400 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.369229044 |
|
|
Sep 18 04:37:03 PM UTC 24 |
Sep 18 04:37:24 PM UTC 24 |
46025800 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.2248422668 |
|
|
Sep 18 04:37:02 PM UTC 24 |
Sep 18 04:37:33 PM UTC 24 |
70955200 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.1409628823 |
|
|
Sep 18 04:37:17 PM UTC 24 |
Sep 18 04:37:37 PM UTC 24 |
29433400 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2027767095 |
|
|
Sep 18 04:37:11 PM UTC 24 |
Sep 18 04:37:40 PM UTC 24 |
81300200 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3557662709 |
|
|
Sep 18 04:37:07 PM UTC 24 |
Sep 18 04:37:41 PM UTC 24 |
722421400 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.1589102203 |
|
|
Sep 18 04:37:16 PM UTC 24 |
Sep 18 04:37:42 PM UTC 24 |
15727200 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.146896386 |
|
|
Sep 18 04:37:16 PM UTC 24 |
Sep 18 04:37:43 PM UTC 24 |
55961800 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.2679051962 |
|
|
Sep 18 04:37:14 PM UTC 24 |
Sep 18 04:37:45 PM UTC 24 |
13297400 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.2031613836 |
|
|
Sep 18 04:36:49 PM UTC 24 |
Sep 18 04:37:47 PM UTC 24 |
124904400 ps |
| T313 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.243570265 |
|
|
Sep 18 04:37:02 PM UTC 24 |
Sep 18 04:37:48 PM UTC 24 |
640171600 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.4075898804 |
|
|
Sep 18 04:37:25 PM UTC 24 |
Sep 18 04:37:52 PM UTC 24 |
39462200 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.475001113 |
|
|
Sep 18 04:37:48 PM UTC 24 |
Sep 18 04:38:05 PM UTC 24 |
80544700 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.1597757355 |
|
|
Sep 18 04:37:23 PM UTC 24 |
Sep 18 04:38:06 PM UTC 24 |
195888800 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.2942216095 |
|
|
Sep 18 04:37:51 PM UTC 24 |
Sep 18 04:38:10 PM UTC 24 |
48709600 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.2673368094 |
|
|
Sep 18 04:37:48 PM UTC 24 |
Sep 18 04:38:11 PM UTC 24 |
25435700 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.404791437 |
|
|
Sep 18 04:37:42 PM UTC 24 |
Sep 18 04:38:12 PM UTC 24 |
608226600 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.1251663451 |
|
|
Sep 18 04:37:43 PM UTC 24 |
Sep 18 04:38:14 PM UTC 24 |
77717400 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.2781453610 |
|
|
Sep 18 04:37:46 PM UTC 24 |
Sep 18 04:38:16 PM UTC 24 |
23036000 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.1241457757 |
|
|
Sep 18 04:37:42 PM UTC 24 |
Sep 18 04:38:17 PM UTC 24 |
725251300 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.4096242792 |
|
|
Sep 18 04:37:52 PM UTC 24 |
Sep 18 04:38:18 PM UTC 24 |
28544700 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.3291419109 |
|
|
Sep 18 04:37:00 PM UTC 24 |
Sep 18 04:38:21 PM UTC 24 |
1236732800 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.1831323808 |
|
|
Sep 18 04:37:35 PM UTC 24 |
Sep 18 04:38:25 PM UTC 24 |
338921000 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.811460792 |
|
|
Sep 18 04:38:07 PM UTC 24 |
Sep 18 04:38:35 PM UTC 24 |
205809500 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1853399296 |
|
|
Sep 18 04:38:18 PM UTC 24 |
Sep 18 04:38:43 PM UTC 24 |
12447200 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.1962131121 |
|
|
Sep 18 04:38:18 PM UTC 24 |
Sep 18 04:38:45 PM UTC 24 |
26334900 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.2357967130 |
|
|
Sep 18 04:38:07 PM UTC 24 |
Sep 18 04:38:45 PM UTC 24 |
19259300 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.762727809 |
|
|
Sep 18 04:38:15 PM UTC 24 |
Sep 18 04:38:47 PM UTC 24 |
187010100 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.1687398411 |
|
|
Sep 18 04:38:22 PM UTC 24 |
Sep 18 04:38:48 PM UTC 24 |
163102600 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.3918158666 |
|
|
Sep 18 04:38:14 PM UTC 24 |
Sep 18 04:38:49 PM UTC 24 |
42424600 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.989229161 |
|
|
Sep 18 04:38:26 PM UTC 24 |
Sep 18 04:38:54 PM UTC 24 |
17370500 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1858975800 |
|
|
Sep 18 04:38:13 PM UTC 24 |
Sep 18 04:38:54 PM UTC 24 |
233589500 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.3829116506 |
|
|
Sep 18 04:38:36 PM UTC 24 |
Sep 18 04:39:03 PM UTC 24 |
218808100 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.3487127749 |
|
|
Sep 18 04:38:49 PM UTC 24 |
Sep 18 04:39:11 PM UTC 24 |
128479900 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2953173677 |
|
|
Sep 18 04:37:39 PM UTC 24 |
Sep 18 04:39:11 PM UTC 24 |
1579464800 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.1279730761 |
|
|
Sep 18 04:38:11 PM UTC 24 |
Sep 18 04:39:12 PM UTC 24 |
2208729400 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.3349044358 |
|
|
Sep 18 04:38:44 PM UTC 24 |
Sep 18 04:39:15 PM UTC 24 |
68423200 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1083590502 |
|
|
Sep 18 04:38:48 PM UTC 24 |
Sep 18 04:39:21 PM UTC 24 |
238345400 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.4106474064 |
|
|
Sep 18 04:38:55 PM UTC 24 |
Sep 18 04:39:22 PM UTC 24 |
17350200 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.1366975913 |
|
|
Sep 18 04:38:46 PM UTC 24 |
Sep 18 04:39:22 PM UTC 24 |
920989700 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.3800215096 |
|
|
Sep 18 04:38:49 PM UTC 24 |
Sep 18 04:39:23 PM UTC 24 |
628791300 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.598469444 |
|
|
Sep 18 04:38:58 PM UTC 24 |
Sep 18 04:39:23 PM UTC 24 |
16190200 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1029941228 |
|
|
Sep 18 04:38:58 PM UTC 24 |
Sep 18 04:39:25 PM UTC 24 |
25408900 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.1977107819 |
|
|
Sep 18 04:38:58 PM UTC 24 |
Sep 18 04:39:26 PM UTC 24 |
38130400 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.3925504557 |
|
|
Sep 18 04:39:04 PM UTC 24 |
Sep 18 04:39:38 PM UTC 24 |
84999000 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2367727943 |
|
|
Sep 18 04:39:16 PM UTC 24 |
Sep 18 04:39:41 PM UTC 24 |
77887300 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.172499990 |
|
|
Sep 18 04:38:45 PM UTC 24 |
Sep 18 04:39:41 PM UTC 24 |
6183513200 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.1297244730 |
|
|
Sep 18 04:39:21 PM UTC 24 |
Sep 18 04:39:42 PM UTC 24 |
14013000 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.1240102307 |
|
|
Sep 18 04:38:41 PM UTC 24 |
Sep 18 04:39:45 PM UTC 24 |
56382900 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.3154681698 |
|
|
Sep 18 04:39:12 PM UTC 24 |
Sep 18 04:39:46 PM UTC 24 |
91659400 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.1748720032 |
|
|
Sep 18 04:39:11 PM UTC 24 |
Sep 18 04:39:47 PM UTC 24 |
158951100 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.615953232 |
|
|
Sep 18 04:39:23 PM UTC 24 |
Sep 18 04:39:49 PM UTC 24 |
25819700 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.437433446 |
|
|
Sep 18 04:38:12 PM UTC 24 |
Sep 18 04:39:50 PM UTC 24 |
3238189100 ps |
| T277 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.340006605 |
|
|
Sep 18 04:39:24 PM UTC 24 |
Sep 18 04:39:51 PM UTC 24 |
38792300 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1822507969 |
|
|
Sep 18 04:39:23 PM UTC 24 |
Sep 18 04:39:51 PM UTC 24 |
109333300 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.312915908 |
|
|
Sep 18 04:39:23 PM UTC 24 |
Sep 18 04:39:52 PM UTC 24 |
49847900 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.3038710309 |
|
|
Sep 18 04:39:23 PM UTC 24 |
Sep 18 04:39:53 PM UTC 24 |
112914600 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.976173230 |
|
|
Sep 18 04:39:26 PM UTC 24 |
Sep 18 04:39:55 PM UTC 24 |
24655400 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.4003019162 |
|
|
Sep 18 04:39:25 PM UTC 24 |
Sep 18 04:39:55 PM UTC 24 |
23530500 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1662676470 |
|
|
Sep 18 04:39:39 PM UTC 24 |
Sep 18 04:40:03 PM UTC 24 |
18111500 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.1014777702 |
|
|
Sep 18 04:39:47 PM UTC 24 |
Sep 18 04:40:09 PM UTC 24 |
24775100 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.1957822448 |
|
|
Sep 18 04:39:43 PM UTC 24 |
Sep 18 04:40:09 PM UTC 24 |
60884400 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.4262820148 |
|
|
Sep 18 04:39:42 PM UTC 24 |
Sep 18 04:40:11 PM UTC 24 |
59704300 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.1119299382 |
|
|
Sep 18 04:39:50 PM UTC 24 |
Sep 18 04:40:12 PM UTC 24 |
17672900 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3926400696 |
|
|
Sep 18 04:39:48 PM UTC 24 |
Sep 18 04:40:12 PM UTC 24 |
18307000 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.995968095 |
|
|
Sep 18 04:41:49 PM UTC 24 |
Sep 18 04:42:11 PM UTC 24 |
47381000 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.1808317823 |
|
|
Sep 18 04:39:42 PM UTC 24 |
Sep 18 04:40:15 PM UTC 24 |
197505900 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.3381400341 |
|
|
Sep 18 04:39:51 PM UTC 24 |
Sep 18 04:40:18 PM UTC 24 |
45408300 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.446995223 |
|
|
Sep 18 04:39:46 PM UTC 24 |
Sep 18 04:40:19 PM UTC 24 |
64948500 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.4107034724 |
|
|
Sep 18 04:39:56 PM UTC 24 |
Sep 18 04:40:20 PM UTC 24 |
37835000 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.2347554297 |
|
|
Sep 18 04:39:52 PM UTC 24 |
Sep 18 04:40:22 PM UTC 24 |
51166700 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3061885014 |
|
|
Sep 18 04:39:55 PM UTC 24 |
Sep 18 04:40:23 PM UTC 24 |
30806800 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.1275099972 |
|
|
Sep 18 04:39:52 PM UTC 24 |
Sep 18 04:40:23 PM UTC 24 |
65050300 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.779634092 |
|
|
Sep 18 04:39:53 PM UTC 24 |
Sep 18 04:40:29 PM UTC 24 |
55718300 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.3595560158 |
|
|
Sep 18 04:40:04 PM UTC 24 |
Sep 18 04:40:31 PM UTC 24 |
100654300 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.2629707655 |
|
|
Sep 18 04:40:11 PM UTC 24 |
Sep 18 04:40:35 PM UTC 24 |
114731600 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.4217316831 |
|
|
Sep 18 04:40:10 PM UTC 24 |
Sep 18 04:40:36 PM UTC 24 |
245391800 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2911605329 |
|
|
Sep 18 04:40:16 PM UTC 24 |
Sep 18 04:40:37 PM UTC 24 |
49666800 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.157797776 |
|
|
Sep 18 04:40:13 PM UTC 24 |
Sep 18 04:40:39 PM UTC 24 |
33182600 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2818990664 |
|
|
Sep 18 04:40:09 PM UTC 24 |
Sep 18 04:40:42 PM UTC 24 |
151751800 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.2805021425 |
|
|
Sep 18 04:40:19 PM UTC 24 |
Sep 18 04:40:43 PM UTC 24 |
14921200 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1594680349 |
|
|
Sep 18 04:40:22 PM UTC 24 |
Sep 18 04:40:44 PM UTC 24 |
41309700 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.17694469 |
|
|
Sep 18 04:40:12 PM UTC 24 |
Sep 18 04:40:45 PM UTC 24 |
154518500 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.2959325731 |
|
|
Sep 18 04:40:24 PM UTC 24 |
Sep 18 04:40:51 PM UTC 24 |
62659000 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.3176531054 |
|
|
Sep 18 04:40:21 PM UTC 24 |
Sep 18 04:40:51 PM UTC 24 |
115667100 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.2453423822 |
|
|
Sep 18 04:40:29 PM UTC 24 |
Sep 18 04:40:51 PM UTC 24 |
151655600 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.246360965 |
|
|
Sep 18 04:40:28 PM UTC 24 |
Sep 18 04:40:54 PM UTC 24 |
13286600 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.3547377630 |
|
|
Sep 18 04:40:21 PM UTC 24 |
Sep 18 04:40:55 PM UTC 24 |
222064600 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.256517955 |
|
|
Sep 18 04:40:21 PM UTC 24 |
Sep 18 04:40:56 PM UTC 24 |
333591000 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.2849518003 |
|
|
Sep 18 04:40:32 PM UTC 24 |
Sep 18 04:40:58 PM UTC 24 |
52404800 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.503702178 |
|
|
Sep 18 04:40:35 PM UTC 24 |
Sep 18 04:41:00 PM UTC 24 |
90777300 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.2312824418 |
|
|
Sep 18 04:40:37 PM UTC 24 |
Sep 18 04:41:02 PM UTC 24 |
294473500 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1796337724 |
|
|
Sep 18 04:40:39 PM UTC 24 |
Sep 18 04:41:05 PM UTC 24 |
227308300 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.749934394 |
|
|
Sep 18 04:40:45 PM UTC 24 |
Sep 18 04:41:08 PM UTC 24 |
58468600 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.497031524 |
|
|
Sep 18 04:40:43 PM UTC 24 |
Sep 18 04:41:09 PM UTC 24 |
12494300 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.2679827749 |
|
|
Sep 18 04:40:45 PM UTC 24 |
Sep 18 04:41:09 PM UTC 24 |
32007200 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.1559094567 |
|
|
Sep 18 04:40:52 PM UTC 24 |
Sep 18 04:41:14 PM UTC 24 |
50031900 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.1602124740 |
|
|
Sep 18 04:40:44 PM UTC 24 |
Sep 18 04:41:15 PM UTC 24 |
58387500 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.1928473432 |
|
|
Sep 18 04:40:55 PM UTC 24 |
Sep 18 04:41:16 PM UTC 24 |
24604500 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4170269568 |
|
|
Sep 18 04:40:46 PM UTC 24 |
Sep 18 04:41:17 PM UTC 24 |
38284800 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1892560610 |
|
|
Sep 18 04:40:57 PM UTC 24 |
Sep 18 04:41:20 PM UTC 24 |
25338200 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1694924575 |
|
|
Sep 18 04:40:52 PM UTC 24 |
Sep 18 04:41:23 PM UTC 24 |
197776800 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.1411369498 |
|
|
Sep 18 04:40:56 PM UTC 24 |
Sep 18 04:41:24 PM UTC 24 |
14681200 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2781522833 |
|
|
Sep 18 04:40:58 PM UTC 24 |
Sep 18 04:41:25 PM UTC 24 |
59666400 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.1686692287 |
|
|
Sep 18 04:41:01 PM UTC 24 |
Sep 18 04:41:27 PM UTC 24 |
99550900 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.1079223467 |
|
|
Sep 18 04:41:10 PM UTC 24 |
Sep 18 04:41:28 PM UTC 24 |
116857400 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.290374973 |
|
|
Sep 18 04:41:03 PM UTC 24 |
Sep 18 04:41:31 PM UTC 24 |
363655900 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.2881440459 |
|
|
Sep 18 04:41:15 PM UTC 24 |
Sep 18 04:41:35 PM UTC 24 |
145349600 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.534372136 |
|
|
Sep 18 04:41:10 PM UTC 24 |
Sep 18 04:41:38 PM UTC 24 |
14670500 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.1791782353 |
|
|
Sep 18 04:41:21 PM UTC 24 |
Sep 18 04:41:39 PM UTC 24 |
18019300 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.949888582 |
|
|
Sep 18 04:41:16 PM UTC 24 |
Sep 18 04:41:39 PM UTC 24 |
127040000 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.373518145 |
|
|
Sep 18 04:41:10 PM UTC 24 |
Sep 18 04:41:39 PM UTC 24 |
13173400 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1226633201 |
|
|
Sep 18 04:41:05 PM UTC 24 |
Sep 18 04:41:40 PM UTC 24 |
52715500 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.2524101468 |
|
|
Sep 18 04:41:24 PM UTC 24 |
Sep 18 04:41:42 PM UTC 24 |
29257900 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.1026058079 |
|
|
Sep 18 04:41:21 PM UTC 24 |
Sep 18 04:41:44 PM UTC 24 |
36276000 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.2077803214 |
|
|
Sep 18 04:41:14 PM UTC 24 |
Sep 18 04:41:46 PM UTC 24 |
48906500 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1295485171 |
|
|
Sep 18 04:41:17 PM UTC 24 |
Sep 18 04:41:48 PM UTC 24 |
50405500 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.2009520822 |
|
|
Sep 18 04:41:25 PM UTC 24 |
Sep 18 04:41:50 PM UTC 24 |
94487200 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.3872532270 |
|
|
Sep 18 04:41:27 PM UTC 24 |
Sep 18 04:41:53 PM UTC 24 |
713664200 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.4169592576 |
|
|
Sep 18 04:41:29 PM UTC 24 |
Sep 18 04:41:57 PM UTC 24 |
151731600 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.1395169905 |
|
|
Sep 18 04:41:26 PM UTC 24 |
Sep 18 04:41:58 PM UTC 24 |
267178600 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.1641088598 |
|
|
Sep 18 04:41:39 PM UTC 24 |
Sep 18 04:42:01 PM UTC 24 |
30683700 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.526030590 |
|
|
Sep 18 04:41:40 PM UTC 24 |
Sep 18 04:42:04 PM UTC 24 |
92737200 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.1842275882 |
|
|
Sep 18 04:41:35 PM UTC 24 |
Sep 18 04:42:04 PM UTC 24 |
21437400 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.2753123746 |
|
|
Sep 18 04:41:40 PM UTC 24 |
Sep 18 04:42:06 PM UTC 24 |
15388500 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1305218979 |
|
|
Sep 18 04:41:46 PM UTC 24 |
Sep 18 04:42:08 PM UTC 24 |
22249700 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.3656109484 |
|
|
Sep 18 04:41:52 PM UTC 24 |
Sep 18 04:42:10 PM UTC 24 |
573998600 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.2709091900 |
|
|
Sep 18 04:41:41 PM UTC 24 |
Sep 18 04:42:13 PM UTC 24 |
695566700 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.3471091702 |
|
|
Sep 18 04:41:45 PM UTC 24 |
Sep 18 04:42:14 PM UTC 24 |
36253400 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.1397523257 |
|
|
Sep 18 04:41:47 PM UTC 24 |
Sep 18 04:42:18 PM UTC 24 |
39496100 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2225671049 |
|
|
Sep 18 04:41:52 PM UTC 24 |
Sep 18 04:42:23 PM UTC 24 |
73545000 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.3570694159 |
|
|
Sep 18 04:42:03 PM UTC 24 |
Sep 18 04:42:23 PM UTC 24 |
32756900 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.3858295235 |
|
|
Sep 18 04:42:04 PM UTC 24 |
Sep 18 04:42:24 PM UTC 24 |
16756500 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1564322446 |
|
|
Sep 18 04:41:54 PM UTC 24 |
Sep 18 04:42:26 PM UTC 24 |
315664900 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.1326441448 |
|
|
Sep 18 04:41:40 PM UTC 24 |
Sep 18 04:42:27 PM UTC 24 |
110671600 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.403704131 |
|
|
Sep 18 04:42:03 PM UTC 24 |
Sep 18 04:42:32 PM UTC 24 |
46715000 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.1449078889 |
|
|
Sep 18 04:42:07 PM UTC 24 |
Sep 18 04:42:34 PM UTC 24 |
105166500 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4193541466 |
|
|
Sep 18 04:42:09 PM UTC 24 |
Sep 18 04:42:35 PM UTC 24 |
52614300 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.1676205364 |
|
|
Sep 18 04:42:11 PM UTC 24 |
Sep 18 04:42:36 PM UTC 24 |
62831700 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.138939817 |
|
|
Sep 18 04:42:14 PM UTC 24 |
Sep 18 04:42:37 PM UTC 24 |
20795700 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.2401743126 |
|
|
Sep 18 04:41:58 PM UTC 24 |
Sep 18 04:42:37 PM UTC 24 |
908880300 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.3853263254 |
|
|
Sep 18 04:42:08 PM UTC 24 |
Sep 18 04:42:38 PM UTC 24 |
45528300 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1089403439 |
|
|
Sep 18 04:42:18 PM UTC 24 |
Sep 18 04:42:38 PM UTC 24 |
185720500 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3049046702 |
|
|
Sep 18 04:42:14 PM UTC 24 |
Sep 18 04:42:41 PM UTC 24 |
26099600 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.1095924538 |
|
|
Sep 18 04:42:07 PM UTC 24 |
Sep 18 04:42:41 PM UTC 24 |
392704700 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.610748903 |
|
|
Sep 18 04:42:27 PM UTC 24 |
Sep 18 04:42:47 PM UTC 24 |
50101900 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.1694476768 |
|
|
Sep 18 04:42:24 PM UTC 24 |
Sep 18 04:42:48 PM UTC 24 |
816614100 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.1233599061 |
|
|
Sep 18 04:42:25 PM UTC 24 |
Sep 18 04:42:50 PM UTC 24 |
17991900 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.387552749 |
|
|
Sep 18 04:42:25 PM UTC 24 |
Sep 18 04:42:51 PM UTC 24 |
28541700 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.2110815513 |
|
|
Sep 18 04:42:24 PM UTC 24 |
Sep 18 04:42:52 PM UTC 24 |
63004800 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.2587251325 |
|
|
Sep 18 04:42:35 PM UTC 24 |
Sep 18 04:42:53 PM UTC 24 |
22130200 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.3188693331 |
|
|
Sep 18 04:42:33 PM UTC 24 |
Sep 18 04:42:54 PM UTC 24 |
189936800 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.2727414446 |
|
|
Sep 18 04:42:28 PM UTC 24 |
Sep 18 04:42:55 PM UTC 24 |
15356500 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.4040626264 |
|
|
Sep 18 04:42:35 PM UTC 24 |
Sep 18 04:42:56 PM UTC 24 |
27008100 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.3857007089 |
|
|
Sep 18 04:42:36 PM UTC 24 |
Sep 18 04:42:59 PM UTC 24 |
32113700 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.942823162 |
|
|
Sep 18 04:42:40 PM UTC 24 |
Sep 18 04:42:59 PM UTC 24 |
58660000 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.895261767 |
|
|
Sep 18 04:42:37 PM UTC 24 |
Sep 18 04:42:59 PM UTC 24 |
15628200 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.128559070 |
|
|
Sep 18 04:42:39 PM UTC 24 |
Sep 18 04:43:00 PM UTC 24 |
38746800 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.3797946311 |
|
|
Sep 18 04:42:43 PM UTC 24 |
Sep 18 04:43:03 PM UTC 24 |
48931100 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.1687455416 |
|
|
Sep 18 04:42:39 PM UTC 24 |
Sep 18 04:43:05 PM UTC 24 |
14689000 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.4215443632 |
|
|
Sep 18 04:42:39 PM UTC 24 |
Sep 18 04:43:05 PM UTC 24 |
17470600 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.1231051325 |
|
|
Sep 18 04:42:49 PM UTC 24 |
Sep 18 04:43:07 PM UTC 24 |
21114600 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.1617003705 |
|
|
Sep 18 04:42:48 PM UTC 24 |
Sep 18 04:43:07 PM UTC 24 |
133737300 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1773801789 |
|
|
Sep 18 04:42:43 PM UTC 24 |
Sep 18 04:43:10 PM UTC 24 |
15353100 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.1273774913 |
|
|
Sep 18 04:42:51 PM UTC 24 |
Sep 18 04:43:11 PM UTC 24 |
30287200 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.4259787442 |
|
|
Sep 18 04:42:55 PM UTC 24 |
Sep 18 04:43:15 PM UTC 24 |
30220400 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.269009796 |
|
|
Sep 18 04:42:57 PM UTC 24 |
Sep 18 04:43:15 PM UTC 24 |
53512500 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.3018439891 |
|
|
Sep 18 04:42:54 PM UTC 24 |
Sep 18 04:43:15 PM UTC 24 |
25152800 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.3780720520 |
|
|
Sep 18 04:42:53 PM UTC 24 |
Sep 18 04:43:16 PM UTC 24 |
56262600 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.2552466077 |
|
|
Sep 18 04:42:52 PM UTC 24 |
Sep 18 04:43:17 PM UTC 24 |
88132700 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.2843655168 |
|
|
Sep 18 04:42:54 PM UTC 24 |
Sep 18 04:43:18 PM UTC 24 |
15127000 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.4064784772 |
|
|
Sep 18 04:42:59 PM UTC 24 |
Sep 18 04:43:19 PM UTC 24 |
25084400 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.2524437218 |
|
|
Sep 18 04:43:02 PM UTC 24 |
Sep 18 04:43:21 PM UTC 24 |
26896400 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.76901626 |
|
|
Sep 18 04:43:04 PM UTC 24 |
Sep 18 04:43:26 PM UTC 24 |
16413900 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.990135471 |
|
|
Sep 18 04:43:06 PM UTC 24 |
Sep 18 04:43:26 PM UTC 24 |
128976700 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.280988261 |
|
|
Sep 18 04:43:00 PM UTC 24 |
Sep 18 04:43:26 PM UTC 24 |
42684800 ps |
| T1265 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.1628236548 |
|
|
Sep 18 04:43:01 PM UTC 24 |
Sep 18 04:43:27 PM UTC 24 |
16130100 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2753161349 |
|
|
Sep 18 04:36:37 PM UTC 24 |
Sep 18 04:47:13 PM UTC 24 |
445456000 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.147157063 |
|
|
Sep 18 04:39:13 PM UTC 24 |
Sep 18 04:48:05 PM UTC 24 |
492046700 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.1665425398 |
|
|
Sep 18 04:37:44 PM UTC 24 |
Sep 18 04:48:44 PM UTC 24 |
726985600 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.659190939 |
|
|
Sep 18 04:39:24 PM UTC 24 |
Sep 18 04:48:54 PM UTC 24 |
1402102600 ps |