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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.06 95.24 93.99 98.31 92.52 97.18 96.99 98.21


Total test records in report: 1266
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T671 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.3269308608 Sep 18 05:44:39 PM UTC 24 Sep 18 05:47:04 PM UTC 24 4594647300 ps
T672 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.4098096235 Sep 18 05:44:46 PM UTC 24 Sep 18 05:47:06 PM UTC 24 3700811100 ps
T673 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.2127944167 Sep 18 05:28:07 PM UTC 24 Sep 18 05:47:07 PM UTC 24 348763400 ps
T674 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.883524922 Sep 18 05:44:18 PM UTC 24 Sep 18 05:47:09 PM UTC 24 10011752800 ps
T116 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1904503963 Sep 18 05:44:59 PM UTC 24 Sep 18 05:47:14 PM UTC 24 1168854300 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.55913793 Sep 18 05:46:11 PM UTC 24 Sep 18 05:47:33 PM UTC 24 2053827200 ps
T675 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.1385033578 Sep 18 05:24:42 PM UTC 24 Sep 18 05:47:35 PM UTC 24 771013000 ps
T676 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.3795248462 Sep 18 05:43:07 PM UTC 24 Sep 18 05:47:36 PM UTC 24 4964997200 ps
T677 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.1575994994 Sep 18 05:47:37 PM UTC 24 Sep 18 05:47:55 PM UTC 24 19772800 ps
T297 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.2183893985 Sep 18 05:01:42 PM UTC 24 Sep 18 05:47:57 PM UTC 24 9054652200 ps
T98 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.1063191000 Sep 18 05:44:43 PM UTC 24 Sep 18 05:48:13 PM UTC 24 79462700 ps
T113 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_type.3929946759 Sep 18 04:58:22 PM UTC 24 Sep 18 05:48:15 PM UTC 24 288248600 ps
T678 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.3405686420 Sep 18 05:32:04 PM UTC 24 Sep 18 05:48:16 PM UTC 24 80152005300 ps
T679 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.1842212059 Sep 18 05:46:28 PM UTC 24 Sep 18 05:48:23 PM UTC 24 68353600 ps
T680 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.448100381 Sep 18 05:47:57 PM UTC 24 Sep 18 05:48:37 PM UTC 24 50872500 ps
T681 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.3447016743 Sep 18 05:47:07 PM UTC 24 Sep 18 05:48:38 PM UTC 24 3385377000 ps
T682 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.440645510 Sep 18 05:46:43 PM UTC 24 Sep 18 05:48:41 PM UTC 24 26751900 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.1679926420 Sep 18 05:45:15 PM UTC 24 Sep 18 05:48:48 PM UTC 24 43732060100 ps
T683 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.2275299861 Sep 18 05:44:59 PM UTC 24 Sep 18 05:48:48 PM UTC 24 2555268300 ps
T114 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.535170299 Sep 18 05:01:36 PM UTC 24 Sep 18 05:48:49 PM UTC 24 1520828300 ps
T684 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.1799542793 Sep 18 05:45:03 PM UTC 24 Sep 18 05:48:49 PM UTC 24 1687711800 ps
T685 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.3482365090 Sep 18 05:48:23 PM UTC 24 Sep 18 05:48:49 PM UTC 24 50837100 ps
T686 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.1659899062 Sep 18 05:47:56 PM UTC 24 Sep 18 05:48:50 PM UTC 24 77905000 ps
T687 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.2495245473 Sep 18 05:48:39 PM UTC 24 Sep 18 05:48:59 PM UTC 24 15294100 ps
T688 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.1951378344 Sep 18 05:48:38 PM UTC 24 Sep 18 05:49:02 PM UTC 24 15106500 ps
T689 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.2980950265 Sep 18 05:48:16 PM UTC 24 Sep 18 05:49:02 PM UTC 24 10633400 ps
T690 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.2949780206 Sep 18 05:47:10 PM UTC 24 Sep 18 05:49:05 PM UTC 24 571636900 ps
T691 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.3676641831 Sep 18 05:48:14 PM UTC 24 Sep 18 05:49:07 PM UTC 24 364128400 ps
T692 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.3552195671 Sep 18 05:44:35 PM UTC 24 Sep 18 05:49:07 PM UTC 24 78228200 ps
T693 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.3269468512 Sep 18 05:46:45 PM UTC 24 Sep 18 05:49:12 PM UTC 24 6958860500 ps
T694 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.2486430121 Sep 18 05:48:48 PM UTC 24 Sep 18 05:49:13 PM UTC 24 94027400 ps
T695 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.104066025 Sep 18 05:46:27 PM UTC 24 Sep 18 05:49:32 PM UTC 24 10012225600 ps
T298 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.3785079568 Sep 18 05:06:03 PM UTC 24 Sep 18 05:49:43 PM UTC 24 9853881900 ps
T187 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.1370899406 Sep 18 05:36:32 PM UTC 24 Sep 18 05:49:48 PM UTC 24 40123871600 ps
T696 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.2290617260 Sep 18 05:48:17 PM UTC 24 Sep 18 05:49:49 PM UTC 24 1579118300 ps
T697 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.964407798 Sep 18 05:47:36 PM UTC 24 Sep 18 05:49:56 PM UTC 24 116085568000 ps
T698 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.2487426345 Sep 18 05:49:34 PM UTC 24 Sep 18 05:49:56 PM UTC 24 31189400 ps
T699 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.1023209633 Sep 18 05:42:51 PM UTC 24 Sep 18 05:50:01 PM UTC 24 3141227700 ps
T229 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.1928264546 Sep 18 05:49:03 PM UTC 24 Sep 18 05:50:15 PM UTC 24 10589600700 ps
T700 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.1994714889 Sep 18 05:50:02 PM UTC 24 Sep 18 05:50:23 PM UTC 24 26968700 ps
T209 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.2581303108 Sep 18 05:49:56 PM UTC 24 Sep 18 05:50:23 PM UTC 24 11655300 ps
T701 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.1131974598 Sep 18 05:48:51 PM UTC 24 Sep 18 05:50:31 PM UTC 24 2881557700 ps
T702 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.3704445951 Sep 18 05:49:44 PM UTC 24 Sep 18 05:50:33 PM UTC 24 71893000 ps
T703 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.2545190754 Sep 18 05:50:17 PM UTC 24 Sep 18 05:50:36 PM UTC 24 27882700 ps
T704 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.3182217907 Sep 18 05:50:24 PM UTC 24 Sep 18 05:50:43 PM UTC 24 15168200 ps
T705 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.2260028935 Sep 18 05:46:47 PM UTC 24 Sep 18 05:50:43 PM UTC 24 45853700 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.2778773325 Sep 18 05:47:34 PM UTC 24 Sep 18 05:50:45 PM UTC 24 4048731000 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.1621550145 Sep 18 05:49:50 PM UTC 24 Sep 18 05:50:46 PM UTC 24 70697000 ps
T706 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.1735369648 Sep 18 05:49:49 PM UTC 24 Sep 18 05:50:50 PM UTC 24 40184900 ps
T707 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.3165578835 Sep 18 04:58:17 PM UTC 24 Sep 18 05:50:51 PM UTC 24 289282069400 ps
T708 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.454294688 Sep 18 05:49:08 PM UTC 24 Sep 18 05:50:53 PM UTC 24 1103190500 ps
T709 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.2511939138 Sep 18 05:50:32 PM UTC 24 Sep 18 05:50:55 PM UTC 24 44644600 ps
T710 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.2535944756 Sep 18 05:49:57 PM UTC 24 Sep 18 05:51:22 PM UTC 24 17793107800 ps
T711 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.414252916 Sep 18 05:47:08 PM UTC 24 Sep 18 05:51:40 PM UTC 24 4000542300 ps
T712 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.2825805008 Sep 18 05:50:44 PM UTC 24 Sep 18 05:51:40 PM UTC 24 1723725700 ps
T713 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.11510356 Sep 18 04:58:31 PM UTC 24 Sep 18 05:51:42 PM UTC 24 12924196000 ps
T714 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.4232684653 Sep 18 05:50:34 PM UTC 24 Sep 18 05:51:46 PM UTC 24 136121700 ps
T715 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.4119132708 Sep 18 05:49:14 PM UTC 24 Sep 18 05:52:09 PM UTC 24 674466700 ps
T716 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.948605554 Sep 18 05:51:43 PM UTC 24 Sep 18 05:52:15 PM UTC 24 59924200 ps
T717 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.3073815220 Sep 18 05:51:47 PM UTC 24 Sep 18 05:52:40 PM UTC 24 40947200 ps
T718 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.2601691712 Sep 18 05:49:14 PM UTC 24 Sep 18 05:52:44 PM UTC 24 100780138100 ps
T719 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.2831673641 Sep 18 05:50:52 PM UTC 24 Sep 18 05:52:46 PM UTC 24 865252600 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.1609207170 Sep 18 05:49:00 PM UTC 24 Sep 18 05:52:47 PM UTC 24 144387200 ps
T720 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.1374386710 Sep 18 05:49:05 PM UTC 24 Sep 18 05:52:53 PM UTC 24 4329174600 ps
T721 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.2495024349 Sep 18 05:44:36 PM UTC 24 Sep 18 05:52:55 PM UTC 24 712983400 ps
T722 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.587451646 Sep 18 05:50:56 PM UTC 24 Sep 18 05:52:55 PM UTC 24 798699100 ps
T189 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.3685139721 Sep 18 05:50:47 PM UTC 24 Sep 18 05:53:00 PM UTC 24 75200000 ps
T723 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.3305670885 Sep 18 05:52:15 PM UTC 24 Sep 18 05:53:05 PM UTC 24 61475700 ps
T724 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.3591645116 Sep 18 05:52:48 PM UTC 24 Sep 18 05:53:10 PM UTC 24 51277500 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1277412831 Sep 18 05:39:18 PM UTC 24 Sep 18 05:53:10 PM UTC 24 160181365100 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.2748406994 Sep 18 05:52:10 PM UTC 24 Sep 18 05:53:10 PM UTC 24 73524600 ps
T725 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.290277922 Sep 18 05:52:48 PM UTC 24 Sep 18 05:53:13 PM UTC 24 25363700 ps
T726 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.917180573 Sep 18 05:52:56 PM UTC 24 Sep 18 05:53:17 PM UTC 24 100867400 ps
T727 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.3991147111 Sep 18 05:52:54 PM UTC 24 Sep 18 05:53:19 PM UTC 24 25632200 ps
T728 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.3982060590 Sep 18 05:52:41 PM UTC 24 Sep 18 05:53:21 PM UTC 24 58816600 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.4121393752 Sep 18 05:51:42 PM UTC 24 Sep 18 05:53:49 PM UTC 24 549024700 ps
T153 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.886219588 Sep 18 04:57:21 PM UTC 24 Sep 18 05:53:51 PM UTC 24 49892366200 ps
T729 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.2360711345 Sep 18 05:48:49 PM UTC 24 Sep 18 05:53:53 PM UTC 24 37325200 ps
T325 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.2102827072 Sep 18 05:50:24 PM UTC 24 Sep 18 05:54:00 PM UTC 24 10012810600 ps
T730 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.994161608 Sep 18 05:45:01 PM UTC 24 Sep 18 05:54:08 PM UTC 24 10568118500 ps
T731 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3747223615 Sep 18 05:52:44 PM UTC 24 Sep 18 05:54:15 PM UTC 24 1347023600 ps
T732 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.722325662 Sep 18 05:53:20 PM UTC 24 Sep 18 05:54:21 PM UTC 24 6305849200 ps
T733 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.1703548253 Sep 18 05:53:11 PM UTC 24 Sep 18 05:54:25 PM UTC 24 1603788100 ps
T734 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.1127628151 Sep 18 05:39:11 PM UTC 24 Sep 18 05:54:30 PM UTC 24 97906300 ps
T735 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.3381740108 Sep 18 05:54:09 PM UTC 24 Sep 18 05:54:31 PM UTC 24 21518900 ps
T736 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.1172340571 Sep 18 05:50:54 PM UTC 24 Sep 18 05:54:36 PM UTC 24 5354003300 ps
T737 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw.2626668491 Sep 18 05:47:15 PM UTC 24 Sep 18 05:54:45 PM UTC 24 36668055900 ps
T738 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.1762262269 Sep 18 05:54:16 PM UTC 24 Sep 18 05:55:00 PM UTC 24 68065900 ps
T739 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.2320572661 Sep 18 05:54:37 PM UTC 24 Sep 18 05:55:01 PM UTC 24 23970200 ps
T740 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.2432285774 Sep 18 05:41:59 PM UTC 24 Sep 18 05:55:07 PM UTC 24 70141276500 ps
T741 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.243017639 Sep 18 05:51:42 PM UTC 24 Sep 18 05:55:10 PM UTC 24 11905356900 ps
T742 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.1269480484 Sep 18 05:54:22 PM UTC 24 Sep 18 05:55:11 PM UTC 24 62192900 ps
T743 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.37282650 Sep 18 05:54:45 PM UTC 24 Sep 18 05:55:11 PM UTC 24 15787300 ps
T744 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.880156358 Sep 18 05:52:56 PM UTC 24 Sep 18 05:55:15 PM UTC 24 10011950300 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.4105745596 Sep 18 05:54:31 PM UTC 24 Sep 18 05:55:16 PM UTC 24 41009000 ps
T745 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.2994916822 Sep 18 05:55:00 PM UTC 24 Sep 18 05:55:18 PM UTC 24 15730700 ps
T746 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.2683885422 Sep 18 05:55:07 PM UTC 24 Sep 18 05:55:26 PM UTC 24 31026100 ps
T747 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.4061313789 Sep 18 05:32:20 PM UTC 24 Sep 18 05:55:26 PM UTC 24 12629122400 ps
T748 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.1095060228 Sep 18 05:54:27 PM UTC 24 Sep 18 05:55:32 PM UTC 24 305132500 ps
T749 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1257362176 Sep 18 05:48:41 PM UTC 24 Sep 18 05:55:32 PM UTC 24 10012374300 ps
T750 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.3491965369 Sep 18 05:53:50 PM UTC 24 Sep 18 05:55:37 PM UTC 24 1899362800 ps
T751 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.966952355 Sep 18 05:55:16 PM UTC 24 Sep 18 05:56:05 PM UTC 24 850491900 ps
T293 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.4038616867 Sep 18 05:55:02 PM UTC 24 Sep 18 05:56:05 PM UTC 24 10029550900 ps
T752 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.1276337108 Sep 18 05:54:01 PM UTC 24 Sep 18 05:56:05 PM UTC 24 564386000 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.818305388 Sep 18 05:54:32 PM UTC 24 Sep 18 05:56:11 PM UTC 24 6731091700 ps
T753 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.2371124139 Sep 18 05:53:18 PM UTC 24 Sep 18 05:56:25 PM UTC 24 7525037500 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.2180070168 Sep 18 05:44:41 PM UTC 24 Sep 18 05:56:34 PM UTC 24 40118536400 ps
T754 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.1608319217 Sep 18 05:56:06 PM UTC 24 Sep 18 05:56:34 PM UTC 24 24398100 ps
T755 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.1598912910 Sep 18 05:53:10 PM UTC 24 Sep 18 05:56:41 PM UTC 24 40891300 ps
T756 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_wo.3996269396 Sep 18 05:53:23 PM UTC 24 Sep 18 05:56:56 PM UTC 24 8851527600 ps
T757 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.1100062034 Sep 18 05:55:27 PM UTC 24 Sep 18 05:56:59 PM UTC 24 3943048300 ps
T758 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.459895467 Sep 18 05:56:12 PM UTC 24 Sep 18 05:57:02 PM UTC 24 36811900 ps
T166 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.1258768348 Sep 18 05:47:05 PM UTC 24 Sep 18 05:57:06 PM UTC 24 82800807100 ps
T759 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.4083493660 Sep 18 05:56:27 PM UTC 24 Sep 18 05:57:10 PM UTC 24 28530700 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.1020207621 Sep 18 05:53:13 PM UTC 24 Sep 18 05:57:12 PM UTC 24 75152100 ps
T760 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.1994776117 Sep 18 05:56:35 PM UTC 24 Sep 18 05:57:16 PM UTC 24 138000600 ps
T761 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.2105876800 Sep 18 05:57:00 PM UTC 24 Sep 18 05:57:21 PM UTC 24 26507500 ps
T762 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.1372021824 Sep 18 05:56:35 PM UTC 24 Sep 18 05:57:21 PM UTC 24 191539900 ps
T763 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.2237060219 Sep 18 05:56:56 PM UTC 24 Sep 18 05:57:22 PM UTC 24 25862800 ps
T764 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.298920871 Sep 18 05:57:03 PM UTC 24 Sep 18 05:57:25 PM UTC 24 26139900 ps
T765 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.3838932865 Sep 18 05:50:43 PM UTC 24 Sep 18 05:57:28 PM UTC 24 72099800 ps
T766 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1717603159 Sep 18 05:57:10 PM UTC 24 Sep 18 05:57:36 PM UTC 24 260012200 ps
T767 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.4194305105 Sep 18 05:53:01 PM UTC 24 Sep 18 05:57:50 PM UTC 24 3059755800 ps
T768 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.2144954217 Sep 18 05:55:33 PM UTC 24 Sep 18 05:57:52 PM UTC 24 977137300 ps
T769 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.1427795876 Sep 18 05:54:01 PM UTC 24 Sep 18 05:58:07 PM UTC 24 26874538900 ps
T97 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.3029234230 Sep 18 05:55:19 PM UTC 24 Sep 18 05:58:08 PM UTC 24 454117500 ps
T167 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.3345447179 Sep 18 05:31:55 PM UTC 24 Sep 18 05:58:18 PM UTC 24 2172731200 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.3378324052 Sep 18 05:49:08 PM UTC 24 Sep 18 05:58:27 PM UTC 24 22990438900 ps
T770 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.2284075876 Sep 18 05:44:36 PM UTC 24 Sep 18 05:58:27 PM UTC 24 253994800 ps
T771 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.1162868307 Sep 18 05:57:21 PM UTC 24 Sep 18 05:58:29 PM UTC 24 4621663000 ps
T772 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.4290444876 Sep 18 05:48:50 PM UTC 24 Sep 18 05:58:35 PM UTC 24 2106005300 ps
T773 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.644348031 Sep 18 05:58:19 PM UTC 24 Sep 18 05:58:40 PM UTC 24 60286000 ps
T774 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.1938870237 Sep 18 05:57:13 PM UTC 24 Sep 18 05:58:51 PM UTC 24 39576200 ps
T775 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.4166481761 Sep 18 05:56:42 PM UTC 24 Sep 18 05:59:04 PM UTC 24 30469044400 ps
T776 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.3563454465 Sep 18 05:57:29 PM UTC 24 Sep 18 05:59:05 PM UTC 24 3047993400 ps
T777 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.600385313 Sep 18 05:58:28 PM UTC 24 Sep 18 05:59:08 PM UTC 24 28770800 ps
T778 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.1271826691 Sep 18 05:58:52 PM UTC 24 Sep 18 05:59:18 PM UTC 24 16926300 ps
T779 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.256767452 Sep 18 05:58:35 PM UTC 24 Sep 18 05:59:21 PM UTC 24 10800200 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.1408244546 Sep 18 05:58:28 PM UTC 24 Sep 18 05:59:22 PM UTC 24 49509100 ps
T780 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.354627664 Sep 18 05:59:06 PM UTC 24 Sep 18 05:59:24 PM UTC 24 48738100 ps
T781 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.3768503541 Sep 18 05:55:11 PM UTC 24 Sep 18 05:59:27 PM UTC 24 105738800 ps
T782 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.4079610233 Sep 18 05:58:29 PM UTC 24 Sep 18 05:59:27 PM UTC 24 65227100 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.3265476810 Sep 18 05:59:07 PM UTC 24 Sep 18 05:59:35 PM UTC 24 23421700 ps
T783 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.999041477 Sep 18 05:55:33 PM UTC 24 Sep 18 05:59:38 PM UTC 24 2736821800 ps
T194 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.2529458722 Sep 18 06:05:18 PM UTC 24 Sep 18 06:08:08 PM UTC 24 139546600 ps
T784 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.1374134837 Sep 18 05:57:51 PM UTC 24 Sep 18 05:59:38 PM UTC 24 625990300 ps
T785 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.1206103200 Sep 18 05:51:23 PM UTC 24 Sep 18 05:59:43 PM UTC 24 7839328000 ps
T786 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.1556800235 Sep 18 05:59:19 PM UTC 24 Sep 18 05:59:48 PM UTC 24 38905200 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.2272374921 Sep 18 05:56:06 PM UTC 24 Sep 18 06:00:04 PM UTC 24 1757195500 ps
T787 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.1550009247 Sep 18 05:57:26 PM UTC 24 Sep 18 06:00:09 PM UTC 24 1589801700 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.3250204981 Sep 18 05:58:41 PM UTC 24 Sep 18 06:00:12 PM UTC 24 1165802300 ps
T788 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.226411594 Sep 18 05:46:45 PM UTC 24 Sep 18 06:00:17 PM UTC 24 40120031100 ps
T789 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.2014769532 Sep 18 05:57:23 PM UTC 24 Sep 18 06:00:24 PM UTC 24 292528000 ps
T790 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.4119919739 Sep 18 05:59:44 PM UTC 24 Sep 18 06:00:24 PM UTC 24 23622000 ps
T791 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.2505632877 Sep 18 05:57:17 PM UTC 24 Sep 18 06:00:27 PM UTC 24 57251700 ps
T792 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.2163951263 Sep 18 06:00:07 PM UTC 24 Sep 18 06:00:31 PM UTC 24 80740600 ps
T793 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.2006502181 Sep 18 05:48:50 PM UTC 24 Sep 18 06:00:32 PM UTC 24 1530477000 ps
T794 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.2928864113 Sep 18 06:04:48 PM UTC 24 Sep 18 06:08:07 PM UTC 24 6765621500 ps
T795 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.1401664684 Sep 18 06:00:10 PM UTC 24 Sep 18 06:00:35 PM UTC 24 60029100 ps
T796 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.3495873290 Sep 18 05:59:39 PM UTC 24 Sep 18 06:00:35 PM UTC 24 101153000 ps
T797 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.2386366038 Sep 18 05:58:10 PM UTC 24 Sep 18 06:00:45 PM UTC 24 18148550900 ps
T798 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.3091858520 Sep 18 06:00:32 PM UTC 24 Sep 18 06:00:59 PM UTC 24 276073800 ps
T799 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.1264838681 Sep 18 05:57:37 PM UTC 24 Sep 18 06:01:10 PM UTC 24 2236150300 ps
T800 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.3207695948 Sep 18 05:54:00 PM UTC 24 Sep 18 06:01:14 PM UTC 24 8131453600 ps
T801 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.1163389984 Sep 18 06:00:46 PM UTC 24 Sep 18 06:01:17 PM UTC 24 13552600 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.48151839 Sep 18 05:59:48 PM UTC 24 Sep 18 06:01:18 PM UTC 24 4492066900 ps
T210 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1494582673 Sep 18 06:00:35 PM UTC 24 Sep 18 06:01:21 PM UTC 24 17373100 ps
T176 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.26683044 Sep 18 05:48:51 PM UTC 24 Sep 18 06:01:23 PM UTC 24 40127954700 ps
T802 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.3926760669 Sep 18 06:01:00 PM UTC 24 Sep 18 06:01:25 PM UTC 24 167291700 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.1111608543 Sep 18 06:00:33 PM UTC 24 Sep 18 06:01:29 PM UTC 24 96083300 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.3912536603 Sep 18 05:50:51 PM UTC 24 Sep 18 06:01:30 PM UTC 24 16425557500 ps
T803 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.3301751103 Sep 18 05:55:12 PM UTC 24 Sep 18 06:01:31 PM UTC 24 102522900 ps
T804 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.2345901760 Sep 18 06:00:35 PM UTC 24 Sep 18 06:01:32 PM UTC 24 49923100 ps
T805 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.688018838 Sep 18 05:58:07 PM UTC 24 Sep 18 06:01:43 PM UTC 24 28525165300 ps
T806 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.3793981980 Sep 18 05:50:36 PM UTC 24 Sep 18 06:01:50 PM UTC 24 83030000 ps
T807 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.2443289088 Sep 18 06:01:25 PM UTC 24 Sep 18 06:01:55 PM UTC 24 304924800 ps
T808 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.1672069421 Sep 18 05:59:24 PM UTC 24 Sep 18 06:02:00 PM UTC 24 5220783400 ps
T809 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.1485561919 Sep 18 06:01:33 PM UTC 24 Sep 18 06:02:02 PM UTC 24 31783200 ps
T810 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.2340603144 Sep 18 05:57:08 PM UTC 24 Sep 18 06:02:02 PM UTC 24 10012850600 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.2429304818 Sep 18 06:00:35 PM UTC 24 Sep 18 06:02:03 PM UTC 24 7983603700 ps
T811 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict_all_en.2425563018 Sep 18 06:01:26 PM UTC 24 Sep 18 06:02:03 PM UTC 24 61392900 ps
T812 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.3926534043 Sep 18 06:01:34 PM UTC 24 Sep 18 06:02:03 PM UTC 24 41222100 ps
T813 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.255399425 Sep 18 05:11:27 PM UTC 24 Sep 18 06:02:04 PM UTC 24 43622589300 ps
T814 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.338239442 Sep 18 05:59:28 PM UTC 24 Sep 18 06:02:05 PM UTC 24 3465116300 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.2309406566 Sep 18 05:59:25 PM UTC 24 Sep 18 06:02:06 PM UTC 24 70648200 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.4235633932 Sep 18 06:01:30 PM UTC 24 Sep 18 06:02:09 PM UTC 24 15984800 ps
T815 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.1266242583 Sep 18 06:01:11 PM UTC 24 Sep 18 06:02:19 PM UTC 24 75973500 ps
T816 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.3176151305 Sep 18 06:01:25 PM UTC 24 Sep 18 06:02:20 PM UTC 24 32164700 ps
T115 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.252501990 Sep 18 05:11:13 PM UTC 24 Sep 18 06:02:22 PM UTC 24 718567800 ps
T817 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.393968621 Sep 18 06:02:03 PM UTC 24 Sep 18 06:02:22 PM UTC 24 18142000 ps
T818 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.2904426436 Sep 18 06:02:06 PM UTC 24 Sep 18 06:02:28 PM UTC 24 16874600 ps
T819 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.4188664723 Sep 18 05:59:36 PM UTC 24 Sep 18 06:02:30 PM UTC 24 9356148800 ps
T820 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.4177766691 Sep 18 06:02:05 PM UTC 24 Sep 18 06:02:32 PM UTC 24 35700000 ps
T821 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.4004958075 Sep 18 06:00:17 PM UTC 24 Sep 18 06:02:34 PM UTC 24 4176932500 ps
T822 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.1033319336 Sep 18 06:02:07 PM UTC 24 Sep 18 06:02:35 PM UTC 24 186241500 ps
T823 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.3527658768 Sep 18 06:00:25 PM UTC 24 Sep 18 06:02:41 PM UTC 24 2275023900 ps
T824 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.1574483753 Sep 18 05:55:13 PM UTC 24 Sep 18 06:02:43 PM UTC 24 1426851400 ps
T326 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.2061955588 Sep 18 06:02:29 PM UTC 24 Sep 18 06:02:46 PM UTC 24 19815200 ps
T825 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.3658333116 Sep 18 06:01:31 PM UTC 24 Sep 18 06:02:47 PM UTC 24 2322786100 ps
T826 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.2544373347 Sep 18 06:00:28 PM UTC 24 Sep 18 06:02:50 PM UTC 24 41395178800 ps
T827 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.1736968997 Sep 18 06:02:04 PM UTC 24 Sep 18 06:02:57 PM UTC 24 38268800 ps
T828 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.3898332491 Sep 18 06:02:04 PM UTC 24 Sep 18 06:03:06 PM UTC 24 47083200 ps
T829 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.324727992 Sep 18 06:02:44 PM UTC 24 Sep 18 06:03:06 PM UTC 24 65632100 ps
T830 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.1833524594 Sep 18 06:02:33 PM UTC 24 Sep 18 06:03:12 PM UTC 24 30709500 ps
T831 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.1916571101 Sep 18 06:02:42 PM UTC 24 Sep 18 06:03:12 PM UTC 24 26799800 ps
T327 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.3016793655 Sep 18 06:01:51 PM UTC 24 Sep 18 06:03:14 PM UTC 24 2928799400 ps
T832 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.3947481007 Sep 18 05:55:37 PM UTC 24 Sep 18 06:03:17 PM UTC 24 7483383300 ps
T833 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.2394878601 Sep 18 06:01:18 PM UTC 24 Sep 18 06:03:18 PM UTC 24 527818100 ps
T195 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.89238180 Sep 18 06:00:25 PM UTC 24 Sep 18 06:03:18 PM UTC 24 40215900 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.2825939710 Sep 18 06:02:34 PM UTC 24 Sep 18 06:03:19 PM UTC 24 10936000 ps
T834 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.298097851 Sep 18 06:00:12 PM UTC 24 Sep 18 06:03:20 PM UTC 24 8439105500 ps
T835 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.2284650528 Sep 18 05:59:22 PM UTC 24 Sep 18 06:03:20 PM UTC 24 30630100 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.51450057 Sep 18 06:02:31 PM UTC 24 Sep 18 06:03:21 PM UTC 24 42939600 ps
T92 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.1110751586 Sep 18 06:03:06 PM UTC 24 Sep 18 06:03:28 PM UTC 24 69296100 ps
T836 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.2059620721 Sep 18 06:03:19 PM UTC 24 Sep 18 06:03:36 PM UTC 24 76885000 ps
T837 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.445713624 Sep 18 06:03:17 PM UTC 24 Sep 18 06:03:40 PM UTC 24 100935100 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.911315022 Sep 18 06:03:14 PM UTC 24 Sep 18 06:03:40 PM UTC 24 25851800 ps
T838 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.2671088425 Sep 18 06:02:36 PM UTC 24 Sep 18 06:03:52 PM UTC 24 7413328500 ps
T839 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.2146760950 Sep 18 06:02:05 PM UTC 24 Sep 18 06:03:57 PM UTC 24 2774544900 ps
T840 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.1242442046 Sep 18 06:03:29 PM UTC 24 Sep 18 06:04:02 PM UTC 24 64290800 ps
T841 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.1035721107 Sep 18 06:02:19 PM UTC 24 Sep 18 06:04:05 PM UTC 24 3232688700 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.1082063868 Sep 18 06:02:48 PM UTC 24 Sep 18 06:04:06 PM UTC 24 2147851600 ps
T842 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.484608729 Sep 18 06:03:07 PM UTC 24 Sep 18 06:04:06 PM UTC 24 68611500 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.3933664191 Sep 18 06:03:14 PM UTC 24 Sep 18 06:04:08 PM UTC 24 144177200 ps
T843 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.4160265113 Sep 18 06:03:41 PM UTC 24 Sep 18 06:04:12 PM UTC 24 11297700 ps
T844 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.2596608819 Sep 18 06:04:03 PM UTC 24 Sep 18 06:04:21 PM UTC 24 179453500 ps
T845 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.722985634 Sep 18 06:03:38 PM UTC 24 Sep 18 06:04:21 PM UTC 24 76925600 ps
T846 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.3410484700 Sep 18 06:01:18 PM UTC 24 Sep 18 06:04:22 PM UTC 24 69340700 ps
T847 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.440472299 Sep 18 06:03:40 PM UTC 24 Sep 18 06:04:26 PM UTC 24 28013500 ps
T848 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.2840629068 Sep 18 06:03:57 PM UTC 24 Sep 18 06:04:27 PM UTC 24 55453700 ps
T849 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.1029539336 Sep 18 06:02:47 PM UTC 24 Sep 18 06:04:31 PM UTC 24 27847600 ps
T850 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.1169916957 Sep 18 06:03:15 PM UTC 24 Sep 18 06:04:35 PM UTC 24 456231200 ps
T851 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.3191447526 Sep 18 06:01:56 PM UTC 24 Sep 18 06:04:41 PM UTC 24 72366500 ps
T852 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.3679655883 Sep 18 05:59:09 PM UTC 24 Sep 18 06:04:42 PM UTC 24 10012541700 ps
T853 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.1248534844 Sep 18 06:02:02 PM UTC 24 Sep 18 06:04:47 PM UTC 24 5717651500 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1815891119 Sep 18 05:56:06 PM UTC 24 Sep 18 06:04:50 PM UTC 24 24547096500 ps
T854 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.754496553 Sep 18 05:59:28 PM UTC 24 Sep 18 06:04:51 PM UTC 24 15129287800 ps
T855 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.3068255162 Sep 18 06:04:22 PM UTC 24 Sep 18 06:04:53 PM UTC 24 19268400 ps
T856 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.1548772903 Sep 18 06:04:31 PM UTC 24 Sep 18 06:04:54 PM UTC 24 14131400 ps
T857 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.2862443603 Sep 18 06:04:32 PM UTC 24 Sep 18 06:04:57 PM UTC 24 193271700 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.3187498706 Sep 18 06:04:27 PM UTC 24 Sep 18 06:05:01 PM UTC 24 30506500 ps
T858 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.3194036072 Sep 18 05:46:41 PM UTC 24 Sep 18 06:05:07 PM UTC 24 9299361900 ps
T859 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.130358955 Sep 18 06:02:57 PM UTC 24 Sep 18 06:05:09 PM UTC 24 747398300 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.2878783906 Sep 18 06:04:22 PM UTC 24 Sep 18 06:05:11 PM UTC 24 49229600 ps
T860 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.538952936 Sep 18 06:01:44 PM UTC 24 Sep 18 06:05:12 PM UTC 24 236183200 ps
T861 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.397681958 Sep 18 06:04:23 PM UTC 24 Sep 18 06:05:17 PM UTC 24 29406000 ps
T862 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.383047454 Sep 18 06:04:52 PM UTC 24 Sep 18 06:05:19 PM UTC 24 36787600 ps
T863 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.2997729200 Sep 18 05:50:46 PM UTC 24 Sep 18 06:05:23 PM UTC 24 40127026200 ps
T864 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.3774088766 Sep 18 06:03:52 PM UTC 24 Sep 18 06:05:24 PM UTC 24 1490284400 ps
T865 /workspaces/repo/scratch/os_regression_2024_09_17/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.643806831 Sep 18 05:49:03 PM UTC 24 Sep 18 06:05:29 PM UTC 24 39493753600 ps
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