Line Coverage for Module : flash_ctrl_arb
Cond Coverage for Module : flash_ctrl_arb
FSM Coverage for Module : flash_ctrl_arb
State, Transition and Sequence Details for FSM :: state_q
Branch Coverage for Module : flash_ctrl_arb
Branches:
Branches:
Branches:
Branches:
Branches:
Assert Coverage for Module : flash_ctrl_arb
Assertion Details
u_state_regs_A
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| TOTAL | 66 | 66 | 100.00 | |
| CONT_ASSIGN | 120 | 1 | 1 | 100.00 |
| ALWAYS | 123 | 3 | 3 | 100.00 |
| ALWAYS | 127 | 22 | 22 | 100.00 |
| ALWAYS | 194 | 25 | 25 | 100.00 |
| ALWAYS | 240 | 13 | 13 | 100.00 |
| CONT_ASSIGN | 275 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 278 | 1 | 1 | 100.00 |
119 logic sw_req; 120 1/1 assign sw_req = sw_ctrl_i.start.q; Tests: T1 T2 T3 121 122 // SEC_CM: CTRL.FSM.SPARSE123 3/3 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, arb_state_e, StReset) Tests: T1 T2 T3 | T1 T2 T3 | T1 T2 T3
PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, arb_state_e, StReset): 123.1 `ifdef SIMULATION 123.2 prim_sparse_fsm_flop #( 123.3 .StateEnumT(arb_state_e), 123.4 .Width($bits(arb_state_e)), 123.5 .ResetValue($bits(arb_state_e)'(StReset)), 123.6 .EnableAlertTriggerSVA(1), 123.7 .CustomForceName("state_q") 123.8 ) u_state_regs ( 123.9 .clk_i ( clk_i ), 123.10 .rst_ni ( rst_ni ), 123.11 .state_i ( state_d ), 123.12 .state_o ( ) 123.13 ); 123.14 always_ff @(posedge clk_i or negedge rst_ni) begin 123.15 1/1 if (!rst_ni) begin Tests: T1 T2 T3 123.16 1/1 state_q <= StReset; Tests: T1 T2 T3 123.17 end else begin 123.18 1/1 state_q <= state_d; Tests: T1 T2 T3 123.19 end 123.20 end 123.21 u_state_regs_A: assert property (@(posedge clk_i) disable iff ((!rst_ni) !== '0) (state_q === u_state_regs.state_o)) 123.22 else begin 123.23 `ifdef UVM 123.24 uvm_pkg::uvm_report_error("ASSERT FAILED", "u_state_regs_A", uvm_pkg::UVM_NONE, 123.25 "../src/lowrisc_opentitan_top_earlgrey_flash_ctrl_0.1/rtl/flash_ctrl_arb.sv", 123, "", 1); 123.26 `else 123.27 $error("%0t: (%0s:%0d) [%m] [ASSERT FAILED] %0s", $time, `__FILE__, `__LINE__, 123.28 `PRIM_STRINGIFY(u_state_regs_A)); 123.29 `endif 123.30 end 123.31 `else 123.32 prim_sparse_fsm_flop #( 123.33 .StateEnumT(arb_state_e), 123.34 .Width($bits(arb_state_e)), 123.35 .ResetValue($bits(arb_state_e)'(StReset)), 123.36 .EnableAlertTriggerSVA(1) 123.37 ) u_state_regs ( 123.38 .clk_i ( `PRIM_FLOP_CLK ), 123.39 .rst_ni ( `PRIM_FLOP_RST ), 123.40 .state_i ( state_d ), 123.41 .state_o ( state_q ) 123.42 ); 123.43 `endif124 125 always_comb begin 126 127 1/1 func_sel = NoneSel; Tests: T1 T2 T3 128 1/1 fifo_clr_o = 1'b0; Tests: T1 T2 T3 129 1/1 state_d = state_q; Tests: T1 T2 T3 130 1/1 fsm_err_o = 1'b0; Tests: T1 T2 T3 131 132 1/1 unique case (state_q) Tests: T1 T2 T3 133 StReset: begin 134 // until the flash phy is done with its own initialization, 135 // no flash controller activity is allowed to commence 136 1/1 if (!flash_phy_busy_i) begin Tests: T1 T2 T3 137 // after flash is ready, the HW interface always takes 138 // precedence for flash control initialization 139 1/1 state_d = StHw; Tests: T1 T2 T3 140 end MISSING_ELSE 141 end 142 143 StHw: begin 144 1/1 func_sel = HwSel; Tests: T1 T2 T3 145 146 1/1 if (!hw_req_i) begin Tests: T1 T2 T3 147 1/1 state_d = StSwIdle; Tests: T1 T2 T3 148 end MISSING_ELSE 149 end 150 151 StSwIdle: begin 152 // software is still selected to enable access to Fifos 153 1/1 func_sel = SwSel; Tests: T1 T2 T3 154 155 1/1 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin Tests: T1 T2 T3 156 // Do not randomly switch unless idle as it may cause stateful operations to be 157 // disturbed 158 1/1 state_d = StDisabled; Tests: T4 T5 T6 159 1/1 end else if (hw_req_i) begin Tests: T1 T2 T3 160 // if hardware request comes in the middle, wipe fifos and enable 161 // switch to hardware interface 162 1/1 fifo_clr_o = 1'b1; Tests: T1 T2 T3 163 1/1 state_d = StHw; Tests: T1 T2 T3 164 1/1 end else if (sw_req) begin Tests: T1 T2 T3 165 1/1 state_d = StSwActive; Tests: T2 T3 T10 166 end MISSING_ELSE 167 end 168 169 StSwActive: begin 170 1/1 func_sel = SwSel; Tests: T2 T3 T10 171 172 // Stay in software active mode until operation completes. 173 // While operations are ongoing, the interface cannot be switched 174 1/1 if (prog_ack_i || rd_ack_i || erase_ack_i) begin Tests: T2 T3 T10 175 1/1 state_d = StSwIdle; Tests: T2 T3 T10 176 end MISSING_ELSE 177 end 178 179 StDisabled: begin 180 1/1 state_d = StDisabled; Tests: T4 T5 T6 181 end 182 183 default: begin 184 fsm_err_o = 1'b1; 185 end 186 endcase // unique case (state_q) 187 188 end // always_comb 189 190 logic ctrl_ack; 191 flash_ctrl_err_t ctrl_err; 192 193 always_comb begin 194 1/1 muxed_ctrl_o = '0; Tests: T1 T2 T3 195 1/1 muxed_addr_o = '0; Tests: T1 T2 T3 196 1/1 sw_ack_o = '0; Tests: T1 T2 T3 197 1/1 sw_err_o = '0; Tests: T1 T2 T3 198 1/1 sw_wready_o = '0; Tests: T1 T2 T3 199 1/1 hw_ack_o = '0; Tests: T1 T2 T3 200 1/1 hw_err_o = '0; Tests: T1 T2 T3 201 202 1/1 hw_wready_o = '0; Tests: T1 T2 T3 203 1/1 prog_fifo_wvalid_o = '0; Tests: T1 T2 T3 204 1/1 prog_fifo_wdata_o = '0; Tests: T1 T2 T3 205 206 1/1 unique case (func_sel) Tests: T1 T2 T3 207 HwSel: begin 208 // ctrl related muxing 209 1/1 muxed_ctrl_o = hw_ctrl_i; Tests: T1 T2 T3 210 1/1 muxed_addr_o = hw_addr_i; Tests: T1 T2 T3 211 1/1 hw_ack_o = ctrl_ack; Tests: T1 T2 T3 212 1/1 hw_err_o = ctrl_err; Tests: T1 T2 T3 213 214 // fifo related muxing 215 1/1 hw_wready_o = prog_fifo_wready_i; Tests: T1 T2 T3 216 1/1 prog_fifo_wvalid_o = hw_wvalid_i; Tests: T1 T2 T3 217 1/1 prog_fifo_wdata_o = hw_wdata_i; Tests: T1 T2 T3 218 end 219 220 SwSel: begin 221 222 // ctrl related muxing 223 1/1 muxed_ctrl_o = sw_ctrl_i; Tests: T1 T2 T3 224 1/1 muxed_addr_o = sw_addr_i; Tests: T1 T2 T3 225 1/1 sw_ack_o = ctrl_ack; Tests: T1 T2 T3 226 1/1 sw_err_o = ctrl_err; Tests: T1 T2 T3 227 228 // fifo related muxing 229 1/1 sw_wready_o = prog_fifo_wready_i; Tests: T1 T2 T3 230 1/1 prog_fifo_wvalid_o = sw_wvalid_i; Tests: T1 T2 T3 231 1/1 prog_fifo_wdata_o = sw_wdata_i; Tests: T1 T2 T3 232 end 233 234 default:; 235 endcase // unique case (func_sel) 236 end 237 238 // pick appropriate feedback 239 always_comb begin 240 1/1 ctrl_ack = '0; Tests: T1 T2 T3 241 1/1 ctrl_err = '0; Tests: T1 T2 T3 242 1/1 ctrl_err_addr_o = '0; Tests: T1 T2 T3 243 244 1/1 unique case (muxed_ctrl_o.op.q) Tests: T1 T2 T3 245 FlashOpProgram: begin 246 1/1 ctrl_ack = prog_ack_i; Tests: T2 T10 T11 247 1/1 ctrl_err = prog_err_i; Tests: T2 T10 T11 248 1/1 ctrl_err_addr_o = prog_err_addr_i; Tests: T2 T10 T11 249 end 250 251 FlashOpErase: begin 252 1/1 ctrl_ack = erase_ack_i; Tests: T2 T10 T16 253 1/1 ctrl_err = erase_err_i; Tests: T2 T10 T16 254 1/1 ctrl_err_addr_o = erase_err_addr_i; Tests: T2 T10 T16 255 end 256 257 FlashOpRead: begin 258 1/1 ctrl_ack = rd_ack_i; Tests: T1 T2 T3 259 1/1 ctrl_err = rd_err_i; Tests: T1 T2 T3 260 1/1 ctrl_err_addr_o = rd_err_addr_i; Tests: T1 T2 T3 261 end 262 263 default: begin 264 // if operation is started but does not match 265 // any valid operation, error back 266 if (muxed_ctrl_o.start) begin 267 ctrl_ack = 1'b1; 268 ctrl_err.invalid_op_err = 1'b1; 269 end MISSING_ELSE 270 end 271 272 endcase // unique case (muxed_ctrl_o.op.q) 273 end 274 275 1/1 assign sel_o = func_sel; Tests: T1 T2 T3 276 277 // At the moment there is no software control indicating phase. 278 1/1 assign phase_o = func_sel == SwSel ? PhaseInvalid : hw_phase_i; Tests: T1 T2 T3
Cond Coverage for Module : flash_ctrl_arb
| Total | Covered | Percent | |
|---|---|---|---|
| Conditions | 8 | 8 | 100.00 |
| Logical | 8 | 8 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 |
LINE 174
EXPRESSION (prog_ack_i || rd_ack_i || erase_ack_i)
-----1---- ----2--- -----3-----
| -1- | -2- | -3- | Status | Tests |
|---|---|---|---|---|
| 0 | 0 | 0 | Covered | T2,T3,T10 |
| 0 | 0 | 1 | Covered | T2,T10,T16 |
| 0 | 1 | 0 | Covered | T2,T3,T10 |
| 1 | 0 | 0 | Covered | T2,T10,T11 |
LINE 278
EXPRESSION ((func_sel == SwSel) ? PhaseInvalid : hw_phase_i)
---------1---------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
LINE 278
SUB-EXPRESSION (func_sel == SwSel)
---------1---------
| -1- | Status | Tests |
|---|---|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T1,T2,T3 |
FSM Coverage for Module : flash_ctrl_arb
| Total | Covered | Percent | ||
|---|---|---|---|---|
| States | 5 | 5 | 100.00 | (Not included in score) |
| Transitions | 6 | 6 | 100.00 | |
| Sequences | 0 | 0 |
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| StDisabled | 158 | Covered | T4,T5,T6 |
| StHw | 139 | Covered | T1,T2,T3 |
| StReset | 133 | Covered | T1,T2,T3 |
| StSwActive | 165 | Covered | T2,T3,T10 |
| StSwIdle | 147 | Covered | T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| StHw->StSwIdle | 147 | Covered | T1,T2,T3 |
| StReset->StHw | 139 | Covered | T1,T2,T3 |
| StSwActive->StSwIdle | 175 | Covered | T2,T3,T10 |
| StSwIdle->StDisabled | 158 | Covered | T4,T5,T6 |
| StSwIdle->StHw | 163 | Covered | T1,T2,T3 |
| StSwIdle->StSwActive | 165 | Covered | T2,T3,T10 |
Branch Coverage for Module : flash_ctrl_arb
| Line No. | Total | Covered | Percent | |
|---|---|---|---|---|
| Branches | 24 | 24 | 100.00 | |
| TERNARY | 278 | 2 | 2 | 100.00 |
| IF | 123 | 2 | 2 | 100.00 |
| CASE | 132 | 12 | 12 | 100.00 |
| CASE | 206 | 3 | 3 | 100.00 |
| CASE | 244 | 5 | 5 | 100.00 |
278 assign phase_o = func_sel == SwSel ? PhaseInvalid : hw_phase_i; -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
123 `PRIM_FLOP_SPARSE_FSM(u_state_regs, state_d, state_q, arb_state_e, StReset) -1- ==> ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| 1 | Covered | T1,T2,T3 |
| 0 | Covered | T1,T2,T3 |
132 unique case (state_q) -1- 133 StReset: begin 134 // until the flash phy is done with its own initialization, 135 // no flash controller activity is allowed to commence 136 if (!flash_phy_busy_i) begin -2- 137 // after flash is ready, the HW interface always takes 138 // precedence for flash control initialization 139 state_d = StHw; ==> 140 end MISSING_ELSE ==> 141 end 142 143 StHw: begin 144 func_sel = HwSel; 145 146 if (!hw_req_i) begin -3- 147 state_d = StSwIdle; ==> 148 end MISSING_ELSE ==> 149 end 150 151 StSwIdle: begin 152 // software is still selected to enable access to Fifos 153 func_sel = SwSel; 154 155 if (prim_mubi_pkg::mubi4_test_true_loose(disable_i)) begin -4- 156 // Do not randomly switch unless idle as it may cause stateful operations to be 157 // disturbed 158 state_d = StDisabled; ==> 159 end else if (hw_req_i) begin -5- 160 // if hardware request comes in the middle, wipe fifos and enable 161 // switch to hardware interface 162 fifo_clr_o = 1'b1; ==> 163 state_d = StHw; 164 end else if (sw_req) begin -6- 165 state_d = StSwActive; ==> 166 end MISSING_ELSE ==> 167 end 168 169 StSwActive: begin 170 func_sel = SwSel; 171 172 // Stay in software active mode until operation completes. 173 // While operations are ongoing, the interface cannot be switched 174 if (prog_ack_i || rd_ack_i || erase_ack_i) begin -7- 175 state_d = StSwIdle; ==> 176 end MISSING_ELSE ==> 177 end 178 179 StDisabled: begin 180 state_d = StDisabled; ==> 181 end 182 183 default: begin 184 fsm_err_o = 1'b1; ==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | Status | Tests |
|---|---|---|---|---|---|---|---|---|
| StReset | 1 | - | - | - | - | - | Covered | T1,T2,T3 |
| StReset | 0 | - | - | - | - | - | Covered | T1,T2,T3 |
| StHw | - | 1 | - | - | - | - | Covered | T1,T2,T3 |
| StHw | - | 0 | - | - | - | - | Covered | T1,T2,T3 |
| StSwIdle | - | - | 1 | - | - | - | Covered | T4,T5,T6 |
| StSwIdle | - | - | 0 | 1 | - | - | Covered | T1,T2,T3 |
| StSwIdle | - | - | 0 | 0 | 1 | - | Covered | T2,T3,T10 |
| StSwIdle | - | - | 0 | 0 | 0 | - | Covered | T1,T2,T3 |
| StSwActive | - | - | - | - | - | 1 | Covered | T2,T3,T10 |
| StSwActive | - | - | - | - | - | 0 | Covered | T2,T3,T10 |
| StDisabled | - | - | - | - | - | - | Covered | T4,T5,T6 |
| default | - | - | - | - | - | - | Covered | T13,T14,T15 |
206 unique case (func_sel) -1- 207 HwSel: begin 208 // ctrl related muxing 209 muxed_ctrl_o = hw_ctrl_i; ==> 210 muxed_addr_o = hw_addr_i; 211 hw_ack_o = ctrl_ack; 212 hw_err_o = ctrl_err; 213 214 // fifo related muxing 215 hw_wready_o = prog_fifo_wready_i; 216 prog_fifo_wvalid_o = hw_wvalid_i; 217 prog_fifo_wdata_o = hw_wdata_i; 218 end 219 220 SwSel: begin 221 222 // ctrl related muxing 223 muxed_ctrl_o = sw_ctrl_i; ==> 224 muxed_addr_o = sw_addr_i; 225 sw_ack_o = ctrl_ack; 226 sw_err_o = ctrl_err; 227 228 // fifo related muxing 229 sw_wready_o = prog_fifo_wready_i; 230 prog_fifo_wvalid_o = sw_wvalid_i; 231 prog_fifo_wdata_o = sw_wdata_i; 232 end 233 234 default:; ==>
Branches:
| -1- | Status | Tests |
|---|---|---|
| HwSel | Covered | T1,T2,T3 |
| SwSel | Covered | T1,T2,T3 |
| default | Covered | T1,T2,T3 |
244 unique case (muxed_ctrl_o.op.q) -1- 245 FlashOpProgram: begin 246 ctrl_ack = prog_ack_i; ==> 247 ctrl_err = prog_err_i; 248 ctrl_err_addr_o = prog_err_addr_i; 249 end 250 251 FlashOpErase: begin 252 ctrl_ack = erase_ack_i; ==> 253 ctrl_err = erase_err_i; 254 ctrl_err_addr_o = erase_err_addr_i; 255 end 256 257 FlashOpRead: begin 258 ctrl_ack = rd_ack_i; ==> 259 ctrl_err = rd_err_i; 260 ctrl_err_addr_o = rd_err_addr_i; 261 end 262 263 default: begin 264 // if operation is started but does not match 265 // any valid operation, error back 266 if (muxed_ctrl_o.start) begin -2- 267 ctrl_ack = 1'b1; ==> 268 ctrl_err.invalid_op_err = 1'b1; 269 end MISSING_ELSE ==>
Branches:
| -1- | -2- | Status | Tests |
|---|---|---|---|
| FlashOpProgram | - | Covered | T2,T10,T11 |
| FlashOpErase | - | Covered | T2,T10,T16 |
| FlashOpRead | - | Covered | T1,T2,T3 |
| default | 1 | Covered | T18,T123,T144 |
| default | 0 | Covered | T1,T2,T3 |
Assert Coverage for Module : flash_ctrl_arb
| Total | Attempted | Percent | Succeeded/Matched | Percent | |
|---|---|---|---|---|---|
| Assertions | 1 | 1 | 100.00 | 1 | 100.00 |
| Cover properties | 0 | 0 | 0 | ||
| Cover sequences | 0 | 0 | 0 | ||
| Total | 1 | 1 | 100.00 | 1 | 100.00 |
Assertion Details
| Name | Attempts | Real Successes | Failures | Incomplete |
| u_state_regs_A | 394250905 | 393379119 | 0 | 0 |
u_state_regs_A
| Name | Attempts | Real Successes | Failures | Incomplete |
|---|---|---|---|---|
| Total | 394250905 | 393379119 | 0 | 0 |
| T1 | 1194 | 1105 | 0 | 0 |
| T2 | 2508 | 2452 | 0 | 0 |
| T3 | 14578 | 14508 | 0 | 0 |
| T4 | 3493 | 2763 | 0 | 0 |
| T10 | 333723 | 321459 | 0 | 0 |
| T11 | 6395 | 6340 | 0 | 0 |
| T16 | 72468 | 72381 | 0 | 0 |
| T17 | 1512 | 1454 | 0 | 0 |
| T18 | 87009 | 86948 | 0 | 0 |
| T19 | 64646 | 64481 | 0 | 0 |