Design subhierarchy
dashboard | hierarchy | modlist | groups | tests | asserts

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NAME   SCORE   LINE   COND   TOGGLE   FSM   BRANCH   ASSERT   
flash_ctrl_core_csr_assert 100.00 100.00
gen_alert_senders[0].u_alert_sender 100.00 100.00
gen_alert_senders[1].u_alert_sender 100.00 100.00
gen_alert_senders[2].u_alert_sender 100.00 100.00
gen_alert_senders[3].u_alert_sender 100.00 100.00
gen_alert_senders[4].u_alert_sender 77.78 77.78
tlul_assert_device 98.95 98.95
 u_ctrl_arb 100.00 100.00 100.00 100.00 100.00 100.00
 u_disable_buf 100.00 100.00 100.00
 u_eflash 97.12 97.63 93.23 99.49 97.62 97.66 97.08
 u_exec_en_buf 100.00 100.00
u_flash_ctrl_erase 100.00 100.00 100.00 100.00
 u_flash_ctrl_prog 97.88 100.00 97.06 100.00 94.44
 u_flash_ctrl_rd 93.49 83.02 93.94 100.00 100.00 90.48
 u_flash_hw_if 95.88 98.53 93.52 95.83 92.11 95.27 100.00
 u_flash_mp 99.54 100.00 98.16 100.00 100.00
u_intr_corr_err 93.75 100.00 75.00 100.00 100.00
u_intr_op_done 93.75 100.00 75.00 100.00 100.00
u_intr_prog_empty 86.94 90.00 77.78 80.00 100.00
u_intr_prog_lvl 86.94 90.00 77.78 80.00 100.00
u_intr_rd_full 86.94 90.00 77.78 80.00 100.00
u_intr_rd_lvl 86.94 90.00 77.78 80.00 100.00
 u_lc_escalation_en_sync 100.00 100.00 100.00 100.00
 u_lc_seed_hw_rd_en_sync 100.00 100.00 100.00 100.00
u_lfsr 100.00 100.00
 u_prog_fifo 97.73 100.00 90.91 100.00 100.00
 u_prog_tl_gate 81.91 95.28 82.14 57.14 87.50 87.50
 u_reg_core 99.29 99.00 98.57 100.00 98.88 100.00
 u_reg_idle 100.00 100.00 100.00
 u_region_cfg 87.91 63.73 100.00 100.00
 u_sw_rd_fifo 93.67 95.12 88.64 90.91 100.00
 u_tl_adapter_eflash 91.46 89.72 80.25 97.66 89.66 100.00
 u_tl_gate 82.00 95.28 85.71 57.14 84.38 87.50
 u_to_prog_fifo 74.37 82.76 64.43 67.44 82.86
 u_to_rd_fifo 84.73 86.41 74.65 80.00 82.61 100.00