Line Coverage for Module :
flash_ctrl_rd
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 44 | 44 | 100.00 |
| ALWAYS | 52 | 3 | 3 | 100.00 |
| ALWAYS | 60 | 5 | 5 | 100.00 |
| ALWAYS | 97 | 4 | 4 | 100.00 |
| CONT_ASSIGN | 104 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 105 | 1 | 1 | 100.00 |
| ALWAYS | 113 | 24 | 24 | 100.00 |
| CONT_ASSIGN | 163 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 164 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 165 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 167 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 180 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 182 | 1 | 1 | 100.00 |
51 always_ff @(posedge clk_i or negedge rst_ni) begin
52 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
53 1/1 st_q <= StIdle;
Tests: T1 T2 T3
54 end else begin
55 1/1 st_q <= st_d;
Tests: T1 T2 T3
56 end
57 end
58
59 always_ff @(posedge clk_i or negedge rst_ni) begin
60 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
61 1/1 op_err_q <= '0;
Tests: T1 T2 T3
62 1/1 end else if (op_start_i && op_done_o) begin
Tests: T1 T2 T3
63 1/1 op_err_q <= '0;
Tests: T1 T2 T3
64 end else begin
65 1/1 op_err_q <= op_err_d;
Tests: T1 T2 T3
66 end
67 end
68
69 prim_count #(
70 .Width(12)
71 ) u_cnt (
72 .clk_i,
73 .rst_ni,
74 .clr_i(op_start_i && op_done_o),
75 .set_i('0),
76 .set_cnt_i('0),
77 .incr_en_i(data_wr_o),
78 .decr_en_i(1'b0),
79 .step_i(12'h1),
80 .commit_i(1'b1),
81 .cnt_o(cnt),
82 .cnt_after_commit_o(),
83 .err_o(cnt_err_o)
84 );
85
86 //always_ff @(posedge clk_i or negedge rst_ni) begin
87 // if (!rst_ni) begin
88 // cnt <= '0;
89 // end else if (op_start_i && op_done_o) begin
90 // cnt <= '0;
91 // end else if (data_wr_o) begin
92 // cnt <= cnt + 1'b1;
93 // end
94 //end
95
96 always_ff @(posedge clk_i or negedge rst_ni) begin
97 1/1 if (!rst_ni) begin
Tests: T1 T2 T3
98 1/1 op_err_addr_o <= '0;
Tests: T1 T2 T3
99 1/1 end else if (~|op_err_q && |op_err_d) begin
Tests: T1 T2 T3
100 1/1 op_err_addr_o <= flash_addr_o;
Tests: T12 T45 T46
101 end
MISSING_ELSE
102 end
103
104 1/1 assign txn_done = flash_req_o & flash_done_i;
Tests: T1 T2 T3
105 1/1 assign cnt_hit = (cnt >= op_num_words_i);
Tests: T1 T2 T3
106
107
108 // when error'd, continue to complete existing read transaction but fill in with all 1's
109 // if this is not done, software may continue to attempt to read out of the fifo
110 // and eventually cause a bus deadlock as the fifo would be empty
111 // This scheme is similar to burst completion up an error
112 always_comb begin
113 1/1 st_d = st_q;
Tests: T1 T2 T3
114 1/1 flash_req_o = 1'b0;
Tests: T1 T2 T3
115 1/1 data_wr_o = 1'b0;
Tests: T1 T2 T3
116 1/1 op_done_o = 1'b0;
Tests: T1 T2 T3
117 1/1 op_err_d = op_err_q;
Tests: T1 T2 T3
118
119 1/1 unique case (st_q)
Tests: T1 T2 T3
120 StIdle: begin
121 1/1 if (cnt_err_o) begin
Tests: T1 T2 T3
122 // if counter error is encountered, just go to error state
123 1/1 st_d = StErr;
Tests: T13 T14 T15
124 1/1 end else if (op_start_i) begin
Tests: T1 T2 T3
125 1/1 op_err_d.oob_err = op_addr_oob_i;
Tests: T1 T2 T3
126 1/1 st_d = |op_err_d ? StErr : StNorm;
Tests: T1 T2 T3
127 end
MISSING_ELSE
128 end
129
130 // Note the address counter is incremented on tx_done
131 // and cleared when the entire operation is complete.
132 StNorm: begin
133 1/1 flash_req_o = op_start_i & data_rdy_i;
Tests: T1 T2 T3
134
135 1/1 if (txn_done) begin
Tests: T1 T2 T3
136 1/1 op_err_d.mp_err = flash_mp_err_i;
Tests: T1 T2 T3
137 1/1 op_err_d.rd_err = flash_rd_err_i;
Tests: T1 T2 T3
138
139 1/1 data_wr_o = 1'b1;
Tests: T1 T2 T3
140
141 1/1 if (cnt_hit) begin
Tests: T1 T2 T3
142 1/1 op_done_o = 1'b1;
Tests: T1 T2 T3
143 1/1 st_d = StIdle;
Tests: T1 T2 T3
144 end else begin
145 1/1 st_d = |op_err_d ? StErr : StNorm;
Tests: T1 T2 T3
146 end
147 end
MISSING_ELSE
148 end
149
150 StErr: begin
151 1/1 data_wr_o = data_rdy_i;
Tests: T12 T45 T46
152
153 1/1 if (data_rdy_i && cnt_hit) begin
Tests: T12 T45 T46
154 1/1 st_d = StIdle;
Tests: T12 T45 T46
155 1/1 op_done_o = 1'b1;
Tests: T12 T45 T46
156 end
MISSING_ELSE
157 end
158 default:;
159 endcase // unique case (st)
160 end
161
162 // overflow error detection is not here, but instead handled at memory protection
163 1/1 assign int_addr = op_addr_i + BusAddrW'(cnt);
Tests: T1 T2 T3
164 1/1 assign flash_addr_o = int_addr[0 +: BusAddrW];
Tests: T1 T2 T3
165 1/1 assign flash_ovfl_o = int_addr[BusAddrW];
Tests: T1 T2 T3
166 // if error, return "empty" data
167 1/1 assign err_sel = data_wr_o & |op_err_o;
Tests: T1 T2 T3
168
169 // When there is no error, return flash data directly.
170 // When the error is a read error specifically, also return flash data as the integrity is
171 // natively handled by the phy.
172 // All other errors do not result in an actual transaction to the flash, and therefore must use
173 // the locally available error value.
174 logic [BusFullWidth-1:0] inv_data_integ;
175 tlul_data_integ_enc u_bus_intg (
176 .data_i({BusWidth{1'b1}}),
177 .data_intg_o(inv_data_integ)
178 );
179
180 1/1 assign data_o = ~err_sel | (err_sel & op_err_o.rd_err) ? flash_data_i : inv_data_integ;
Tests: T1 T2 T3
181
182 1/1 assign op_err_o = op_err_q | op_err_d;
Tests: T1 T2 T3
Cond Coverage for Module :
flash_ctrl_rd
| Total | Covered | Percent |
|---|
| Conditions | 33 | 31 | 93.94 |
| Logical | 33 | 31 | 93.94 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 62
EXPRESSION (op_start_i && op_done_o)
-----1---- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T13,T14,T15 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 71
EXPRESSION (op_start_i && op_done_o)
-----1---- ----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T13,T14,T15 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 99
EXPRESSION (((~|op_err_q)) && ((|op_err_d)))
-------1------ ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T12,T45,T46 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T12,T45,T46 |
LINE 104
EXPRESSION (flash_req_o & flash_done_i)
-----1----- ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T67,T45 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 126
EXPRESSION (((|op_err_d)) ? StErr : StNorm)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Not Covered | |
LINE 133
EXPRESSION (op_start_i & data_rdy_i)
-----1---- -----2----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T133,T123 |
| 1 | 0 | Covered | T162,T163,T164 |
| 1 | 1 | Covered | T1,T2,T3 |
LINE 145
EXPRESSION (((|op_err_d)) ? StErr : StNorm)
------1------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T2,T3 |
| 1 | Covered | T12,T45,T46 |
LINE 153
EXPRESSION (data_rdy_i && cnt_hit)
-----1---- ---2---
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T40,T165,T162 |
| 1 | 0 | Covered | T12,T45,T46 |
| 1 | 1 | Covered | T12,T45,T46 |
LINE 167
EXPRESSION (data_wr_o & ((|op_err_o)))
----1---- ------2------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T40,T165,T162 |
| 1 | 0 | Covered | T1,T2,T3 |
| 1 | 1 | Covered | T12,T45,T46 |
LINE 180
EXPRESSION ((((~err_sel)) | (err_sel & op_err_o.rd_err)) ? flash_data_i : inv_data_integ)
----------------------1---------------------
| -1- | Status | Tests |
|---|
| 0 | Covered | T12,T45,T46 |
| 1 | Covered | T1,T2,T3 |
LINE 180
SUB-EXPRESSION (((~err_sel)) | (err_sel & op_err_o.rd_err))
------1----- -------------2-------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T12,T45,T46 |
| 0 | 1 | Covered | T53,T54,T33 |
| 1 | 0 | Covered | T1,T2,T3 |
LINE 180
SUB-EXPRESSION (err_sel & op_err_o.rd_err)
---1--- -------2-------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Not Covered | |
| 1 | 0 | Covered | T12,T45,T46 |
| 1 | 1 | Covered | T53,T54,T33 |
FSM Coverage for Module :
flash_ctrl_rd
Summary for FSM :: st_q
| Total | Covered | Percent | |
| States |
3 |
3 |
100.00 |
(Not included in score) |
| Transitions |
5 |
5 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: st_q
| states | Line No. | Covered | Tests |
| StErr |
123 |
Covered |
T12,T45,T46 |
| StIdle |
143 |
Covered |
T1,T2,T3 |
| StNorm |
126 |
Covered |
T1,T2,T3 |
| transitions | Line No. | Covered | Tests |
| StErr->StIdle |
154 |
Covered |
T12,T45,T46 |
| StIdle->StErr |
123 |
Covered |
T13,T14,T15 |
| StIdle->StNorm |
126 |
Covered |
T1,T2,T3 |
| StNorm->StErr |
145 |
Covered |
T12,T45,T46 |
| StNorm->StIdle |
143 |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
flash_ctrl_rd
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
19 |
90.48 |
| TERNARY |
180 |
2 |
2 |
100.00 |
| IF |
52 |
2 |
2 |
100.00 |
| IF |
60 |
3 |
3 |
100.00 |
| IF |
97 |
3 |
3 |
100.00 |
| CASE |
119 |
11 |
9 |
81.82 |
180 assign data_o = ~err_sel | (err_sel & op_err_o.rd_err) ? flash_data_i : inv_data_integ;
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T12,T45,T46 |
52 if (!rst_ni) begin
-1-
53 st_q <= StIdle;
==>
54 end else begin
55 st_q <= st_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T3 |
| 0 |
Covered |
T1,T2,T3 |
60 if (!rst_ni) begin
-1-
61 op_err_q <= '0;
==>
62 end else if (op_start_i && op_done_o) begin
-2-
63 op_err_q <= '0;
==>
64 end else begin
65 op_err_q <= op_err_d;
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T1,T2,T3 |
| 0 |
0 |
Covered |
T1,T2,T3 |
97 if (!rst_ni) begin
-1-
98 op_err_addr_o <= '0;
==>
99 end else if (~|op_err_q && |op_err_d) begin
-2-
100 op_err_addr_o <= flash_addr_o;
==>
101 end
MISSING_ELSE
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T3 |
| 0 |
1 |
Covered |
T12,T45,T46 |
| 0 |
0 |
Covered |
T1,T2,T3 |
119 unique case (st_q)
-1-
120 StIdle: begin
121 if (cnt_err_o) begin
-2-
122 // if counter error is encountered, just go to error state
123 st_d = StErr;
==>
124 end else if (op_start_i) begin
-3-
125 op_err_d.oob_err = op_addr_oob_i;
126 st_d = |op_err_d ? StErr : StNorm;
-4-
==>
==>
127 end
MISSING_ELSE
==>
128 end
129
130 // Note the address counter is incremented on tx_done
131 // and cleared when the entire operation is complete.
132 StNorm: begin
133 flash_req_o = op_start_i & data_rdy_i;
134
135 if (txn_done) begin
-5-
136 op_err_d.mp_err = flash_mp_err_i;
137 op_err_d.rd_err = flash_rd_err_i;
138
139 data_wr_o = 1'b1;
140
141 if (cnt_hit) begin
-6-
142 op_done_o = 1'b1;
==>
143 st_d = StIdle;
144 end else begin
145 st_d = |op_err_d ? StErr : StNorm;
-7-
==>
==>
146 end
147 end
MISSING_ELSE
==>
148 end
149
150 StErr: begin
151 data_wr_o = data_rdy_i;
152
153 if (data_rdy_i && cnt_hit) begin
-8-
154 st_d = StIdle;
==>
155 op_done_o = 1'b1;
156 end
MISSING_ELSE
==>
157 end
158 default:;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| StIdle |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T13,T14,T15 |
| StIdle |
0 |
1 |
1 |
- |
- |
- |
- |
Not Covered |
|
| StIdle |
0 |
1 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StIdle |
0 |
0 |
- |
- |
- |
- |
- |
Covered |
T1,T2,T3 |
| StNorm |
- |
- |
- |
1 |
1 |
- |
- |
Covered |
T1,T2,T3 |
| StNorm |
- |
- |
- |
1 |
0 |
1 |
- |
Covered |
T12,T45,T46 |
| StNorm |
- |
- |
- |
1 |
0 |
0 |
- |
Covered |
T1,T2,T3 |
| StNorm |
- |
- |
- |
0 |
- |
- |
- |
Covered |
T1,T2,T3 |
| StErr |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T12,T45,T46 |
| StErr |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T12,T45,T46 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|