| T1088 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.824756865 |
|
|
Oct 12 01:18:56 PM UTC 24 |
Oct 12 01:23:11 PM UTC 24 |
70066900 ps |
| T1089 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.1507310232 |
|
|
Oct 12 01:22:49 PM UTC 24 |
Oct 12 01:23:16 PM UTC 24 |
14739700 ps |
| T1090 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.1919949496 |
|
|
Oct 12 01:19:27 PM UTC 24 |
Oct 12 01:23:16 PM UTC 24 |
39254100 ps |
| T1091 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1384583132 |
|
|
Oct 12 01:20:13 PM UTC 24 |
Oct 12 01:23:23 PM UTC 24 |
73671000 ps |
| T1092 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.1832965816 |
|
|
Oct 12 01:20:23 PM UTC 24 |
Oct 12 01:23:27 PM UTC 24 |
61166200 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.734334931 |
|
|
Oct 12 01:20:54 PM UTC 24 |
Oct 12 01:23:30 PM UTC 24 |
427496900 ps |
| T1093 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.2171351901 |
|
|
Oct 12 01:20:49 PM UTC 24 |
Oct 12 01:23:31 PM UTC 24 |
22398800 ps |
| T1094 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.3407769786 |
|
|
Oct 12 01:20:20 PM UTC 24 |
Oct 12 01:23:35 PM UTC 24 |
58638700 ps |
| T1095 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.437290705 |
|
|
Oct 12 01:20:01 PM UTC 24 |
Oct 12 01:23:44 PM UTC 24 |
7608660000 ps |
| T1096 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.3295886798 |
|
|
Oct 12 01:19:24 PM UTC 24 |
Oct 12 01:23:46 PM UTC 24 |
108988700 ps |
| T1097 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.2663267967 |
|
|
Oct 12 01:19:25 PM UTC 24 |
Oct 12 01:23:46 PM UTC 24 |
21566039500 ps |
| T1098 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.242640432 |
|
|
Oct 12 01:20:42 PM UTC 24 |
Oct 12 01:23:57 PM UTC 24 |
39516400 ps |
| T1099 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3568686588 |
|
|
Oct 12 01:21:27 PM UTC 24 |
Oct 12 01:24:01 PM UTC 24 |
34693400 ps |
| T1100 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.2077992935 |
|
|
Oct 12 01:21:06 PM UTC 24 |
Oct 12 01:24:07 PM UTC 24 |
41665200 ps |
| T1101 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.3220936972 |
|
|
Oct 12 01:19:47 PM UTC 24 |
Oct 12 01:24:08 PM UTC 24 |
698047300 ps |
| T1102 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.2631902058 |
|
|
Oct 12 01:21:09 PM UTC 24 |
Oct 12 01:24:10 PM UTC 24 |
77585500 ps |
| T1103 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.2409320559 |
|
|
Oct 12 01:21:47 PM UTC 24 |
Oct 12 01:24:13 PM UTC 24 |
120038700 ps |
| T1104 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3167144262 |
|
|
Oct 12 01:21:39 PM UTC 24 |
Oct 12 01:24:17 PM UTC 24 |
143128300 ps |
| T1105 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3664758377 |
|
|
Oct 12 01:21:12 PM UTC 24 |
Oct 12 01:24:19 PM UTC 24 |
81176100 ps |
| T1106 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.396028111 |
|
|
Oct 12 01:21:51 PM UTC 24 |
Oct 12 01:24:21 PM UTC 24 |
282208600 ps |
| T1107 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1333937254 |
|
|
Oct 12 01:21:56 PM UTC 24 |
Oct 12 01:24:22 PM UTC 24 |
43753500 ps |
| T1108 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.2912117711 |
|
|
Oct 12 01:21:35 PM UTC 24 |
Oct 12 01:24:25 PM UTC 24 |
37466800 ps |
| T1109 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.904916255 |
|
|
Oct 12 01:21:23 PM UTC 24 |
Oct 12 01:24:28 PM UTC 24 |
59170900 ps |
| T1110 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2960488160 |
|
|
Oct 12 01:21:55 PM UTC 24 |
Oct 12 01:24:31 PM UTC 24 |
72581000 ps |
| T1111 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.2882119404 |
|
|
Oct 12 01:21:12 PM UTC 24 |
Oct 12 01:24:33 PM UTC 24 |
40648900 ps |
| T1112 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.3975827233 |
|
|
Oct 12 01:21:59 PM UTC 24 |
Oct 12 01:24:45 PM UTC 24 |
627396600 ps |
| T1113 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.3189904421 |
|
|
Oct 12 01:21:26 PM UTC 24 |
Oct 12 01:24:52 PM UTC 24 |
46234100 ps |
| T1114 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.188648639 |
|
|
Oct 12 01:21:42 PM UTC 24 |
Oct 12 01:24:54 PM UTC 24 |
33615300 ps |
| T86 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.3082132142 |
|
|
Oct 12 01:22:32 PM UTC 24 |
Oct 12 01:24:59 PM UTC 24 |
38445300 ps |
| T1115 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.2997391144 |
|
|
Oct 12 01:22:10 PM UTC 24 |
Oct 12 01:25:02 PM UTC 24 |
75457700 ps |
| T1116 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3291084366 |
|
|
Oct 12 01:22:04 PM UTC 24 |
Oct 12 01:25:03 PM UTC 24 |
37420100 ps |
| T1117 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.1301706105 |
|
|
Oct 12 12:36:42 PM UTC 24 |
Oct 12 01:25:09 PM UTC 24 |
37200311000 ps |
| T1118 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.3292792653 |
|
|
Oct 12 12:28:43 PM UTC 24 |
Oct 12 01:25:14 PM UTC 24 |
43144155800 ps |
| T1119 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.1798860354 |
|
|
Oct 12 12:19:22 PM UTC 24 |
Oct 12 01:25:18 PM UTC 24 |
135976874100 ps |
| T1120 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1519230442 |
|
|
Oct 12 01:22:14 PM UTC 24 |
Oct 12 01:25:22 PM UTC 24 |
81337000 ps |
| T1121 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.2483622100 |
|
|
Oct 12 01:22:25 PM UTC 24 |
Oct 12 01:25:27 PM UTC 24 |
144941700 ps |
| T1122 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.340519872 |
|
|
Oct 12 01:22:20 PM UTC 24 |
Oct 12 01:25:28 PM UTC 24 |
73158200 ps |
| T1123 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.3534881687 |
|
|
Oct 12 01:22:26 PM UTC 24 |
Oct 12 01:25:29 PM UTC 24 |
71207600 ps |
| T1124 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.2938263710 |
|
|
Oct 12 01:22:07 PM UTC 24 |
Oct 12 01:25:31 PM UTC 24 |
162062100 ps |
| T1125 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3103345404 |
|
|
Oct 12 01:22:29 PM UTC 24 |
Oct 12 01:25:32 PM UTC 24 |
36732800 ps |
| T1126 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.2880697270 |
|
|
Oct 12 01:22:18 PM UTC 24 |
Oct 12 01:25:32 PM UTC 24 |
259139200 ps |
| T1127 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3368693265 |
|
|
Oct 12 01:22:21 PM UTC 24 |
Oct 12 01:25:34 PM UTC 24 |
163236400 ps |
| T1128 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3582064285 |
|
|
Oct 12 01:22:38 PM UTC 24 |
Oct 12 01:25:35 PM UTC 24 |
60709900 ps |
| T1129 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.3922977577 |
|
|
Oct 12 01:22:41 PM UTC 24 |
Oct 12 01:25:44 PM UTC 24 |
150393500 ps |
| T1130 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1526775487 |
|
|
Oct 12 01:22:47 PM UTC 24 |
Oct 12 01:25:50 PM UTC 24 |
146017100 ps |
| T1131 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.4216390314 |
|
|
Oct 12 01:22:45 PM UTC 24 |
Oct 12 01:25:53 PM UTC 24 |
71855200 ps |
| T1132 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3882805939 |
|
|
Oct 12 12:40:01 PM UTC 24 |
Oct 12 01:29:30 PM UTC 24 |
21476134400 ps |
| T1133 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3995742028 |
|
|
Oct 12 12:43:28 PM UTC 24 |
Oct 12 01:35:18 PM UTC 24 |
5146153100 ps |
| T15 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.466297153 |
|
|
Oct 12 12:10:11 PM UTC 24 |
Oct 12 01:55:26 PM UTC 24 |
28579998500 ps |
| T16 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.1904750030 |
|
|
Oct 12 12:04:40 PM UTC 24 |
Oct 12 02:00:40 PM UTC 24 |
3104279100 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3928944420 |
|
|
Oct 12 12:17:21 PM UTC 24 |
Oct 12 02:10:40 PM UTC 24 |
2062068600 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.1234670685 |
|
|
Oct 12 12:21:59 PM UTC 24 |
Oct 12 02:12:50 PM UTC 24 |
4115816300 ps |
| T1134 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2682389260 |
|
|
Oct 12 11:26:16 AM UTC 24 |
Oct 12 11:26:38 AM UTC 24 |
13024900 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2158378519 |
|
|
Oct 12 11:26:18 AM UTC 24 |
Oct 12 11:26:40 AM UTC 24 |
15667600 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2931252981 |
|
|
Oct 12 11:26:18 AM UTC 24 |
Oct 12 11:26:40 AM UTC 24 |
26798600 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3039814333 |
|
|
Oct 12 11:26:15 AM UTC 24 |
Oct 12 11:26:41 AM UTC 24 |
70570800 ps |
| T1135 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2674321097 |
|
|
Oct 12 11:26:18 AM UTC 24 |
Oct 12 11:26:42 AM UTC 24 |
18757200 ps |
| T1136 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.397660658 |
|
|
Oct 12 11:26:17 AM UTC 24 |
Oct 12 11:26:42 AM UTC 24 |
41605200 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1575420444 |
|
|
Oct 12 11:26:19 AM UTC 24 |
Oct 12 11:26:48 AM UTC 24 |
64870200 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2848346724 |
|
|
Oct 12 11:26:21 AM UTC 24 |
Oct 12 11:26:49 AM UTC 24 |
33772000 ps |
| T1137 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2645096282 |
|
|
Oct 12 11:26:24 AM UTC 24 |
Oct 12 11:26:49 AM UTC 24 |
38914400 ps |
| T76 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1867711590 |
|
|
Oct 12 11:26:22 AM UTC 24 |
Oct 12 11:26:51 AM UTC 24 |
72076400 ps |
| T1138 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.847565411 |
|
|
Oct 12 11:26:24 AM UTC 24 |
Oct 12 11:26:51 AM UTC 24 |
12292300 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.948704303 |
|
|
Oct 12 11:26:26 AM UTC 24 |
Oct 12 11:26:53 AM UTC 24 |
17780700 ps |
| T1139 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.222383887 |
|
|
Oct 12 11:26:30 AM UTC 24 |
Oct 12 11:26:53 AM UTC 24 |
41870000 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1465333626 |
|
|
Oct 12 11:26:32 AM UTC 24 |
Oct 12 11:26:54 AM UTC 24 |
42930900 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2770216460 |
|
|
Oct 12 11:26:24 AM UTC 24 |
Oct 12 11:26:55 AM UTC 24 |
69821500 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2325223777 |
|
|
Oct 12 11:26:39 AM UTC 24 |
Oct 12 11:27:02 AM UTC 24 |
93470700 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.733182907 |
|
|
Oct 12 11:26:20 AM UTC 24 |
Oct 12 11:27:03 AM UTC 24 |
296666600 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1680651810 |
|
|
Oct 12 11:26:43 AM UTC 24 |
Oct 12 11:27:12 AM UTC 24 |
39050700 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2802563560 |
|
|
Oct 12 11:26:50 AM UTC 24 |
Oct 12 11:27:12 AM UTC 24 |
24210600 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3085294202 |
|
|
Oct 12 11:26:43 AM UTC 24 |
Oct 12 11:27:13 AM UTC 24 |
217631900 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2243523255 |
|
|
Oct 12 11:26:52 AM UTC 24 |
Oct 12 11:27:13 AM UTC 24 |
16759900 ps |
| T1140 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2591890016 |
|
|
Oct 12 11:26:48 AM UTC 24 |
Oct 12 11:27:14 AM UTC 24 |
21501500 ps |
| T1141 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1882820127 |
|
|
Oct 12 11:26:49 AM UTC 24 |
Oct 12 11:27:14 AM UTC 24 |
13315700 ps |
| T1142 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4267064659 |
|
|
Oct 12 11:26:52 AM UTC 24 |
Oct 12 11:27:18 AM UTC 24 |
15506000 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2551755857 |
|
|
Oct 12 11:26:20 AM UTC 24 |
Oct 12 11:27:22 AM UTC 24 |
1146188500 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2725622700 |
|
|
Oct 12 11:26:54 AM UTC 24 |
Oct 12 11:27:22 AM UTC 24 |
113979600 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3098328957 |
|
|
Oct 12 11:26:56 AM UTC 24 |
Oct 12 11:27:26 AM UTC 24 |
32641500 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2728891617 |
|
|
Oct 12 11:26:56 AM UTC 24 |
Oct 12 11:27:26 AM UTC 24 |
63413300 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2366091704 |
|
|
Oct 12 11:26:57 AM UTC 24 |
Oct 12 11:27:26 AM UTC 24 |
73371300 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.224119922 |
|
|
Oct 12 11:26:41 AM UTC 24 |
Oct 12 11:27:27 AM UTC 24 |
494373200 ps |
| T1143 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1365298588 |
|
|
Oct 12 11:27:05 AM UTC 24 |
Oct 12 11:27:28 AM UTC 24 |
13020800 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3886916234 |
|
|
Oct 12 11:26:42 AM UTC 24 |
Oct 12 11:27:29 AM UTC 24 |
154330900 ps |
| T1144 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1606490817 |
|
|
Oct 12 11:27:04 AM UTC 24 |
Oct 12 11:27:30 AM UTC 24 |
29562200 ps |
| T327 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.3281933449 |
|
|
Oct 12 11:27:09 AM UTC 24 |
Oct 12 11:27:31 AM UTC 24 |
15931100 ps |
| T1145 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1819510775 |
|
|
Oct 12 11:27:10 AM UTC 24 |
Oct 12 11:27:31 AM UTC 24 |
45189600 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1776030545 |
|
|
Oct 12 11:26:19 AM UTC 24 |
Oct 12 11:27:31 AM UTC 24 |
71228500 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3812417881 |
|
|
Oct 12 11:27:13 AM UTC 24 |
Oct 12 11:27:39 AM UTC 24 |
18135100 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2278681804 |
|
|
Oct 12 11:26:55 AM UTC 24 |
Oct 12 11:27:41 AM UTC 24 |
878139700 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1506385769 |
|
|
Oct 12 11:27:14 AM UTC 24 |
Oct 12 11:27:41 AM UTC 24 |
96788400 ps |
| T1146 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.695280842 |
|
|
Oct 12 11:26:54 AM UTC 24 |
Oct 12 11:27:45 AM UTC 24 |
262996100 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1911324195 |
|
|
Oct 12 11:27:18 AM UTC 24 |
Oct 12 11:27:45 AM UTC 24 |
355183500 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2675869490 |
|
|
Oct 12 11:27:27 AM UTC 24 |
Oct 12 11:27:50 AM UTC 24 |
42264900 ps |
| T1147 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3343819289 |
|
|
Oct 12 11:27:26 AM UTC 24 |
Oct 12 11:27:51 AM UTC 24 |
14954400 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.417720434 |
|
|
Oct 12 11:27:29 AM UTC 24 |
Oct 12 11:27:51 AM UTC 24 |
231009800 ps |
| T1148 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1999083800 |
|
|
Oct 12 11:27:28 AM UTC 24 |
Oct 12 11:27:51 AM UTC 24 |
41217900 ps |
| T1149 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1005720301 |
|
|
Oct 12 11:27:26 AM UTC 24 |
Oct 12 11:27:52 AM UTC 24 |
37860500 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2976891903 |
|
|
Oct 12 11:27:30 AM UTC 24 |
Oct 12 11:27:52 AM UTC 24 |
22850400 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.498269458 |
|
|
Oct 12 11:27:22 AM UTC 24 |
Oct 12 11:27:53 AM UTC 24 |
109051800 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3639257085 |
|
|
Oct 12 11:27:32 AM UTC 24 |
Oct 12 11:28:19 AM UTC 24 |
652549100 ps |
| T1150 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.242764699 |
|
|
Oct 12 11:26:38 AM UTC 24 |
Oct 12 11:27:54 AM UTC 24 |
37675000 ps |
| T1151 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1243901291 |
|
|
Oct 12 11:27:32 AM UTC 24 |
Oct 12 11:27:59 AM UTC 24 |
115632800 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.413193609 |
|
|
Oct 12 11:27:32 AM UTC 24 |
Oct 12 11:27:59 AM UTC 24 |
166169900 ps |
| T1152 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1935378068 |
|
|
Oct 12 11:27:13 AM UTC 24 |
Oct 12 11:28:02 AM UTC 24 |
20610300 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.243435887 |
|
|
Oct 12 11:27:40 AM UTC 24 |
Oct 12 11:28:07 AM UTC 24 |
90781900 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2450030500 |
|
|
Oct 12 11:26:55 AM UTC 24 |
Oct 12 11:28:07 AM UTC 24 |
3017780900 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.2357561220 |
|
|
Oct 12 11:27:46 AM UTC 24 |
Oct 12 11:28:08 AM UTC 24 |
17185000 ps |
| T1153 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3115249575 |
|
|
Oct 12 11:27:42 AM UTC 24 |
Oct 12 11:28:08 AM UTC 24 |
12184400 ps |
| T1154 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1039390675 |
|
|
Oct 12 11:27:15 AM UTC 24 |
Oct 12 11:28:11 AM UTC 24 |
761920300 ps |
| T364 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2847327892 |
|
|
Oct 12 11:27:14 AM UTC 24 |
Oct 12 11:28:11 AM UTC 24 |
1148667400 ps |
| T1155 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1680995314 |
|
|
Oct 12 11:27:45 AM UTC 24 |
Oct 12 11:28:11 AM UTC 24 |
24413200 ps |
| T1156 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2800853535 |
|
|
Oct 12 11:27:54 AM UTC 24 |
Oct 12 11:28:15 AM UTC 24 |
13380400 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.2741199084 |
|
|
Oct 12 11:27:55 AM UTC 24 |
Oct 12 11:28:17 AM UTC 24 |
70883400 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3976431271 |
|
|
Oct 12 11:27:50 AM UTC 24 |
Oct 12 11:28:18 AM UTC 24 |
66524800 ps |
| T1157 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.957752325 |
|
|
Oct 12 11:27:54 AM UTC 24 |
Oct 12 11:28:19 AM UTC 24 |
28359200 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1059883746 |
|
|
Oct 12 11:27:52 AM UTC 24 |
Oct 12 11:28:19 AM UTC 24 |
54073900 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1056231216 |
|
|
Oct 12 11:27:55 AM UTC 24 |
Oct 12 11:28:21 AM UTC 24 |
85845000 ps |
| T1158 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1438058162 |
|
|
Oct 12 11:27:51 AM UTC 24 |
Oct 12 11:28:23 AM UTC 24 |
165615900 ps |
| T1159 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1920203578 |
|
|
Oct 12 11:28:00 AM UTC 24 |
Oct 12 11:28:24 AM UTC 24 |
121716700 ps |
| T1160 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3155462183 |
|
|
Oct 12 11:27:52 AM UTC 24 |
Oct 12 11:28:26 AM UTC 24 |
75108500 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.718014619 |
|
|
Oct 12 11:28:00 AM UTC 24 |
Oct 12 11:28:27 AM UTC 24 |
66952800 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.291905378 |
|
|
Oct 12 11:28:03 AM UTC 24 |
Oct 12 11:28:28 AM UTC 24 |
134614000 ps |
| T1161 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2795335039 |
|
|
Oct 12 11:28:10 AM UTC 24 |
Oct 12 11:28:31 AM UTC 24 |
12835000 ps |
| T1162 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2645487455 |
|
|
Oct 12 11:28:08 AM UTC 24 |
Oct 12 11:28:33 AM UTC 24 |
29875500 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1646773567 |
|
|
Oct 12 11:28:10 AM UTC 24 |
Oct 12 11:28:33 AM UTC 24 |
21342200 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3526889902 |
|
|
Oct 12 11:28:12 AM UTC 24 |
Oct 12 11:28:38 AM UTC 24 |
97220000 ps |
| T1163 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.788514861 |
|
|
Oct 12 11:27:15 AM UTC 24 |
Oct 12 11:28:39 AM UTC 24 |
5042329700 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.325552049 |
|
|
Oct 12 11:26:41 AM UTC 24 |
Oct 12 11:28:39 AM UTC 24 |
12148066600 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2167687335 |
|
|
Oct 12 11:27:29 AM UTC 24 |
Oct 12 11:28:39 AM UTC 24 |
85884100 ps |
| T1164 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1162182651 |
|
|
Oct 12 11:28:12 AM UTC 24 |
Oct 12 11:28:39 AM UTC 24 |
104366900 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.3213567838 |
|
|
Oct 12 11:28:19 AM UTC 24 |
Oct 12 11:28:42 AM UTC 24 |
54386500 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3956890967 |
|
|
Oct 12 11:28:13 AM UTC 24 |
Oct 12 11:28:42 AM UTC 24 |
221659300 ps |
| T1165 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.669016705 |
|
|
Oct 12 11:28:18 AM UTC 24 |
Oct 12 11:28:45 AM UTC 24 |
43656300 ps |
| T1166 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3125088007 |
|
|
Oct 12 11:28:19 AM UTC 24 |
Oct 12 11:28:45 AM UTC 24 |
29798800 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2325426357 |
|
|
Oct 12 11:28:12 AM UTC 24 |
Oct 12 11:28:46 AM UTC 24 |
3747346500 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2449415572 |
|
|
Oct 12 11:28:20 AM UTC 24 |
Oct 12 11:28:47 AM UTC 24 |
145854600 ps |
| T1167 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1784898130 |
|
|
Oct 12 11:28:22 AM UTC 24 |
Oct 12 11:28:48 AM UTC 24 |
177027600 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.452601177 |
|
|
Oct 12 11:28:25 AM UTC 24 |
Oct 12 11:28:50 AM UTC 24 |
32685500 ps |
| T1168 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1538952081 |
|
|
Oct 12 11:28:29 AM UTC 24 |
Oct 12 11:28:50 AM UTC 24 |
28126400 ps |
| T1169 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3307124195 |
|
|
Oct 12 11:28:27 AM UTC 24 |
Oct 12 11:28:53 AM UTC 24 |
14550600 ps |
| T1170 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.160775288 |
|
|
Oct 12 11:28:28 AM UTC 24 |
Oct 12 11:28:53 AM UTC 24 |
18301200 ps |
| T1171 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1645953822 |
|
|
Oct 12 11:28:32 AM UTC 24 |
Oct 12 11:28:56 AM UTC 24 |
71089700 ps |
| T1172 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2229173270 |
|
|
Oct 12 11:28:31 AM UTC 24 |
Oct 12 11:28:57 AM UTC 24 |
30582500 ps |
| T1173 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1820951322 |
|
|
Oct 12 11:28:34 AM UTC 24 |
Oct 12 11:29:01 AM UTC 24 |
91212900 ps |
| T1174 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.843807713 |
|
|
Oct 12 11:28:40 AM UTC 24 |
Oct 12 11:29:03 AM UTC 24 |
17257200 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1814201557 |
|
|
Oct 12 11:28:34 AM UTC 24 |
Oct 12 11:29:04 AM UTC 24 |
96112800 ps |
| T1175 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1295849152 |
|
|
Oct 12 11:28:40 AM UTC 24 |
Oct 12 11:29:06 AM UTC 24 |
14569100 ps |
| T1176 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2791413477 |
|
|
Oct 12 11:28:20 AM UTC 24 |
Oct 12 11:29:07 AM UTC 24 |
692641400 ps |
| T1177 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2115045708 |
|
|
Oct 12 11:28:40 AM UTC 24 |
Oct 12 11:29:07 AM UTC 24 |
12212500 ps |
| T1178 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.690301823 |
|
|
Oct 12 11:28:40 AM UTC 24 |
Oct 12 11:29:08 AM UTC 24 |
290841700 ps |
| T1179 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3635464196 |
|
|
Oct 12 11:28:48 AM UTC 24 |
Oct 12 11:29:10 AM UTC 24 |
16386900 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1033583153 |
|
|
Oct 12 11:28:44 AM UTC 24 |
Oct 12 11:29:10 AM UTC 24 |
67953500 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1771206165 |
|
|
Oct 12 11:28:42 AM UTC 24 |
Oct 12 11:29:12 AM UTC 24 |
481313700 ps |
| T1180 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3003103267 |
|
|
Oct 12 11:28:46 AM UTC 24 |
Oct 12 11:29:12 AM UTC 24 |
51794900 ps |
| T1181 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1341663229 |
|
|
Oct 12 11:28:46 AM UTC 24 |
Oct 12 11:29:12 AM UTC 24 |
105009300 ps |
| T1182 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3280638154 |
|
|
Oct 12 11:28:48 AM UTC 24 |
Oct 12 11:29:15 AM UTC 24 |
45083500 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.917461357 |
|
|
Oct 12 11:28:42 AM UTC 24 |
Oct 12 11:29:15 AM UTC 24 |
402293700 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1083194868 |
|
|
Oct 12 11:28:51 AM UTC 24 |
Oct 12 11:29:16 AM UTC 24 |
113110600 ps |
| T1183 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3233809728 |
|
|
Oct 12 11:28:58 AM UTC 24 |
Oct 12 11:29:18 AM UTC 24 |
38781800 ps |
| T1184 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4015164304 |
|
|
Oct 12 11:28:57 AM UTC 24 |
Oct 12 11:29:19 AM UTC 24 |
20069400 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1450918667 |
|
|
Oct 12 11:28:54 AM UTC 24 |
Oct 12 11:29:19 AM UTC 24 |
81769500 ps |
| T1185 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3760118020 |
|
|
Oct 12 11:28:50 AM UTC 24 |
Oct 12 11:29:20 AM UTC 24 |
130560300 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2629049969 |
|
|
Oct 12 11:28:58 AM UTC 24 |
Oct 12 11:29:20 AM UTC 24 |
32286600 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2887123993 |
|
|
Oct 12 11:27:31 AM UTC 24 |
Oct 12 11:29:26 AM UTC 24 |
18181294900 ps |
| T1186 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3357629972 |
|
|
Oct 12 11:29:02 AM UTC 24 |
Oct 12 11:29:29 AM UTC 24 |
54576400 ps |
| T1187 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3257805149 |
|
|
Oct 12 11:29:08 AM UTC 24 |
Oct 12 11:29:29 AM UTC 24 |
15192600 ps |
| T1188 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.554458326 |
|
|
Oct 12 11:29:06 AM UTC 24 |
Oct 12 11:29:32 AM UTC 24 |
36620800 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4106807972 |
|
|
Oct 12 11:29:04 AM UTC 24 |
Oct 12 11:29:32 AM UTC 24 |
400392100 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1908953333 |
|
|
Oct 12 11:29:06 AM UTC 24 |
Oct 12 11:29:34 AM UTC 24 |
412668600 ps |
| T1189 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2758044401 |
|
|
Oct 12 11:29:11 AM UTC 24 |
Oct 12 11:29:35 AM UTC 24 |
84333900 ps |
| T1190 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1274795902 |
|
|
Oct 12 11:29:08 AM UTC 24 |
Oct 12 11:29:35 AM UTC 24 |
18996700 ps |
| T1191 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2889653407 |
|
|
Oct 12 11:29:09 AM UTC 24 |
Oct 12 11:29:35 AM UTC 24 |
124292600 ps |
| T1192 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.684460514 |
|
|
Oct 12 11:29:06 AM UTC 24 |
Oct 12 11:29:36 AM UTC 24 |
72972300 ps |
| T1193 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.4088944638 |
|
|
Oct 12 11:29:15 AM UTC 24 |
Oct 12 11:29:37 AM UTC 24 |
26826000 ps |
| T1194 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3283335449 |
|
|
Oct 12 11:29:13 AM UTC 24 |
Oct 12 11:29:39 AM UTC 24 |
94632600 ps |
| T1195 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1431862674 |
|
|
Oct 12 11:29:15 AM UTC 24 |
Oct 12 11:29:41 AM UTC 24 |
14119500 ps |
| T1196 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1540366589 |
|
|
Oct 12 11:29:13 AM UTC 24 |
Oct 12 11:29:43 AM UTC 24 |
67701200 ps |
| T1197 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3183893470 |
|
|
Oct 12 11:29:16 AM UTC 24 |
Oct 12 11:29:43 AM UTC 24 |
43157300 ps |
| T295 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3831221131 |
|
|
Oct 12 11:29:20 AM UTC 24 |
Oct 12 11:29:45 AM UTC 24 |
249581900 ps |
| T1198 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3862396140 |
|
|
Oct 12 11:29:20 AM UTC 24 |
Oct 12 11:29:46 AM UTC 24 |
13521500 ps |
| T1199 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.851357354 |
|
|
Oct 12 11:29:19 AM UTC 24 |
Oct 12 11:29:47 AM UTC 24 |
67385300 ps |
| T1200 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1293154723 |
|
|
Oct 12 11:29:20 AM UTC 24 |
Oct 12 11:29:49 AM UTC 24 |
828413600 ps |
| T1201 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3653078536 |
|
|
Oct 12 11:29:27 AM UTC 24 |
Oct 12 11:29:52 AM UTC 24 |
11316700 ps |
| T1202 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3672648558 |
|
|
Oct 12 11:29:30 AM UTC 24 |
Oct 12 11:29:55 AM UTC 24 |
16174800 ps |
| T1203 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.25724525 |
|
|
Oct 12 11:29:30 AM UTC 24 |
Oct 12 11:29:58 AM UTC 24 |
136591900 ps |
| T1204 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3020770360 |
|
|
Oct 12 11:29:36 AM UTC 24 |
Oct 12 11:29:58 AM UTC 24 |
29191800 ps |
| T1205 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3148284989 |
|
|
Oct 12 11:29:11 AM UTC 24 |
Oct 12 11:29:59 AM UTC 24 |
281559600 ps |
| T1206 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1438383579 |
|
|
Oct 12 11:29:36 AM UTC 24 |
Oct 12 11:30:00 AM UTC 24 |
20800000 ps |
| T1207 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3200225154 |
|
|
Oct 12 11:29:36 AM UTC 24 |
Oct 12 11:30:01 AM UTC 24 |
24223000 ps |
| T1208 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2110478009 |
|
|
Oct 12 11:29:35 AM UTC 24 |
Oct 12 11:30:03 AM UTC 24 |
62235900 ps |
| T1209 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3944439100 |
|
|
Oct 12 11:29:37 AM UTC 24 |
Oct 12 11:30:04 AM UTC 24 |
74425300 ps |
| T1210 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2076117736 |
|
|
Oct 12 11:29:34 AM UTC 24 |
Oct 12 11:30:04 AM UTC 24 |
104693400 ps |
| T1211 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3755294381 |
|
|
Oct 12 11:29:33 AM UTC 24 |
Oct 12 11:30:05 AM UTC 24 |
59527600 ps |
| T1212 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2965395518 |
|
|
Oct 12 11:29:45 AM UTC 24 |
Oct 12 11:30:07 AM UTC 24 |
17560700 ps |
| T1213 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1198801225 |
|
|
Oct 12 11:29:45 AM UTC 24 |
Oct 12 11:30:07 AM UTC 24 |
26465000 ps |
| T1214 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4277595784 |
|
|
Oct 12 11:29:41 AM UTC 24 |
Oct 12 11:30:07 AM UTC 24 |
38012400 ps |
| T1215 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1183351913 |
|
|
Oct 12 11:29:39 AM UTC 24 |
Oct 12 11:30:10 AM UTC 24 |
39001800 ps |
| T1216 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1877101669 |
|
|
Oct 12 11:29:46 AM UTC 24 |
Oct 12 11:30:10 AM UTC 24 |
262059500 ps |
| T1217 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1939919636 |
|
|
Oct 12 11:29:45 AM UTC 24 |
Oct 12 11:30:11 AM UTC 24 |
18271500 ps |
| T1218 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1587769562 |
|
|
Oct 12 11:29:47 AM UTC 24 |
Oct 12 11:30:17 AM UTC 24 |
36732700 ps |
| T1219 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.113068072 |
|
|
Oct 12 11:29:53 AM UTC 24 |
Oct 12 11:30:18 AM UTC 24 |
57655200 ps |
| T1220 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.217598898 |
|
|
Oct 12 11:29:48 AM UTC 24 |
Oct 12 11:30:19 AM UTC 24 |
67389300 ps |
| T1221 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2010397748 |
|
|
Oct 12 11:29:46 AM UTC 24 |
Oct 12 11:30:19 AM UTC 24 |
230948300 ps |
| T1222 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.966338503 |
|
|
Oct 12 11:29:56 AM UTC 24 |
Oct 12 11:30:22 AM UTC 24 |
14469300 ps |
| T1223 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2468081853 |
|
|
Oct 12 11:30:00 AM UTC 24 |
Oct 12 11:30:24 AM UTC 24 |
147528100 ps |
| T1224 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1567219451 |
|
|
Oct 12 11:29:59 AM UTC 24 |
Oct 12 11:30:25 AM UTC 24 |
46086700 ps |
| T1225 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2285198886 |
|
|
Oct 12 11:29:59 AM UTC 24 |
Oct 12 11:30:26 AM UTC 24 |
33578500 ps |
| T1226 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2515770308 |
|
|
Oct 12 11:30:05 AM UTC 24 |
Oct 12 11:30:27 AM UTC 24 |
89844400 ps |
| T1227 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3427563015 |
|
|
Oct 12 11:30:05 AM UTC 24 |
Oct 12 11:30:28 AM UTC 24 |
88385900 ps |
| T1228 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1332901958 |
|
|
Oct 12 11:30:06 AM UTC 24 |
Oct 12 11:30:29 AM UTC 24 |
135739000 ps |
| T1229 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2866814033 |
|
|
Oct 12 11:30:01 AM UTC 24 |
Oct 12 11:30:30 AM UTC 24 |
161587200 ps |
| T1230 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3426306694 |
|
|
Oct 12 11:29:38 AM UTC 24 |
Oct 12 11:30:30 AM UTC 24 |
380906400 ps |
| T1231 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.2849986164 |
|
|
Oct 12 11:30:08 AM UTC 24 |
Oct 12 11:30:30 AM UTC 24 |
63635400 ps |
| T1232 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3149059103 |
|
|
Oct 12 11:30:05 AM UTC 24 |
Oct 12 11:30:32 AM UTC 24 |
13370400 ps |
| T1233 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.6464689 |
|
|
Oct 12 11:30:10 AM UTC 24 |
Oct 12 11:30:33 AM UTC 24 |
54814800 ps |
| T1234 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.36527473 |
|
|
Oct 12 11:30:12 AM UTC 24 |
Oct 12 11:30:33 AM UTC 24 |
116682000 ps |
| T1235 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3405994681 |
|
|
Oct 12 11:30:12 AM UTC 24 |
Oct 12 11:30:34 AM UTC 24 |
26748300 ps |
| T1236 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4265525144 |
|
|
Oct 12 11:30:02 AM UTC 24 |
Oct 12 11:30:35 AM UTC 24 |
77145800 ps |
| T1237 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.2136243227 |
|
|
Oct 12 11:30:14 AM UTC 24 |
Oct 12 11:30:36 AM UTC 24 |
16139100 ps |
| T1238 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4055070307 |
|
|
Oct 12 11:30:08 AM UTC 24 |
Oct 12 11:30:38 AM UTC 24 |
61933100 ps |
| T1239 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3604861591 |
|
|
Oct 12 11:30:08 AM UTC 24 |
Oct 12 11:30:38 AM UTC 24 |
209948400 ps |
| T1240 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.86870945 |
|
|
Oct 12 11:30:17 AM UTC 24 |
Oct 12 11:30:39 AM UTC 24 |
34374700 ps |
| T1241 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.3022851600 |
|
|
Oct 12 11:30:19 AM UTC 24 |
Oct 12 11:30:40 AM UTC 24 |
18666500 ps |
| T1242 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.2343586982 |
|
|
Oct 12 11:30:19 AM UTC 24 |
Oct 12 11:30:41 AM UTC 24 |
14914000 ps |
| T1243 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.1768557016 |
|
|
Oct 12 11:30:20 AM UTC 24 |
Oct 12 11:30:42 AM UTC 24 |
26033700 ps |
| T1244 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2613616281 |
|
|
Oct 12 11:30:20 AM UTC 24 |
Oct 12 11:30:43 AM UTC 24 |
30845800 ps |
| T1245 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.646639539 |
|
|
Oct 12 11:30:23 AM UTC 24 |
Oct 12 11:30:46 AM UTC 24 |
20406700 ps |
| T1246 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.1787417438 |
|
|
Oct 12 11:30:25 AM UTC 24 |
Oct 12 11:30:47 AM UTC 24 |
59871200 ps |
| T1247 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.507742601 |
|
|
Oct 12 11:30:26 AM UTC 24 |
Oct 12 11:30:49 AM UTC 24 |
14141200 ps |
| T1248 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.831071585 |
|
|
Oct 12 11:30:25 AM UTC 24 |
Oct 12 11:30:49 AM UTC 24 |
28979300 ps |
| T1249 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1445806205 |
|
|
Oct 12 11:30:27 AM UTC 24 |
Oct 12 11:30:49 AM UTC 24 |
43034400 ps |
| T1250 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2152190526 |
|
|
Oct 12 11:30:29 AM UTC 24 |
Oct 12 11:30:52 AM UTC 24 |
103237800 ps |
| T1251 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.2892048223 |
|
|
Oct 12 11:30:30 AM UTC 24 |
Oct 12 11:30:54 AM UTC 24 |
70990400 ps |
| T1252 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.718132981 |
|
|
Oct 12 11:30:30 AM UTC 24 |
Oct 12 11:30:54 AM UTC 24 |
18259700 ps |
| T1253 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.875363140 |
|
|
Oct 12 11:30:32 AM UTC 24 |
Oct 12 11:30:54 AM UTC 24 |
17533000 ps |
| T1254 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2416843640 |
|
|
Oct 12 11:30:34 AM UTC 24 |
Oct 12 11:30:57 AM UTC 24 |
14922000 ps |
| T1255 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2495384871 |
|
|
Oct 12 11:30:35 AM UTC 24 |
Oct 12 11:30:57 AM UTC 24 |
23427100 ps |
| T1256 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.599578097 |
|
|
Oct 12 11:30:31 AM UTC 24 |
Oct 12 11:30:57 AM UTC 24 |
37308700 ps |
| T1257 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.4051170433 |
|
|
Oct 12 11:30:34 AM UTC 24 |
Oct 12 11:30:57 AM UTC 24 |
44977800 ps |
| T1258 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.289343575 |
|
|
Oct 12 11:30:33 AM UTC 24 |
Oct 12 11:30:58 AM UTC 24 |
42535600 ps |
| T1259 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.3137428850 |
|
|
Oct 12 11:30:36 AM UTC 24 |
Oct 12 11:30:58 AM UTC 24 |
65328500 ps |
| T1260 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.4136702426 |
|
|
Oct 12 11:30:37 AM UTC 24 |
Oct 12 11:31:00 AM UTC 24 |
51606500 ps |
| T1261 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.3756229836 |
|
|
Oct 12 11:30:38 AM UTC 24 |
Oct 12 11:31:02 AM UTC 24 |
16625300 ps |
| T1262 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.1527308777 |
|
|
Oct 12 11:30:39 AM UTC 24 |
Oct 12 11:31:02 AM UTC 24 |
17412800 ps |
| T1263 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1238801159 |
|
|
Oct 12 11:30:39 AM UTC 24 |
Oct 12 11:31:03 AM UTC 24 |
57871700 ps |
| T1264 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.95359819 |
|
|
Oct 12 11:30:41 AM UTC 24 |
Oct 12 11:31:05 AM UTC 24 |
17110800 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3137143453 |
|
|
Oct 12 11:27:42 AM UTC 24 |
Oct 12 11:38:04 AM UTC 24 |
1123105400 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2095520420 |
|
|
Oct 12 11:26:58 AM UTC 24 |
Oct 12 11:39:08 AM UTC 24 |
1403315200 ps |
| T244 |
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.585699271 |
|
|
Oct 12 11:28:08 AM UTC 24 |
Oct 12 11:40:06 AM UTC 24 |
826932900 ps |