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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.05 95.23 93.89 98.31 92.52 97.14 97.00 98.24


Total test records in report: 1267
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html | tests23.html | tests24.html | tests25.html | tests26.html
T356 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2860934555 Oct 12 11:28:16 AM UTC 24 Oct 12 11:40:33 AM UTC 24 1471777000 ps
T350 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3033154393 Oct 12 11:28:54 AM UTC 24 Oct 12 11:40:57 AM UTC 24 336091400 ps
T255 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3867625083 Oct 12 11:29:06 AM UTC 24 Oct 12 11:41:34 AM UTC 24 1645549000 ps
T357 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1413596441 Oct 12 11:29:35 AM UTC 24 Oct 12 11:42:00 AM UTC 24 703310500 ps
T353 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2764583413 Oct 12 11:26:24 AM UTC 24 Oct 12 11:46:29 AM UTC 24 1417786900 ps
T1265 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3439623114 Oct 12 11:28:25 AM UTC 24 Oct 12 11:49:03 AM UTC 24 919784600 ps
T351 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3514717784 Oct 12 11:29:13 AM UTC 24 Oct 12 11:49:28 AM UTC 24 2918340700 ps
T354 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3749197069 Oct 12 11:26:15 AM UTC 24 Oct 12 11:49:32 AM UTC 24 403607000 ps
T352 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1710759238 Oct 12 11:29:20 AM UTC 24 Oct 12 11:49:38 AM UTC 24 1068833400 ps
T261 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.505547991 Oct 12 11:29:49 AM UTC 24 Oct 12 11:50:02 AM UTC 24 349714600 ps
T359 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.596915111 Oct 12 11:29:42 AM UTC 24 Oct 12 11:50:14 AM UTC 24 5059299800 ps
T360 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3687932917 Oct 12 11:30:05 AM UTC 24 Oct 12 11:50:27 AM UTC 24 1793873800 ps
T358 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1096548623 Oct 12 11:27:22 AM UTC 24 Oct 12 11:50:47 AM UTC 24 471714000 ps
T355 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.4265134648 Oct 12 11:26:43 AM UTC 24 Oct 12 11:51:09 AM UTC 24 891674200 ps
T1266 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3503238526 Oct 12 11:27:54 AM UTC 24 Oct 12 11:52:23 AM UTC 24 372345700 ps
T361 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.459294830 Oct 12 11:28:39 AM UTC 24 Oct 12 11:52:33 AM UTC 24 1752552200 ps
T1267 /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2849493479 Oct 12 11:28:46 AM UTC 24 Oct 12 11:52:38 AM UTC 24 357341700 ps

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_invalid_op.1172367217
Short name T18
Test name
Test status
Simulation time 2672981000 ps
CPU time 71.16 seconds
Started Oct 12 11:52:34 AM UTC 24
Finished Oct 12 11:53:47 AM UTC 24
Peak memory 272976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1172367217 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_invalid_op.1172367217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mp_regions.2995934886
Short name T26
Test name
Test status
Simulation time 19317037400 ps
CPU time 272.56 seconds
Started Oct 12 11:50:44 AM UTC 24
Finished Oct 12 11:55:21 AM UTC 24
Peak memory 283284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2995934886 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_mp_regions.2995934886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_rw.2725622700
Short name T235
Test name
Test status
Simulation time 113979600 ps
CPU time 26.65 seconds
Started Oct 12 11:26:54 AM UTC 24
Finished Oct 12 11:27:22 AM UTC 24
Peak memory 274364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725622700 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_rw.2725622700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_otp_reset.3259074627
Short name T4
Test name
Test status
Simulation time 77251300 ps
CPU time 196.47 seconds
Started Oct 12 11:50:15 AM UTC 24
Finished Oct 12 11:53:35 AM UTC 24
Peak memory 275008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259074627 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_otp_reset.3259074627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_derr.4037152555
Short name T60
Test name
Test status
Simulation time 620741500 ps
CPU time 152.26 seconds
Started Oct 12 11:58:34 AM UTC 24
Finished Oct 12 12:01:10 PM UTC 24
Peak memory 291648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4037152555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 0.flash_ctrl_ro_derr.4037152555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_oversize_error.2388032181
Short name T54
Test name
Test status
Simulation time 2148017800 ps
CPU time 191.97 seconds
Started Oct 12 12:00:11 PM UTC 24
Finished Oct 12 12:03:27 PM UTC 24
Peak memory 303800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2388032181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 0.flash_ctrl_oversize_error.2388032181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_cm.1904750030
Short name T16
Test name
Test status
Simulation time 3104279100 ps
CPU time 6886.92 seconds
Started Oct 12 12:04:40 PM UTC 24
Finished Oct 12 02:00:40 PM UTC 24
Peak memory 314004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1904750030 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_cm.1904750030
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma.2175758334
Short name T98
Test name
Test status
Simulation time 211727568000 ps
CPU time 1990.75 seconds
Started Oct 12 11:49:39 AM UTC 24
Finished Oct 12 12:23:16 PM UTC 24
Peak memory 277588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175758334
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma.2175758334
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_mem_rw_with_rand_reset.1680651810
Short name T130
Test name
Test status
Simulation time 39050700 ps
CPU time 27.15 seconds
Started Oct 12 11:26:43 AM UTC 24
Finished Oct 12 11:27:12 AM UTC 24
Peak memory 292864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1680651810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 1.flash_ctrl_csr_mem_rw_with_rand_reset.1680651810
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_erase_suspend.2897023034
Short name T27
Test name
Test status
Simulation time 1478618200 ps
CPU time 429.45 seconds
Started Oct 12 11:49:33 AM UTC 24
Finished Oct 12 11:56:49 AM UTC 24
Peak memory 274844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897023034 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_erase_suspend.2897023034
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_sec_otp.2298038140
Short name T115
Test name
Test status
Simulation time 4122721800 ps
CPU time 141.68 seconds
Started Oct 12 12:07:01 PM UTC 24
Finished Oct 12 12:09:25 PM UTC 24
Peak memory 272804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298038140 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_sec_otp.2298038140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_bit_bash.2450030500
Short name T363
Test name
Test status
Simulation time 3017780900 ps
CPU time 70.76 seconds
Started Oct 12 11:26:55 AM UTC 24
Finished Oct 12 11:28:07 AM UTC 24
Peak memory 276424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2450030500 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_bit_bash.2450030500
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd.635501166
Short name T44
Test name
Test status
Simulation time 11163232500 ps
CPU time 269.58 seconds
Started Oct 12 12:01:29 PM UTC 24
Finished Oct 12 12:06:03 PM UTC 24
Peak memory 303808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635501166 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_rd.635501166
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_mid_op_rst.3706657075
Short name T30
Test name
Test status
Simulation time 1310474100 ps
CPU time 99.27 seconds
Started Oct 12 11:52:38 AM UTC 24
Finished Oct 12 11:54:20 AM UTC 24
Peak memory 270772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706657075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mid_op_rst.3706657075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_otp_reset.585066131
Short name T184
Test name
Test status
Simulation time 40844800 ps
CPU time 220.64 seconds
Started Oct 12 12:56:27 PM UTC 24
Finished Oct 12 01:00:11 PM UTC 24
Peak memory 271048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585066131 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_otp_reset.585066131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_rw.1575420444
Short name T75
Test name
Test status
Simulation time 64870200 ps
CPU time 27.15 seconds
Started Oct 12 11:26:19 AM UTC 24
Finished Oct 12 11:26:48 AM UTC 24
Peak memory 274556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575420444 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_rw.1575420444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_intr_test.2931252981
Short name T245
Test name
Test status
Simulation time 26798600 ps
CPU time 21.13 seconds
Started Oct 12 11:26:18 AM UTC 24
Finished Oct 12 11:26:40 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931252981 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_test.2931252981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_intg_err.2764583413
Short name T353
Test name
Test status
Simulation time 1417786900 ps
CPU time 1187.73 seconds
Started Oct 12 11:26:24 AM UTC 24
Finished Oct 12 11:46:29 AM UTC 24
Peak memory 278584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764583413 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_intg_err.2764583413
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_prog_rma_wipe_err.2532002490
Short name T134
Test name
Test status
Simulation time 10035837900 ps
CPU time 72.57 seconds
Started Oct 12 12:06:47 PM UTC 24
Finished Oct 12 12:08:02 PM UTC 24
Peak memory 281124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2532002490 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 0.flash_ctrl_hw_prog_rma_wipe_err.2532002490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_otp_reset.601870150
Short name T94
Test name
Test status
Simulation time 128196300 ps
CPU time 185.73 seconds
Started Oct 12 12:23:22 PM UTC 24
Finished Oct 12 12:26:30 PM UTC 24
Peak memory 270908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=601870150 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_otp_reset.601870150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro_serr.2839890956
Short name T48
Test name
Test status
Simulation time 1290567200 ps
CPU time 141.68 seconds
Started Oct 12 11:55:59 AM UTC 24
Finished Oct 12 11:58:24 AM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2839890956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_ro_serr.2839890956
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_access_after_disable.3727774190
Short name T8
Test name
Test status
Simulation time 32095600 ps
CPU time 20.96 seconds
Started Oct 12 12:06:11 PM UTC 24
Finished Oct 12 12:06:33 PM UTC 24
Peak memory 275116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3727774190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_access_after_disable.3727774190
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_lcmgr_intg.616455377
Short name T138
Test name
Test status
Simulation time 25805200 ps
CPU time 20.41 seconds
Started Oct 12 12:06:44 PM UTC 24
Finished Oct 12 12:07:06 PM UTC 24
Peak memory 274992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=616455377 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash
_ctrl_lcmgr_intg.616455377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_errors.3085294202
Short name T223
Test name
Test status
Simulation time 217631900 ps
CPU time 28.14 seconds
Started Oct 12 11:26:43 AM UTC 24
Finished Oct 12 11:27:13 AM UTC 24
Peak memory 276416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085294202 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_errors.3085294202
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sec_info_access.3698666420
Short name T39
Test name
Test status
Simulation time 859539800 ps
CPU time 76.49 seconds
Started Oct 12 12:04:52 PM UTC 24
Finished Oct 12 12:06:10 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698666420 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sec_info_access.3698666420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rma_err.3539696047
Short name T178
Test name
Test status
Simulation time 160141641800 ps
CPU time 1032.61 seconds
Started Oct 12 12:18:15 PM UTC 24
Finished Oct 12 12:35:40 PM UTC 24
Peak memory 272800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=3539696047 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.
flash_ctrl_rma_err.3539696047
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_prog_rma_wipe_err.2979881316
Short name T84
Test name
Test status
Simulation time 10016390100 ps
CPU time 202.33 seconds
Started Oct 12 12:55:54 PM UTC 24
Finished Oct 12 12:59:20 PM UTC 24
Peak memory 274948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2979881316 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 13.flash_ctrl_hw_prog_rma_wipe_err.2979881316
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_alert_test.2067047612
Short name T111
Test name
Test status
Simulation time 41368400 ps
CPU time 20.24 seconds
Started Oct 12 12:06:50 PM UTC 24
Finished Oct 12 12:07:12 PM UTC 24
Peak memory 268816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2067047612 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_alert_test.2067047612
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_derr_detect.4293446187
Short name T83
Test name
Test status
Simulation time 8017815500 ps
CPU time 251.31 seconds
Started Oct 12 12:21:02 PM UTC 24
Finished Oct 12 12:25:17 PM UTC 24
Peak memory 287552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4293446187 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 3.flash_ctrl_derr_detect.4293446187
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fetch_code.1828906057
Short name T12
Test name
Test status
Simulation time 385525100 ps
CPU time 34.08 seconds
Started Oct 12 11:50:47 AM UTC 24
Finished Oct 12 11:51:23 AM UTC 24
Peak memory 272984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18
28906057 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_fetc
h_code.1828906057
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_ctrl_arb.2638045148
Short name T192
Test name
Test status
Simulation time 352959674200 ps
CPU time 2503.91 seconds
Started Oct 12 12:12:29 PM UTC 24
Finished Oct 12 12:54:40 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638045148 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_ctrl_arb.2638045148
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mid_op_rst.642903392
Short name T65
Test name
Test status
Simulation time 1523655700 ps
CPU time 107.92 seconds
Started Oct 12 12:07:10 PM UTC 24
Finished Oct 12 12:09:00 PM UTC 24
Peak memory 270708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642903392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mid_op_rst.642903392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_re_evict.1128665295
Short name T36
Test name
Test status
Simulation time 80482300 ps
CPU time 45.59 seconds
Started Oct 12 12:04:03 PM UTC 24
Finished Oct 12 12:04:50 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128665295 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_re_evict.1128665295
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_mem_rw_with_rand_reset.3526889902
Short name T284
Test name
Test status
Simulation time 97220000 ps
CPU time 24.65 seconds
Started Oct 12 11:28:12 AM UTC 24
Finished Oct 12 11:28:38 AM UTC 24
Peak memory 292864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3526889902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 7.flash_ctrl_csr_mem_rw_with_rand_reset.3526889902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd_slow_flash.3897491133
Short name T47
Test name
Test status
Simulation time 12471706100 ps
CPU time 360.34 seconds
Started Oct 12 12:09:32 PM UTC 24
Finished Oct 12 12:15:38 PM UTC 24
Peak memory 301616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3897491133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 1.flash_ctrl_intr_rd_slow_flash.3897491133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_errors.1540366589
Short name T1196
Test name
Test status
Simulation time 67701200 ps
CPU time 28.33 seconds
Started Oct 12 11:29:13 AM UTC 24
Finished Oct 12 11:29:43 AM UTC 24
Peak memory 276376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540366589 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_errors.1540366589
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_partial_access.2243523255
Short name T230
Test name
Test status
Simulation time 16759900 ps
CPU time 19.86 seconds
Started Oct 12 11:26:52 AM UTC 24
Finished Oct 12 11:27:13 AM UTC 24
Peak memory 276368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243523255 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_partial_access.2243523255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_dir_rd.1967045983
Short name T10
Test name
Test status
Simulation time 57199100 ps
CPU time 129.4 seconds
Started Oct 12 11:47:13 AM UTC 24
Finished Oct 12 11:49:25 AM UTC 24
Peak memory 272848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967045983 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_dir_rd.1967045983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rand_ops.4273201051
Short name T89
Test name
Test status
Simulation time 1545003400 ps
CPU time 1113.91 seconds
Started Oct 12 12:06:57 PM UTC 24
Finished Oct 12 12:25:46 PM UTC 24
Peak memory 298164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273201051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rand_ops.4273201051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wr_intg.2689913407
Short name T7
Test name
Test status
Simulation time 58422200 ps
CPU time 22.48 seconds
Started Oct 12 12:06:04 PM UTC 24
Finished Oct 12 12:06:28 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2689913407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 0.flash_ctrl_wr_intg.2689913407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_re_evict.419002024
Short name T412
Test name
Test status
Simulation time 525956200 ps
CPU time 44.17 seconds
Started Oct 12 12:31:26 PM UTC 24
Finished Oct 12 12:32:12 PM UTC 24
Peak memory 285412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419002024 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_re_evict.419002024
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_disable.2794653407
Short name T201
Test name
Test status
Simulation time 29497000 ps
CPU time 26.3 seconds
Started Oct 12 01:08:00 PM UTC 24
Finished Oct 12 01:08:28 PM UTC 24
Peak memory 285340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2794653407 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_
ctrl_disable.2794653407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb_redun.4189904016
Short name T59
Test name
Test status
Simulation time 666340700 ps
CPU time 30.26 seconds
Started Oct 12 12:10:57 PM UTC 24
Finished Oct 12 12:11:28 PM UTC 24
Peak memory 275408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4189904016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb_redun.4189904016
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fs_sup.664214119
Short name T415
Test name
Test status
Simulation time 349718600 ps
CPU time 52.12 seconds
Started Oct 12 12:17:54 PM UTC 24
Finished Oct 12 12:18:48 PM UTC 24
Peak memory 275000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6642141
19 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fs
_sup.664214119
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_lcmgr_intg.2413722686
Short name T745
Test name
Test status
Simulation time 15741400 ps
CPU time 22.73 seconds
Started Oct 12 01:04:00 PM UTC 24
Finished Oct 12 01:04:24 PM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2413722686 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.fla
sh_ctrl_lcmgr_intg.2413722686
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_ack_consistency.53345727
Short name T69
Test name
Test status
Simulation time 15781300 ps
CPU time 21.76 seconds
Started Oct 12 12:18:01 PM UTC 24
Finished Oct 12 12:18:24 PM UTC 24
Peak memory 293072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=53345727 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flas
h_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_ack_consistency.53345727
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_cm.822583551
Short name T14
Test name
Test status
Simulation time 9654807800 ps
CPU time 6473.5 seconds
Started Oct 12 12:27:33 PM UTC 24
Finished Oct 12 02:16:36 PM UTC 24
Peak memory 318108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822583551 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_cm.822583551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_derr_detect.3832514150
Short name T265
Test name
Test status
Simulation time 6644305200 ps
CPU time 270.95 seconds
Started Oct 12 12:08:53 PM UTC 24
Finished Oct 12 12:13:29 PM UTC 24
Peak memory 289540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3832514150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 1.flash_ctrl_derr_detect.3832514150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_intg.373762526
Short name T200
Test name
Test status
Simulation time 126051000 ps
CPU time 44.24 seconds
Started Oct 12 12:05:49 PM UTC 24
Finished Oct 12 12:06:35 PM UTC 24
Peak memory 285256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373762526
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_intg.373762526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict.2927392757
Short name T428
Test name
Test status
Simulation time 352166500 ps
CPU time 52.32 seconds
Started Oct 12 12:21:52 PM UTC 24
Finished Oct 12 12:22:46 PM UTC 24
Peak memory 287632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927392757 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_evict.2927392757
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_intg_err.3033154393
Short name T350
Test name
Test status
Simulation time 336091400 ps
CPU time 712.87 seconds
Started Oct 12 11:28:54 AM UTC 24
Finished Oct 12 11:40:57 AM UTC 24
Peak memory 276692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033154393 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_intg_err.3033154393
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_intr_test.1438383579
Short name T1206
Test name
Test status
Simulation time 20800000 ps
CPU time 22.49 seconds
Started Oct 12 11:29:36 AM UTC 24
Finished Oct 12 11:30:00 AM UTC 24
Peak memory 274392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438383579 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_test.1438383579
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_errors.498269458
Short name T226
Test name
Test status
Simulation time 109051800 ps
CPU time 29.61 seconds
Started Oct 12 11:27:22 AM UTC 24
Finished Oct 12 11:27:53 AM UTC 24
Peak memory 276616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498269458 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_errors.498269458
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw.4279069352
Short name T297
Test name
Test status
Simulation time 15994207100 ps
CPU time 527.76 seconds
Started Oct 12 12:14:06 PM UTC 24
Finished Oct 12 12:23:01 PM UTC 24
Peak memory 332476 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279069352 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw.4279069352
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_access_after_disable.4138142152
Short name T21
Test name
Test status
Simulation time 12056400 ps
CPU time 25.52 seconds
Started Oct 12 12:10:55 PM UTC 24
Finished Oct 12 12:11:22 PM UTC 24
Peak memory 275112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=4138142152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_access_after_disable.4138142152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_intg_err.459294830
Short name T361
Test name
Test status
Simulation time 1752552200 ps
CPU time 1414.33 seconds
Started Oct 12 11:28:39 AM UTC 24
Finished Oct 12 11:52:33 AM UTC 24
Peak memory 278580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459294830 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_intg_err.459294830
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_read_seed_err.1826957656
Short name T182
Test name
Test status
Simulation time 136982200 ps
CPU time 22.42 seconds
Started Oct 12 12:11:21 PM UTC 24
Finished Oct 12 12:11:45 PM UTC 24
Peak memory 269016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1826957656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
1.flash_ctrl_hw_read_seed_err.1826957656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_prog_rma_wipe_err.1816688858
Short name T270
Test name
Test status
Simulation time 10012577300 ps
CPU time 161.26 seconds
Started Oct 12 12:50:41 PM UTC 24
Finished Oct 12 12:53:24 PM UTC 24
Peak memory 299748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1816688858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 11.flash_ctrl_hw_prog_rma_wipe_err.1816688858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_connect.1683403503
Short name T101
Test name
Test status
Simulation time 28301100 ps
CPU time 26.71 seconds
Started Oct 12 12:27:44 PM UTC 24
Finished Oct 12 12:28:12 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683403503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_connect.1683403503
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_host_grant_err.1510551669
Short name T81
Test name
Test status
Simulation time 49224900 ps
CPU time 21.52 seconds
Started Oct 12 12:06:34 PM UTC 24
Finished Oct 12 12:06:57 PM UTC 24
Peak memory 275516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=1510551669 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_host_grant_err.1510551669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_type.4058790102
Short name T108
Test name
Test status
Simulation time 3011308900 ps
CPU time 2697.78 seconds
Started Oct 12 12:13:11 PM UTC 24
Finished Oct 12 12:58:39 PM UTC 24
Peak memory 272916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=40
58790102 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl
_error_prog_type.4058790102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_prog_win.3725506275
Short name T205
Test name
Test status
Simulation time 679012300 ps
CPU time 1157.4 seconds
Started Oct 12 11:51:45 AM UTC 24
Finished Oct 12 12:11:19 PM UTC 24
Peak memory 285160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725506275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_prog_win.3725506275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd.4011160185
Short name T347
Test name
Test status
Simulation time 1450157900 ps
CPU time 161.75 seconds
Started Oct 12 12:57:36 PM UTC 24
Finished Oct 12 01:00:21 PM UTC 24
Peak memory 301756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4011160185 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_rd.4011160185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_sec_info_access.1842429635
Short name T396
Test name
Test status
Simulation time 5110456700 ps
CPU time 73.46 seconds
Started Oct 12 12:48:17 PM UTC 24
Finished Oct 12 12:49:32 PM UTC 24
Peak memory 272872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1842429635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sec_info_access.1842429635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma.2644483866
Short name T135
Test name
Test status
Simulation time 178926137600 ps
CPU time 1890.86 seconds
Started Oct 12 12:07:01 PM UTC 24
Finished Oct 12 12:38:54 PM UTC 24
Peak memory 277600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644483866
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma.2644483866
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_disable.373193222
Short name T122
Test name
Test status
Simulation time 12938300 ps
CPU time 41.37 seconds
Started Oct 12 01:07:20 PM UTC 24
Finished Oct 12 01:08:03 PM UTC 24
Peak memory 285256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=373193222 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_disable.373193222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict_all_en.904557384
Short name T422
Test name
Test status
Simulation time 91431300 ps
CPU time 51.08 seconds
Started Oct 12 01:03:30 PM UTC 24
Finished Oct 12 01:04:23 PM UTC 24
Peak memory 287620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=904557384 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ct
rl_rw_evict_all_en.904557384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_sec_info_access.1152382219
Short name T397
Test name
Test status
Simulation time 7014930300 ps
CPU time 68.17 seconds
Started Oct 12 01:09:37 PM UTC 24
Finished Oct 12 01:10:47 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152382219 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_sec_info_access.1152382219
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_sec_info_access.1686409688
Short name T403
Test name
Test status
Simulation time 432558200 ps
CPU time 87.8 seconds
Started Oct 12 01:10:57 PM UTC 24
Finished Oct 12 01:12:27 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686409688 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_sec_info_access.1686409688
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_mp_regions.1303077315
Short name T411
Test name
Test status
Simulation time 5092070500 ps
CPU time 179.64 seconds
Started Oct 12 12:28:32 PM UTC 24
Finished Oct 12 12:31:35 PM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1303077315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 5.flash_ctrl_mp_regions.1303077315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_derr.3585810684
Short name T215
Test name
Test status
Simulation time 1320321300 ps
CPU time 226.76 seconds
Started Oct 12 12:08:35 PM UTC 24
Finished Oct 12 12:12:26 PM UTC 24
Peak memory 295656 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3585810684 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 1.flash_ctrl_rw_derr.3585810684
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_derr.304690052
Short name T207
Test name
Test status
Simulation time 2581160200 ps
CPU time 130.73 seconds
Started Oct 12 12:25:34 PM UTC 24
Finished Oct 12 12:27:47 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304690052 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 4.flash_ctrl_ro_derr.304690052
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_rma_reset.586545983
Short name T186
Test name
Test status
Simulation time 50126484500 ps
CPU time 879.3 seconds
Started Oct 12 12:53:43 PM UTC 24
Finished Oct 12 01:08:33 PM UTC 24
Peak memory 274812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586545983 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_rma_reset.586545983
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb_redun.2878967345
Short name T167
Test name
Test status
Simulation time 695900700 ps
CPU time 27.52 seconds
Started Oct 12 12:06:29 PM UTC 24
Finished Oct 12 12:06:58 PM UTC 24
Peak memory 273228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=2878967345 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -
cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb_redun.2878967345
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_disable.1378946996
Short name T5
Test name
Test status
Simulation time 23222200 ps
CPU time 31.79 seconds
Started Oct 12 12:04:39 PM UTC 24
Finished Oct 12 12:05:13 PM UTC 24
Peak memory 285312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1378946996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_c
trl_disable.1378946996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_sec_otp.1368660272
Short name T316
Test name
Test status
Simulation time 3011580300 ps
CPU time 127.05 seconds
Started Oct 12 12:46:49 PM UTC 24
Finished Oct 12 12:48:58 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368660272 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_sec_otp.1368660272
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_full_mem_access.1713429269
Short name T214
Test name
Test status
Simulation time 378379470400 ps
CPU time 3238.49 seconds
Started Oct 12 12:12:37 PM UTC 24
Finished Oct 12 01:07:12 PM UTC 24
Peak memory 285296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713429269 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_full_mem_access.1713429269
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_bit_bash.2551755857
Short name T248
Test name
Test status
Simulation time 1146188500 ps
CPU time 59.79 seconds
Started Oct 12 11:26:20 AM UTC 24
Finished Oct 12 11:27:22 AM UTC 24
Peak memory 276404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2551755857 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_bit_bash.2551755857
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_errors.3956890967
Short name T250
Test name
Test status
Simulation time 221659300 ps
CPU time 27.73 seconds
Started Oct 12 11:28:13 AM UTC 24
Finished Oct 12 11:28:42 AM UTC 24
Peak memory 276552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956890967 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_errors.3956890967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_ro.290563606
Short name T13
Test name
Test status
Simulation time 2386294000 ps
CPU time 120.41 seconds
Started Oct 12 11:54:21 AM UTC 24
Finished Oct 12 11:56:24 AM UTC 24
Peak memory 307904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=290563606 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ro.290563606
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb_redun.902121589
Short name T170
Test name
Test status
Simulation time 891222500 ps
CPU time 29.19 seconds
Started Oct 12 12:17:58 PM UTC 24
Finished Oct 12 12:18:29 PM UTC 24
Peak memory 275308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=902121589 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 2.flash_ctrl_phy_arb_redun.902121589
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_lcmgr_intg.3897540419
Short name T652
Test name
Test status
Simulation time 130255300 ps
CPU time 18.9 seconds
Started Oct 12 12:53:22 PM UTC 24
Finished Oct 12 12:53:42 PM UTC 24
Peak memory 270892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3897540419 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.fla
sh_ctrl_lcmgr_intg.3897540419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_intr_test.2629049969
Short name T349
Test name
Test status
Simulation time 32286600 ps
CPU time 20.49 seconds
Started Oct 12 11:28:58 AM UTC 24
Finished Oct 12 11:29:20 AM UTC 24
Peak memory 274456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629049969 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_test.2629049969
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_intg_err.1710759238
Short name T352
Test name
Test status
Simulation time 1068833400 ps
CPU time 1200.51 seconds
Started Oct 12 11:29:20 AM UTC 24
Finished Oct 12 11:49:38 AM UTC 24
Peak memory 276532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1710759238 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_intg_err.1710759238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_intg_err.596915111
Short name T359
Test name
Test status
Simulation time 5059299800 ps
CPU time 1215.27 seconds
Started Oct 12 11:29:42 AM UTC 24
Finished Oct 12 11:50:14 AM UTC 24
Peak memory 276592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596915111 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_intg_err.596915111
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_tl_intg_err.1096548623
Short name T358
Test name
Test status
Simulation time 471714000 ps
CPU time 1384.73 seconds
Started Oct 12 11:27:22 AM UTC 24
Finished Oct 12 11:50:47 AM UTC 24
Peak memory 278580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1096548623 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_tl_intg_err.1096548623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_config_regwen.3615878325
Short name T247
Test name
Test status
Simulation time 33548300 ps
CPU time 20.89 seconds
Started Oct 12 12:06:43 PM UTC 24
Finished Oct 12 12:07:05 PM UTC 24
Peak memory 272960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3615878325 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_config_regwen.3615878325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_fs_sup.1327109995
Short name T104
Test name
Test status
Simulation time 321147500 ps
CPU time 43.9 seconds
Started Oct 12 12:06:28 PM UTC 24
Finished Oct 12 12:07:14 PM UTC 24
Peak memory 273144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327109
995 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_f
s_sup.1327109995
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_read_seed_err.1790619150
Short name T181
Test name
Test status
Simulation time 35058500 ps
CPU time 20.04 seconds
Started Oct 12 12:06:47 PM UTC 24
Finished Oct 12 12:07:08 PM UTC 24
Peak memory 275004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1790619150 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
0.flash_ctrl_hw_read_seed_err.1790619150
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict.3152680120
Short name T35
Test name
Test status
Simulation time 80148600 ps
CPU time 47.19 seconds
Started Oct 12 12:09:43 PM UTC 24
Finished Oct 12 12:10:32 PM UTC 24
Peak memory 287468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152680120 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw_evict.3152680120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw_evict_all_en.3759281904
Short name T51
Test name
Test status
Simulation time 185076400 ps
CPU time 47.71 seconds
Started Oct 12 12:10:05 PM UTC 24
Finished Oct 12 12:10:55 PM UTC 24
Peak memory 285376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3759281904 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ct
rl_rw_evict_all_en.3759281904
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_otp_reset.391002721
Short name T388
Test name
Test status
Simulation time 40264400 ps
CPU time 221.11 seconds
Started Oct 12 12:53:43 PM UTC 24
Finished Oct 12 12:57:27 PM UTC 24
Peak memory 274952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391002721 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_otp_reset.391002721
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_disable.109346100
Short name T120
Test name
Test status
Simulation time 12830100 ps
CPU time 35.48 seconds
Started Oct 12 01:00:20 PM UTC 24
Finished Oct 12 01:00:57 PM UTC 24
Peak memory 285256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=109346100 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_disable.109346100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_disable.3549899659
Short name T370
Test name
Test status
Simulation time 10027800 ps
CPU time 39.84 seconds
Started Oct 12 01:02:08 PM UTC 24
Finished Oct 12 01:02:49 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3549899659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_
ctrl_disable.3549899659
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_sec_info_access.3787224668
Short name T406
Test name
Test status
Simulation time 4517795300 ps
CPU time 71.64 seconds
Started Oct 12 01:02:14 PM UTC 24
Finished Oct 12 01:03:27 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3787224668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sec_info_access.3787224668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_sec_info_access.2957089212
Short name T756
Test name
Test status
Simulation time 2111516500 ps
CPU time 91.21 seconds
Started Oct 12 01:03:53 PM UTC 24
Finished Oct 12 01:05:27 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957089212 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sec_info_access.2957089212
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_disable.143969364
Short name T97
Test name
Test status
Simulation time 26847200 ps
CPU time 44.11 seconds
Started Oct 12 12:17:07 PM UTC 24
Finished Oct 12 12:17:53 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=143969364 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_disable.143969364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_sec_info_access.187551814
Short name T404
Test name
Test status
Simulation time 2035701300 ps
CPU time 107.63 seconds
Started Oct 12 01:08:03 PM UTC 24
Finished Oct 12 01:09:53 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187551814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_sec_info_access.187551814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_sec_info_access.3045649174
Short name T394
Test name
Test status
Simulation time 1594032800 ps
CPU time 79.41 seconds
Started Oct 12 01:11:23 PM UTC 24
Finished Oct 12 01:12:45 PM UTC 24
Peak memory 274908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045649174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_sec_info_access.3045649174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_disable.2819891165
Short name T372
Test name
Test status
Simulation time 99911400 ps
CPU time 42.92 seconds
Started Oct 12 01:12:32 PM UTC 24
Finished Oct 12 01:13:16 PM UTC 24
Peak memory 285252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2819891165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_
ctrl_disable.2819891165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict.71123899
Short name T416
Test name
Test status
Simulation time 69782400 ps
CPU time 45.72 seconds
Started Oct 12 01:12:58 PM UTC 24
Finished Oct 12 01:13:45 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71123899 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_rw_evict.71123899
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_disable.1250477280
Short name T393
Test name
Test status
Simulation time 16940400 ps
CPU time 40.75 seconds
Started Oct 12 01:17:48 PM UTC 24
Finished Oct 12 01:18:30 PM UTC 24
Peak memory 285336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1250477280 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_
ctrl_disable.1250477280
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr.4179272901
Short name T32
Test name
Test status
Simulation time 1919354000 ps
CPU time 74.69 seconds
Started Oct 12 12:01:58 PM UTC 24
Finished Oct 12 12:03:15 PM UTC 24
Peak memory 275020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179272901 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr.4179272901
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb_redun.208133113
Short name T168
Test name
Test status
Simulation time 695837200 ps
CPU time 37.38 seconds
Started Oct 12 12:22:32 PM UTC 24
Finished Oct 12 12:23:11 PM UTC 24
Peak memory 275288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=208133113 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 3.flash_ctrl_phy_arb_redun.208133113
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_intg_err.3867625083
Short name T255
Test name
Test status
Simulation time 1645549000 ps
CPU time 737.28 seconds
Started Oct 12 11:29:06 AM UTC 24
Finished Oct 12 11:41:34 AM UTC 24
Peak memory 276696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867625083 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_intg_err.3867625083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_ack_consistency.3035099389
Short name T204
Test name
Test status
Simulation time 66400500 ps
CPU time 22.68 seconds
Started Oct 12 12:06:35 PM UTC 24
Finished Oct 12 12:06:59 PM UTC 24
Peak memory 273264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3035099389 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_ack_consistency.3035099389
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_error_mp.568352592
Short name T276
Test name
Test status
Simulation time 9768412000 ps
CPU time 3061.93 seconds
Started Oct 12 11:52:24 AM UTC 24
Finished Oct 12 12:44:03 PM UTC 24
Peak memory 275640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=568352592 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_error_mp.568352592
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw.551997273
Short name T56
Test name
Test status
Simulation time 9583537600 ps
CPU time 557.56 seconds
Started Oct 12 11:54:37 AM UTC 24
Finished Oct 12 12:04:03 PM UTC 24
Peak memory 320156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551997273 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw.551997273
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_ctrl_arb.3866310257
Short name T211
Test name
Test status
Simulation time 298331596300 ps
CPU time 3423.9 seconds
Started Oct 12 12:07:01 PM UTC 24
Finished Oct 12 01:04:42 PM UTC 24
Peak memory 277744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3866310257 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_ctrl_arb.3866310257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_invalid_op.3456581618
Short name T323
Test name
Test status
Simulation time 1579058400 ps
CPU time 89.76 seconds
Started Oct 12 01:02:56 PM UTC 24
Finished Oct 12 01:04:28 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3456581618 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_invalid_op.3456581618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_aliasing.733182907
Short name T234
Test name
Test status
Simulation time 296666600 ps
CPU time 41.56 seconds
Started Oct 12 11:26:20 AM UTC 24
Finished Oct 12 11:27:03 AM UTC 24
Peak memory 274568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733182907 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_aliasing.733182907
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_hw_reset.1776030545
Short name T281
Test name
Test status
Simulation time 71228500 ps
CPU time 70.34 seconds
Started Oct 12 11:26:19 AM UTC 24
Finished Oct 12 11:27:31 AM UTC 24
Peak memory 276412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776030545 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_csr_hw_reset.1776030545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_csr_mem_rw_with_rand_reset.1867711590
Short name T76
Test name
Test status
Simulation time 72076400 ps
CPU time 27.13 seconds
Started Oct 12 11:26:22 AM UTC 24
Finished Oct 12 11:26:51 AM UTC 24
Peak memory 290816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1867711590 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 0.flash_ctrl_csr_mem_rw_with_rand_reset.1867711590
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_partial_access.2158378519
Short name T228
Test name
Test status
Simulation time 15667600 ps
CPU time 21.05 seconds
Started Oct 12 11:26:18 AM UTC 24
Finished Oct 12 11:26:40 AM UTC 24
Peak memory 276568 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158378519 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_partial_access.2158378519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_mem_walk.2674321097
Short name T1135
Test name
Test status
Simulation time 18757200 ps
CPU time 22.79 seconds
Started Oct 12 11:26:18 AM UTC 24
Finished Oct 12 11:26:42 AM UTC 24
Peak memory 274376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674321097 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_mem_walk.2674321097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_same_csr_outstanding.2848346724
Short name T233
Test name
Test status
Simulation time 33772000 ps
CPU time 26.63 seconds
Started Oct 12 11:26:21 AM UTC 24
Finished Oct 12 11:26:49 AM UTC 24
Peak memory 274360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2848346724 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_
same_csr_outstanding.2848346724
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors.2682389260
Short name T1134
Test name
Test status
Simulation time 13024900 ps
CPU time 20.59 seconds
Started Oct 12 11:26:16 AM UTC 24
Finished Oct 12 11:26:38 AM UTC 24
Peak memory 274496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=268
2389260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sha
dow_reg_errors.2682389260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_shadow_reg_errors_with_csr_rw.397660658
Short name T1136
Test name
Test status
Simulation time 41605200 ps
CPU time 24.15 seconds
Started Oct 12 11:26:17 AM UTC 24
Finished Oct 12 11:26:42 AM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=397660658 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.397660658
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_errors.3039814333
Short name T129
Test name
Test status
Simulation time 70570800 ps
CPU time 24.71 seconds
Started Oct 12 11:26:15 AM UTC 24
Finished Oct 12 11:26:41 AM UTC 24
Peak memory 276552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3039814333 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_errors.3039814333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/0.flash_ctrl_tl_intg_err.3749197069
Short name T354
Test name
Test status
Simulation time 403607000 ps
CPU time 1377.95 seconds
Started Oct 12 11:26:15 AM UTC 24
Finished Oct 12 11:49:32 AM UTC 24
Peak memory 278592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749197069 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_tl_intg_err.3749197069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_aliasing.224119922
Short name T237
Test name
Test status
Simulation time 494373200 ps
CPU time 44.6 seconds
Started Oct 12 11:26:41 AM UTC 24
Finished Oct 12 11:27:27 AM UTC 24
Peak memory 274552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=224119922 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_aliasing.224119922
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_bit_bash.325552049
Short name T285
Test name
Test status
Simulation time 12148066600 ps
CPU time 115.55 seconds
Started Oct 12 11:26:41 AM UTC 24
Finished Oct 12 11:28:39 AM UTC 24
Peak memory 276428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325552049 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_bit_bash.325552049
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_hw_reset.242764699
Short name T1150
Test name
Test status
Simulation time 37675000 ps
CPU time 73.92 seconds
Started Oct 12 11:26:38 AM UTC 24
Finished Oct 12 11:27:54 AM UTC 24
Peak memory 274376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242764699 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_hw_reset.242764699
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_csr_rw.2325223777
Short name T77
Test name
Test status
Simulation time 93470700 ps
CPU time 22.03 seconds
Started Oct 12 11:26:39 AM UTC 24
Finished Oct 12 11:27:02 AM UTC 24
Peak memory 274556 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2325223777 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_csr_rw.2325223777
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_intr_test.948704303
Short name T246
Test name
Test status
Simulation time 17780700 ps
CPU time 25.76 seconds
Started Oct 12 11:26:26 AM UTC 24
Finished Oct 12 11:26:53 AM UTC 24
Peak memory 274172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948704303 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_test.948704303
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_partial_access.1465333626
Short name T229
Test name
Test status
Simulation time 42930900 ps
CPU time 21.08 seconds
Started Oct 12 11:26:32 AM UTC 24
Finished Oct 12 11:26:54 AM UTC 24
Peak memory 276356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465333626 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_partial_access.1465333626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_mem_walk.222383887
Short name T1139
Test name
Test status
Simulation time 41870000 ps
CPU time 21.84 seconds
Started Oct 12 11:26:30 AM UTC 24
Finished Oct 12 11:26:53 AM UTC 24
Peak memory 274384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222383887 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_mem_walk.222383887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_same_csr_outstanding.3886916234
Short name T249
Test name
Test status
Simulation time 154330900 ps
CPU time 45.39 seconds
Started Oct 12 11:26:42 AM UTC 24
Finished Oct 12 11:27:29 AM UTC 24
Peak memory 276400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3886916234 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_
same_csr_outstanding.3886916234
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors.2645096282
Short name T1137
Test name
Test status
Simulation time 38914400 ps
CPU time 23.83 seconds
Started Oct 12 11:26:24 AM UTC 24
Finished Oct 12 11:26:49 AM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264
5096282 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sha
dow_reg_errors.2645096282
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_shadow_reg_errors_with_csr_rw.847565411
Short name T1138
Test name
Test status
Simulation time 12292300 ps
CPU time 25.46 seconds
Started Oct 12 11:26:24 AM UTC 24
Finished Oct 12 11:26:51 AM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=847565411 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.847565411
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/1.flash_ctrl_tl_errors.2770216460
Short name T132
Test name
Test status
Simulation time 69821500 ps
CPU time 29.12 seconds
Started Oct 12 11:26:24 AM UTC 24
Finished Oct 12 11:26:55 AM UTC 24
Peak memory 276376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770216460 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_tl_errors.2770216460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_mem_rw_with_rand_reset.1771206165
Short name T258
Test name
Test status
Simulation time 481313700 ps
CPU time 27.83 seconds
Started Oct 12 11:28:42 AM UTC 24
Finished Oct 12 11:29:12 AM UTC 24
Peak memory 276612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1771206165 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 10.flash_ctrl_csr_mem_rw_with_rand_reset.1771206165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_csr_rw.690301823
Short name T1178
Test name
Test status
Simulation time 290841700 ps
CPU time 25.99 seconds
Started Oct 12 11:28:40 AM UTC 24
Finished Oct 12 11:29:08 AM UTC 24
Peak memory 274632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690301823 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_csr_rw.690301823
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_intr_test.843807713
Short name T1174
Test name
Test status
Simulation time 17257200 ps
CPU time 21.6 seconds
Started Oct 12 11:28:40 AM UTC 24
Finished Oct 12 11:29:03 AM UTC 24
Peak memory 274396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843807713 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_test.843807713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_same_csr_outstanding.917461357
Short name T289
Test name
Test status
Simulation time 402293700 ps
CPU time 30.82 seconds
Started Oct 12 11:28:42 AM UTC 24
Finished Oct 12 11:29:15 AM UTC 24
Peak memory 274384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
917461357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_
same_csr_outstanding.917461357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors.1295849152
Short name T1175
Test name
Test status
Simulation time 14569100 ps
CPU time 24.22 seconds
Started Oct 12 11:28:40 AM UTC 24
Finished Oct 12 11:29:06 AM UTC 24
Peak memory 274244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129
5849152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_sh
adow_reg_errors.1295849152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_shadow_reg_errors_with_csr_rw.2115045708
Short name T1177
Test name
Test status
Simulation time 12212500 ps
CPU time 25.61 seconds
Started Oct 12 11:28:40 AM UTC 24
Finished Oct 12 11:29:07 AM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2115045708 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.f
lash_ctrl_shadow_reg_errors_with_csr_rw.2115045708
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/10.flash_ctrl_tl_errors.1814201557
Short name T256
Test name
Test status
Simulation time 96112800 ps
CPU time 29.11 seconds
Started Oct 12 11:28:34 AM UTC 24
Finished Oct 12 11:29:04 AM UTC 24
Peak memory 276376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814201557 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_tl_errors.1814201557
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_mem_rw_with_rand_reset.1083194868
Short name T291
Test name
Test status
Simulation time 113110600 ps
CPU time 23.09 seconds
Started Oct 12 11:28:51 AM UTC 24
Finished Oct 12 11:29:16 AM UTC 24
Peak memory 276484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1083194868 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 11.flash_ctrl_csr_mem_rw_with_rand_reset.1083194868
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_csr_rw.3280638154
Short name T1182
Test name
Test status
Simulation time 45083500 ps
CPU time 24.89 seconds
Started Oct 12 11:28:48 AM UTC 24
Finished Oct 12 11:29:15 AM UTC 24
Peak memory 274360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280638154 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_csr_rw.3280638154
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_intr_test.3635464196
Short name T1179
Test name
Test status
Simulation time 16386900 ps
CPU time 20.77 seconds
Started Oct 12 11:28:48 AM UTC 24
Finished Oct 12 11:29:10 AM UTC 24
Peak memory 274200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3635464196 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_test.3635464196
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_same_csr_outstanding.3760118020
Short name T1185
Test name
Test status
Simulation time 130560300 ps
CPU time 27.93 seconds
Started Oct 12 11:28:50 AM UTC 24
Finished Oct 12 11:29:20 AM UTC 24
Peak memory 274376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3760118020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl
_same_csr_outstanding.3760118020
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors.3003103267
Short name T1180
Test name
Test status
Simulation time 51794900 ps
CPU time 24.4 seconds
Started Oct 12 11:28:46 AM UTC 24
Finished Oct 12 11:29:12 AM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300
3103267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sh
adow_reg_errors.3003103267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_shadow_reg_errors_with_csr_rw.1341663229
Short name T1181
Test name
Test status
Simulation time 105009300 ps
CPU time 24.66 seconds
Started Oct 12 11:28:46 AM UTC 24
Finished Oct 12 11:29:12 AM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1341663229 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1341663229
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_errors.1033583153
Short name T257
Test name
Test status
Simulation time 67953500 ps
CPU time 24.98 seconds
Started Oct 12 11:28:44 AM UTC 24
Finished Oct 12 11:29:10 AM UTC 24
Peak memory 276616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033583153 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_errors.1033583153
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/11.flash_ctrl_tl_intg_err.2849493479
Short name T1267
Test name
Test status
Simulation time 357341700 ps
CPU time 1412.17 seconds
Started Oct 12 11:28:46 AM UTC 24
Finished Oct 12 11:52:38 AM UTC 24
Peak memory 278580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849493479 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_tl_intg_err.2849493479
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_mem_rw_with_rand_reset.1908953333
Short name T294
Test name
Test status
Simulation time 412668600 ps
CPU time 26.08 seconds
Started Oct 12 11:29:06 AM UTC 24
Finished Oct 12 11:29:34 AM UTC 24
Peak memory 286916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1908953333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 12.flash_ctrl_csr_mem_rw_with_rand_reset.1908953333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_csr_rw.3357629972
Short name T1186
Test name
Test status
Simulation time 54576400 ps
CPU time 25.4 seconds
Started Oct 12 11:29:02 AM UTC 24
Finished Oct 12 11:29:29 AM UTC 24
Peak memory 274376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357629972 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_csr_rw.3357629972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_same_csr_outstanding.4106807972
Short name T293
Test name
Test status
Simulation time 400392100 ps
CPU time 26.6 seconds
Started Oct 12 11:29:04 AM UTC 24
Finished Oct 12 11:29:32 AM UTC 24
Peak memory 276604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4106807972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl
_same_csr_outstanding.4106807972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors.4015164304
Short name T1184
Test name
Test status
Simulation time 20069400 ps
CPU time 21.19 seconds
Started Oct 12 11:28:57 AM UTC 24
Finished Oct 12 11:29:19 AM UTC 24
Peak memory 274244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401
5164304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sh
adow_reg_errors.4015164304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_shadow_reg_errors_with_csr_rw.3233809728
Short name T1183
Test name
Test status
Simulation time 38781800 ps
CPU time 18.63 seconds
Started Oct 12 11:28:58 AM UTC 24
Finished Oct 12 11:29:18 AM UTC 24
Peak memory 274436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3233809728 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3233809728
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/12.flash_ctrl_tl_errors.1450918667
Short name T260
Test name
Test status
Simulation time 81769500 ps
CPU time 24.43 seconds
Started Oct 12 11:28:54 AM UTC 24
Finished Oct 12 11:29:19 AM UTC 24
Peak memory 276616 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1450918667 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_tl_errors.1450918667
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_mem_rw_with_rand_reset.2758044401
Short name T1189
Test name
Test status
Simulation time 84333900 ps
CPU time 22.91 seconds
Started Oct 12 11:29:11 AM UTC 24
Finished Oct 12 11:29:35 AM UTC 24
Peak memory 291012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2758044401 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 13.flash_ctrl_csr_mem_rw_with_rand_reset.2758044401
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_csr_rw.2889653407
Short name T1191
Test name
Test status
Simulation time 124292600 ps
CPU time 25.49 seconds
Started Oct 12 11:29:09 AM UTC 24
Finished Oct 12 11:29:35 AM UTC 24
Peak memory 274368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889653407 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_csr_rw.2889653407
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_intr_test.1274795902
Short name T1190
Test name
Test status
Simulation time 18996700 ps
CPU time 26.43 seconds
Started Oct 12 11:29:08 AM UTC 24
Finished Oct 12 11:29:35 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274795902 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_test.1274795902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_same_csr_outstanding.3148284989
Short name T1205
Test name
Test status
Simulation time 281559600 ps
CPU time 46.27 seconds
Started Oct 12 11:29:11 AM UTC 24
Finished Oct 12 11:29:59 AM UTC 24
Peak memory 274372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3148284989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl
_same_csr_outstanding.3148284989
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors.554458326
Short name T1188
Test name
Test status
Simulation time 36620800 ps
CPU time 24.31 seconds
Started Oct 12 11:29:06 AM UTC 24
Finished Oct 12 11:29:32 AM UTC 24
Peak memory 274248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=554
458326 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sha
dow_reg_errors.554458326
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_shadow_reg_errors_with_csr_rw.3257805149
Short name T1187
Test name
Test status
Simulation time 15192600 ps
CPU time 20.48 seconds
Started Oct 12 11:29:08 AM UTC 24
Finished Oct 12 11:29:29 AM UTC 24
Peak memory 274240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3257805149 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3257805149
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/13.flash_ctrl_tl_errors.684460514
Short name T1192
Test name
Test status
Simulation time 72972300 ps
CPU time 28.43 seconds
Started Oct 12 11:29:06 AM UTC 24
Finished Oct 12 11:29:36 AM UTC 24
Peak memory 276380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684460514 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_tl_errors.684460514
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_mem_rw_with_rand_reset.3831221131
Short name T295
Test name
Test status
Simulation time 249581900 ps
CPU time 23.62 seconds
Started Oct 12 11:29:20 AM UTC 24
Finished Oct 12 11:29:45 AM UTC 24
Peak memory 286916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3831221131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 14.flash_ctrl_csr_mem_rw_with_rand_reset.3831221131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_csr_rw.3183893470
Short name T1197
Test name
Test status
Simulation time 43157300 ps
CPU time 25.25 seconds
Started Oct 12 11:29:16 AM UTC 24
Finished Oct 12 11:29:43 AM UTC 24
Peak memory 274368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3183893470 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_csr_rw.3183893470
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_intr_test.4088944638
Short name T1193
Test name
Test status
Simulation time 26826000 ps
CPU time 20.94 seconds
Started Oct 12 11:29:15 AM UTC 24
Finished Oct 12 11:29:37 AM UTC 24
Peak memory 274200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4088944638 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_intr_test.4088944638
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_same_csr_outstanding.851357354
Short name T1199
Test name
Test status
Simulation time 67385300 ps
CPU time 26.79 seconds
Started Oct 12 11:29:19 AM UTC 24
Finished Oct 12 11:29:47 AM UTC 24
Peak memory 276428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
851357354 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_
same_csr_outstanding.851357354
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors.3283335449
Short name T1194
Test name
Test status
Simulation time 94632600 ps
CPU time 24.51 seconds
Started Oct 12 11:29:13 AM UTC 24
Finished Oct 12 11:29:39 AM UTC 24
Peak memory 274244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328
3335449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sh
adow_reg_errors.3283335449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_shadow_reg_errors_with_csr_rw.1431862674
Short name T1195
Test name
Test status
Simulation time 14119500 ps
CPU time 24.94 seconds
Started Oct 12 11:29:15 AM UTC 24
Finished Oct 12 11:29:41 AM UTC 24
Peak memory 274304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1431862674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.f
lash_ctrl_shadow_reg_errors_with_csr_rw.1431862674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/14.flash_ctrl_tl_intg_err.3514717784
Short name T351
Test name
Test status
Simulation time 2918340700 ps
CPU time 1198.18 seconds
Started Oct 12 11:29:13 AM UTC 24
Finished Oct 12 11:49:28 AM UTC 24
Peak memory 276600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514717784 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_tl_intg_err.3514717784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_mem_rw_with_rand_reset.2076117736
Short name T1210
Test name
Test status
Simulation time 104693400 ps
CPU time 28.35 seconds
Started Oct 12 11:29:34 AM UTC 24
Finished Oct 12 11:30:04 AM UTC 24
Peak memory 286916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2076117736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 15.flash_ctrl_csr_mem_rw_with_rand_reset.2076117736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_csr_rw.25724525
Short name T1203
Test name
Test status
Simulation time 136591900 ps
CPU time 26.42 seconds
Started Oct 12 11:29:30 AM UTC 24
Finished Oct 12 11:29:58 AM UTC 24
Peak memory 274372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25724525 -assert n
opostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace
s/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_csr_rw.25724525
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_intr_test.3672648558
Short name T1202
Test name
Test status
Simulation time 16174800 ps
CPU time 23.35 seconds
Started Oct 12 11:29:30 AM UTC 24
Finished Oct 12 11:29:55 AM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672648558 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_test.3672648558
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_same_csr_outstanding.3755294381
Short name T1211
Test name
Test status
Simulation time 59527600 ps
CPU time 30.33 seconds
Started Oct 12 11:29:33 AM UTC 24
Finished Oct 12 11:30:05 AM UTC 24
Peak memory 274380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3755294381 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl
_same_csr_outstanding.3755294381
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors.3862396140
Short name T1198
Test name
Test status
Simulation time 13521500 ps
CPU time 24.18 seconds
Started Oct 12 11:29:20 AM UTC 24
Finished Oct 12 11:29:46 AM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386
2396140 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sh
adow_reg_errors.3862396140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_shadow_reg_errors_with_csr_rw.3653078536
Short name T1201
Test name
Test status
Simulation time 11316700 ps
CPU time 23.25 seconds
Started Oct 12 11:29:27 AM UTC 24
Finished Oct 12 11:29:52 AM UTC 24
Peak memory 274240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3653078536 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3653078536
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/15.flash_ctrl_tl_errors.1293154723
Short name T1200
Test name
Test status
Simulation time 828413600 ps
CPU time 27.17 seconds
Started Oct 12 11:29:20 AM UTC 24
Finished Oct 12 11:29:49 AM UTC 24
Peak memory 276352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293154723 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_tl_errors.1293154723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_mem_rw_with_rand_reset.1183351913
Short name T1215
Test name
Test status
Simulation time 39001800 ps
CPU time 28.58 seconds
Started Oct 12 11:29:39 AM UTC 24
Finished Oct 12 11:30:10 AM UTC 24
Peak memory 286720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1183351913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 16.flash_ctrl_csr_mem_rw_with_rand_reset.1183351913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_csr_rw.3944439100
Short name T1209
Test name
Test status
Simulation time 74425300 ps
CPU time 25.11 seconds
Started Oct 12 11:29:37 AM UTC 24
Finished Oct 12 11:30:04 AM UTC 24
Peak memory 276404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944439100 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_csr_rw.3944439100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_same_csr_outstanding.3426306694
Short name T1230
Test name
Test status
Simulation time 380906400 ps
CPU time 49.89 seconds
Started Oct 12 11:29:38 AM UTC 24
Finished Oct 12 11:30:30 AM UTC 24
Peak memory 276424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
3426306694 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl
_same_csr_outstanding.3426306694
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors.3020770360
Short name T1204
Test name
Test status
Simulation time 29191800 ps
CPU time 20.51 seconds
Started Oct 12 11:29:36 AM UTC 24
Finished Oct 12 11:29:58 AM UTC 24
Peak memory 274440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302
0770360 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_sh
adow_reg_errors.3020770360
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_shadow_reg_errors_with_csr_rw.3200225154
Short name T1207
Test name
Test status
Simulation time 24223000 ps
CPU time 23.54 seconds
Started Oct 12 11:29:36 AM UTC 24
Finished Oct 12 11:30:01 AM UTC 24
Peak memory 274216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3200225154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3200225154
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_errors.2110478009
Short name T1208
Test name
Test status
Simulation time 62235900 ps
CPU time 26.7 seconds
Started Oct 12 11:29:35 AM UTC 24
Finished Oct 12 11:30:03 AM UTC 24
Peak memory 276372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110478009 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_errors.2110478009
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/16.flash_ctrl_tl_intg_err.1413596441
Short name T357
Test name
Test status
Simulation time 703310500 ps
CPU time 733.9 seconds
Started Oct 12 11:29:35 AM UTC 24
Finished Oct 12 11:42:00 AM UTC 24
Peak memory 276500 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1413596441 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_tl_intg_err.1413596441
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_mem_rw_with_rand_reset.1587769562
Short name T1218
Test name
Test status
Simulation time 36732700 ps
CPU time 28.53 seconds
Started Oct 12 11:29:47 AM UTC 24
Finished Oct 12 11:30:17 AM UTC 24
Peak memory 286724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1587769562 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 17.flash_ctrl_csr_mem_rw_with_rand_reset.1587769562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_csr_rw.1877101669
Short name T1216
Test name
Test status
Simulation time 262059500 ps
CPU time 22.5 seconds
Started Oct 12 11:29:46 AM UTC 24
Finished Oct 12 11:30:10 AM UTC 24
Peak memory 274360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1877101669 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_csr_rw.1877101669
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_intr_test.1198801225
Short name T1213
Test name
Test status
Simulation time 26465000 ps
CPU time 20.94 seconds
Started Oct 12 11:29:45 AM UTC 24
Finished Oct 12 11:30:07 AM UTC 24
Peak memory 274376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198801225 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_test.1198801225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_same_csr_outstanding.2010397748
Short name T1221
Test name
Test status
Simulation time 230948300 ps
CPU time 31.04 seconds
Started Oct 12 11:29:46 AM UTC 24
Finished Oct 12 11:30:19 AM UTC 24
Peak memory 276488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2010397748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl
_same_csr_outstanding.2010397748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors.1939919636
Short name T1217
Test name
Test status
Simulation time 18271500 ps
CPU time 24.19 seconds
Started Oct 12 11:29:45 AM UTC 24
Finished Oct 12 11:30:11 AM UTC 24
Peak memory 274244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=193
9919636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_sh
adow_reg_errors.1939919636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_shadow_reg_errors_with_csr_rw.2965395518
Short name T1212
Test name
Test status
Simulation time 17560700 ps
CPU time 20.75 seconds
Started Oct 12 11:29:45 AM UTC 24
Finished Oct 12 11:30:07 AM UTC 24
Peak memory 274212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2965395518 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.f
lash_ctrl_shadow_reg_errors_with_csr_rw.2965395518
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/17.flash_ctrl_tl_errors.4277595784
Short name T1214
Test name
Test status
Simulation time 38012400 ps
CPU time 25.36 seconds
Started Oct 12 11:29:41 AM UTC 24
Finished Oct 12 11:30:07 AM UTC 24
Peak memory 276552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277595784 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_tl_errors.4277595784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_mem_rw_with_rand_reset.2866814033
Short name T1229
Test name
Test status
Simulation time 161587200 ps
CPU time 27.45 seconds
Started Oct 12 11:30:01 AM UTC 24
Finished Oct 12 11:30:30 AM UTC 24
Peak memory 286724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=2866814033 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 18.flash_ctrl_csr_mem_rw_with_rand_reset.2866814033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_csr_rw.2285198886
Short name T1225
Test name
Test status
Simulation time 33578500 ps
CPU time 25.45 seconds
Started Oct 12 11:29:59 AM UTC 24
Finished Oct 12 11:30:26 AM UTC 24
Peak memory 274360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285198886 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_csr_rw.2285198886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_intr_test.1567219451
Short name T1224
Test name
Test status
Simulation time 46086700 ps
CPU time 24.46 seconds
Started Oct 12 11:29:59 AM UTC 24
Finished Oct 12 11:30:25 AM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567219451 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_test.1567219451
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_same_csr_outstanding.2468081853
Short name T1223
Test name
Test status
Simulation time 147528100 ps
CPU time 23.01 seconds
Started Oct 12 11:30:00 AM UTC 24
Finished Oct 12 11:30:24 AM UTC 24
Peak memory 276604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2468081853 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl
_same_csr_outstanding.2468081853
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors.113068072
Short name T1219
Test name
Test status
Simulation time 57655200 ps
CPU time 24.29 seconds
Started Oct 12 11:29:53 AM UTC 24
Finished Oct 12 11:30:18 AM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=113
068072 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sha
dow_reg_errors.113068072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_shadow_reg_errors_with_csr_rw.966338503
Short name T1222
Test name
Test status
Simulation time 14469300 ps
CPU time 25.05 seconds
Started Oct 12 11:29:56 AM UTC 24
Finished Oct 12 11:30:22 AM UTC 24
Peak memory 274236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=966338503 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.966338503
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_errors.217598898
Short name T1220
Test name
Test status
Simulation time 67389300 ps
CPU time 28.65 seconds
Started Oct 12 11:29:48 AM UTC 24
Finished Oct 12 11:30:19 AM UTC 24
Peak memory 276428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217598898 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_errors.217598898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/18.flash_ctrl_tl_intg_err.505547991
Short name T261
Test name
Test status
Simulation time 349714600 ps
CPU time 1195.57 seconds
Started Oct 12 11:29:49 AM UTC 24
Finished Oct 12 11:50:02 AM UTC 24
Peak memory 276484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505547991 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_tl_intg_err.505547991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_mem_rw_with_rand_reset.3604861591
Short name T1239
Test name
Test status
Simulation time 209948400 ps
CPU time 28.64 seconds
Started Oct 12 11:30:08 AM UTC 24
Finished Oct 12 11:30:38 AM UTC 24
Peak memory 286720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3604861591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 19.flash_ctrl_csr_mem_rw_with_rand_reset.3604861591
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_csr_rw.1332901958
Short name T1228
Test name
Test status
Simulation time 135739000 ps
CPU time 21.93 seconds
Started Oct 12 11:30:06 AM UTC 24
Finished Oct 12 11:30:29 AM UTC 24
Peak memory 274352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1332901958 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_csr_rw.1332901958
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_intr_test.3427563015
Short name T1227
Test name
Test status
Simulation time 88385900 ps
CPU time 22.18 seconds
Started Oct 12 11:30:05 AM UTC 24
Finished Oct 12 11:30:28 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427563015 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_test.3427563015
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_same_csr_outstanding.4055070307
Short name T1238
Test name
Test status
Simulation time 61933100 ps
CPU time 27.97 seconds
Started Oct 12 11:30:08 AM UTC 24
Finished Oct 12 11:30:38 AM UTC 24
Peak memory 274344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
4055070307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl
_same_csr_outstanding.4055070307
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors.2515770308
Short name T1226
Test name
Test status
Simulation time 89844400 ps
CPU time 20.58 seconds
Started Oct 12 11:30:05 AM UTC 24
Finished Oct 12 11:30:27 AM UTC 24
Peak memory 273984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251
5770308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sh
adow_reg_errors.2515770308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_shadow_reg_errors_with_csr_rw.3149059103
Short name T1232
Test name
Test status
Simulation time 13370400 ps
CPU time 25.34 seconds
Started Oct 12 11:30:05 AM UTC 24
Finished Oct 12 11:30:32 AM UTC 24
Peak memory 274244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3149059103 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.f
lash_ctrl_shadow_reg_errors_with_csr_rw.3149059103
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_errors.4265525144
Short name T1236
Test name
Test status
Simulation time 77145800 ps
CPU time 31.44 seconds
Started Oct 12 11:30:02 AM UTC 24
Finished Oct 12 11:30:35 AM UTC 24
Peak memory 276356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265525144 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_errors.4265525144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/19.flash_ctrl_tl_intg_err.3687932917
Short name T360
Test name
Test status
Simulation time 1793873800 ps
CPU time 1205.24 seconds
Started Oct 12 11:30:05 AM UTC 24
Finished Oct 12 11:50:27 AM UTC 24
Peak memory 276316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3687932917 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_tl_intg_err.3687932917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_aliasing.2278681804
Short name T365
Test name
Test status
Simulation time 878139700 ps
CPU time 44.76 seconds
Started Oct 12 11:26:55 AM UTC 24
Finished Oct 12 11:27:41 AM UTC 24
Peak memory 274488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278681804 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_aliasing.2278681804
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_hw_reset.695280842
Short name T1146
Test name
Test status
Simulation time 262996100 ps
CPU time 49.45 seconds
Started Oct 12 11:26:54 AM UTC 24
Finished Oct 12 11:27:45 AM UTC 24
Peak memory 276408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695280842 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_csr_hw_reset.695280842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_csr_mem_rw_with_rand_reset.3098328957
Short name T131
Test name
Test status
Simulation time 32641500 ps
CPU time 28.31 seconds
Started Oct 12 11:26:56 AM UTC 24
Finished Oct 12 11:27:26 AM UTC 24
Peak memory 292864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3098328957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 2.flash_ctrl_csr_mem_rw_with_rand_reset.3098328957
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_intr_test.2802563560
Short name T253
Test name
Test status
Simulation time 24210600 ps
CPU time 20.06 seconds
Started Oct 12 11:26:50 AM UTC 24
Finished Oct 12 11:27:12 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802563560 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_test.2802563560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_mem_walk.4267064659
Short name T1142
Test name
Test status
Simulation time 15506000 ps
CPU time 24.82 seconds
Started Oct 12 11:26:52 AM UTC 24
Finished Oct 12 11:27:18 AM UTC 24
Peak memory 274372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4267064659 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mem_walk.4267064659
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_same_csr_outstanding.2728891617
Short name T236
Test name
Test status
Simulation time 63413300 ps
CPU time 28.97 seconds
Started Oct 12 11:26:56 AM UTC 24
Finished Oct 12 11:27:26 AM UTC 24
Peak memory 276140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2728891617 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_
same_csr_outstanding.2728891617
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors.2591890016
Short name T1140
Test name
Test status
Simulation time 21501500 ps
CPU time 24.34 seconds
Started Oct 12 11:26:48 AM UTC 24
Finished Oct 12 11:27:14 AM UTC 24
Peak memory 274240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259
1890016 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sha
dow_reg_errors.2591890016
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_shadow_reg_errors_with_csr_rw.1882820127
Short name T1141
Test name
Test status
Simulation time 13315700 ps
CPU time 23.44 seconds
Started Oct 12 11:26:49 AM UTC 24
Finished Oct 12 11:27:14 AM UTC 24
Peak memory 274484 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1882820127 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1882820127
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/2.flash_ctrl_tl_intg_err.4265134648
Short name T355
Test name
Test status
Simulation time 891674200 ps
CPU time 1445.42 seconds
Started Oct 12 11:26:43 AM UTC 24
Finished Oct 12 11:51:09 AM UTC 24
Peak memory 278580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265134648 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_tl_intg_err.4265134648
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/20.flash_ctrl_intr_test.2849986164
Short name T1231
Test name
Test status
Simulation time 63635400 ps
CPU time 20.71 seconds
Started Oct 12 11:30:08 AM UTC 24
Finished Oct 12 11:30:30 AM UTC 24
Peak memory 274196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849986164 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_test.2849986164
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/21.flash_ctrl_intr_test.6464689
Short name T1233
Test name
Test status
Simulation time 54814800 ps
CPU time 21.52 seconds
Started Oct 12 11:30:10 AM UTC 24
Finished Oct 12 11:30:33 AM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6464689 -assert nopostproc +UVM_TESTNAME=flash_c
trl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_test.6464689
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/22.flash_ctrl_intr_test.3405994681
Short name T1235
Test name
Test status
Simulation time 26748300 ps
CPU time 20.95 seconds
Started Oct 12 11:30:12 AM UTC 24
Finished Oct 12 11:30:34 AM UTC 24
Peak memory 274196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405994681 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_test.3405994681
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/23.flash_ctrl_intr_test.36527473
Short name T1234
Test name
Test status
Simulation time 116682000 ps
CPU time 20.52 seconds
Started Oct 12 11:30:12 AM UTC 24
Finished Oct 12 11:30:33 AM UTC 24
Peak memory 274196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36527473 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_intr_test.36527473
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/24.flash_ctrl_intr_test.2136243227
Short name T1237
Test name
Test status
Simulation time 16139100 ps
CPU time 20.73 seconds
Started Oct 12 11:30:14 AM UTC 24
Finished Oct 12 11:30:36 AM UTC 24
Peak memory 274184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2136243227 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_test.2136243227
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/25.flash_ctrl_intr_test.86870945
Short name T1240
Test name
Test status
Simulation time 34374700 ps
CPU time 20.9 seconds
Started Oct 12 11:30:17 AM UTC 24
Finished Oct 12 11:30:39 AM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86870945 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_test.86870945
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/26.flash_ctrl_intr_test.3022851600
Short name T1241
Test name
Test status
Simulation time 18666500 ps
CPU time 20.38 seconds
Started Oct 12 11:30:19 AM UTC 24
Finished Oct 12 11:30:40 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3022851600 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_test.3022851600
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/27.flash_ctrl_intr_test.2343586982
Short name T1242
Test name
Test status
Simulation time 14914000 ps
CPU time 21 seconds
Started Oct 12 11:30:19 AM UTC 24
Finished Oct 12 11:30:41 AM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343586982 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_test.2343586982
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/28.flash_ctrl_intr_test.1768557016
Short name T1243
Test name
Test status
Simulation time 26033700 ps
CPU time 20.81 seconds
Started Oct 12 11:30:20 AM UTC 24
Finished Oct 12 11:30:42 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1768557016 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_test.1768557016
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/29.flash_ctrl_intr_test.2613616281
Short name T1244
Test name
Test status
Simulation time 30845800 ps
CPU time 21.42 seconds
Started Oct 12 11:30:20 AM UTC 24
Finished Oct 12 11:30:43 AM UTC 24
Peak memory 274200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613616281 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_test.2613616281
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_aliasing.788514861
Short name T1163
Test name
Test status
Simulation time 5042329700 ps
CPU time 81.75 seconds
Started Oct 12 11:27:15 AM UTC 24
Finished Oct 12 11:28:39 AM UTC 24
Peak memory 274488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=788514861 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_aliasing.788514861
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_bit_bash.2847327892
Short name T364
Test name
Test status
Simulation time 1148667400 ps
CPU time 55.28 seconds
Started Oct 12 11:27:14 AM UTC 24
Finished Oct 12 11:28:11 AM UTC 24
Peak memory 276620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847327892 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_bit_bash.2847327892
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_hw_reset.1935378068
Short name T1152
Test name
Test status
Simulation time 20610300 ps
CPU time 47.85 seconds
Started Oct 12 11:27:13 AM UTC 24
Finished Oct 12 11:28:02 AM UTC 24
Peak memory 276428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1935378068 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_hw_reset.1935378068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_mem_rw_with_rand_reset.1911324195
Short name T225
Test name
Test status
Simulation time 355183500 ps
CPU time 26 seconds
Started Oct 12 11:27:18 AM UTC 24
Finished Oct 12 11:27:45 AM UTC 24
Peak memory 286728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1911324195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 3.flash_ctrl_csr_mem_rw_with_rand_reset.1911324195
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_csr_rw.1506385769
Short name T304
Test name
Test status
Simulation time 96788400 ps
CPU time 26.36 seconds
Started Oct 12 11:27:14 AM UTC 24
Finished Oct 12 11:27:41 AM UTC 24
Peak memory 276424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1506385769 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_csr_rw.1506385769
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_intr_test.3281933449
Short name T327
Test name
Test status
Simulation time 15931100 ps
CPU time 21.18 seconds
Started Oct 12 11:27:09 AM UTC 24
Finished Oct 12 11:27:31 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281933449 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_test.3281933449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_partial_access.3812417881
Short name T231
Test name
Test status
Simulation time 18135100 ps
CPU time 24.88 seconds
Started Oct 12 11:27:13 AM UTC 24
Finished Oct 12 11:27:39 AM UTC 24
Peak memory 276364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812417881 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_partial_access.3812417881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_mem_walk.1819510775
Short name T1145
Test name
Test status
Simulation time 45189600 ps
CPU time 20.32 seconds
Started Oct 12 11:27:10 AM UTC 24
Finished Oct 12 11:27:31 AM UTC 24
Peak memory 274388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819510775 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mem_walk.1819510775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_same_csr_outstanding.1039390675
Short name T1154
Test name
Test status
Simulation time 761920300 ps
CPU time 53.92 seconds
Started Oct 12 11:27:15 AM UTC 24
Finished Oct 12 11:28:11 AM UTC 24
Peak memory 276420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1039390675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_
same_csr_outstanding.1039390675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors.1606490817
Short name T1144
Test name
Test status
Simulation time 29562200 ps
CPU time 24.51 seconds
Started Oct 12 11:27:04 AM UTC 24
Finished Oct 12 11:27:30 AM UTC 24
Peak memory 274248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160
6490817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sha
dow_reg_errors.1606490817
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_shadow_reg_errors_with_csr_rw.1365298588
Short name T1143
Test name
Test status
Simulation time 13020800 ps
CPU time 20.87 seconds
Started Oct 12 11:27:05 AM UTC 24
Finished Oct 12 11:27:28 AM UTC 24
Peak memory 274436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1365298588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1365298588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_errors.2366091704
Short name T224
Test name
Test status
Simulation time 73371300 ps
CPU time 27.9 seconds
Started Oct 12 11:26:57 AM UTC 24
Finished Oct 12 11:27:26 AM UTC 24
Peak memory 276360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366091704 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_errors.2366091704
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/3.flash_ctrl_tl_intg_err.2095520420
Short name T243
Test name
Test status
Simulation time 1403315200 ps
CPU time 719.72 seconds
Started Oct 12 11:26:58 AM UTC 24
Finished Oct 12 11:39:08 AM UTC 24
Peak memory 276488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2095520420 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_tl_intg_err.2095520420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/30.flash_ctrl_intr_test.646639539
Short name T1245
Test name
Test status
Simulation time 20406700 ps
CPU time 21.64 seconds
Started Oct 12 11:30:23 AM UTC 24
Finished Oct 12 11:30:46 AM UTC 24
Peak memory 274196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=646639539 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_test.646639539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/31.flash_ctrl_intr_test.1787417438
Short name T1246
Test name
Test status
Simulation time 59871200 ps
CPU time 20.87 seconds
Started Oct 12 11:30:25 AM UTC 24
Finished Oct 12 11:30:47 AM UTC 24
Peak memory 274184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787417438 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_test.1787417438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/32.flash_ctrl_intr_test.831071585
Short name T1248
Test name
Test status
Simulation time 28979300 ps
CPU time 22.26 seconds
Started Oct 12 11:30:25 AM UTC 24
Finished Oct 12 11:30:49 AM UTC 24
Peak memory 274268 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831071585 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_test.831071585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/33.flash_ctrl_intr_test.507742601
Short name T1247
Test name
Test status
Simulation time 14141200 ps
CPU time 21.13 seconds
Started Oct 12 11:30:26 AM UTC 24
Finished Oct 12 11:30:49 AM UTC 24
Peak memory 274196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507742601 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_test.507742601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/34.flash_ctrl_intr_test.1445806205
Short name T1249
Test name
Test status
Simulation time 43034400 ps
CPU time 20.3 seconds
Started Oct 12 11:30:27 AM UTC 24
Finished Oct 12 11:30:49 AM UTC 24
Peak memory 274264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445806205 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_test.1445806205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/35.flash_ctrl_intr_test.2152190526
Short name T1250
Test name
Test status
Simulation time 103237800 ps
CPU time 21.1 seconds
Started Oct 12 11:30:29 AM UTC 24
Finished Oct 12 11:30:52 AM UTC 24
Peak memory 274392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2152190526 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_test.2152190526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/36.flash_ctrl_intr_test.2892048223
Short name T1251
Test name
Test status
Simulation time 70990400 ps
CPU time 22.19 seconds
Started Oct 12 11:30:30 AM UTC 24
Finished Oct 12 11:30:54 AM UTC 24
Peak memory 274248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892048223 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_test.2892048223
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/37.flash_ctrl_intr_test.718132981
Short name T1252
Test name
Test status
Simulation time 18259700 ps
CPU time 22.33 seconds
Started Oct 12 11:30:30 AM UTC 24
Finished Oct 12 11:30:54 AM UTC 24
Peak memory 274396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718132981 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_test.718132981
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/38.flash_ctrl_intr_test.599578097
Short name T1256
Test name
Test status
Simulation time 37308700 ps
CPU time 24.29 seconds
Started Oct 12 11:30:31 AM UTC 24
Finished Oct 12 11:30:57 AM UTC 24
Peak memory 274196 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599578097 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_test.599578097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/39.flash_ctrl_intr_test.875363140
Short name T1253
Test name
Test status
Simulation time 17533000 ps
CPU time 21.54 seconds
Started Oct 12 11:30:32 AM UTC 24
Finished Oct 12 11:30:54 AM UTC 24
Peak memory 274200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875363140 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_test.875363140
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_aliasing.3639257085
Short name T367
Test name
Test status
Simulation time 652549100 ps
CPU time 45.34 seconds
Started Oct 12 11:27:32 AM UTC 24
Finished Oct 12 11:28:19 AM UTC 24
Peak memory 274380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639257085 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_aliasing.3639257085
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_bit_bash.2887123993
Short name T292
Test name
Test status
Simulation time 18181294900 ps
CPU time 112.24 seconds
Started Oct 12 11:27:31 AM UTC 24
Finished Oct 12 11:29:26 AM UTC 24
Peak memory 276412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2887123993 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_bit_bash.2887123993
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_hw_reset.2167687335
Short name T286
Test name
Test status
Simulation time 85884100 ps
CPU time 68.52 seconds
Started Oct 12 11:27:29 AM UTC 24
Finished Oct 12 11:28:39 AM UTC 24
Peak memory 276412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2167687335 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_hw_reset.2167687335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_mem_rw_with_rand_reset.413193609
Short name T227
Test name
Test status
Simulation time 166169900 ps
CPU time 25.79 seconds
Started Oct 12 11:27:32 AM UTC 24
Finished Oct 12 11:27:59 AM UTC 24
Peak memory 276480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=413193609 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 4.flash_ctrl_csr_mem_rw_with_rand_reset.413193609
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_csr_rw.2976891903
Short name T366
Test name
Test status
Simulation time 22850400 ps
CPU time 21.33 seconds
Started Oct 12 11:27:30 AM UTC 24
Finished Oct 12 11:27:52 AM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2976891903 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_csr_rw.2976891903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_intr_test.2675869490
Short name T328
Test name
Test status
Simulation time 42264900 ps
CPU time 21.22 seconds
Started Oct 12 11:27:27 AM UTC 24
Finished Oct 12 11:27:50 AM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2675869490 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_test.2675869490
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_partial_access.417720434
Short name T232
Test name
Test status
Simulation time 231009800 ps
CPU time 20.96 seconds
Started Oct 12 11:27:29 AM UTC 24
Finished Oct 12 11:27:51 AM UTC 24
Peak memory 276356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_mem_partial_access +en_scb=0 +cdc_instrumentation_enabled
=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417720434 -assert nopostproc
+UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_partial_access.417720434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_mem_partial_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_mem_walk.1999083800
Short name T1148
Test name
Test status
Simulation time 41217900 ps
CPU time 22.2 seconds
Started Oct 12 11:27:28 AM UTC 24
Finished Oct 12 11:27:51 AM UTC 24
Peak memory 274380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_mem_walk +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999083800 -assert nopostproc +UVM_TEST
NAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mem_walk.1999083800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_mem_walk/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_same_csr_outstanding.1243901291
Short name T1151
Test name
Test status
Simulation time 115632800 ps
CPU time 25.37 seconds
Started Oct 12 11:27:32 AM UTC 24
Finished Oct 12 11:27:59 AM UTC 24
Peak memory 276424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1243901291 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_
same_csr_outstanding.1243901291
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors.1005720301
Short name T1149
Test name
Test status
Simulation time 37860500 ps
CPU time 24.79 seconds
Started Oct 12 11:27:26 AM UTC 24
Finished Oct 12 11:27:52 AM UTC 24
Peak memory 274504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100
5720301 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sha
dow_reg_errors.1005720301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/4.flash_ctrl_shadow_reg_errors_with_csr_rw.3343819289
Short name T1147
Test name
Test status
Simulation time 14954400 ps
CPU time 23.24 seconds
Started Oct 12 11:27:26 AM UTC 24
Finished Oct 12 11:27:51 AM UTC 24
Peak memory 274240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3343819289 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.3343819289
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/40.flash_ctrl_intr_test.289343575
Short name T1258
Test name
Test status
Simulation time 42535600 ps
CPU time 23.68 seconds
Started Oct 12 11:30:33 AM UTC 24
Finished Oct 12 11:30:58 AM UTC 24
Peak memory 274248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=289343575 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_intr_test.289343575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/40.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/41.flash_ctrl_intr_test.2416843640
Short name T1254
Test name
Test status
Simulation time 14922000 ps
CPU time 21.62 seconds
Started Oct 12 11:30:34 AM UTC 24
Finished Oct 12 11:30:57 AM UTC 24
Peak memory 274376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416843640 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_intr_test.2416843640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/41.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/42.flash_ctrl_intr_test.4051170433
Short name T1257
Test name
Test status
Simulation time 44977800 ps
CPU time 22.24 seconds
Started Oct 12 11:30:34 AM UTC 24
Finished Oct 12 11:30:57 AM UTC 24
Peak memory 274252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4051170433 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_intr_test.4051170433
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/42.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/43.flash_ctrl_intr_test.2495384871
Short name T1255
Test name
Test status
Simulation time 23427100 ps
CPU time 20.67 seconds
Started Oct 12 11:30:35 AM UTC 24
Finished Oct 12 11:30:57 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495384871 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_intr_test.2495384871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/43.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/44.flash_ctrl_intr_test.3137428850
Short name T1259
Test name
Test status
Simulation time 65328500 ps
CPU time 21.02 seconds
Started Oct 12 11:30:36 AM UTC 24
Finished Oct 12 11:30:58 AM UTC 24
Peak memory 274392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137428850 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_intr_test.3137428850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/44.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/45.flash_ctrl_intr_test.4136702426
Short name T1260
Test name
Test status
Simulation time 51606500 ps
CPU time 21.79 seconds
Started Oct 12 11:30:37 AM UTC 24
Finished Oct 12 11:31:00 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136702426 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_intr_test.4136702426
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/45.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/46.flash_ctrl_intr_test.3756229836
Short name T1261
Test name
Test status
Simulation time 16625300 ps
CPU time 22.35 seconds
Started Oct 12 11:30:38 AM UTC 24
Finished Oct 12 11:31:02 AM UTC 24
Peak memory 274248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3756229836 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_intr_test.3756229836
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/46.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/47.flash_ctrl_intr_test.1527308777
Short name T1262
Test name
Test status
Simulation time 17412800 ps
CPU time 21.43 seconds
Started Oct 12 11:30:39 AM UTC 24
Finished Oct 12 11:31:02 AM UTC 24
Peak memory 274184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527308777 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_intr_test.1527308777
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/47.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/48.flash_ctrl_intr_test.1238801159
Short name T1263
Test name
Test status
Simulation time 57871700 ps
CPU time 22.27 seconds
Started Oct 12 11:30:39 AM UTC 24
Finished Oct 12 11:31:03 AM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1238801159 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_intr_test.1238801159
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/48.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/49.flash_ctrl_intr_test.95359819
Short name T1264
Test name
Test status
Simulation time 17110800 ps
CPU time 22.5 seconds
Started Oct 12 11:30:41 AM UTC 24
Finished Oct 12 11:31:05 AM UTC 24
Peak memory 274204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95359819 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_intr_test.95359819
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/49.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_mem_rw_with_rand_reset.3155462183
Short name T1160
Test name
Test status
Simulation time 75108500 ps
CPU time 32.85 seconds
Started Oct 12 11:27:52 AM UTC 24
Finished Oct 12 11:28:26 AM UTC 24
Peak memory 286920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=3155462183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 5.flash_ctrl_csr_mem_rw_with_rand_reset.3155462183
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_csr_rw.3976431271
Short name T290
Test name
Test status
Simulation time 66524800 ps
CPU time 26.12 seconds
Started Oct 12 11:27:50 AM UTC 24
Finished Oct 12 11:28:18 AM UTC 24
Peak memory 274368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3976431271 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_csr_rw.3976431271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_intr_test.2357561220
Short name T329
Test name
Test status
Simulation time 17185000 ps
CPU time 20.67 seconds
Started Oct 12 11:27:46 AM UTC 24
Finished Oct 12 11:28:08 AM UTC 24
Peak memory 274392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357561220 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_test.2357561220
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_same_csr_outstanding.1438058162
Short name T1158
Test name
Test status
Simulation time 165615900 ps
CPU time 30.39 seconds
Started Oct 12 11:27:51 AM UTC 24
Finished Oct 12 11:28:23 AM UTC 24
Peak memory 276420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1438058162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_
same_csr_outstanding.1438058162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors.3115249575
Short name T1153
Test name
Test status
Simulation time 12184400 ps
CPU time 24.4 seconds
Started Oct 12 11:27:42 AM UTC 24
Finished Oct 12 11:28:08 AM UTC 24
Peak memory 274240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311
5249575 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sha
dow_reg_errors.3115249575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_shadow_reg_errors_with_csr_rw.1680995314
Short name T1155
Test name
Test status
Simulation time 24413200 ps
CPU time 24.36 seconds
Started Oct 12 11:27:45 AM UTC 24
Finished Oct 12 11:28:11 AM UTC 24
Peak memory 274244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1680995314 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.1680995314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_errors.243435887
Short name T251
Test name
Test status
Simulation time 90781900 ps
CPU time 25.85 seconds
Started Oct 12 11:27:40 AM UTC 24
Finished Oct 12 11:28:07 AM UTC 24
Peak memory 276372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243435887 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_errors.243435887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/5.flash_ctrl_tl_intg_err.3137143453
Short name T242
Test name
Test status
Simulation time 1123105400 ps
CPU time 612.38 seconds
Started Oct 12 11:27:42 AM UTC 24
Finished Oct 12 11:38:04 AM UTC 24
Peak memory 276752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137143453 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_tl_intg_err.3137143453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_mem_rw_with_rand_reset.718014619
Short name T283
Test name
Test status
Simulation time 66952800 ps
CPU time 25.58 seconds
Started Oct 12 11:28:00 AM UTC 24
Finished Oct 12 11:28:27 AM UTC 24
Peak memory 286720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=718014619 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_lo
g /dev/null -cm_name 6.flash_ctrl_csr_mem_rw_with_rand_reset.718014619
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_csr_rw.1056231216
Short name T282
Test name
Test status
Simulation time 85845000 ps
CPU time 24.85 seconds
Started Oct 12 11:27:55 AM UTC 24
Finished Oct 12 11:28:21 AM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056231216 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_csr_rw.1056231216
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_intr_test.2741199084
Short name T330
Test name
Test status
Simulation time 70883400 ps
CPU time 20.77 seconds
Started Oct 12 11:27:55 AM UTC 24
Finished Oct 12 11:28:17 AM UTC 24
Peak memory 274176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2741199084 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_test.2741199084
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_same_csr_outstanding.1920203578
Short name T1159
Test name
Test status
Simulation time 121716700 ps
CPU time 22.41 seconds
Started Oct 12 11:28:00 AM UTC 24
Finished Oct 12 11:28:24 AM UTC 24
Peak memory 274356 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1920203578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_
same_csr_outstanding.1920203578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors.2800853535
Short name T1156
Test name
Test status
Simulation time 13380400 ps
CPU time 19.98 seconds
Started Oct 12 11:27:54 AM UTC 24
Finished Oct 12 11:28:15 AM UTC 24
Peak memory 274224 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280
0853535 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sha
dow_reg_errors.2800853535
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_shadow_reg_errors_with_csr_rw.957752325
Short name T1157
Test name
Test status
Simulation time 28359200 ps
CPU time 23.58 seconds
Started Oct 12 11:27:54 AM UTC 24
Finished Oct 12 11:28:19 AM UTC 24
Peak memory 274420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=957752325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.957752325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_errors.1059883746
Short name T252
Test name
Test status
Simulation time 54073900 ps
CPU time 26.26 seconds
Started Oct 12 11:27:52 AM UTC 24
Finished Oct 12 11:28:19 AM UTC 24
Peak memory 276352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059883746 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_errors.1059883746
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/6.flash_ctrl_tl_intg_err.3503238526
Short name T1266
Test name
Test status
Simulation time 372345700 ps
CPU time 1449.04 seconds
Started Oct 12 11:27:54 AM UTC 24
Finished Oct 12 11:52:23 AM UTC 24
Peak memory 278584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503238526 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_tl_intg_err.3503238526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_csr_rw.1162182651
Short name T1164
Test name
Test status
Simulation time 104366900 ps
CPU time 26.26 seconds
Started Oct 12 11:28:12 AM UTC 24
Finished Oct 12 11:28:39 AM UTC 24
Peak memory 274360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1162182651 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_csr_rw.1162182651
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_intr_test.1646773567
Short name T331
Test name
Test status
Simulation time 21342200 ps
CPU time 22.41 seconds
Started Oct 12 11:28:10 AM UTC 24
Finished Oct 12 11:28:33 AM UTC 24
Peak memory 274192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646773567 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_test.1646773567
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_same_csr_outstanding.2325426357
Short name T287
Test name
Test status
Simulation time 3747346500 ps
CPU time 32.33 seconds
Started Oct 12 11:28:12 AM UTC 24
Finished Oct 12 11:28:46 AM UTC 24
Peak memory 276588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2325426357 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_
same_csr_outstanding.2325426357
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors.2645487455
Short name T1162
Test name
Test status
Simulation time 29875500 ps
CPU time 23.44 seconds
Started Oct 12 11:28:08 AM UTC 24
Finished Oct 12 11:28:33 AM UTC 24
Peak memory 274488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264
5487455 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sha
dow_reg_errors.2645487455
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_shadow_reg_errors_with_csr_rw.2795335039
Short name T1161
Test name
Test status
Simulation time 12835000 ps
CPU time 20.21 seconds
Started Oct 12 11:28:10 AM UTC 24
Finished Oct 12 11:28:31 AM UTC 24
Peak memory 274240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2795335039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.2795335039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_errors.291905378
Short name T254
Test name
Test status
Simulation time 134614000 ps
CPU time 23.93 seconds
Started Oct 12 11:28:03 AM UTC 24
Finished Oct 12 11:28:28 AM UTC 24
Peak memory 276376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291905378 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_errors.291905378
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/7.flash_ctrl_tl_intg_err.585699271
Short name T244
Test name
Test status
Simulation time 826932900 ps
CPU time 707.41 seconds
Started Oct 12 11:28:08 AM UTC 24
Finished Oct 12 11:40:06 AM UTC 24
Peak memory 276496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585699271 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_tl_intg_err.585699271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_mem_rw_with_rand_reset.1784898130
Short name T1167
Test name
Test status
Simulation time 177027600 ps
CPU time 23.9 seconds
Started Oct 12 11:28:22 AM UTC 24
Finished Oct 12 11:28:48 AM UTC 24
Peak memory 290888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1784898130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 8.flash_ctrl_csr_mem_rw_with_rand_reset.1784898130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_csr_rw.2449415572
Short name T288
Test name
Test status
Simulation time 145854600 ps
CPU time 25.55 seconds
Started Oct 12 11:28:20 AM UTC 24
Finished Oct 12 11:28:47 AM UTC 24
Peak memory 274368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449415572 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_csr_rw.2449415572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_intr_test.3213567838
Short name T332
Test name
Test status
Simulation time 54386500 ps
CPU time 21.02 seconds
Started Oct 12 11:28:19 AM UTC 24
Finished Oct 12 11:28:42 AM UTC 24
Peak memory 274248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213567838 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_test.3213567838
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_same_csr_outstanding.2791413477
Short name T1176
Test name
Test status
Simulation time 692641400 ps
CPU time 44.85 seconds
Started Oct 12 11:28:20 AM UTC 24
Finished Oct 12 11:29:07 AM UTC 24
Peak memory 276396 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
2791413477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_
same_csr_outstanding.2791413477
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors.669016705
Short name T1165
Test name
Test status
Simulation time 43656300 ps
CPU time 25.85 seconds
Started Oct 12 11:28:18 AM UTC 24
Finished Oct 12 11:28:45 AM UTC 24
Peak memory 274228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669
016705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_shad
ow_reg_errors.669016705
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_shadow_reg_errors_with_csr_rw.3125088007
Short name T1166
Test name
Test status
Simulation time 29798800 ps
CPU time 24.77 seconds
Started Oct 12 11:28:19 AM UTC 24
Finished Oct 12 11:28:45 AM UTC 24
Peak memory 274436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3125088007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.fl
ash_ctrl_shadow_reg_errors_with_csr_rw.3125088007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/8.flash_ctrl_tl_intg_err.2860934555
Short name T356
Test name
Test status
Simulation time 1471777000 ps
CPU time 726.08 seconds
Started Oct 12 11:28:16 AM UTC 24
Finished Oct 12 11:40:33 AM UTC 24
Peak memory 276688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860934555 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_tl_intg_err.2860934555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_mem_rw_with_rand_reset.1820951322
Short name T1173
Test name
Test status
Simulation time 91212900 ps
CPU time 25.98 seconds
Started Oct 12 11:28:34 AM UTC 24
Finished Oct 12 11:29:01 AM UTC 24
Peak memory 288772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +
csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw
/dv/tools/sim.tcl +ntb_random_seed=1820951322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_l
og /dev/null -cm_name 9.flash_ctrl_csr_mem_rw_with_rand_reset.1820951322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_csr_rw.2229173270
Short name T1172
Test name
Test status
Simulation time 30582500 ps
CPU time 25 seconds
Started Oct 12 11:28:31 AM UTC 24
Finished Oct 12 11:28:57 AM UTC 24
Peak memory 274360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +csr_test_mode=1 +en_scb=0 +en_scb=0 +cdc_instrumentat
ion_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229173270 -assert
nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspa
ces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_csr_rw.2229173270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_intr_test.1538952081
Short name T1168
Test name
Test status
Simulation time 28126400 ps
CPU time 20.15 seconds
Started Oct 12 11:28:29 AM UTC 24
Finished Oct 12 11:28:50 AM UTC 24
Peak memory 274392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538952081 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_test.1538952081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_same_csr_outstanding.1645953822
Short name T1171
Test name
Test status
Simulation time 71089700 ps
CPU time 22.95 seconds
Started Oct 12 11:28:32 AM UTC 24
Finished Oct 12 11:28:56 AM UTC 24
Peak memory 274372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +csr_test_mode=1 +en_scb=0 +en_scb=0
+cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=
1645953822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_
same_csr_outstanding.1645953822
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors.3307124195
Short name T1169
Test name
Test status
Simulation time 14550600 ps
CPU time 24.63 seconds
Started Oct 12 11:28:27 AM UTC 24
Finished Oct 12 11:28:53 AM UTC 24
Peak memory 274248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors +csr_test_mode=1 +en_scb=0 +en_scb=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330
7124195 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sha
dow_reg_errors.3307124195
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_shadow_reg_errors_with_csr_rw.160775288
Short name T1170
Test name
Test status
Simulation time 18301200 ps
CPU time 23.98 seconds
Started Oct 12 11:28:28 AM UTC 24
Finished Oct 12 11:28:53 AM UTC 24
Peak memory 274220 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_shadow_reg_errors_with_csr_rw +csr_test_mode=1 +en_scb=0
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=160775288 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.fla
sh_ctrl_shadow_reg_errors_with_csr_rw.160775288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_shadow_reg_errors_with_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_errors.452601177
Short name T259
Test name
Test status
Simulation time 32685500 ps
CPU time 23.98 seconds
Started Oct 12 11:28:25 AM UTC 24
Finished Oct 12 11:28:50 AM UTC 24
Peak memory 276300 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452601177 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_errors.452601177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top/9.flash_ctrl_tl_intg_err.3439623114
Short name T1265
Test name
Test status
Simulation time 919784600 ps
CPU time 1220.97 seconds
Started Oct 12 11:28:25 AM UTC 24
Finished Oct 12 11:49:03 AM UTC 24
Peak memory 278536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439623114 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_tl_intg_err.3439623114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_connect.2389554210
Short name T23
Test name
Test status
Simulation time 38650200 ps
CPU time 20.01 seconds
Started Oct 12 12:05:27 PM UTC 24
Finished Oct 12 12:05:48 PM UTC 24
Peak memory 294936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389554210 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_connect.2389554210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_derr_detect.693642772
Short name T62
Test name
Test status
Simulation time 1235834200 ps
CPU time 252.52 seconds
Started Oct 12 11:59:00 AM UTC 24
Finished Oct 12 12:03:17 PM UTC 24
Peak memory 289664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=693642772 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -
cm_name 0.flash_ctrl_derr_detect.693642772
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_full_mem_access.3334131144
Short name T151
Test name
Test status
Simulation time 55761123600 ps
CPU time 3529.51 seconds
Started Oct 12 11:51:10 AM UTC 24
Finished Oct 12 12:50:42 PM UTC 24
Peak memory 287820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334131144 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_full_mem_access.3334131144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_addr_infection.3257351382
Short name T383
Test name
Test status
Simulation time 27522400 ps
CPU time 46.18 seconds
Started Oct 12 12:06:49 PM UTC 24
Finished Oct 12 12:07:37 PM UTC 24
Peak memory 277004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325735138
2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ho
st_addr_infection.3257351382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_host_ctrl_arb.2298802577
Short name T611
Test name
Test status
Simulation time 277915452400 ps
CPU time 3432.22 seconds
Started Oct 12 11:50:28 AM UTC 24
Finished Oct 12 12:48:22 PM UTC 24
Peak memory 277696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2298802577 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_host_ctrl_arb.2298802577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_rma_reset.3342108262
Short name T6
Test name
Test status
Simulation time 40128471900 ps
CPU time 909.73 seconds
Started Oct 12 11:50:03 AM UTC 24
Finished Oct 12 12:05:26 PM UTC 24
Peak memory 274744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342108262
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_rma_reset.3342108262
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_hw_sec_otp.1735413615
Short name T11
Test name
Test status
Simulation time 1803701400 ps
CPU time 73.26 seconds
Started Oct 12 11:49:29 AM UTC 24
Finished Oct 12 11:50:44 AM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735413615 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_hw_sec_otp.1735413615
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_integrity.2825108618
Short name T219
Test name
Test status
Simulation time 23069898000 ps
CPU time 669.97 seconds
Started Oct 12 12:01:10 PM UTC 24
Finished Oct 12 12:12:30 PM UTC 24
Peak memory 336580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2825108618 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_integr
ity.2825108618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_rd_slow_flash.4037208628
Short name T78
Test name
Test status
Simulation time 6000310000 ps
CPU time 188.94 seconds
Started Oct 12 12:03:16 PM UTC 24
Finished Oct 12 12:06:28 PM UTC 24
Peak memory 303672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=4037208628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 0.flash_ctrl_intr_rd_slow_flash.4037208628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_intr_wr_slow_flash.3186929888
Short name T37
Test name
Test status
Simulation time 50875146900 ps
CPU time 300.17 seconds
Started Oct 12 12:03:18 PM UTC 24
Finished Oct 12 12:08:23 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186929888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 0.flash_ctrl_intr_wr_slow_flash.3186929888
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_phy_arb.2254287160
Short name T28
Test name
Test status
Simulation time 1514186200 ps
CPU time 710.77 seconds
Started Oct 12 11:49:27 AM UTC 24
Finished Oct 12 12:01:28 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254287160 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_phy_arb.2254287160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_prog_reset.840411036
Short name T238
Test name
Test status
Simulation time 43316600 ps
CPU time 20.18 seconds
Started Oct 12 12:03:28 PM UTC 24
Finished Oct 12 12:03:50 PM UTC 24
Peak memory 274984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840411036 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_prog_reset.840411036
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rand_ops.4121658022
Short name T87
Test name
Test status
Simulation time 128039300 ps
CPU time 1084.55 seconds
Started Oct 12 11:45:30 AM UTC 24
Finished Oct 12 12:03:50 PM UTC 24
Peak memory 293332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121658022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rand_ops.4121658022
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_buff_evict.3963367850
Short name T17
Test name
Test status
Simulation time 168346000 ps
CPU time 157.59 seconds
Started Oct 12 11:49:03 AM UTC 24
Finished Oct 12 11:51:44 AM UTC 24
Peak memory 272844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963367850 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_buff_evict.3963367850
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rd_ooo.770635408
Short name T382
Test name
Test status
Simulation time 74435800 ps
CPU time 67.31 seconds
Started Oct 12 12:06:49 PM UTC 24
Finished Oct 12 12:07:59 PM UTC 24
Peak memory 285524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=100 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770635408 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_ooo_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rd_ooo.770635408
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rd_ooo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep.2007933807
Short name T64
Test name
Test status
Simulation time 151583900 ps
CPU time 20.91 seconds
Started Oct 12 11:54:14 AM UTC 24
Finished Oct 12 11:54:36 AM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007933807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep.2007933807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_derr.2851364800
Short name T57
Test name
Test status
Simulation time 18905800 ps
CPU time 32.97 seconds
Started Oct 12 11:58:25 AM UTC 24
Finished Oct 12 11:58:59 AM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2851364800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flas
h_ctrl_read_word_sweep_derr.2851364800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_read_word_sweep_serr.181816182
Short name T55
Test name
Test status
Simulation time 207960600 ps
CPU time 34.55 seconds
Started Oct 12 11:55:22 AM UTC 24
Finished Oct 12 11:55:58 AM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181816182 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_read_word_sweep_serr.181816182
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rma_err.484254556
Short name T99
Test name
Test status
Simulation time 98892120200 ps
CPU time 1049.31 seconds
Started Oct 12 12:06:43 PM UTC 24
Finished Oct 12 12:24:26 PM UTC 24
Peak memory 275592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=484254556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.f
lash_ctrl_rma_err.484254556
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_derr.4034647221
Short name T61
Test name
Test status
Simulation time 1333782000 ps
CPU time 195.24 seconds
Started Oct 12 11:58:38 AM UTC 24
Finished Oct 12 12:01:57 PM UTC 24
Peak memory 295836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=4034647221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 0.flash_ctrl_rw_derr.4034647221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict.1587784174
Short name T33
Test name
Test status
Simulation time 39273800 ps
CPU time 46.04 seconds
Started Oct 12 12:03:51 PM UTC 24
Finished Oct 12 12:04:39 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1587784174 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_evict.1587784174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_evict_all_en.2138721227
Short name T34
Test name
Test status
Simulation time 83773600 ps
CPU time 46.08 seconds
Started Oct 12 12:03:51 PM UTC 24
Finished Oct 12 12:04:39 PM UTC 24
Peak memory 285408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2138721227 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ct
rl_rw_evict_all_en.2138721227
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_rw_serr.2533149746
Short name T50
Test name
Test status
Simulation time 4457385000 ps
CPU time 221.71 seconds
Started Oct 12 11:56:24 AM UTC 24
Finished Oct 12 12:00:10 PM UTC 24
Peak memory 305876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2533149746 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_rw_serr.2533149746
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_address.3616068350
Short name T72
Test name
Test status
Simulation time 1733893800 ps
CPU time 105.47 seconds
Started Oct 12 11:56:50 AM UTC 24
Finished Oct 12 11:58:37 AM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=361
6068350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_ser
r_address.3616068350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_serr_counter.2518413512
Short name T49
Test name
Test status
Simulation time 1672286100 ps
CPU time 101.74 seconds
Started Oct 12 11:56:49 AM UTC 24
Finished Oct 12 11:58:33 AM UTC 24
Peak memory 275136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25
18413512 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_se
rr_counter.2518413512
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke.3429507373
Short name T1
Test name
Test status
Simulation time 23668200 ps
CPU time 117.44 seconds
Started Oct 12 11:42:49 AM UTC 24
Finished Oct 12 11:44:48 AM UTC 24
Peak memory 287380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429507373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke.3429507373
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_smoke_hw.1116764329
Short name T2
Test name
Test status
Simulation time 14287400 ps
CPU time 37.43 seconds
Started Oct 12 11:44:50 AM UTC 24
Finished Oct 12 11:45:29 AM UTC 24
Peak memory 270688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116764329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_smoke_hw.1116764329
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_stress_all.385719917
Short name T483
Test name
Test status
Simulation time 2150891700 ps
CPU time 1329.87 seconds
Started Oct 12 12:05:14 PM UTC 24
Finished Oct 12 12:27:41 PM UTC 24
Peak memory 304248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385719917 -assert nopostproc +UVM_TESTNA
ME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_stress_all.385719917
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_sw_op.4082875966
Short name T3
Test name
Test status
Simulation time 66490800 ps
CPU time 41.55 seconds
Started Oct 12 11:46:29 AM UTC 24
Finished Oct 12 11:47:12 AM UTC 24
Peak memory 272736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082875966 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_sw_op.4082875966
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_wo.656328595
Short name T71
Test name
Test status
Simulation time 2535932800 ps
CPU time 187.99 seconds
Started Oct 12 11:53:36 AM UTC 24
Finished Oct 12 11:56:48 AM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=656328595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_wo.656328595
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/0.flash_ctrl_write_word_sweep.3536667880
Short name T19
Test name
Test status
Simulation time 66778100 ps
CPU time 23.01 seconds
Started Oct 12 11:53:48 AM UTC 24
Finished Oct 12 11:54:13 AM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536667880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_write_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.flash_ctrl_write_word_sweep.3536667880
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/0.flash_ctrl_write_word_sweep/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_alert_test.1240948451
Short name T112
Test name
Test status
Simulation time 18991900 ps
CPU time 20.85 seconds
Started Oct 12 12:11:28 PM UTC 24
Finished Oct 12 12:11:51 PM UTC 24
Peak memory 274944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240948451 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_alert_test.1240948451
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_config_regwen.3276928297
Short name T220
Test name
Test status
Simulation time 67521500 ps
CPU time 21.82 seconds
Started Oct 12 12:11:11 PM UTC 24
Finished Oct 12 12:11:34 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276928297 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_config_regwen.3276928297
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_connect.4063196600
Short name T24
Test name
Test status
Simulation time 22198600 ps
CPU time 20.96 seconds
Started Oct 12 12:10:33 PM UTC 24
Finished Oct 12 12:10:55 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063196600 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_connect.4063196600
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_disable.1884407278
Short name T117
Test name
Test status
Simulation time 12880800 ps
CPU time 33.58 seconds
Started Oct 12 12:10:10 PM UTC 24
Finished Oct 12 12:10:45 PM UTC 24
Peak memory 285276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1884407278 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_c
trl_disable.1884407278
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_erase_suspend.798607494
Short name T31
Test name
Test status
Simulation time 16022227100 ps
CPU time 803.06 seconds
Started Oct 12 12:07:01 PM UTC 24
Finished Oct 12 12:20:35 PM UTC 24
Peak memory 277624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798607494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_erase_suspend.798607494
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_mp.148598758
Short name T278
Test name
Test status
Simulation time 19294679200 ps
CPU time 3167.2 seconds
Started Oct 12 12:07:08 PM UTC 24
Finished Oct 12 01:00:30 PM UTC 24
Peak memory 275644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=148598758 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_mp.148598758
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_error_prog_win.2376261058
Short name T279
Test name
Test status
Simulation time 700754800 ps
CPU time 1265.36 seconds
Started Oct 12 12:07:07 PM UTC 24
Finished Oct 12 12:28:29 PM UTC 24
Peak memory 287940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376261058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_error_prog_win.2376261058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fetch_code.1266429502
Short name T53
Test name
Test status
Simulation time 407123000 ps
CPU time 31.11 seconds
Started Oct 12 12:07:03 PM UTC 24
Finished Oct 12 12:07:36 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=12
66429502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_fetc
h_code.1266429502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_fs_sup.4211819180
Short name T263
Test name
Test status
Simulation time 670142500 ps
CPU time 47.08 seconds
Started Oct 12 12:10:56 PM UTC 24
Finished Oct 12 12:11:45 PM UTC 24
Peak memory 272980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4211819
180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_f
s_sup.4211819180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_full_mem_access.3380462169
Short name T154
Test name
Test status
Simulation time 49892817700 ps
CPU time 4077.56 seconds
Started Oct 12 12:07:05 PM UTC 24
Finished Oct 12 01:15:51 PM UTC 24
Peak memory 277648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380462169 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_full_mem_access.3380462169
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_addr_infection.1098463212
Short name T296
Test name
Test status
Simulation time 64419000 ps
CPU time 47.08 seconds
Started Oct 12 12:11:26 PM UTC 24
Finished Oct 12 12:12:15 PM UTC 24
Peak memory 285352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109846321
2 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ho
st_addr_infection.1098463212
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_host_dir_rd.427657032
Short name T216
Test name
Test status
Simulation time 58388800 ps
CPU time 157.12 seconds
Started Oct 12 12:06:58 PM UTC 24
Finished Oct 12 12:09:39 PM UTC 24
Peak memory 272848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=427657032 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_host_dir_rd.427657032
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_prog_rma_wipe_err.3544247739
Short name T105
Test name
Test status
Simulation time 10020299300 ps
CPU time 229.86 seconds
Started Oct 12 12:11:23 PM UTC 24
Finished Oct 12 12:15:17 PM UTC 24
Peak memory 295512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3544247739 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 1.flash_ctrl_hw_prog_rma_wipe_err.3544247739
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_hw_rma_reset.3622738101
Short name T137
Test name
Test status
Simulation time 40124946600 ps
CPU time 999.34 seconds
Started Oct 12 12:07:01 PM UTC 24
Finished Oct 12 12:23:54 PM UTC 24
Peak memory 277592 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3622738101
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_hw_rma_reset.3622738101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_integrity.3007645206
Short name T450
Test name
Test status
Simulation time 13763888900 ps
CPU time 665.25 seconds
Started Oct 12 12:09:00 PM UTC 24
Finished Oct 12 12:20:15 PM UTC 24
Peak memory 340836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3007645206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_integr
ity.3007645206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_rd.2351666871
Short name T46
Test name
Test status
Simulation time 9205793000 ps
CPU time 249.83 seconds
Started Oct 12 12:09:14 PM UTC 24
Finished Oct 12 12:13:28 PM UTC 24
Peak memory 293504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2351666871 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_rd.2351666871
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr.3041923923
Short name T38
Test name
Test status
Simulation time 3061331800 ps
CPU time 101.91 seconds
Started Oct 12 12:09:26 PM UTC 24
Finished Oct 12 12:11:10 PM UTC 24
Peak memory 275016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041923923 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr.3041923923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_intr_wr_slow_flash.1161365760
Short name T79
Test name
Test status
Simulation time 105366084800 ps
CPU time 316.43 seconds
Started Oct 12 12:09:40 PM UTC 24
Finished Oct 12 12:15:01 PM UTC 24
Peak memory 271104 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1161365760 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 1.flash_ctrl_intr_wr_slow_flash.1161365760
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_invalid_op.3377789883
Short name T90
Test name
Test status
Simulation time 3054635300 ps
CPU time 82.06 seconds
Started Oct 12 12:07:10 PM UTC 24
Finished Oct 12 12:08:34 PM UTC 24
Peak memory 270800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377789883 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_invalid_op.3377789883
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_lcmgr_intg.3121465176
Short name T171
Test name
Test status
Simulation time 47281800 ps
CPU time 21.42 seconds
Started Oct 12 12:11:19 PM UTC 24
Finished Oct 12 12:11:42 PM UTC 24
Peak memory 273044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3121465176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flas
h_ctrl_lcmgr_intg.3121465176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_mp_regions.4272085400
Short name T29
Test name
Test status
Simulation time 60979766200 ps
CPU time 465.95 seconds
Started Oct 12 12:07:02 PM UTC 24
Finished Oct 12 12:14:55 PM UTC 24
Peak memory 283148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4272085400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 1.flash_ctrl_mp_regions.4272085400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_otp_reset.2977111570
Short name T133
Test name
Test status
Simulation time 161672000 ps
CPU time 200.71 seconds
Started Oct 12 12:07:01 PM UTC 24
Finished Oct 12 12:10:25 PM UTC 24
Peak memory 274736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977111570 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_otp_reset.2977111570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_oversize_error.60036859
Short name T206
Test name
Test status
Simulation time 2361135300 ps
CPU time 211.06 seconds
Started Oct 12 12:08:53 PM UTC 24
Finished Oct 12 12:12:28 PM UTC 24
Peak memory 305872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=60036859 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.flash_ctrl_oversize_error.60036859
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_ack_consistency.2246062121
Short name T68
Test name
Test status
Simulation time 43186600 ps
CPU time 22.44 seconds
Started Oct 12 12:11:02 PM UTC 24
Finished Oct 12 12:11:25 PM UTC 24
Peak memory 293160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246062121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_ack_consistency.2246062121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_arb.2484645014
Short name T126
Test name
Test status
Simulation time 167225500 ps
CPU time 228.43 seconds
Started Oct 12 12:07:00 PM UTC 24
Finished Oct 12 12:10:52 PM UTC 24
Peak memory 274892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484645014 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_arb.2484645014
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_phy_host_grant_err.4017573077
Short name T202
Test name
Test status
Simulation time 44053300 ps
CPU time 21.31 seconds
Started Oct 12 12:10:58 PM UTC 24
Finished Oct 12 12:11:20 PM UTC 24
Peak memory 273280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=4017573077 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err
_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.
vdb -cm_log /dev/null -cm_name 1.flash_ctrl_phy_host_grant_err.4017573077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_prog_reset.1931752799
Short name T381
Test name
Test status
Simulation time 82280300 ps
CPU time 21.77 seconds
Started Oct 12 12:09:41 PM UTC 24
Finished Oct 12 12:10:04 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931752799 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_prog_reset.1931752799
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_buff_evict.635501369
Short name T74
Test name
Test status
Simulation time 91129100 ps
CPU time 157.45 seconds
Started Oct 12 12:07:00 PM UTC 24
Finished Oct 12 12:09:40 PM UTC 24
Peak memory 272852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635501369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_buff_evict.635501369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rd_intg.274132116
Short name T208
Test name
Test status
Simulation time 70541900 ps
CPU time 45.52 seconds
Started Oct 12 12:10:46 PM UTC 24
Finished Oct 12 12:11:33 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274132116
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rd_intg.274132116
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_re_evict.2495210540
Short name T386
Test name
Test status
Simulation time 62074000 ps
CPU time 49.25 seconds
Started Oct 12 12:10:09 PM UTC 24
Finished Oct 12 12:11:01 PM UTC 24
Peak memory 287472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2495210540 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_re_evict.2495210540
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_derr.874074769
Short name T380
Test name
Test status
Simulation time 24480600 ps
CPU time 38.86 seconds
Started Oct 12 12:08:12 PM UTC 24
Finished Oct 12 12:08:52 PM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=874074769 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_read_word_sweep_derr.874074769
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_read_word_sweep_serr.815179098
Short name T379
Test name
Test status
Simulation time 59968700 ps
CPU time 32.2 seconds
Started Oct 12 12:07:37 PM UTC 24
Finished Oct 12 12:08:11 PM UTC 24
Peak memory 275088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=815179098 -assert nopostproc +U
VM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_read_word_sweep_serr.815179098
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rma_err.2089656183
Short name T100
Test name
Test status
Simulation time 46561842000 ps
CPU time 901.4 seconds
Started Oct 12 12:11:18 PM UTC 24
Finished Oct 12 12:26:31 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +flash_erase_latency=50 +test_timeout_ns=30
0_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb
_random_seed=2089656183 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_err_vseq +en_cov=1 -cm line+cond+fsm
+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.
flash_ctrl_rma_err.2089656183
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rma_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro.673808338
Short name T125
Test name
Test status
Simulation time 1795899000 ps
CPU time 133.23 seconds
Started Oct 12 12:07:15 PM UTC 24
Finished Oct 12 12:09:31 PM UTC 24
Peak memory 291648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=673808338 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ro.673808338
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_derr.2262895315
Short name T45
Test name
Test status
Simulation time 3621176700 ps
CPU time 149.51 seconds
Started Oct 12 12:08:24 PM UTC 24
Finished Oct 12 12:10:56 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262895315 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 1.flash_ctrl_ro_derr.2262895315
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_ro_serr.1481683477
Short name T114
Test name
Test status
Simulation time 631902700 ps
CPU time 147.51 seconds
Started Oct 12 12:07:38 PM UTC 24
Finished Oct 12 12:10:09 PM UTC 24
Peak memory 291540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1481683477 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash
_ctrl_ro_serr.1481683477
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_rw.2746704938
Short name T437
Test name
Test status
Simulation time 3969829400 ps
CPU time 681.09 seconds
Started Oct 12 12:07:36 PM UTC 24
Finished Oct 12 12:19:07 PM UTC 24
Peak memory 320172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746704938 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_rw.2746704938
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_cm.466297153
Short name T15
Test name
Test status
Simulation time 28579998500 ps
CPU time 6249.6 seconds
Started Oct 12 12:10:11 PM UTC 24
Finished Oct 12 01:55:26 PM UTC 24
Peak memory 318092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466297153 -assert nopostproc +UVM_TESTNAME=f
lash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_cm.466297153
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sec_info_access.2408705998
Short name T40
Test name
Test status
Simulation time 20979712400 ps
CPU time 107.05 seconds
Started Oct 12 12:10:26 PM UTC 24
Finished Oct 12 12:12:15 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408705998 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sec_info_access.2408705998
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_address.2224274915
Short name T384
Test name
Test status
Simulation time 1507669900 ps
CPU time 68.11 seconds
Started Oct 12 12:08:03 PM UTC 24
Finished Oct 12 12:09:13 PM UTC 24
Peak memory 285376 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222
4274915 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser
r_address.2224274915
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_serr_counter.616727175
Short name T262
Test name
Test status
Simulation time 4237699900 ps
CPU time 100.9 seconds
Started Oct 12 12:07:59 PM UTC 24
Finished Oct 12 12:09:43 PM UTC 24
Peak memory 285392 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61
6727175 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_ser
r_counter.616727175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke.440670323
Short name T300
Test name
Test status
Simulation time 81754500 ps
CPU time 340.4 seconds
Started Oct 12 12:06:50 PM UTC 24
Finished Oct 12 12:12:36 PM UTC 24
Peak memory 289228 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440670323 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke.440670323
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_smoke_hw.1702598665
Short name T127
Test name
Test status
Simulation time 37343800 ps
CPU time 40.82 seconds
Started Oct 12 12:06:56 PM UTC 24
Finished Oct 12 12:07:39 PM UTC 24
Peak memory 270684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702598665 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_smoke_hw.1702598665
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_stress_all.2235828064
Short name T570
Test name
Test status
Simulation time 1788655600 ps
CPU time 1913.84 seconds
Started Oct 12 12:10:27 PM UTC 24
Finished Oct 12 12:42:43 PM UTC 24
Peak memory 305704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235828064 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_stress_all.2235828064
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_sw_op.251988413
Short name T128
Test name
Test status
Simulation time 20218400 ps
CPU time 36.46 seconds
Started Oct 12 12:06:57 PM UTC 24
Finished Oct 12 12:07:35 PM UTC 24
Peak memory 272928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=251988413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_sw_op.251988413
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wo.314102023
Short name T376
Test name
Test status
Simulation time 7370335900 ps
CPU time 267.55 seconds
Started Oct 12 12:07:13 PM UTC 24
Finished Oct 12 12:11:45 PM UTC 24
Peak memory 275168 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=314102023 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.flash_ctrl_wo.314102023
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/1.flash_ctrl_wr_intg.2632138452
Short name T9
Test name
Test status
Simulation time 89792800 ps
CPU time 22.6 seconds
Started Oct 12 12:10:53 PM UTC 24
Finished Oct 12 12:11:17 PM UTC 24
Peak memory 275056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=2632138452 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 1.flash_ctrl_wr_intg.2632138452
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/1.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_alert_test.3706316317
Short name T623
Test name
Test status
Simulation time 106863100 ps
CPU time 24.64 seconds
Started Oct 12 12:48:51 PM UTC 24
Finished Oct 12 12:49:17 PM UTC 24
Peak memory 268932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3706316317 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_alert_test.3706316317
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_connect.1245117839
Short name T103
Test name
Test status
Simulation time 27315500 ps
CPU time 26.86 seconds
Started Oct 12 12:48:22 PM UTC 24
Finished Oct 12 12:48:50 PM UTC 24
Peak memory 284768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245117839 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_connect.1245117839
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_disable.4034248130
Short name T387
Test name
Test status
Simulation time 21471800 ps
CPU time 39.45 seconds
Started Oct 12 12:48:14 PM UTC 24
Finished Oct 12 12:48:55 PM UTC 24
Peak memory 285340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4034248130 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_
ctrl_disable.4034248130
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_prog_rma_wipe_err.1014170137
Short name T635
Test name
Test status
Simulation time 10020057000 ps
CPU time 142.19 seconds
Started Oct 12 12:48:46 PM UTC 24
Finished Oct 12 12:51:10 PM UTC 24
Peak memory 338472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1014170137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 10.flash_ctrl_hw_prog_rma_wipe_err.1014170137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_read_seed_err.799201336
Short name T617
Test name
Test status
Simulation time 15481000 ps
CPU time 15.28 seconds
Started Oct 12 12:48:40 PM UTC 24
Finished Oct 12 12:48:57 PM UTC 24
Peak memory 269004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=799201336 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
0.flash_ctrl_hw_read_seed_err.799201336
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_hw_rma_reset.256758597
Short name T716
Test name
Test status
Simulation time 100158109800 ps
CPU time 896.87 seconds
Started Oct 12 12:46:50 PM UTC 24
Finished Oct 12 01:01:57 PM UTC 24
Peak memory 274744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256758597 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_hw_rma_reset.256758597
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd.2775374774
Short name T342
Test name
Test status
Simulation time 609779600 ps
CPU time 114.56 seconds
Started Oct 12 12:47:34 PM UTC 24
Finished Oct 12 12:49:30 PM UTC 24
Peak memory 305848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2775374774 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_intr_rd.2775374774
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_intr_rd_slow_flash.1252226082
Short name T43
Test name
Test status
Simulation time 105716247500 ps
CPU time 351.78 seconds
Started Oct 12 12:47:34 PM UTC 24
Finished Oct 12 12:53:30 PM UTC 24
Peak memory 303728 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1252226082 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 10.flash_ctrl_intr_rd_slow_flash.1252226082
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_invalid_op.1876220229
Short name T612
Test name
Test status
Simulation time 1975559600 ps
CPU time 90.89 seconds
Started Oct 12 12:46:53 PM UTC 24
Finished Oct 12 12:48:26 PM UTC 24
Peak memory 270928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876220229 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_invalid_op.1876220229
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_lcmgr_intg.3804601488
Short name T616
Test name
Test status
Simulation time 43316300 ps
CPU time 23.56 seconds
Started Oct 12 12:48:28 PM UTC 24
Finished Oct 12 12:48:53 PM UTC 24
Peak memory 270860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3804601488 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.fla
sh_ctrl_lcmgr_intg.3804601488
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_mp_regions.3658502693
Short name T152
Test name
Test status
Simulation time 12897803000 ps
CPU time 986.86 seconds
Started Oct 12 12:46:52 PM UTC 24
Finished Oct 12 01:03:30 PM UTC 24
Peak memory 282744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3658502693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 10.flash_ctrl_mp_regions.3658502693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_otp_reset.644883254
Short name T189
Test name
Test status
Simulation time 149164100 ps
CPU time 201.85 seconds
Started Oct 12 12:46:52 PM UTC 24
Finished Oct 12 12:50:17 PM UTC 24
Peak memory 270648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=644883254 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_otp_reset.644883254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_phy_arb.3310249673
Short name T640
Test name
Test status
Simulation time 365448100 ps
CPU time 321.14 seconds
Started Oct 12 12:46:48 PM UTC 24
Finished Oct 12 12:52:13 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310249673 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_phy_arb.3310249673
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_prog_reset.1322930711
Short name T628
Test name
Test status
Simulation time 7231061000 ps
CPU time 169.73 seconds
Started Oct 12 12:47:43 PM UTC 24
Finished Oct 12 12:50:35 PM UTC 24
Peak memory 275016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322930711 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_prog_reset.1322930711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rand_ops.303511146
Short name T697
Test name
Test status
Simulation time 332779800 ps
CPU time 785.31 seconds
Started Oct 12 12:46:44 PM UTC 24
Finished Oct 12 12:59:57 PM UTC 24
Peak memory 293336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303511146 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rand_ops.303511146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_re_evict.3139064509
Short name T620
Test name
Test status
Simulation time 87868100 ps
CPU time 60.13 seconds
Started Oct 12 12:48:04 PM UTC 24
Finished Oct 12 12:49:06 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139064509 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_re_evict.3139064509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_ro.946103361
Short name T621
Test name
Test status
Simulation time 5832151900 ps
CPU time 124.93 seconds
Started Oct 12 12:47:03 PM UTC 24
Finished Oct 12 12:49:11 PM UTC 24
Peak memory 291468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=946103361 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_ro.946103361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw.668765382
Short name T659
Test name
Test status
Simulation time 4293927700 ps
CPU time 470.77 seconds
Started Oct 12 12:47:23 PM UTC 24
Finished Oct 12 12:55:20 PM UTC 24
Peak memory 320352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668765382 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw.668765382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict.6665510
Short name T614
Test name
Test status
Simulation time 31429000 ps
CPU time 53.43 seconds
Started Oct 12 12:47:50 PM UTC 24
Finished Oct 12 12:48:45 PM UTC 24
Peak memory 287652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6665510 -assert nopostpro
c +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_rw_evict.6665510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_rw_evict_all_en.2329164732
Short name T618
Test name
Test status
Simulation time 50974700 ps
CPU time 55.24 seconds
Started Oct 12 12:48:02 PM UTC 24
Finished Oct 12 12:48:59 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2329164732 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_c
trl_rw_evict_all_en.2329164732
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_smoke.3643222968
Short name T633
Test name
Test status
Simulation time 26150500 ps
CPU time 260.07 seconds
Started Oct 12 12:46:40 PM UTC 24
Finished Oct 12 12:51:04 PM UTC 24
Peak memory 289240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3643222968 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_smoke.3643222968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/10.flash_ctrl_wo.4277266410
Short name T624
Test name
Test status
Simulation time 7556561000 ps
CPU time 161.7 seconds
Started Oct 12 12:46:54 PM UTC 24
Finished Oct 12 12:49:39 PM UTC 24
Peak memory 270928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4277266410 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.flash_ctrl_wo.4277266410
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/10.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_alert_test.2755594447
Short name T634
Test name
Test status
Simulation time 150160600 ps
CPU time 17.43 seconds
Started Oct 12 12:50:46 PM UTC 24
Finished Oct 12 12:51:05 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755594447 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_alert_test.2755594447
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_connect.669450843
Short name T630
Test name
Test status
Simulation time 29193800 ps
CPU time 24.72 seconds
Started Oct 12 12:50:19 PM UTC 24
Finished Oct 12 12:50:45 PM UTC 24
Peak memory 295008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669450843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_connect.669450843
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_disable.4192489307
Short name T124
Test name
Test status
Simulation time 12158200 ps
CPU time 39.76 seconds
Started Oct 12 12:50:11 PM UTC 24
Finished Oct 12 12:50:53 PM UTC 24
Peak memory 285336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4192489307 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_
ctrl_disable.4192489307
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_read_seed_err.3844191723
Short name T632
Test name
Test status
Simulation time 20171300 ps
CPU time 24 seconds
Started Oct 12 12:50:36 PM UTC 24
Finished Oct 12 12:51:02 PM UTC 24
Peak memory 269012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3844191723 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
11.flash_ctrl_hw_read_seed_err.3844191723
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_rma_reset.1347518623
Short name T713
Test name
Test status
Simulation time 40121496600 ps
CPU time 752.68 seconds
Started Oct 12 12:49:00 PM UTC 24
Finished Oct 12 01:01:41 PM UTC 24
Peak memory 274864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347518623
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_rma_res
et.1347518623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_hw_sec_otp.3274391593
Short name T636
Test name
Test status
Simulation time 6362702100 ps
CPU time 146.5 seconds
Started Oct 12 12:48:57 PM UTC 24
Finished Oct 12 12:51:27 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274391593 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_hw_sec_otp.3274391593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd.4115714444
Short name T644
Test name
Test status
Simulation time 1678089100 ps
CPU time 219.37 seconds
Started Oct 12 12:49:18 PM UTC 24
Finished Oct 12 12:53:01 PM UTC 24
Peak memory 301720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115714444 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_intr_rd.4115714444
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_intr_rd_slow_flash.1623417837
Short name T345
Test name
Test status
Simulation time 91640989300 ps
CPU time 269.75 seconds
Started Oct 12 12:49:31 PM UTC 24
Finished Oct 12 12:54:05 PM UTC 24
Peak memory 301640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1623417837 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 11.flash_ctrl_intr_rd_slow_flash.1623417837
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_invalid_op.3107326395
Short name T627
Test name
Test status
Simulation time 3424423900 ps
CPU time 61.5 seconds
Started Oct 12 12:49:07 PM UTC 24
Finished Oct 12 12:50:10 PM UTC 24
Peak memory 270800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107326395 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_invalid_op.3107326395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_lcmgr_intg.1898361029
Short name T631
Test name
Test status
Simulation time 48406700 ps
CPU time 17.48 seconds
Started Oct 12 12:50:33 PM UTC 24
Finished Oct 12 12:50:52 PM UTC 24
Peak memory 270860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1898361029 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.fla
sh_ctrl_lcmgr_intg.1898361029
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_mp_regions.705915800
Short name T641
Test name
Test status
Simulation time 12623619000 ps
CPU time 201.79 seconds
Started Oct 12 12:49:02 PM UTC 24
Finished Oct 12 12:52:27 PM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=705915800 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 11.flash_ctrl_mp_regions.705915800
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_otp_reset.1916452017
Short name T320
Test name
Test status
Simulation time 73515300 ps
CPU time 202.68 seconds
Started Oct 12 12:49:00 PM UTC 24
Finished Oct 12 12:52:26 PM UTC 24
Peak memory 275212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916452017 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_otp_reset.1916452017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_phy_arb.3644693238
Short name T692
Test name
Test status
Simulation time 298268900 ps
CPU time 619.9 seconds
Started Oct 12 12:48:56 PM UTC 24
Finished Oct 12 12:59:24 PM UTC 24
Peak memory 275032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644693238 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_phy_arb.3644693238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rand_ops.749138154
Short name T682
Test name
Test status
Simulation time 84188400 ps
CPU time 596.02 seconds
Started Oct 12 12:48:53 PM UTC 24
Finished Oct 12 12:58:56 PM UTC 24
Peak memory 291032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749138154 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rand_ops.749138154
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_re_evict.1189883889
Short name T414
Test name
Test status
Simulation time 72440300 ps
CPU time 41.34 seconds
Started Oct 12 12:49:57 PM UTC 24
Finished Oct 12 12:50:40 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189883889 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_re_evict.1189883889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_ro.3456304174
Short name T638
Test name
Test status
Simulation time 2290984300 ps
CPU time 147.91 seconds
Started Oct 12 12:49:16 PM UTC 24
Finished Oct 12 12:51:46 PM UTC 24
Peak memory 291548 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3456304174 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_ro.3456304174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw.4093892537
Short name T679
Test name
Test status
Simulation time 21596660700 ps
CPU time 540.31 seconds
Started Oct 12 12:49:18 PM UTC 24
Finished Oct 12 12:58:25 PM UTC 24
Peak memory 320212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093892537 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw.4093892537
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_rw_evict.1352478906
Short name T425
Test name
Test status
Simulation time 41105800 ps
CPU time 37.52 seconds
Started Oct 12 12:49:39 PM UTC 24
Finished Oct 12 12:50:18 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1352478906 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_rw_evict.1352478906
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_sec_info_access.50001889
Short name T637
Test name
Test status
Simulation time 1423634700 ps
CPU time 74.1 seconds
Started Oct 12 12:50:18 PM UTC 24
Finished Oct 12 12:51:34 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50001889 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_T
EST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_sec_info_access.50001889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/11.flash_ctrl_smoke.1699844215
Short name T639
Test name
Test status
Simulation time 218124400 ps
CPU time 192.85 seconds
Started Oct 12 12:48:53 PM UTC 24
Finished Oct 12 12:52:09 PM UTC 24
Peak memory 289236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699844215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.flash_ctrl_smoke.1699844215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/11.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_alert_test.2042393461
Short name T654
Test name
Test status
Simulation time 153694900 ps
CPU time 24.2 seconds
Started Oct 12 12:53:31 PM UTC 24
Finished Oct 12 12:53:57 PM UTC 24
Peak memory 268796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042393461 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_alert_test.2042393461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_connect.465415731
Short name T651
Test name
Test status
Simulation time 17765400 ps
CPU time 28.58 seconds
Started Oct 12 12:53:12 PM UTC 24
Finished Oct 12 12:53:42 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465415731 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_connect.465415731
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_disable.877523392
Short name T645
Test name
Test status
Simulation time 24307800 ps
CPU time 31.48 seconds
Started Oct 12 12:52:38 PM UTC 24
Finished Oct 12 12:53:11 PM UTC 24
Peak memory 285380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=877523392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_disable.877523392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_prog_rma_wipe_err.73050439
Short name T690
Test name
Test status
Simulation time 10012502800 ps
CPU time 350.2 seconds
Started Oct 12 12:53:26 PM UTC 24
Finished Oct 12 12:59:21 PM UTC 24
Peak memory 346860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=73050439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 12.flash_ctrl_hw_prog_rma_wipe_err.73050439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_read_seed_err.243442643
Short name T653
Test name
Test status
Simulation time 118258700 ps
CPU time 27.31 seconds
Started Oct 12 12:53:25 PM UTC 24
Finished Oct 12 12:53:54 PM UTC 24
Peak memory 270848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=243442643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
2.flash_ctrl_hw_read_seed_err.243442643
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_rma_reset.1018321722
Short name T739
Test name
Test status
Simulation time 40120363400 ps
CPU time 764.36 seconds
Started Oct 12 12:51:03 PM UTC 24
Finished Oct 12 01:03:56 PM UTC 24
Peak memory 274928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018321722
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_rma_res
et.1018321722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_hw_sec_otp.3226313016
Short name T648
Test name
Test status
Simulation time 15113475500 ps
CPU time 154.9 seconds
Started Oct 12 12:50:54 PM UTC 24
Finished Oct 12 12:53:31 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226313016 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_hw_sec_otp.3226313016
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd.1330915254
Short name T662
Test name
Test status
Simulation time 3936389000 ps
CPU time 221.27 seconds
Started Oct 12 12:51:47 PM UTC 24
Finished Oct 12 12:55:32 PM UTC 24
Peak memory 301720 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1330915254 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_intr_rd.1330915254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_intr_rd_slow_flash.3332021138
Short name T678
Test name
Test status
Simulation time 40037132700 ps
CPU time 366.85 seconds
Started Oct 12 12:52:10 PM UTC 24
Finished Oct 12 12:58:22 PM UTC 24
Peak memory 301624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3332021138 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 12.flash_ctrl_intr_rd_slow_flash.3332021138
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_invalid_op.178128889
Short name T643
Test name
Test status
Simulation time 3659188500 ps
CPU time 84.24 seconds
Started Oct 12 12:51:11 PM UTC 24
Finished Oct 12 12:52:37 PM UTC 24
Peak memory 274900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178128889 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_invalid_op.178128889
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_mp_regions.4082374591
Short name T160
Test name
Test status
Simulation time 22130248700 ps
CPU time 173.21 seconds
Started Oct 12 12:51:06 PM UTC 24
Finished Oct 12 12:54:02 PM UTC 24
Peak memory 275080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4082374591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 12.flash_ctrl_mp_regions.4082374591
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_otp_reset.4034271858
Short name T190
Test name
Test status
Simulation time 80705200 ps
CPU time 181.2 seconds
Started Oct 12 12:51:05 PM UTC 24
Finished Oct 12 12:54:09 PM UTC 24
Peak memory 272892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034271858 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_otp_reset.4034271858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_phy_arb.3850083646
Short name T711
Test name
Test status
Simulation time 1486727300 ps
CPU time 616.64 seconds
Started Oct 12 12:50:53 PM UTC 24
Finished Oct 12 01:01:17 PM UTC 24
Peak memory 272796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850083646 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_phy_arb.3850083646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_prog_reset.838928424
Short name T642
Test name
Test status
Simulation time 36619700 ps
CPU time 20.05 seconds
Started Oct 12 12:52:14 PM UTC 24
Finished Oct 12 12:52:36 PM UTC 24
Peak memory 275032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838928424 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_prog_reset.838928424
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rand_ops.972300118
Short name T767
Test name
Test status
Simulation time 142780400 ps
CPU time 922.1 seconds
Started Oct 12 12:50:47 PM UTC 24
Finished Oct 12 01:06:19 PM UTC 24
Peak memory 293528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=972300118 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rand_ops.972300118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_re_evict.767227466
Short name T647
Test name
Test status
Simulation time 76840900 ps
CPU time 52.45 seconds
Started Oct 12 12:52:36 PM UTC 24
Finished Oct 12 12:53:30 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=767227466 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_re_evict.767227466
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_ro.714584832
Short name T650
Test name
Test status
Simulation time 470463100 ps
CPU time 126.21 seconds
Started Oct 12 12:51:28 PM UTC 24
Finished Oct 12 12:53:36 PM UTC 24
Peak memory 303824 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=714584832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_ro.714584832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw.3383533108
Short name T701
Test name
Test status
Simulation time 8411908200 ps
CPU time 530.31 seconds
Started Oct 12 12:51:35 PM UTC 24
Finished Oct 12 01:00:32 PM UTC 24
Peak memory 330404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383533108 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw.3383533108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict.823498973
Short name T426
Test name
Test status
Simulation time 80988400 ps
CPU time 57.48 seconds
Started Oct 12 12:52:26 PM UTC 24
Finished Oct 12 12:53:26 PM UTC 24
Peak memory 287636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=823498973 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_rw_evict.823498973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_rw_evict_all_en.1743364623
Short name T646
Test name
Test status
Simulation time 44810800 ps
CPU time 51.89 seconds
Started Oct 12 12:52:28 PM UTC 24
Finished Oct 12 12:53:21 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1743364623 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_c
trl_rw_evict_all_en.1743364623
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_sec_info_access.3694545603
Short name T657
Test name
Test status
Simulation time 2094488500 ps
CPU time 80.86 seconds
Started Oct 12 12:53:02 PM UTC 24
Finished Oct 12 12:54:25 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694545603 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_sec_info_access.3694545603
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_smoke.1955199309
Short name T649
Test name
Test status
Simulation time 427263900 ps
CPU time 165.1 seconds
Started Oct 12 12:50:46 PM UTC 24
Finished Oct 12 12:53:34 PM UTC 24
Peak memory 289236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955199309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_smoke.1955199309
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/12.flash_ctrl_wo.3022057161
Short name T655
Test name
Test status
Simulation time 4569295300 ps
CPU time 158.65 seconds
Started Oct 12 12:51:24 PM UTC 24
Finished Oct 12 12:54:06 PM UTC 24
Peak memory 270928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3022057161 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.flash_ctrl_wo.3022057161
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/12.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_alert_test.2491832704
Short name T670
Test name
Test status
Simulation time 126959500 ps
CPU time 21.65 seconds
Started Oct 12 12:56:01 PM UTC 24
Finished Oct 12 12:56:23 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491832704 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_alert_test.2491832704
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_connect.2179269965
Short name T667
Test name
Test status
Simulation time 40189300 ps
CPU time 26.93 seconds
Started Oct 12 12:55:33 PM UTC 24
Finished Oct 12 12:56:01 PM UTC 24
Peak memory 295004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179269965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_connect.2179269965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_disable.3997911576
Short name T665
Test name
Test status
Simulation time 11264400 ps
CPU time 23.17 seconds
Started Oct 12 12:55:29 PM UTC 24
Finished Oct 12 12:55:53 PM UTC 24
Peak memory 285252 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3997911576 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_
ctrl_disable.3997911576
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_read_seed_err.603934911
Short name T668
Test name
Test status
Simulation time 26801400 ps
CPU time 23.66 seconds
Started Oct 12 12:55:39 PM UTC 24
Finished Oct 12 12:56:04 PM UTC 24
Peak memory 271188 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=603934911 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
3.flash_ctrl_hw_read_seed_err.603934911
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_hw_sec_otp.797955914
Short name T656
Test name
Test status
Simulation time 696710700 ps
CPU time 41.46 seconds
Started Oct 12 12:53:38 PM UTC 24
Finished Oct 12 12:54:21 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=797955914 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_hw_sec_otp.797955914
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd.3832906198
Short name T673
Test name
Test status
Simulation time 2490767300 ps
CPU time 175.54 seconds
Started Oct 12 12:54:10 PM UTC 24
Finished Oct 12 12:57:09 PM UTC 24
Peak memory 301780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3832906198 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_intr_rd.3832906198
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_intr_rd_slow_flash.2198760097
Short name T675
Test name
Test status
Simulation time 9315960200 ps
CPU time 190.04 seconds
Started Oct 12 12:54:21 PM UTC 24
Finished Oct 12 12:57:34 PM UTC 24
Peak memory 305784 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2198760097 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 13.flash_ctrl_intr_rd_slow_flash.2198760097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_invalid_op.3519989437
Short name T663
Test name
Test status
Simulation time 6109834700 ps
CPU time 93.38 seconds
Started Oct 12 12:53:57 PM UTC 24
Finished Oct 12 12:55:33 PM UTC 24
Peak memory 274892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519989437 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_invalid_op.3519989437
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_lcmgr_intg.1438420478
Short name T666
Test name
Test status
Simulation time 30081600 ps
CPU time 24.44 seconds
Started Oct 12 12:55:34 PM UTC 24
Finished Oct 12 12:56:00 PM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1438420478 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.fla
sh_ctrl_lcmgr_intg.1438420478
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_mp_regions.3132346467
Short name T161
Test name
Test status
Simulation time 16804527100 ps
CPU time 538.05 seconds
Started Oct 12 12:53:54 PM UTC 24
Finished Oct 12 01:02:59 PM UTC 24
Peak memory 285216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3132346467 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 13.flash_ctrl_mp_regions.3132346467
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_phy_arb.757355674
Short name T680
Test name
Test status
Simulation time 523466000 ps
CPU time 292.21 seconds
Started Oct 12 12:53:35 PM UTC 24
Finished Oct 12 12:58:31 PM UTC 24
Peak memory 274976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757355674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_phy_arb.757355674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_prog_reset.2785520753
Short name T677
Test name
Test status
Simulation time 2175976900 ps
CPU time 217.33 seconds
Started Oct 12 12:54:26 PM UTC 24
Finished Oct 12 12:58:06 PM UTC 24
Peak memory 271120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785520753 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_prog_reset.2785520753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rand_ops.3474373714
Short name T809
Test name
Test status
Simulation time 664272200 ps
CPU time 956.38 seconds
Started Oct 12 12:53:32 PM UTC 24
Finished Oct 12 01:09:40 PM UTC 24
Peak memory 293332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3474373714 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rand_ops.3474373714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_re_evict.2819423787
Short name T669
Test name
Test status
Simulation time 186447500 ps
CPU time 59.3 seconds
Started Oct 12 12:55:22 PM UTC 24
Finished Oct 12 12:56:23 PM UTC 24
Peak memory 285416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819423787 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_re_evict.2819423787
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_ro.1516527663
Short name T671
Test name
Test status
Simulation time 579751400 ps
CPU time 137.3 seconds
Started Oct 12 12:54:06 PM UTC 24
Finished Oct 12 12:56:26 PM UTC 24
Peak memory 291540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1516527663 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_ro.1516527663
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw.3999153363
Short name T719
Test name
Test status
Simulation time 6205241300 ps
CPU time 479.91 seconds
Started Oct 12 12:54:07 PM UTC 24
Finished Oct 12 01:02:13 PM UTC 24
Peak memory 332496 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999153363 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw.3999153363
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict.3762007270
Short name T660
Test name
Test status
Simulation time 31966800 ps
CPU time 50.78 seconds
Started Oct 12 12:54:36 PM UTC 24
Finished Oct 12 12:55:28 PM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762007270 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_rw_evict.3762007270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_rw_evict_all_en.4207636322
Short name T661
Test name
Test status
Simulation time 29310500 ps
CPU time 46.65 seconds
Started Oct 12 12:54:41 PM UTC 24
Finished Oct 12 12:55:29 PM UTC 24
Peak memory 285404 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=4207636322 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_c
trl_rw_evict_all_en.4207636322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_sec_info_access.3504097895
Short name T399
Test name
Test status
Simulation time 3321339100 ps
CPU time 69.8 seconds
Started Oct 12 12:55:30 PM UTC 24
Finished Oct 12 12:56:41 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504097895 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_sec_info_access.3504097895
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_smoke.2841359513
Short name T676
Test name
Test status
Simulation time 52506000 ps
CPU time 239.78 seconds
Started Oct 12 12:53:31 PM UTC 24
Finished Oct 12 12:57:35 PM UTC 24
Peak memory 289240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2841359513 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_smoke.2841359513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/13.flash_ctrl_wo.4145460989
Short name T674
Test name
Test status
Simulation time 2511918100 ps
CPU time 189.14 seconds
Started Oct 12 12:54:04 PM UTC 24
Finished Oct 12 12:57:16 PM UTC 24
Peak memory 272976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4145460989 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.flash_ctrl_wo.4145460989
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/13.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_alert_test.3948203951
Short name T695
Test name
Test status
Simulation time 35990000 ps
CPU time 27.32 seconds
Started Oct 12 12:59:09 PM UTC 24
Finished Oct 12 12:59:38 PM UTC 24
Peak memory 268820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3948203951 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_alert_test.3948203951
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_connect.801646429
Short name T689
Test name
Test status
Simulation time 51745200 ps
CPU time 23.17 seconds
Started Oct 12 12:58:50 PM UTC 24
Finished Oct 12 12:59:15 PM UTC 24
Peak memory 294944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=801646429 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_connect.801646429
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_disable.671260020
Short name T685
Test name
Test status
Simulation time 22362600 ps
CPU time 34.27 seconds
Started Oct 12 12:58:32 PM UTC 24
Finished Oct 12 12:59:08 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=671260020 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_disable.671260020
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_prog_rma_wipe_err.1067946846
Short name T715
Test name
Test status
Simulation time 10011629200 ps
CPU time 165.79 seconds
Started Oct 12 12:59:05 PM UTC 24
Finished Oct 12 01:01:53 PM UTC 24
Peak memory 348928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1067946846 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 14.flash_ctrl_hw_prog_rma_wipe_err.1067946846
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_read_seed_err.188893972
Short name T691
Test name
Test status
Simulation time 18363400 ps
CPU time 17.9 seconds
Started Oct 12 12:59:04 PM UTC 24
Finished Oct 12 12:59:23 PM UTC 24
Peak memory 269008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=188893972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
4.flash_ctrl_hw_read_seed_err.188893972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_rma_reset.3053469511
Short name T798
Test name
Test status
Simulation time 40123721100 ps
CPU time 749.49 seconds
Started Oct 12 12:56:26 PM UTC 24
Finished Oct 12 01:09:05 PM UTC 24
Peak memory 274736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053469511
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_rma_res
et.3053469511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_hw_sec_otp.2693543365
Short name T326
Test name
Test status
Simulation time 3997154000 ps
CPU time 70.4 seconds
Started Oct 12 12:56:24 PM UTC 24
Finished Oct 12 12:57:36 PM UTC 24
Peak memory 274864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693543365 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_hw_sec_otp.2693543365
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_intr_rd_slow_flash.3752762240
Short name T702
Test name
Test status
Simulation time 46464016100 ps
CPU time 179.38 seconds
Started Oct 12 12:57:37 PM UTC 24
Finished Oct 12 01:00:39 PM UTC 24
Peak memory 303664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3752762240 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 14.flash_ctrl_intr_rd_slow_flash.3752762240
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_invalid_op.2880305502
Short name T683
Test name
Test status
Simulation time 4105237500 ps
CPU time 111.39 seconds
Started Oct 12 12:57:10 PM UTC 24
Finished Oct 12 12:59:03 PM UTC 24
Peak memory 270864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880305502 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_invalid_op.2880305502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_lcmgr_intg.4063375449
Short name T694
Test name
Test status
Simulation time 15523100 ps
CPU time 28.67 seconds
Started Oct 12 12:58:57 PM UTC 24
Finished Oct 12 12:59:28 PM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4063375449 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.fla
sh_ctrl_lcmgr_intg.4063375449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_mp_regions.1793974982
Short name T153
Test name
Test status
Simulation time 33108892600 ps
CPU time 519.3 seconds
Started Oct 12 12:56:42 PM UTC 24
Finished Oct 12 01:05:28 PM UTC 24
Peak memory 283172 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1793974982 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 14.flash_ctrl_mp_regions.1793974982
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_phy_arb.3137401313
Short name T773
Test name
Test status
Simulation time 3826255900 ps
CPU time 634.36 seconds
Started Oct 12 12:56:24 PM UTC 24
Finished Oct 12 01:07:06 PM UTC 24
Peak memory 274752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137401313 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_phy_arb.3137401313
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_prog_reset.3925113269
Short name T703
Test name
Test status
Simulation time 8370471900 ps
CPU time 156.52 seconds
Started Oct 12 12:58:07 PM UTC 24
Finished Oct 12 01:00:47 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925113269 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_prog_reset.3925113269
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rand_ops.365216707
Short name T726
Test name
Test status
Simulation time 57606100 ps
CPU time 396.29 seconds
Started Oct 12 12:56:05 PM UTC 24
Finished Oct 12 01:02:46 PM UTC 24
Peak memory 283096 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365216707 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rand_ops.365216707
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_re_evict.3240919635
Short name T687
Test name
Test status
Simulation time 227864700 ps
CPU time 46.18 seconds
Started Oct 12 12:58:26 PM UTC 24
Finished Oct 12 12:59:14 PM UTC 24
Peak memory 285412 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240919635 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_re_evict.3240919635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_ro.569724936
Short name T693
Test name
Test status
Simulation time 1217542200 ps
CPU time 114.83 seconds
Started Oct 12 12:57:28 PM UTC 24
Finished Oct 12 12:59:25 PM UTC 24
Peak memory 301792 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=569724936 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_ro.569724936
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict.3069749434
Short name T686
Test name
Test status
Simulation time 65703600 ps
CPU time 50.57 seconds
Started Oct 12 12:58:21 PM UTC 24
Finished Oct 12 12:59:13 PM UTC 24
Peak memory 285544 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069749434 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_rw_evict.3069749434
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_rw_evict_all_en.2510978577
Short name T684
Test name
Test status
Simulation time 28996200 ps
CPU time 39.32 seconds
Started Oct 12 12:58:23 PM UTC 24
Finished Oct 12 12:59:03 PM UTC 24
Peak memory 287632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2510978577 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_c
trl_rw_evict_all_en.2510978577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_sec_info_access.2322546941
Short name T400
Test name
Test status
Simulation time 4342519100 ps
CPU time 63.48 seconds
Started Oct 12 12:58:40 PM UTC 24
Finished Oct 12 12:59:45 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322546941 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_sec_info_access.2322546941
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_smoke.4091129755
Short name T681
Test name
Test status
Simulation time 672790600 ps
CPU time 165.17 seconds
Started Oct 12 12:56:02 PM UTC 24
Finished Oct 12 12:58:49 PM UTC 24
Peak memory 291288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091129755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_smoke.4091129755
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/14.flash_ctrl_wo.1860871106
Short name T700
Test name
Test status
Simulation time 8962334300 ps
CPU time 188.11 seconds
Started Oct 12 12:57:17 PM UTC 24
Finished Oct 12 01:00:28 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1860871106 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.flash_ctrl_wo.1860871106
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/14.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_alert_test.979076802
Short name T708
Test name
Test status
Simulation time 213669800 ps
CPU time 17.83 seconds
Started Oct 12 01:00:47 PM UTC 24
Finished Oct 12 01:01:06 PM UTC 24
Peak memory 274948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=979076802 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_alert_test.979076802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_connect.1653739671
Short name T705
Test name
Test status
Simulation time 16367800 ps
CPU time 24.35 seconds
Started Oct 12 01:00:29 PM UTC 24
Finished Oct 12 01:00:54 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653739671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_connect.1653739671
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_prog_rma_wipe_err.3905966300
Short name T740
Test name
Test status
Simulation time 10012055600 ps
CPU time 196.1 seconds
Started Oct 12 01:00:40 PM UTC 24
Finished Oct 12 01:03:59 PM UTC 24
Peak memory 371240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3905966300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 15.flash_ctrl_hw_prog_rma_wipe_err.3905966300
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_read_seed_err.2657843350
Short name T707
Test name
Test status
Simulation time 46426900 ps
CPU time 26.13 seconds
Started Oct 12 01:00:33 PM UTC 24
Finished Oct 12 01:01:01 PM UTC 24
Peak memory 271076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2657843350 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
15.flash_ctrl_hw_read_seed_err.2657843350
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_rma_reset.2070994598
Short name T1076
Test name
Test status
Simulation time 380323200600 ps
CPU time 1385.28 seconds
Started Oct 12 12:59:21 PM UTC 24
Finished Oct 12 01:22:42 PM UTC 24
Peak memory 275000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070994598
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_rma_res
et.2070994598
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_hw_sec_otp.3526684235
Short name T731
Test name
Test status
Simulation time 10327216900 ps
CPU time 216.76 seconds
Started Oct 12 12:59:15 PM UTC 24
Finished Oct 12 01:02:55 PM UTC 24
Peak memory 274980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3526684235 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_hw_sec_otp.3526684235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd.3799367031
Short name T714
Test name
Test status
Simulation time 524820800 ps
CPU time 125.58 seconds
Started Oct 12 12:59:40 PM UTC 24
Finished Oct 12 01:01:48 PM UTC 24
Peak memory 301756 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799367031 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_intr_rd.3799367031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_intr_rd_slow_flash.3495156709
Short name T727
Test name
Test status
Simulation time 12017891800 ps
CPU time 177.36 seconds
Started Oct 12 12:59:46 PM UTC 24
Finished Oct 12 01:02:46 PM UTC 24
Peak memory 303668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3495156709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 15.flash_ctrl_intr_rd_slow_flash.3495156709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_invalid_op.4177733100
Short name T704
Test name
Test status
Simulation time 18257603200 ps
CPU time 83.23 seconds
Started Oct 12 12:59:25 PM UTC 24
Finished Oct 12 01:00:50 PM UTC 24
Peak memory 274892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177733100 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_invalid_op.4177733100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_lcmgr_intg.107928228
Short name T706
Test name
Test status
Simulation time 15749300 ps
CPU time 22.98 seconds
Started Oct 12 01:00:31 PM UTC 24
Finished Oct 12 01:00:55 PM UTC 24
Peak memory 274956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=107928228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flas
h_ctrl_lcmgr_intg.107928228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_mp_regions.2481557101
Short name T723
Test name
Test status
Simulation time 21281055300 ps
CPU time 186.34 seconds
Started Oct 12 12:59:24 PM UTC 24
Finished Oct 12 01:02:33 PM UTC 24
Peak memory 274956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2481557101 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 15.flash_ctrl_mp_regions.2481557101
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_otp_reset.4123367419
Short name T728
Test name
Test status
Simulation time 141548400 ps
CPU time 208.03 seconds
Started Oct 12 12:59:22 PM UTC 24
Finished Oct 12 01:02:53 PM UTC 24
Peak memory 270856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4123367419 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_otp_reset.4123367419
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_phy_arb.2360835826
Short name T748
Test name
Test status
Simulation time 1048979800 ps
CPU time 323.17 seconds
Started Oct 12 12:59:15 PM UTC 24
Finished Oct 12 01:04:43 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360835826 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_phy_arb.2360835826
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_prog_reset.1098168472
Short name T699
Test name
Test status
Simulation time 41619400 ps
CPU time 20.04 seconds
Started Oct 12 12:59:59 PM UTC 24
Finished Oct 12 01:00:20 PM UTC 24
Peak memory 270812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1098168472 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_prog_reset.1098168472
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rand_ops.1553510238
Short name T856
Test name
Test status
Simulation time 227422300 ps
CPU time 792.32 seconds
Started Oct 12 12:59:14 PM UTC 24
Finished Oct 12 01:12:36 PM UTC 24
Peak memory 291284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553510238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rand_ops.1553510238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_re_evict.234812738
Short name T712
Test name
Test status
Simulation time 74288600 ps
CPU time 63.26 seconds
Started Oct 12 01:00:12 PM UTC 24
Finished Oct 12 01:01:17 PM UTC 24
Peak memory 285416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234812738 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_re_evict.234812738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_ro.2061994842
Short name T710
Test name
Test status
Simulation time 497304400 ps
CPU time 100.54 seconds
Started Oct 12 12:59:28 PM UTC 24
Finished Oct 12 01:01:11 PM UTC 24
Peak memory 291540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2061994842 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_ro.2061994842
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw.2009771390
Short name T778
Test name
Test status
Simulation time 6572373100 ps
CPU time 462.17 seconds
Started Oct 12 12:59:38 PM UTC 24
Finished Oct 12 01:07:27 PM UTC 24
Peak memory 320340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009771390 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw.2009771390
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict.814179862
Short name T709
Test name
Test status
Simulation time 45566100 ps
CPU time 54.95 seconds
Started Oct 12 01:00:10 PM UTC 24
Finished Oct 12 01:01:07 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814179862 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_rw_evict.814179862
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_rw_evict_all_en.1514085084
Short name T430
Test name
Test status
Simulation time 231712800 ps
CPU time 40.68 seconds
Started Oct 12 01:00:11 PM UTC 24
Finished Oct 12 01:00:53 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1514085084 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_c
trl_rw_evict_all_en.1514085084
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_sec_info_access.1342253805
Short name T717
Test name
Test status
Simulation time 2081197700 ps
CPU time 99.78 seconds
Started Oct 12 01:00:22 PM UTC 24
Finished Oct 12 01:02:03 PM UTC 24
Peak memory 275052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342253805 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_sec_info_access.1342253805
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_smoke.1438314276
Short name T724
Test name
Test status
Simulation time 34213400 ps
CPU time 197.64 seconds
Started Oct 12 12:59:13 PM UTC 24
Finished Oct 12 01:02:34 PM UTC 24
Peak memory 289232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1438314276 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_smoke.1438314276
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/15.flash_ctrl_wo.635061502
Short name T721
Test name
Test status
Simulation time 6239488700 ps
CPU time 178.01 seconds
Started Oct 12 12:59:26 PM UTC 24
Finished Oct 12 01:02:27 PM UTC 24
Peak memory 270932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=635061502 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.flash_ctrl_wo.635061502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/15.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_alert_test.3074444509
Short name T735
Test name
Test status
Simulation time 91901300 ps
CPU time 23.24 seconds
Started Oct 12 01:02:35 PM UTC 24
Finished Oct 12 01:03:00 PM UTC 24
Peak memory 268820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074444509 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_alert_test.3074444509
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_connect.2906988256
Short name T730
Test name
Test status
Simulation time 26872500 ps
CPU time 28.51 seconds
Started Oct 12 01:02:25 PM UTC 24
Finished Oct 12 01:02:55 PM UTC 24
Peak memory 284832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906988256 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_connect.2906988256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_prog_rma_wipe_err.276588318
Short name T271
Test name
Test status
Simulation time 10072403400 ps
CPU time 52.29 seconds
Started Oct 12 01:02:35 PM UTC 24
Finished Oct 12 01:03:29 PM UTC 24
Peak memory 275368 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=276588318 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 16.flash_ctrl_hw_prog_rma_wipe_err.276588318
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_read_seed_err.903981321
Short name T729
Test name
Test status
Simulation time 55774600 ps
CPU time 19.61 seconds
Started Oct 12 01:02:34 PM UTC 24
Finished Oct 12 01:02:55 PM UTC 24
Peak memory 270844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=903981321 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
6.flash_ctrl_hw_read_seed_err.903981321
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_rma_reset.2814745580
Short name T921
Test name
Test status
Simulation time 120163316100 ps
CPU time 909.62 seconds
Started Oct 12 01:00:58 PM UTC 24
Finished Oct 12 01:16:18 PM UTC 24
Peak memory 274928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814745580
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_rma_res
et.2814745580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_hw_sec_otp.1511542185
Short name T718
Test name
Test status
Simulation time 3131118800 ps
CPU time 69.59 seconds
Started Oct 12 01:00:56 PM UTC 24
Finished Oct 12 01:02:07 PM UTC 24
Peak memory 272928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511542185 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_hw_sec_otp.1511542185
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd.503938577
Short name T738
Test name
Test status
Simulation time 719256100 ps
CPU time 128.45 seconds
Started Oct 12 01:01:41 PM UTC 24
Finished Oct 12 01:03:52 PM UTC 24
Peak memory 305848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503938577 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_intr_rd.503938577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_intr_rd_slow_flash.4146416300
Short name T769
Test name
Test status
Simulation time 61792048000 ps
CPU time 280.21 seconds
Started Oct 12 01:01:49 PM UTC 24
Finished Oct 12 01:06:33 PM UTC 24
Peak memory 303668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=4146416300 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 16.flash_ctrl_intr_rd_slow_flash.4146416300
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_invalid_op.2573822575
Short name T722
Test name
Test status
Simulation time 7581697300 ps
CPU time 83.16 seconds
Started Oct 12 01:01:07 PM UTC 24
Finished Oct 12 01:02:33 PM UTC 24
Peak memory 270992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573822575 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_invalid_op.2573822575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_lcmgr_intg.2983971585
Short name T732
Test name
Test status
Simulation time 15522300 ps
CPU time 26.72 seconds
Started Oct 12 01:02:28 PM UTC 24
Finished Oct 12 01:02:57 PM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2983971585 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.fla
sh_ctrl_lcmgr_intg.2983971585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_mp_regions.382326683
Short name T754
Test name
Test status
Simulation time 7764009700 ps
CPU time 241.12 seconds
Started Oct 12 01:01:07 PM UTC 24
Finished Oct 12 01:05:12 PM UTC 24
Peak memory 274956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=382326683 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 16.flash_ctrl_mp_regions.382326683
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_otp_reset.2863158562
Short name T751
Test name
Test status
Simulation time 76730700 ps
CPU time 226.61 seconds
Started Oct 12 01:01:01 PM UTC 24
Finished Oct 12 01:04:52 PM UTC 24
Peak memory 275212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863158562 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_otp_reset.2863158562
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_phy_arb.396743675
Short name T846
Test name
Test status
Simulation time 2816891000 ps
CPU time 649.97 seconds
Started Oct 12 01:00:56 PM UTC 24
Finished Oct 12 01:11:53 PM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396743675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_phy_arb.396743675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_prog_reset.2609375615
Short name T720
Test name
Test status
Simulation time 38121000 ps
CPU time 29.05 seconds
Started Oct 12 01:01:54 PM UTC 24
Finished Oct 12 01:02:25 PM UTC 24
Peak memory 274968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609375615 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_prog_reset.2609375615
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rand_ops.4193141775
Short name T859
Test name
Test status
Simulation time 63655300 ps
CPU time 712.74 seconds
Started Oct 12 01:00:55 PM UTC 24
Finished Oct 12 01:12:56 PM UTC 24
Peak memory 291284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4193141775 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rand_ops.4193141775
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_re_evict.3694549414
Short name T736
Test name
Test status
Simulation time 133655500 ps
CPU time 56.75 seconds
Started Oct 12 01:02:05 PM UTC 24
Finished Oct 12 01:03:03 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694549414 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_re_evict.3694549414
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_ro.4010862400
Short name T734
Test name
Test status
Simulation time 436547400 ps
CPU time 99.64 seconds
Started Oct 12 01:01:18 PM UTC 24
Finished Oct 12 01:02:59 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4010862400 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_ro.4010862400
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw.3410843486
Short name T808
Test name
Test status
Simulation time 7938963700 ps
CPU time 492.82 seconds
Started Oct 12 01:01:19 PM UTC 24
Finished Oct 12 01:09:38 PM UTC 24
Peak memory 322316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410843486 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw.3410843486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict.1759035828
Short name T725
Test name
Test status
Simulation time 70425800 ps
CPU time 35.14 seconds
Started Oct 12 01:01:58 PM UTC 24
Finished Oct 12 01:02:35 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1759035828 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_rw_evict.1759035828
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_rw_evict_all_en.1387994877
Short name T733
Test name
Test status
Simulation time 31555000 ps
CPU time 54.93 seconds
Started Oct 12 01:02:02 PM UTC 24
Finished Oct 12 01:02:58 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1387994877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_c
trl_rw_evict_all_en.1387994877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_smoke.234621587
Short name T753
Test name
Test status
Simulation time 232461600 ps
CPU time 252.48 seconds
Started Oct 12 01:00:52 PM UTC 24
Finished Oct 12 01:05:08 PM UTC 24
Peak memory 289232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234621587 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_smoke.234621587
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/16.flash_ctrl_wo.3117979709
Short name T741
Test name
Test status
Simulation time 8027639600 ps
CPU time 171.89 seconds
Started Oct 12 01:01:12 PM UTC 24
Finished Oct 12 01:04:07 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3117979709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.flash_ctrl_wo.3117979709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/16.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_alert_test.1957707334
Short name T747
Test name
Test status
Simulation time 58520300 ps
CPU time 25.01 seconds
Started Oct 12 01:04:12 PM UTC 24
Finished Oct 12 01:04:39 PM UTC 24
Peak memory 274804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957707334 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_alert_test.1957707334
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_connect.2270267494
Short name T744
Test name
Test status
Simulation time 14572600 ps
CPU time 22.57 seconds
Started Oct 12 01:03:57 PM UTC 24
Finished Oct 12 01:04:21 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270267494 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_connect.2270267494
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_disable.1064023135
Short name T743
Test name
Test status
Simulation time 12716900 ps
CPU time 22.79 seconds
Started Oct 12 01:03:48 PM UTC 24
Finished Oct 12 01:04:12 PM UTC 24
Peak memory 285248 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1064023135 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_
ctrl_disable.1064023135
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_prog_rma_wipe_err.3129117160
Short name T759
Test name
Test status
Simulation time 10029870700 ps
CPU time 88.22 seconds
Started Oct 12 01:04:12 PM UTC 24
Finished Oct 12 01:05:43 PM UTC 24
Peak memory 301488 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3129117160 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 17.flash_ctrl_hw_prog_rma_wipe_err.3129117160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_read_seed_err.148319935
Short name T746
Test name
Test status
Simulation time 25451600 ps
CPU time 20.69 seconds
Started Oct 12 01:04:07 PM UTC 24
Finished Oct 12 01:04:30 PM UTC 24
Peak memory 270980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=148319935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1
7.flash_ctrl_hw_read_seed_err.148319935
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_rma_reset.2589365145
Short name T969
Test name
Test status
Simulation time 90141692000 ps
CPU time 945.83 seconds
Started Oct 12 01:02:54 PM UTC 24
Finished Oct 12 01:18:51 PM UTC 24
Peak memory 274808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589365145
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_rma_res
et.2589365145
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_hw_sec_otp.1084836234
Short name T749
Test name
Test status
Simulation time 8738618500 ps
CPU time 113.13 seconds
Started Oct 12 01:02:50 PM UTC 24
Finished Oct 12 01:04:45 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084836234 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_hw_sec_otp.1084836234
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd.2354647361
Short name T780
Test name
Test status
Simulation time 5986724700 ps
CPU time 271.16 seconds
Started Oct 12 01:03:00 PM UTC 24
Finished Oct 12 01:07:35 PM UTC 24
Peak memory 293528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354647361 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_intr_rd.2354647361
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_intr_rd_slow_flash.273417460
Short name T775
Test name
Test status
Simulation time 22221108400 ps
CPU time 244.03 seconds
Started Oct 12 01:03:01 PM UTC 24
Finished Oct 12 01:07:09 PM UTC 24
Peak memory 303668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=273417460 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 17.flash_ctrl_intr_rd_slow_flash.273417460
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_mp_regions.3350661771
Short name T807
Test name
Test status
Simulation time 5720543400 ps
CPU time 393.98 seconds
Started Oct 12 01:02:56 PM UTC 24
Finished Oct 12 01:09:35 PM UTC 24
Peak memory 283164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3350661771 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 17.flash_ctrl_mp_regions.3350661771
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_otp_reset.27823077
Short name T188
Test name
Test status
Simulation time 136326700 ps
CPU time 140.13 seconds
Started Oct 12 01:02:55 PM UTC 24
Finished Oct 12 01:05:18 PM UTC 24
Peak memory 271040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27823077 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_otp_reset.27823077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_phy_arb.4131195025
Short name T821
Test name
Test status
Simulation time 2849609300 ps
CPU time 471.43 seconds
Started Oct 12 01:02:47 PM UTC 24
Finished Oct 12 01:10:44 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131195025 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_phy_arb.4131195025
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_prog_reset.4125209526
Short name T755
Test name
Test status
Simulation time 7496376800 ps
CPU time 130.55 seconds
Started Oct 12 01:03:04 PM UTC 24
Finished Oct 12 01:05:17 PM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125209526 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_prog_reset.4125209526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rand_ops.1597639148
Short name T943
Test name
Test status
Simulation time 83905000 ps
CPU time 871.42 seconds
Started Oct 12 01:02:47 PM UTC 24
Finished Oct 12 01:17:29 PM UTC 24
Peak memory 291284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597639148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rand_ops.1597639148
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_re_evict.2725344013
Short name T213
Test name
Test status
Simulation time 70746900 ps
CPU time 51.87 seconds
Started Oct 12 01:03:32 PM UTC 24
Finished Oct 12 01:04:25 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725344013 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_re_evict.2725344013
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_ro.2928882548
Short name T750
Test name
Test status
Simulation time 515436600 ps
CPU time 106.5 seconds
Started Oct 12 01:02:59 PM UTC 24
Finished Oct 12 01:04:47 PM UTC 24
Peak memory 303772 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2928882548 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_ro.2928882548
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw.431590449
Short name T840
Test name
Test status
Simulation time 17999276900 ps
CPU time 511.97 seconds
Started Oct 12 01:03:00 PM UTC 24
Finished Oct 12 01:11:38 PM UTC 24
Peak memory 330580 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431590449 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw.431590449
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_rw_evict.1908591608
Short name T742
Test name
Test status
Simulation time 28072000 ps
CPU time 41.11 seconds
Started Oct 12 01:03:29 PM UTC 24
Finished Oct 12 01:04:11 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908591608 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_rw_evict.1908591608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/17.flash_ctrl_smoke.2802394908
Short name T758
Test name
Test status
Simulation time 50871500 ps
CPU time 179.09 seconds
Started Oct 12 01:02:36 PM UTC 24
Finished Oct 12 01:05:39 PM UTC 24
Peak memory 287180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802394908 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.flash_ctrl_smoke.2802394908
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/17.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_alert_test.1980379902
Short name T768
Test name
Test status
Simulation time 55150900 ps
CPU time 25.29 seconds
Started Oct 12 01:05:57 PM UTC 24
Finished Oct 12 01:06:23 PM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980379902 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_alert_test.1980379902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_connect.3487190685
Short name T761
Test name
Test status
Simulation time 22412500 ps
CPU time 26.86 seconds
Started Oct 12 01:05:29 PM UTC 24
Finished Oct 12 01:05:57 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487190685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_connect.3487190685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_disable.1830601993
Short name T760
Test name
Test status
Simulation time 13433000 ps
CPU time 36.36 seconds
Started Oct 12 01:05:18 PM UTC 24
Finished Oct 12 01:05:56 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1830601993 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_
ctrl_disable.1830601993
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_prog_rma_wipe_err.3731411815
Short name T771
Test name
Test status
Simulation time 10054380200 ps
CPU time 57.56 seconds
Started Oct 12 01:05:43 PM UTC 24
Finished Oct 12 01:06:43 PM UTC 24
Peak memory 275164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3731411815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 18.flash_ctrl_hw_prog_rma_wipe_err.3731411815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_read_seed_err.4217158486
Short name T764
Test name
Test status
Simulation time 26649800 ps
CPU time 26.78 seconds
Started Oct 12 01:05:39 PM UTC 24
Finished Oct 12 01:06:07 PM UTC 24
Peak memory 270848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4217158486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
18.flash_ctrl_hw_read_seed_err.4217158486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_rma_reset.757478882
Short name T965
Test name
Test status
Simulation time 40123584200 ps
CPU time 843.14 seconds
Started Oct 12 01:04:29 PM UTC 24
Finished Oct 12 01:18:42 PM UTC 24
Peak memory 274752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757478882 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_rma_reset.757478882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_hw_sec_otp.1658784968
Short name T752
Test name
Test status
Simulation time 752243900 ps
CPU time 38.53 seconds
Started Oct 12 01:04:26 PM UTC 24
Finished Oct 12 01:05:06 PM UTC 24
Peak memory 272868 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658784968 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_hw_sec_otp.1658784968
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd.4209386202
Short name T788
Test name
Test status
Simulation time 1509814500 ps
CPU time 182.73 seconds
Started Oct 12 01:04:52 PM UTC 24
Finished Oct 12 01:07:58 PM UTC 24
Peak memory 305852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4209386202 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_intr_rd.4209386202
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_intr_rd_slow_flash.1199694395
Short name T801
Test name
Test status
Simulation time 12301777800 ps
CPU time 241.51 seconds
Started Oct 12 01:05:14 PM UTC 24
Finished Oct 12 01:09:19 PM UTC 24
Peak memory 303668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1199694395 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 18.flash_ctrl_intr_rd_slow_flash.1199694395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_invalid_op.1344645886
Short name T765
Test name
Test status
Simulation time 1565102600 ps
CPU time 83.35 seconds
Started Oct 12 01:04:43 PM UTC 24
Finished Oct 12 01:06:08 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344645886 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_invalid_op.1344645886
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_lcmgr_intg.1813877287
Short name T762
Test name
Test status
Simulation time 66086000 ps
CPU time 26.76 seconds
Started Oct 12 01:05:31 PM UTC 24
Finished Oct 12 01:05:59 PM UTC 24
Peak memory 270892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1813877287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.fla
sh_ctrl_lcmgr_intg.1813877287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_mp_regions.316708217
Short name T779
Test name
Test status
Simulation time 18293236800 ps
CPU time 165.4 seconds
Started Oct 12 01:04:40 PM UTC 24
Finished Oct 12 01:07:28 PM UTC 24
Peak memory 274952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=316708217 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 18.flash_ctrl_mp_regions.316708217
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_otp_reset.2324777780
Short name T776
Test name
Test status
Simulation time 76571300 ps
CPU time 159.86 seconds
Started Oct 12 01:04:30 PM UTC 24
Finished Oct 12 01:07:13 PM UTC 24
Peak memory 270712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324777780 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_otp_reset.2324777780
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_phy_arb.2322125072
Short name T834
Test name
Test status
Simulation time 280362000 ps
CPU time 399.66 seconds
Started Oct 12 01:04:25 PM UTC 24
Finished Oct 12 01:11:10 PM UTC 24
Peak memory 274888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2322125072 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_phy_arb.2322125072
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_prog_reset.2510981129
Short name T757
Test name
Test status
Simulation time 60872700 ps
CPU time 15.36 seconds
Started Oct 12 01:05:14 PM UTC 24
Finished Oct 12 01:05:30 PM UTC 24
Peak memory 274908 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510981129 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_prog_reset.2510981129
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rand_ops.1938166253
Short name T971
Test name
Test status
Simulation time 292295400 ps
CPU time 859.37 seconds
Started Oct 12 01:04:24 PM UTC 24
Finished Oct 12 01:18:53 PM UTC 24
Peak memory 293332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938166253 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rand_ops.1938166253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_re_evict.1743985019
Short name T766
Test name
Test status
Simulation time 90187000 ps
CPU time 56.55 seconds
Started Oct 12 01:05:18 PM UTC 24
Finished Oct 12 01:06:16 PM UTC 24
Peak memory 287364 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743985019 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_re_evict.1743985019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_ro.1262722924
Short name T770
Test name
Test status
Simulation time 1876513400 ps
CPU time 112.16 seconds
Started Oct 12 01:04:46 PM UTC 24
Finished Oct 12 01:06:40 PM UTC 24
Peak memory 291528 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1262722924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_ro.1262722924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw.3865827501
Short name T867
Test name
Test status
Simulation time 57698859100 ps
CPU time 502.9 seconds
Started Oct 12 01:04:48 PM UTC 24
Finished Oct 12 01:13:17 PM UTC 24
Peak memory 336576 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3865827501 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw.3865827501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict.396108848
Short name T419
Test name
Test status
Simulation time 28836600 ps
CPU time 58.81 seconds
Started Oct 12 01:05:14 PM UTC 24
Finished Oct 12 01:06:14 PM UTC 24
Peak memory 285420 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396108848 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_rw_evict.396108848
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_rw_evict_all_en.359677440
Short name T763
Test name
Test status
Simulation time 73318800 ps
CPU time 50.86 seconds
Started Oct 12 01:05:14 PM UTC 24
Finished Oct 12 01:06:07 PM UTC 24
Peak memory 285372 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=359677440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ct
rl_rw_evict_all_en.359677440
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_sec_info_access.4153274235
Short name T772
Test name
Test status
Simulation time 906767100 ps
CPU time 80.98 seconds
Started Oct 12 01:05:27 PM UTC 24
Finished Oct 12 01:06:51 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153274235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_sec_info_access.4153274235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_smoke.3933090610
Short name T774
Test name
Test status
Simulation time 862085500 ps
CPU time 164.09 seconds
Started Oct 12 01:04:22 PM UTC 24
Finished Oct 12 01:07:09 PM UTC 24
Peak memory 291344 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933090610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_smoke.3933090610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/18.flash_ctrl_wo.425410591
Short name T783
Test name
Test status
Simulation time 39868447100 ps
CPU time 184.32 seconds
Started Oct 12 01:04:44 PM UTC 24
Finished Oct 12 01:07:51 PM UTC 24
Peak memory 270996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=425410591 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.flash_ctrl_wo.425410591
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/18.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_alert_test.1753993166
Short name T789
Test name
Test status
Simulation time 107138100 ps
CPU time 20.89 seconds
Started Oct 12 01:07:40 PM UTC 24
Finished Oct 12 01:08:02 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753993166 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_alert_test.1753993166
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_connect.2778230598
Short name T785
Test name
Test status
Simulation time 17385600 ps
CPU time 26.52 seconds
Started Oct 12 01:07:26 PM UTC 24
Finished Oct 12 01:07:53 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2778230598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_connect.2778230598
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_prog_rma_wipe_err.1631081947
Short name T795
Test name
Test status
Simulation time 10073056200 ps
CPU time 71.43 seconds
Started Oct 12 01:07:36 PM UTC 24
Finished Oct 12 01:08:50 PM UTC 24
Peak memory 279072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1631081947 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 19.flash_ctrl_hw_prog_rma_wipe_err.1631081947
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_read_seed_err.3441339290
Short name T786
Test name
Test status
Simulation time 50045400 ps
CPU time 24.09 seconds
Started Oct 12 01:07:29 PM UTC 24
Finished Oct 12 01:07:55 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3441339290 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
19.flash_ctrl_hw_read_seed_err.3441339290
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_rma_reset.3698415184
Short name T982
Test name
Test status
Simulation time 50127067300 ps
CPU time 780.89 seconds
Started Oct 12 01:06:09 PM UTC 24
Finished Oct 12 01:19:19 PM UTC 24
Peak memory 272688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698415184
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_rma_res
et.3698415184
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_hw_sec_otp.3711257084
Short name T791
Test name
Test status
Simulation time 4994821000 ps
CPU time 144.7 seconds
Started Oct 12 01:06:08 PM UTC 24
Finished Oct 12 01:08:35 PM UTC 24
Peak memory 272800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711257084 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_hw_sec_otp.3711257084
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd.2563735123
Short name T820
Test name
Test status
Simulation time 1850977200 ps
CPU time 233.41 seconds
Started Oct 12 01:06:43 PM UTC 24
Finished Oct 12 01:10:40 PM UTC 24
Peak memory 301852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563735123 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_intr_rd.2563735123
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_intr_rd_slow_flash.267712909
Short name T832
Test name
Test status
Simulation time 23885339100 ps
CPU time 251.13 seconds
Started Oct 12 01:06:52 PM UTC 24
Finished Oct 12 01:11:06 PM UTC 24
Peak memory 301620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=267712909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 19.flash_ctrl_intr_rd_slow_flash.267712909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_invalid_op.1673215218
Short name T782
Test name
Test status
Simulation time 1546262000 ps
CPU time 85.18 seconds
Started Oct 12 01:06:21 PM UTC 24
Finished Oct 12 01:07:48 PM UTC 24
Peak memory 270796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1673215218 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_invalid_op.1673215218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_lcmgr_intg.739747608
Short name T781
Test name
Test status
Simulation time 15152200 ps
CPU time 18.76 seconds
Started Oct 12 01:07:28 PM UTC 24
Finished Oct 12 01:07:48 PM UTC 24
Peak memory 274956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=739747608 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flas
h_ctrl_lcmgr_intg.739747608
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_mp_regions.181480705
Short name T155
Test name
Test status
Simulation time 8553997000 ps
CPU time 614.66 seconds
Started Oct 12 01:06:18 PM UTC 24
Finished Oct 12 01:16:40 PM UTC 24
Peak memory 283176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=181480705 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 19.flash_ctrl_mp_regions.181480705
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_otp_reset.2540198978
Short name T815
Test name
Test status
Simulation time 57755600 ps
CPU time 230.08 seconds
Started Oct 12 01:06:16 PM UTC 24
Finished Oct 12 01:10:09 PM UTC 24
Peak memory 275004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540198978 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_otp_reset.2540198978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_phy_arb.1385844077
Short name T797
Test name
Test status
Simulation time 2803730900 ps
CPU time 173.56 seconds
Started Oct 12 01:06:07 PM UTC 24
Finished Oct 12 01:09:03 PM UTC 24
Peak memory 272796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385844077 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_phy_arb.1385844077
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_prog_reset.1773452521
Short name T777
Test name
Test status
Simulation time 20363500 ps
CPU time 15.72 seconds
Started Oct 12 01:07:07 PM UTC 24
Finished Oct 12 01:07:24 PM UTC 24
Peak memory 270804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1773452521 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_prog_reset.1773452521
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rand_ops.1539241639
Short name T912
Test name
Test status
Simulation time 81984800 ps
CPU time 594.52 seconds
Started Oct 12 01:06:00 PM UTC 24
Finished Oct 12 01:16:01 PM UTC 24
Peak memory 289236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539241639 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rand_ops.1539241639
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_re_evict.1109006714
Short name T784
Test name
Test status
Simulation time 110688200 ps
CPU time 40.77 seconds
Started Oct 12 01:07:10 PM UTC 24
Finished Oct 12 01:07:53 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109006714 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_re_evict.1109006714
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_ro.2413941287
Short name T793
Test name
Test status
Simulation time 6424147600 ps
CPU time 126.51 seconds
Started Oct 12 01:06:34 PM UTC 24
Finished Oct 12 01:08:43 PM UTC 24
Peak memory 303780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2413941287 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_ro.2413941287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict.4279198041
Short name T787
Test name
Test status
Simulation time 44536300 ps
CPU time 47.94 seconds
Started Oct 12 01:07:07 PM UTC 24
Finished Oct 12 01:07:57 PM UTC 24
Peak memory 285416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4279198041 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_rw_evict.4279198041
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_rw_evict_all_en.3480570004
Short name T420
Test name
Test status
Simulation time 42448700 ps
CPU time 47.38 seconds
Started Oct 12 01:07:09 PM UTC 24
Finished Oct 12 01:07:58 PM UTC 24
Peak memory 285540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3480570004 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_c
trl_rw_evict_all_en.3480570004
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_sec_info_access.683501817
Short name T409
Test name
Test status
Simulation time 1584751900 ps
CPU time 83.26 seconds
Started Oct 12 01:07:20 PM UTC 24
Finished Oct 12 01:08:46 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683501817 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_sec_info_access.683501817
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_smoke.2719992260
Short name T792
Test name
Test status
Simulation time 51068500 ps
CPU time 154.89 seconds
Started Oct 12 01:05:58 PM UTC 24
Finished Oct 12 01:08:35 PM UTC 24
Peak memory 289240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2719992260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_smoke.2719992260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/19.flash_ctrl_wo.4156653620
Short name T810
Test name
Test status
Simulation time 4736087500 ps
CPU time 197 seconds
Started Oct 12 01:06:24 PM UTC 24
Finished Oct 12 01:09:44 PM UTC 24
Peak memory 270992 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4156653620 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.flash_ctrl_wo.4156653620
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/19.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_access_after_disable.3150799228
Short name T22
Test name
Test status
Simulation time 18607500 ps
CPU time 24.43 seconds
Started Oct 12 12:17:53 PM UTC 24
Finished Oct 12 12:18:19 PM UTC 24
Peak memory 275244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_rw=5 +otf_num_hr=0 +en_always_all
=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3150799228 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_access_after_disabl
e_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default
.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_access_after_disable.3150799228
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_access_after_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_alert_test.875206266
Short name T113
Test name
Test status
Simulation time 37542200 ps
CPU time 21.37 seconds
Started Oct 12 12:18:30 PM UTC 24
Finished Oct 12 12:18:52 PM UTC 24
Peak memory 274940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875206266 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_alert_test.875206266
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_config_regwen.1462955643
Short name T362
Test name
Test status
Simulation time 68173500 ps
CPU time 21.52 seconds
Started Oct 12 12:18:11 PM UTC 24
Finished Oct 12 12:18:34 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462955643 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_config_regwen.1462955643
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_connect.403420348
Short name T25
Test name
Test status
Simulation time 39632100 ps
CPU time 28.7 seconds
Started Oct 12 12:17:45 PM UTC 24
Finished Oct 12 12:18:15 PM UTC 24
Peak memory 295004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403420348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_connect.403420348
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_derr_detect.2878694006
Short name T82
Test name
Test status
Simulation time 1179909100 ps
CPU time 243.07 seconds
Started Oct 12 12:15:35 PM UTC 24
Finished Oct 12 12:19:42 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2878694006 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 2.flash_ctrl_derr_detect.2878694006
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_erase_suspend.4122518114
Short name T66
Test name
Test status
Simulation time 775048400 ps
CPU time 453.98 seconds
Started Oct 12 12:12:16 PM UTC 24
Finished Oct 12 12:19:57 PM UTC 24
Peak memory 274836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122518114 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_erase_suspend.4122518114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_mp.3785099442
Short name T277
Test name
Test status
Simulation time 13050945400 ps
CPU time 2663.44 seconds
Started Oct 12 12:13:28 PM UTC 24
Finished Oct 12 12:58:20 PM UTC 24
Peak memory 274912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785099442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_mp.3785099442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_error_prog_win.2383664841
Short name T280
Test name
Test status
Simulation time 3998075400 ps
CPU time 1357.53 seconds
Started Oct 12 12:13:15 PM UTC 24
Finished Oct 12 12:36:10 PM UTC 24
Peak memory 285164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383664841 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_error_prog_win.2383664841
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_fetch_code.3118762793
Short name T58
Test name
Test status
Simulation time 1842362800 ps
CPU time 33.35 seconds
Started Oct 12 12:12:36 PM UTC 24
Finished Oct 12 12:13:11 PM UTC 24
Peak memory 275028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31
18762793 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_fetc
h_code.3118762793
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_addr_infection.2121190628
Short name T445
Test name
Test status
Simulation time 26924300 ps
CPU time 48.89 seconds
Started Oct 12 12:18:26 PM UTC 24
Finished Oct 12 12:19:16 PM UTC 24
Peak memory 285416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212119062
8 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_addr_infection_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ho
st_addr_infection.2121190628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_host_addr_infection/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_host_dir_rd.2932177241
Short name T264
Test name
Test status
Simulation time 40472900 ps
CPU time 110.78 seconds
Started Oct 12 12:11:46 PM UTC 24
Finished Oct 12 12:13:39 PM UTC 24
Peak memory 272848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2932177241 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_host_dir_rd.2932177241
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_prog_rma_wipe_err.3292730700
Short name T175
Test name
Test status
Simulation time 10018394500 ps
CPU time 115.75 seconds
Started Oct 12 12:18:24 PM UTC 24
Finished Oct 12 12:20:23 PM UTC 24
Peak memory 340536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3292730700 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_hw_prog_rma_wipe_err.3292730700
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_read_seed_err.2516775902
Short name T268
Test name
Test status
Simulation time 46847800 ps
CPU time 24.01 seconds
Started Oct 12 12:18:20 PM UTC 24
Finished Oct 12 12:18:46 PM UTC 24
Peak memory 270844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2516775902 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
2.flash_ctrl_hw_read_seed_err.2516775902
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma.1537611033
Short name T136
Test name
Test status
Simulation time 230240434500 ps
CPU time 2089.82 seconds
Started Oct 12 12:12:18 PM UTC 24
Finished Oct 12 12:47:32 PM UTC 24
Peak memory 274872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537611033
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma.1537611033
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_rma_reset.3503842253
Short name T195
Test name
Test status
Simulation time 40125139900 ps
CPU time 951.86 seconds
Started Oct 12 12:12:20 PM UTC 24
Finished Oct 12 12:28:24 PM UTC 24
Peak memory 274816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503842253
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_rma_reset.3503842253
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_hw_sec_otp.2796987305
Short name T116
Test name
Test status
Simulation time 4695046400 ps
CPU time 165.05 seconds
Started Oct 12 12:12:16 PM UTC 24
Finished Oct 12 12:15:05 PM UTC 24
Peak memory 272796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796987305 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_hw_sec_otp.2796987305
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_integrity.1177287372
Short name T473
Test name
Test status
Simulation time 3453341800 ps
CPU time 584.93 seconds
Started Oct 12 12:15:40 PM UTC 24
Finished Oct 12 12:25:33 PM UTC 24
Peak memory 336604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1177287372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_integr
ity.1177287372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd.2422679903
Short name T313
Test name
Test status
Simulation time 9039902300 ps
CPU time 171.74 seconds
Started Oct 12 12:15:54 PM UTC 24
Finished Oct 12 12:18:49 PM UTC 24
Peak memory 301760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2422679903 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_rd.2422679903
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_rd_slow_flash.2686058520
Short name T335
Test name
Test status
Simulation time 6074760300 ps
CPU time 200.16 seconds
Started Oct 12 12:16:09 PM UTC 24
Finished Oct 12 12:19:32 PM UTC 24
Peak memory 293428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2686058520 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 2.flash_ctrl_intr_rd_slow_flash.2686058520
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr.3184572535
Short name T298
Test name
Test status
Simulation time 1914038700 ps
CPU time 94.36 seconds
Started Oct 12 12:16:07 PM UTC 24
Finished Oct 12 12:17:44 PM UTC 24
Peak memory 270932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184572535 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr.3184572535
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_intr_wr_slow_flash.639780614
Short name T459
Test name
Test status
Simulation time 84926549700 ps
CPU time 364.49 seconds
Started Oct 12 12:16:16 PM UTC 24
Finished Oct 12 12:22:25 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=639780614 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 2.flash_ctrl_intr_wr_slow_flash.639780614
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_invalid_op.469776287
Short name T156
Test name
Test status
Simulation time 8358356900 ps
CPU time 85.59 seconds
Started Oct 12 12:13:30 PM UTC 24
Finished Oct 12 12:14:57 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=469776287 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_invalid_op.469776287
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_lcmgr_intg.1861587447
Short name T183
Test name
Test status
Simulation time 15956000 ps
CPU time 20.37 seconds
Started Oct 12 12:18:19 PM UTC 24
Finished Oct 12 12:18:41 PM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1861587447 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_lcmgr_intg.1861587447
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mid_op_rst.3439939910
Short name T67
Test name
Test status
Simulation time 1639887500 ps
CPU time 113.62 seconds
Started Oct 12 12:13:35 PM UTC 24
Finished Oct 12 12:15:31 PM UTC 24
Peak memory 270708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439939910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_mid_op_rst.3439939910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_mp_regions.520192083
Short name T80
Test name
Test status
Simulation time 37098340000 ps
CPU time 321.44 seconds
Started Oct 12 12:12:31 PM UTC 24
Finished Oct 12 12:17:58 PM UTC 24
Peak memory 283144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=520192083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 2.flash_ctrl_mp_regions.520192083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_otp_reset.1120553652
Short name T93
Test name
Test status
Simulation time 305144900 ps
CPU time 174.58 seconds
Started Oct 12 12:12:27 PM UTC 24
Finished Oct 12 12:15:25 PM UTC 24
Peak memory 274928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120553652 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_otp_reset.1120553652
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_oversize_error.2516303997
Short name T221
Test name
Test status
Simulation time 2123569600 ps
CPU time 169.14 seconds
Started Oct 12 12:15:39 PM UTC 24
Finished Oct 12 12:18:31 PM UTC 24
Peak memory 291508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2516303997 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 2.flash_ctrl_oversize_error.2516303997
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_phy_arb.2684874973
Short name T240
Test name
Test status
Simulation time 740011500 ps
CPU time 599.26 seconds
Started Oct 12 12:11:51 PM UTC 24
Finished Oct 12 12:21:59 PM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684874973 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_phy_arb.2684874973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_prog_reset.3516425585
Short name T442
Test name
Test status
Simulation time 204542600 ps
CPU time 26.46 seconds
Started Oct 12 12:16:38 PM UTC 24
Finished Oct 12 12:17:06 PM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516425585 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_prog_reset.3516425585
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rand_ops.4196517218
Short name T158
Test name
Test status
Simulation time 1667681300 ps
CPU time 949.73 seconds
Started Oct 12 12:11:43 PM UTC 24
Finished Oct 12 12:27:44 PM UTC 24
Peak memory 295384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4196517218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rand_ops.4196517218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_buff_evict.1766166822
Short name T164
Test name
Test status
Simulation time 732784600 ps
CPU time 228.87 seconds
Started Oct 12 12:11:46 PM UTC 24
Finished Oct 12 12:15:39 PM UTC 24
Peak memory 272780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766166822 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_buff_evict.1766166822
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rd_intg.2865563610
Short name T301
Test name
Test status
Simulation time 134083200 ps
CPU time 47.84 seconds
Started Oct 12 12:17:47 PM UTC 24
Finished Oct 12 12:18:36 PM UTC 24
Peak memory 285480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +otf_num_hr=100 +en_always_read=1 +cdc_ins
trumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=286556361
0 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rd_path_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rd_intg.2865563610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rd_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_re_evict.2225955637
Short name T157
Test name
Test status
Simulation time 287784900 ps
CPU time 48.41 seconds
Started Oct 12 12:17:07 PM UTC 24
Finished Oct 12 12:17:57 PM UTC 24
Peak memory 287444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225955637 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_re_evict.2225955637
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_derr.2944366779
Short name T299
Test name
Test status
Simulation time 59270800 ps
CPU time 33.67 seconds
Started Oct 12 12:15:19 PM UTC 24
Finished Oct 12 12:15:54 PM UTC 24
Peak memory 275092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2944366779 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flas
h_ctrl_read_word_sweep_derr.2944366779
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_read_word_sweep_serr.1093335534
Short name T163
Test name
Test status
Simulation time 25496500 ps
CPU time 34.91 seconds
Started Oct 12 12:14:57 PM UTC 24
Finished Oct 12 12:15:34 PM UTC 24
Peak memory 275068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1093335534 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_read_word_sweep_serr.1093335534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro.392016810
Short name T239
Test name
Test status
Simulation time 1143104700 ps
CPU time 138.59 seconds
Started Oct 12 12:13:54 PM UTC 24
Finished Oct 12 12:16:15 PM UTC 24
Peak memory 301752 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=392016810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ro.392016810
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_derr.2559146416
Short name T222
Test name
Test status
Simulation time 3111016300 ps
CPU time 182.86 seconds
Started Oct 12 12:15:26 PM UTC 24
Finished Oct 12 12:18:32 PM UTC 24
Peak memory 291512 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559146416 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 2.flash_ctrl_ro_derr.2559146416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_ro_serr.3062801516
Short name T378
Test name
Test status
Simulation time 3192677600 ps
CPU time 164.14 seconds
Started Oct 12 12:14:58 PM UTC 24
Finished Oct 12 12:17:46 PM UTC 24
Peak memory 291540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3062801516 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash
_ctrl_ro_serr.3062801516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_derr.2900060935
Short name T447
Test name
Test status
Simulation time 4601360500 ps
CPU time 231.65 seconds
Started Oct 12 12:15:32 PM UTC 24
Finished Oct 12 12:19:28 PM UTC 24
Peak memory 297688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2900060935 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 2.flash_ctrl_rw_derr.2900060935
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict.457592953
Short name T52
Test name
Test status
Simulation time 122392400 ps
CPU time 57.72 seconds
Started Oct 12 12:16:41 PM UTC 24
Finished Oct 12 12:17:40 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457592953 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_evict.457592953
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_evict_all_en.3332863597
Short name T427
Test name
Test status
Simulation time 30744300 ps
CPU time 48.5 seconds
Started Oct 12 12:17:02 PM UTC 24
Finished Oct 12 12:17:52 PM UTC 24
Peak memory 287560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3332863597 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ct
rl_rw_evict_all_en.3332863597
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_rw_serr.3801411177
Short name T444
Test name
Test status
Simulation time 3305482900 ps
CPU time 223.09 seconds
Started Oct 12 12:15:00 PM UTC 24
Finished Oct 12 12:18:48 PM UTC 24
Peak memory 291588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=3801411177 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_rw_serr.3801411177
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_cm.3928944420
Short name T139
Test name
Test status
Simulation time 2062068600 ps
CPU time 6728.17 seconds
Started Oct 12 12:17:21 PM UTC 24
Finished Oct 12 02:10:40 PM UTC 24
Peak memory 311960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3928944420 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_cm.3928944420
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sec_info_access.2044835888
Short name T172
Test name
Test status
Simulation time 5067602900 ps
CPU time 81.34 seconds
Started Oct 12 12:17:35 PM UTC 24
Finished Oct 12 12:18:58 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044835888 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sec_info_access.2044835888
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_address.4228662182
Short name T441
Test name
Test status
Simulation time 6605178100 ps
CPU time 117.8 seconds
Started Oct 12 12:15:05 PM UTC 24
Finished Oct 12 12:17:06 PM UTC 24
Peak memory 275140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=422
8662182 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_ser
r_address.4228662182
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_serr_counter.3968262815
Short name T217
Test name
Test status
Simulation time 686115900 ps
CPU time 63.38 seconds
Started Oct 12 12:15:02 PM UTC 24
Finished Oct 12 12:16:08 PM UTC 24
Peak memory 285380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39
68262815 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_se
rr_counter.3968262815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke.3400788257
Short name T377
Test name
Test status
Simulation time 21751500 ps
CPU time 115.83 seconds
Started Oct 12 12:11:35 PM UTC 24
Finished Oct 12 12:13:34 PM UTC 24
Peak memory 287180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400788257 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke.3400788257
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_smoke_hw.4054575706
Short name T439
Test name
Test status
Simulation time 45315600 ps
CPU time 40.93 seconds
Started Oct 12 12:11:35 PM UTC 24
Finished Oct 12 12:12:18 PM UTC 24
Peak memory 270688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054575706 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_smoke_hw.4054575706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_stress_all.35861172
Short name T544
Test name
Test status
Simulation time 10800039300 ps
CPU time 1196.99 seconds
Started Oct 12 12:17:42 PM UTC 24
Finished Oct 12 12:37:52 PM UTC 24
Peak memory 293276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35861172 -assert nopostproc +UVM_TESTNAM
E=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_stress_all.35861172
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_sw_op.835183858
Short name T440
Test name
Test status
Simulation time 25790300 ps
CPU time 47.64 seconds
Started Oct 12 12:11:46 PM UTC 24
Finished Oct 12 12:12:35 PM UTC 24
Peak memory 272716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835183858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_sw_op.835183858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wo.3473102348
Short name T443
Test name
Test status
Simulation time 9802794000 ps
CPU time 216.42 seconds
Started Oct 12 12:13:40 PM UTC 24
Finished Oct 12 12:17:20 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3473102348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.flash_ctrl_wo.3473102348
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/2.flash_ctrl_wr_intg.1357455906
Short name T20
Test name
Test status
Simulation time 148940100 ps
CPU time 25.57 seconds
Started Oct 12 12:17:53 PM UTC 24
Finished Oct 12 12:18:20 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=10 +otf_num_hr=0 +ecc_mode=1 +en_always_pr
og=1 +otf_rd_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl
+ntb_random_seed=1357455906 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_wr_path_intg_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 2.flash_ctrl_wr_intg.1357455906
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/2.flash_ctrl_wr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_alert_test.1883101602
Short name T794
Test name
Test status
Simulation time 44630400 ps
CPU time 17.44 seconds
Started Oct 12 01:08:28 PM UTC 24
Finished Oct 12 01:08:47 PM UTC 24
Peak memory 268800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883101602 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_alert_test.1883101602
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_connect.2115136818
Short name T790
Test name
Test status
Simulation time 19454800 ps
CPU time 24.98 seconds
Started Oct 12 01:08:04 PM UTC 24
Finished Oct 12 01:08:31 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2115136818 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_connect.2115136818
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_hw_sec_otp.2442928618
Short name T811
Test name
Test status
Simulation time 2055189500 ps
CPU time 113.24 seconds
Started Oct 12 01:07:49 PM UTC 24
Finished Oct 12 01:09:45 PM UTC 24
Peak memory 274664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442928618 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_hw_sec_otp.2442928618
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd.1888330513
Short name T827
Test name
Test status
Simulation time 1566118300 ps
CPU time 181.44 seconds
Started Oct 12 01:07:53 PM UTC 24
Finished Oct 12 01:10:58 PM UTC 24
Peak memory 305884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888330513 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_intr_rd.1888330513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_intr_rd_slow_flash.3802138782
Short name T842
Test name
Test status
Simulation time 71648352400 ps
CPU time 224.17 seconds
Started Oct 12 01:07:54 PM UTC 24
Finished Oct 12 01:11:42 PM UTC 24
Peak memory 303664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3802138782 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 20.flash_ctrl_intr_rd_slow_flash.3802138782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_otp_reset.3969476377
Short name T824
Test name
Test status
Simulation time 152107100 ps
CPU time 173.86 seconds
Started Oct 12 01:07:52 PM UTC 24
Finished Oct 12 01:10:49 PM UTC 24
Peak memory 274804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969476377 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_otp_reset.3969476377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_prog_reset.2215571443
Short name T829
Test name
Test status
Simulation time 6656805300 ps
CPU time 179.63 seconds
Started Oct 12 01:07:56 PM UTC 24
Finished Oct 12 01:10:58 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2215571443 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_prog_reset.2215571443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict.973819245
Short name T321
Test name
Test status
Simulation time 46827400 ps
CPU time 47.85 seconds
Started Oct 12 01:07:58 PM UTC 24
Finished Oct 12 01:08:47 PM UTC 24
Peak memory 285424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973819245 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_rw_evict.973819245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_rw_evict_all_en.3327467221
Short name T796
Test name
Test status
Simulation time 48035500 ps
CPU time 51.84 seconds
Started Oct 12 01:07:59 PM UTC 24
Finished Oct 12 01:08:52 PM UTC 24
Peak memory 285384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3327467221 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_c
trl_rw_evict_all_en.3327467221
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/20.flash_ctrl_smoke.3062500302
Short name T830
Test name
Test status
Simulation time 33648400 ps
CPU time 186.77 seconds
Started Oct 12 01:07:49 PM UTC 24
Finished Oct 12 01:10:59 PM UTC 24
Peak memory 287244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062500302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.flash_ctrl_smoke.3062500302
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/20.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_alert_test.819249471
Short name T806
Test name
Test status
Simulation time 44257500 ps
CPU time 21.5 seconds
Started Oct 12 01:09:06 PM UTC 24
Finished Oct 12 01:09:29 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819249471 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_alert_test.819249471
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_connect.3455421628
Short name T804
Test name
Test status
Simulation time 55741900 ps
CPU time 23.11 seconds
Started Oct 12 01:09:04 PM UTC 24
Finished Oct 12 01:09:28 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455421628 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_connect.3455421628
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_disable.1328546996
Short name T805
Test name
Test status
Simulation time 32162900 ps
CPU time 36.67 seconds
Started Oct 12 01:08:51 PM UTC 24
Finished Oct 12 01:09:29 PM UTC 24
Peak memory 285400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1328546996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_
ctrl_disable.1328546996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_hw_sec_otp.331273506
Short name T835
Test name
Test status
Simulation time 4138593300 ps
CPU time 156.68 seconds
Started Oct 12 01:08:34 PM UTC 24
Finished Oct 12 01:11:13 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331273506 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_hw_sec_otp.331273506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd.2721107008
Short name T819
Test name
Test status
Simulation time 1326344500 ps
CPU time 114.51 seconds
Started Oct 12 01:08:36 PM UTC 24
Finished Oct 12 01:10:33 PM UTC 24
Peak memory 305972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721107008 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_intr_rd.2721107008
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_intr_rd_slow_flash.929247431
Short name T348
Test name
Test status
Simulation time 53054843200 ps
CPU time 362.58 seconds
Started Oct 12 01:08:44 PM UTC 24
Finished Oct 12 01:14:51 PM UTC 24
Peak memory 301620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=929247431 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 21.flash_ctrl_intr_rd_slow_flash.929247431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_otp_reset.435696781
Short name T825
Test name
Test status
Simulation time 43250300 ps
CPU time 131.22 seconds
Started Oct 12 01:08:36 PM UTC 24
Finished Oct 12 01:10:50 PM UTC 24
Peak memory 274928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435696781 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_otp_reset.435696781
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_prog_reset.2454608632
Short name T800
Test name
Test status
Simulation time 280230400 ps
CPU time 22.59 seconds
Started Oct 12 01:08:46 PM UTC 24
Finished Oct 12 01:09:10 PM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454608632 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_prog_reset.2454608632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict.3411880818
Short name T802
Test name
Test status
Simulation time 28544900 ps
CPU time 34.43 seconds
Started Oct 12 01:08:48 PM UTC 24
Finished Oct 12 01:09:24 PM UTC 24
Peak memory 287464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411880818 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_rw_evict.3411880818
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_rw_evict_all_en.2862483309
Short name T803
Test name
Test status
Simulation time 89918000 ps
CPU time 37.81 seconds
Started Oct 12 01:08:48 PM UTC 24
Finished Oct 12 01:09:28 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2862483309 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_c
trl_rw_evict_all_en.2862483309
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_sec_info_access.146390428
Short name T402
Test name
Test status
Simulation time 4289677800 ps
CPU time 91.11 seconds
Started Oct 12 01:08:53 PM UTC 24
Finished Oct 12 01:10:26 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146390428 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_sec_info_access.146390428
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/21.flash_ctrl_smoke.650855744
Short name T812
Test name
Test status
Simulation time 275511600 ps
CPU time 71.34 seconds
Started Oct 12 01:08:32 PM UTC 24
Finished Oct 12 01:09:45 PM UTC 24
Peak memory 285136 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=650855744 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.flash_ctrl_smoke.650855744
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/21.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_alert_test.1919398433
Short name T813
Test name
Test status
Simulation time 265044400 ps
CPU time 25.06 seconds
Started Oct 12 01:09:40 PM UTC 24
Finished Oct 12 01:10:07 PM UTC 24
Peak memory 268996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919398433 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_alert_test.1919398433
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_connect.2198802080
Short name T814
Test name
Test status
Simulation time 62174500 ps
CPU time 26.74 seconds
Started Oct 12 01:09:39 PM UTC 24
Finished Oct 12 01:10:07 PM UTC 24
Peak memory 284832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198802080 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_connect.2198802080
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_disable.3887934821
Short name T368
Test name
Test status
Simulation time 35383900 ps
CPU time 42.87 seconds
Started Oct 12 01:09:30 PM UTC 24
Finished Oct 12 01:10:15 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3887934821 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_
ctrl_disable.3887934821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_hw_sec_otp.723668402
Short name T838
Test name
Test status
Simulation time 71501661000 ps
CPU time 141.89 seconds
Started Oct 12 01:09:11 PM UTC 24
Finished Oct 12 01:11:36 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=723668402 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_hw_sec_otp.723668402
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd.534903959
Short name T336
Test name
Test status
Simulation time 3322152800 ps
CPU time 284.83 seconds
Started Oct 12 01:09:25 PM UTC 24
Finished Oct 12 01:14:13 PM UTC 24
Peak memory 293504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=534903959 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_intr_rd.534903959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_intr_rd_slow_flash.2672447671
Short name T844
Test name
Test status
Simulation time 23144771600 ps
CPU time 139.97 seconds
Started Oct 12 01:09:29 PM UTC 24
Finished Oct 12 01:11:51 PM UTC 24
Peak memory 303796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2672447671 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 22.flash_ctrl_intr_rd_slow_flash.2672447671
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_otp_reset.3042934251
Short name T185
Test name
Test status
Simulation time 211853400 ps
CPU time 156.57 seconds
Started Oct 12 01:09:19 PM UTC 24
Finished Oct 12 01:11:58 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3042934251 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_otp_reset.3042934251
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_prog_reset.1992308914
Short name T865
Test name
Test status
Simulation time 3822420700 ps
CPU time 222.45 seconds
Started Oct 12 01:09:29 PM UTC 24
Finished Oct 12 01:13:15 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992308914 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_prog_reset.1992308914
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_rw_evict.3982895506
Short name T816
Test name
Test status
Simulation time 41379000 ps
CPU time 50.34 seconds
Started Oct 12 01:09:29 PM UTC 24
Finished Oct 12 01:10:21 PM UTC 24
Peak memory 285416 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982895506 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_rw_evict.3982895506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/22.flash_ctrl_smoke.4024862860
Short name T828
Test name
Test status
Simulation time 29424500 ps
CPU time 108.69 seconds
Started Oct 12 01:09:07 PM UTC 24
Finished Oct 12 01:10:58 PM UTC 24
Peak memory 287184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024862860 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.flash_ctrl_smoke.4024862860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/22.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_alert_test.3478483560
Short name T831
Test name
Test status
Simulation time 49816800 ps
CPU time 26.09 seconds
Started Oct 12 01:10:32 PM UTC 24
Finished Oct 12 01:10:59 PM UTC 24
Peak memory 268948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478483560 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_alert_test.3478483560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_connect.1004997438
Short name T822
Test name
Test status
Simulation time 24392000 ps
CPU time 17.99 seconds
Started Oct 12 01:10:26 PM UTC 24
Finished Oct 12 01:10:46 PM UTC 24
Peak memory 295008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1004997438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_connect.1004997438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_disable.3865242755
Short name T823
Test name
Test status
Simulation time 10883600 ps
CPU time 30.72 seconds
Started Oct 12 01:10:15 PM UTC 24
Finished Oct 12 01:10:47 PM UTC 24
Peak memory 285340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3865242755 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_
ctrl_disable.3865242755
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_hw_sec_otp.2326928120
Short name T818
Test name
Test status
Simulation time 498775500 ps
CPU time 45.21 seconds
Started Oct 12 01:09:45 PM UTC 24
Finished Oct 12 01:10:32 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326928120 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_hw_sec_otp.2326928120
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_intr_rd_slow_flash.3333208093
Short name T333
Test name
Test status
Simulation time 208185167800 ps
CPU time 488.48 seconds
Started Oct 12 01:10:08 PM UTC 24
Finished Oct 12 01:18:22 PM UTC 24
Peak memory 303664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3333208093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 23.flash_ctrl_intr_rd_slow_flash.3333208093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_otp_reset.1341059621
Short name T389
Test name
Test status
Simulation time 38620400 ps
CPU time 163.06 seconds
Started Oct 12 01:09:45 PM UTC 24
Finished Oct 12 01:12:32 PM UTC 24
Peak memory 270900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341059621 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_otp_reset.1341059621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_prog_reset.1731053048
Short name T817
Test name
Test status
Simulation time 67692200 ps
CPU time 21.84 seconds
Started Oct 12 01:10:08 PM UTC 24
Finished Oct 12 01:10:31 PM UTC 24
Peak memory 270800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731053048 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_prog_reset.1731053048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict.2337564753
Short name T826
Test name
Test status
Simulation time 27949800 ps
CPU time 43.97 seconds
Started Oct 12 01:10:10 PM UTC 24
Finished Oct 12 01:10:55 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337564753 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_rw_evict.2337564753
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_rw_evict_all_en.3478908171
Short name T433
Test name
Test status
Simulation time 37013600 ps
CPU time 43.44 seconds
Started Oct 12 01:10:11 PM UTC 24
Finished Oct 12 01:10:56 PM UTC 24
Peak memory 285408 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3478908171 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_c
trl_rw_evict_all_en.3478908171
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_sec_info_access.926430852
Short name T841
Test name
Test status
Simulation time 9741763800 ps
CPU time 76.61 seconds
Started Oct 12 01:10:22 PM UTC 24
Finished Oct 12 01:11:41 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=926430852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_sec_info_access.926430852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/23.flash_ctrl_smoke.3358897308
Short name T890
Test name
Test status
Simulation time 87004400 ps
CPU time 301.72 seconds
Started Oct 12 01:09:45 PM UTC 24
Finished Oct 12 01:14:52 PM UTC 24
Peak memory 289240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3358897308 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.flash_ctrl_smoke.3358897308
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/23.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_alert_test.4063242758
Short name T836
Test name
Test status
Simulation time 97170700 ps
CPU time 19.41 seconds
Started Oct 12 01:10:59 PM UTC 24
Finished Oct 12 01:11:20 PM UTC 24
Peak memory 268804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4063242758 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_alert_test.4063242758
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_connect.637834007
Short name T837
Test name
Test status
Simulation time 13721400 ps
CPU time 24.1 seconds
Started Oct 12 01:10:57 PM UTC 24
Finished Oct 12 01:11:22 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637834007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_connect.637834007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_disable.1050110329
Short name T123
Test name
Test status
Simulation time 14909200 ps
CPU time 34.96 seconds
Started Oct 12 01:10:51 PM UTC 24
Finished Oct 12 01:11:27 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1050110329 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_
ctrl_disable.1050110329
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_hw_sec_otp.2326678768
Short name T324
Test name
Test status
Simulation time 4672339500 ps
CPU time 215.19 seconds
Started Oct 12 01:10:34 PM UTC 24
Finished Oct 12 01:14:12 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2326678768 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_hw_sec_otp.2326678768
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd.110189277
Short name T868
Test name
Test status
Simulation time 720099800 ps
CPU time 150.18 seconds
Started Oct 12 01:10:45 PM UTC 24
Finished Oct 12 01:13:18 PM UTC 24
Peak memory 305856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110189277 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_intr_rd.110189277
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_intr_rd_slow_flash.543592604
Short name T913
Test name
Test status
Simulation time 24244732000 ps
CPU time 311.3 seconds
Started Oct 12 01:10:46 PM UTC 24
Finished Oct 12 01:16:02 PM UTC 24
Peak memory 301620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=543592604 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 24.flash_ctrl_intr_rd_slow_flash.543592604
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_otp_reset.1826690971
Short name T858
Test name
Test status
Simulation time 259775600 ps
CPU time 126.51 seconds
Started Oct 12 01:10:41 PM UTC 24
Finished Oct 12 01:12:50 PM UTC 24
Peak memory 270860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826690971 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_otp_reset.1826690971
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_prog_reset.2618720649
Short name T833
Test name
Test status
Simulation time 19018100 ps
CPU time 19.28 seconds
Started Oct 12 01:10:47 PM UTC 24
Finished Oct 12 01:11:08 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618720649 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_prog_reset.2618720649
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict.2611897018
Short name T843
Test name
Test status
Simulation time 72472000 ps
CPU time 52.46 seconds
Started Oct 12 01:10:48 PM UTC 24
Finished Oct 12 01:11:42 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611897018 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_rw_evict.2611897018
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_rw_evict_all_en.3258817745
Short name T839
Test name
Test status
Simulation time 29091200 ps
CPU time 47.28 seconds
Started Oct 12 01:10:49 PM UTC 24
Finished Oct 12 01:11:38 PM UTC 24
Peak memory 285456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3258817745 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_c
trl_rw_evict_all_en.3258817745
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/24.flash_ctrl_smoke.1574072650
Short name T870
Test name
Test status
Simulation time 103194000 ps
CPU time 176.11 seconds
Started Oct 12 01:10:34 PM UTC 24
Finished Oct 12 01:13:33 PM UTC 24
Peak memory 287312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574072650 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.flash_ctrl_smoke.1574072650
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/24.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_alert_test.1110945887
Short name T848
Test name
Test status
Simulation time 61685900 ps
CPU time 26.49 seconds
Started Oct 12 01:11:36 PM UTC 24
Finished Oct 12 01:12:04 PM UTC 24
Peak memory 268932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1110945887 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_alert_test.1110945887
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_connect.288868286
Short name T845
Test name
Test status
Simulation time 42431400 ps
CPU time 22.8 seconds
Started Oct 12 01:11:28 PM UTC 24
Finished Oct 12 01:11:53 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=288868286 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_connect.288868286
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_disable.968530188
Short name T371
Test name
Test status
Simulation time 27250100 ps
CPU time 41.34 seconds
Started Oct 12 01:11:20 PM UTC 24
Finished Oct 12 01:12:03 PM UTC 24
Peak memory 275100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=968530188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c
trl_disable.968530188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_hw_sec_otp.516556792
Short name T850
Test name
Test status
Simulation time 8156110000 ps
CPU time 65.93 seconds
Started Oct 12 01:10:59 PM UTC 24
Finished Oct 12 01:12:07 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516556792 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_hw_sec_otp.516556792
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd.2443784322
Short name T885
Test name
Test status
Simulation time 6105031300 ps
CPU time 205.57 seconds
Started Oct 12 01:11:00 PM UTC 24
Finished Oct 12 01:14:29 PM UTC 24
Peak memory 301692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2443784322 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_intr_rd.2443784322
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_intr_rd_slow_flash.3916945621
Short name T906
Test name
Test status
Simulation time 14798071400 ps
CPU time 259.36 seconds
Started Oct 12 01:11:07 PM UTC 24
Finished Oct 12 01:15:31 PM UTC 24
Peak memory 301812 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3916945621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 25.flash_ctrl_intr_rd_slow_flash.3916945621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_otp_reset.1615176426
Short name T878
Test name
Test status
Simulation time 334341800 ps
CPU time 175.63 seconds
Started Oct 12 01:11:00 PM UTC 24
Finished Oct 12 01:13:59 PM UTC 24
Peak memory 272952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615176426 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_otp_reset.1615176426
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_prog_reset.3393253919
Short name T873
Test name
Test status
Simulation time 2120344300 ps
CPU time 152.97 seconds
Started Oct 12 01:11:09 PM UTC 24
Finished Oct 12 01:13:44 PM UTC 24
Peak memory 275036 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3393253919 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_prog_reset.3393253919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict.4062319556
Short name T434
Test name
Test status
Simulation time 105617600 ps
CPU time 36.3 seconds
Started Oct 12 01:11:11 PM UTC 24
Finished Oct 12 01:11:48 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062319556 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_rw_evict.4062319556
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_rw_evict_all_en.2963128162
Short name T847
Test name
Test status
Simulation time 68292600 ps
CPU time 43.62 seconds
Started Oct 12 01:11:14 PM UTC 24
Finished Oct 12 01:11:59 PM UTC 24
Peak memory 287452 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2963128162 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_c
trl_rw_evict_all_en.2963128162
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/25.flash_ctrl_smoke.908468880
Short name T855
Test name
Test status
Simulation time 24409300 ps
CPU time 90.99 seconds
Started Oct 12 01:10:59 PM UTC 24
Finished Oct 12 01:12:32 PM UTC 24
Peak memory 287192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908468880 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.flash_ctrl_smoke.908468880
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/25.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_alert_test.2416887728
Short name T854
Test name
Test status
Simulation time 218756000 ps
CPU time 29.25 seconds
Started Oct 12 01:12:01 PM UTC 24
Finished Oct 12 01:12:31 PM UTC 24
Peak memory 274956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416887728 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_alert_test.2416887728
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_connect.1468505002
Short name T853
Test name
Test status
Simulation time 131728900 ps
CPU time 30.17 seconds
Started Oct 12 01:12:00 PM UTC 24
Finished Oct 12 01:12:31 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468505002 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_connect.1468505002
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_disable.1010430807
Short name T851
Test name
Test status
Simulation time 15213100 ps
CPU time 32.92 seconds
Started Oct 12 01:11:54 PM UTC 24
Finished Oct 12 01:12:29 PM UTC 24
Peak memory 285340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1010430807 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_
ctrl_disable.1010430807
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_hw_sec_otp.2859303867
Short name T874
Test name
Test status
Simulation time 1349894900 ps
CPU time 125.46 seconds
Started Oct 12 01:11:40 PM UTC 24
Finished Oct 12 01:13:47 PM UTC 24
Peak memory 275044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859303867 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_hw_sec_otp.2859303867
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd.1129305516
Short name T919
Test name
Test status
Simulation time 16361098500 ps
CPU time 266.12 seconds
Started Oct 12 01:11:43 PM UTC 24
Finished Oct 12 01:16:13 PM UTC 24
Peak memory 301696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1129305516 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_intr_rd.1129305516
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_intr_rd_slow_flash.1150008190
Short name T334
Test name
Test status
Simulation time 51479097500 ps
CPU time 463.67 seconds
Started Oct 12 01:11:43 PM UTC 24
Finished Oct 12 01:19:32 PM UTC 24
Peak memory 303672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1150008190 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 26.flash_ctrl_intr_rd_slow_flash.1150008190
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_otp_reset.2190870932
Short name T899
Test name
Test status
Simulation time 397750200 ps
CPU time 209.92 seconds
Started Oct 12 01:11:42 PM UTC 24
Finished Oct 12 01:15:15 PM UTC 24
Peak memory 270652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190870932 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_otp_reset.2190870932
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_prog_reset.2597065564
Short name T849
Test name
Test status
Simulation time 300350700 ps
CPU time 16.26 seconds
Started Oct 12 01:11:49 PM UTC 24
Finished Oct 12 01:12:06 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597065564 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_prog_reset.2597065564
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict.3637915237
Short name T857
Test name
Test status
Simulation time 28035300 ps
CPU time 51.79 seconds
Started Oct 12 01:11:52 PM UTC 24
Finished Oct 12 01:12:45 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637915237 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_rw_evict.3637915237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_rw_evict_all_en.1210738459
Short name T852
Test name
Test status
Simulation time 31284800 ps
CPU time 34.64 seconds
Started Oct 12 01:11:53 PM UTC 24
Finished Oct 12 01:12:29 PM UTC 24
Peak memory 285384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1210738459 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_c
trl_rw_evict_all_en.1210738459
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_sec_info_access.2662762453
Short name T879
Test name
Test status
Simulation time 12256098200 ps
CPU time 121.51 seconds
Started Oct 12 01:11:57 PM UTC 24
Finished Oct 12 01:14:00 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662762453 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_sec_info_access.2662762453
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/26.flash_ctrl_smoke.1200798238
Short name T882
Test name
Test status
Simulation time 26341100 ps
CPU time 158.8 seconds
Started Oct 12 01:11:40 PM UTC 24
Finished Oct 12 01:14:21 PM UTC 24
Peak memory 276952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200798238 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.flash_ctrl_smoke.1200798238
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/26.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_alert_test.2782340256
Short name T860
Test name
Test status
Simulation time 35431900 ps
CPU time 19.43 seconds
Started Oct 12 01:12:36 PM UTC 24
Finished Oct 12 01:12:57 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782340256 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_alert_test.2782340256
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_connect.1534136676
Short name T862
Test name
Test status
Simulation time 14648600 ps
CPU time 22.88 seconds
Started Oct 12 01:12:33 PM UTC 24
Finished Oct 12 01:12:57 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534136676 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_connect.1534136676
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_hw_sec_otp.165420821
Short name T866
Test name
Test status
Simulation time 4364382000 ps
CPU time 70.41 seconds
Started Oct 12 01:12:05 PM UTC 24
Finished Oct 12 01:13:17 PM UTC 24
Peak memory 274976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165420821 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_hw_sec_otp.165420821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd.169499973
Short name T888
Test name
Test status
Simulation time 732658800 ps
CPU time 154.96 seconds
Started Oct 12 01:12:08 PM UTC 24
Finished Oct 12 01:14:46 PM UTC 24
Peak memory 305856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169499973 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_intr_rd.169499973
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_intr_rd_slow_flash.2574689538
Short name T901
Test name
Test status
Simulation time 9593620300 ps
CPU time 173.24 seconds
Started Oct 12 01:12:27 PM UTC 24
Finished Oct 12 01:15:24 PM UTC 24
Peak memory 303668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2574689538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 27.flash_ctrl_intr_rd_slow_flash.2574689538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_otp_reset.1599413738
Short name T898
Test name
Test status
Simulation time 143249700 ps
CPU time 178.99 seconds
Started Oct 12 01:12:07 PM UTC 24
Finished Oct 12 01:15:09 PM UTC 24
Peak memory 274952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599413738 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_otp_reset.1599413738
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_prog_reset.2680194070
Short name T861
Test name
Test status
Simulation time 112301900 ps
CPU time 26.04 seconds
Started Oct 12 01:12:29 PM UTC 24
Finished Oct 12 01:12:57 PM UTC 24
Peak memory 270864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680194070 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_prog_reset.2680194070
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict.3467670874
Short name T864
Test name
Test status
Simulation time 34389700 ps
CPU time 38.85 seconds
Started Oct 12 01:12:31 PM UTC 24
Finished Oct 12 01:13:11 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467670874 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_rw_evict.3467670874
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_rw_evict_all_en.1451226799
Short name T863
Test name
Test status
Simulation time 31467900 ps
CPU time 34.2 seconds
Started Oct 12 01:12:32 PM UTC 24
Finished Oct 12 01:13:07 PM UTC 24
Peak memory 285604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1451226799 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_c
trl_rw_evict_all_en.1451226799
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_sec_info_access.166993275
Short name T880
Test name
Test status
Simulation time 30772347000 ps
CPU time 96.99 seconds
Started Oct 12 01:12:33 PM UTC 24
Finished Oct 12 01:14:12 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166993275 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_sec_info_access.166993275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/27.flash_ctrl_smoke.2764992534
Short name T877
Test name
Test status
Simulation time 104451500 ps
CPU time 111.06 seconds
Started Oct 12 01:12:04 PM UTC 24
Finished Oct 12 01:13:57 PM UTC 24
Peak memory 287192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2764992534 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.flash_ctrl_smoke.2764992534
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/27.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_alert_test.3135901817
Short name T875
Test name
Test status
Simulation time 269082500 ps
CPU time 29.82 seconds
Started Oct 12 01:13:18 PM UTC 24
Finished Oct 12 01:13:49 PM UTC 24
Peak memory 274952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3135901817 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_alert_test.3135901817
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_connect.3524235929
Short name T872
Test name
Test status
Simulation time 52351300 ps
CPU time 22.51 seconds
Started Oct 12 01:13:17 PM UTC 24
Finished Oct 12 01:13:41 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524235929 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_connect.3524235929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_disable.3802170580
Short name T871
Test name
Test status
Simulation time 33639100 ps
CPU time 26.18 seconds
Started Oct 12 01:13:12 PM UTC 24
Finished Oct 12 01:13:39 PM UTC 24
Peak memory 285468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3802170580 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_
ctrl_disable.3802170580
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_hw_sec_otp.1482327759
Short name T886
Test name
Test status
Simulation time 18027875300 ps
CPU time 112.55 seconds
Started Oct 12 01:12:47 PM UTC 24
Finished Oct 12 01:14:41 PM UTC 24
Peak memory 274976 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482327759 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_hw_sec_otp.1482327759
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd.944485515
Short name T914
Test name
Test status
Simulation time 1397315000 ps
CPU time 181.81 seconds
Started Oct 12 01:12:57 PM UTC 24
Finished Oct 12 01:16:02 PM UTC 24
Peak memory 301760 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944485515 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_intr_rd.944485515
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_intr_rd_slow_flash.4266746383
Short name T920
Test name
Test status
Simulation time 18887209000 ps
CPU time 191.66 seconds
Started Oct 12 01:12:58 PM UTC 24
Finished Oct 12 01:16:13 PM UTC 24
Peak memory 303668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=4266746383 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 28.flash_ctrl_intr_rd_slow_flash.4266746383
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_otp_reset.3359034862
Short name T191
Test name
Test status
Simulation time 378401000 ps
CPU time 154.69 seconds
Started Oct 12 01:12:51 PM UTC 24
Finished Oct 12 01:15:28 PM UTC 24
Peak memory 270860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359034862 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_otp_reset.3359034862
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_prog_reset.2888789118
Short name T869
Test name
Test status
Simulation time 85860200 ps
CPU time 21.63 seconds
Started Oct 12 01:12:58 PM UTC 24
Finished Oct 12 01:13:21 PM UTC 24
Peak memory 275088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888789118 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_prog_reset.2888789118
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_rw_evict_all_en.785448572
Short name T876
Test name
Test status
Simulation time 41665400 ps
CPU time 39.9 seconds
Started Oct 12 01:13:08 PM UTC 24
Finished Oct 12 01:13:50 PM UTC 24
Peak memory 285380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=785448572 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ct
rl_rw_evict_all_en.785448572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_sec_info_access.2569587588
Short name T887
Test name
Test status
Simulation time 2913667300 ps
CPU time 88.06 seconds
Started Oct 12 01:13:16 PM UTC 24
Finished Oct 12 01:14:46 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569587588 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_sec_info_access.2569587588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/28.flash_ctrl_smoke.856092774
Short name T908
Test name
Test status
Simulation time 131985900 ps
CPU time 168.53 seconds
Started Oct 12 01:12:45 PM UTC 24
Finished Oct 12 01:15:37 PM UTC 24
Peak memory 287176 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856092774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.flash_ctrl_smoke.856092774
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/28.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_alert_test.1763120010
Short name T884
Test name
Test status
Simulation time 223033000 ps
CPU time 28.7 seconds
Started Oct 12 01:13:58 PM UTC 24
Finished Oct 12 01:14:28 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763120010 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_alert_test.1763120010
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_connect.2190671205
Short name T883
Test name
Test status
Simulation time 54430200 ps
CPU time 29.28 seconds
Started Oct 12 01:13:51 PM UTC 24
Finished Oct 12 01:14:22 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2190671205 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_connect.2190671205
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_disable.4280190110
Short name T881
Test name
Test status
Simulation time 51057600 ps
CPU time 25.2 seconds
Started Oct 12 01:13:48 PM UTC 24
Finished Oct 12 01:14:14 PM UTC 24
Peak memory 285308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4280190110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_
ctrl_disable.4280190110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_hw_sec_otp.1847702882
Short name T900
Test name
Test status
Simulation time 8863201700 ps
CPU time 114.99 seconds
Started Oct 12 01:13:19 PM UTC 24
Finished Oct 12 01:15:17 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847702882 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_hw_sec_otp.1847702882
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd.114917695
Short name T909
Test name
Test status
Simulation time 4261387100 ps
CPU time 137.49 seconds
Started Oct 12 01:13:33 PM UTC 24
Finished Oct 12 01:15:53 PM UTC 24
Peak memory 301712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114917695 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_intr_rd.114917695
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_intr_rd_slow_flash.2702945000
Short name T1012
Test name
Test status
Simulation time 88527455000 ps
CPU time 391.38 seconds
Started Oct 12 01:13:39 PM UTC 24
Finished Oct 12 01:20:16 PM UTC 24
Peak memory 301620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2702945000 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 29.flash_ctrl_intr_rd_slow_flash.2702945000
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_otp_reset.1391730397
Short name T916
Test name
Test status
Simulation time 112983900 ps
CPU time 160.31 seconds
Started Oct 12 01:13:22 PM UTC 24
Finished Oct 12 01:16:06 PM UTC 24
Peak memory 274936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391730397 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_otp_reset.1391730397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_prog_reset.4273776959
Short name T92
Test name
Test status
Simulation time 42385700 ps
CPU time 15.48 seconds
Started Oct 12 01:13:42 PM UTC 24
Finished Oct 12 01:13:58 PM UTC 24
Peak memory 270916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273776959 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_prog_reset.4273776959
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict.325470519
Short name T435
Test name
Test status
Simulation time 57341600 ps
CPU time 57.64 seconds
Started Oct 12 01:13:46 PM UTC 24
Finished Oct 12 01:14:45 PM UTC 24
Peak memory 287472 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325470519 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_rw_evict.325470519
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_rw_evict_all_en.3204302422
Short name T889
Test name
Test status
Simulation time 283046100 ps
CPU time 59.45 seconds
Started Oct 12 01:13:47 PM UTC 24
Finished Oct 12 01:14:48 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3204302422 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_c
trl_rw_evict_all_en.3204302422
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_sec_info_access.3985213977
Short name T895
Test name
Test status
Simulation time 1982964100 ps
CPU time 70.83 seconds
Started Oct 12 01:13:50 PM UTC 24
Finished Oct 12 01:15:03 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3985213977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_sec_info_access.3985213977
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/29.flash_ctrl_smoke.5731664
Short name T935
Test name
Test status
Simulation time 103083700 ps
CPU time 241.55 seconds
Started Oct 12 01:13:18 PM UTC 24
Finished Oct 12 01:17:23 PM UTC 24
Peak memory 287184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5731664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TE
ST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.flash_ctrl_smoke.5731664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/29.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_alert_test.2065097532
Short name T465
Test name
Test status
Simulation time 111542100 ps
CPU time 23.41 seconds
Started Oct 12 12:22:51 PM UTC 24
Finished Oct 12 12:23:15 PM UTC 24
Peak memory 274956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065097532 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_alert_test.2065097532
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_config_regwen.2487598000
Short name T306
Test name
Test status
Simulation time 39583800 ps
CPU time 20.72 seconds
Started Oct 12 12:22:38 PM UTC 24
Finished Oct 12 12:23:00 PM UTC 24
Peak memory 272896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487598000 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_config_regwen.2487598000
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_connect.2840984351
Short name T463
Test name
Test status
Simulation time 128089000 ps
CPU time 15.22 seconds
Started Oct 12 12:22:27 PM UTC 24
Finished Oct 12 12:22:43 PM UTC 24
Peak memory 295068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840984351 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_connect.2840984351
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_disable.3244410235
Short name T308
Test name
Test status
Simulation time 17976900 ps
CPU time 33 seconds
Started Oct 12 12:21:56 PM UTC 24
Finished Oct 12 12:22:31 PM UTC 24
Peak memory 285272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3244410235 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_c
trl_disable.3244410235
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_erase_suspend.1766805385
Short name T496
Test name
Test status
Simulation time 3353183200 ps
CPU time 593.78 seconds
Started Oct 12 12:18:50 PM UTC 24
Finished Oct 12 12:28:52 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766805385 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_erase_suspend.1766805385
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_mp.1695908163
Short name T737
Test name
Test status
Simulation time 5605801300 ps
CPU time 2626.7 seconds
Started Oct 12 12:19:33 PM UTC 24
Finished Oct 12 01:03:47 PM UTC 24
Peak memory 272852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695908163 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_mp.1695908163
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_error_prog_win.2084251402
Short name T561
Test name
Test status
Simulation time 8271392800 ps
CPU time 1267.26 seconds
Started Oct 12 12:19:30 PM UTC 24
Finished Oct 12 12:40:51 PM UTC 24
Peak memory 285292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084251402 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_error_prog_win.2084251402
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fetch_code.4245060255
Short name T449
Test name
Test status
Simulation time 99198800 ps
CPU time 26.76 seconds
Started Oct 12 12:19:21 PM UTC 24
Finished Oct 12 12:19:49 PM UTC 24
Peak memory 274900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42
45060255 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_fetc
h_code.4245060255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_fs_sup.3110997497
Short name T467
Test name
Test status
Simulation time 1482420600 ps
CPU time 51.6 seconds
Started Oct 12 12:22:28 PM UTC 24
Finished Oct 12 12:23:21 PM UTC 24
Peak memory 275000 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110997
497 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_f
s_sup.3110997497
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_full_mem_access.1798860354
Short name T1119
Test name
Test status
Simulation time 135976874100 ps
CPU time 3912.4 seconds
Started Oct 12 12:19:22 PM UTC 24
Finished Oct 12 01:25:18 PM UTC 24
Peak memory 275596 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1798860354 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_full_mem_access.1798860354
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_ctrl_arb.2929861860
Short name T672
Test name
Test status
Simulation time 479079755100 ps
CPU time 2213.3 seconds
Started Oct 12 12:19:08 PM UTC 24
Finished Oct 12 12:56:26 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929861860 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_ctrl_arb.2929861860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_host_dir_rd.1810090980
Short name T452
Test name
Test status
Simulation time 56059300 ps
CPU time 137.1 seconds
Started Oct 12 12:18:42 PM UTC 24
Finished Oct 12 12:21:02 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810090980 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_host_dir_rd.1810090980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_prog_rma_wipe_err.3156193581
Short name T194
Test name
Test status
Simulation time 10011778800 ps
CPU time 128.51 seconds
Started Oct 12 12:22:51 PM UTC 24
Finished Oct 12 12:25:01 PM UTC 24
Peak memory 360996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3156193581 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_hw_prog_rma_wipe_err.3156193581
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_read_seed_err.3174549486
Short name T266
Test name
Test status
Simulation time 25678100 ps
CPU time 20.62 seconds
Started Oct 12 12:22:46 PM UTC 24
Finished Oct 12 12:23:08 PM UTC 24
Peak memory 269028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3174549486 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
3.flash_ctrl_hw_read_seed_err.3174549486
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_rma_reset.1159010988
Short name T197
Test name
Test status
Simulation time 270243883800 ps
CPU time 963.38 seconds
Started Oct 12 12:18:53 PM UTC 24
Finished Oct 12 12:35:08 PM UTC 24
Peak memory 274880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159010988
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_rma_reset.1159010988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_hw_sec_otp.1245354646
Short name T456
Test name
Test status
Simulation time 8436692100 ps
CPU time 178.52 seconds
Started Oct 12 12:18:49 PM UTC 24
Finished Oct 12 12:21:51 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245354646 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_hw_sec_otp.1245354646
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_integrity.1679095096
Short name T514
Test name
Test status
Simulation time 4102152200 ps
CPU time 663.91 seconds
Started Oct 12 12:21:10 PM UTC 24
Finished Oct 12 12:32:23 PM UTC 24
Peak memory 330460 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1679095096 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_integr
ity.1679095096
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd.381769209
Short name T338
Test name
Test status
Simulation time 1822975900 ps
CPU time 231.36 seconds
Started Oct 12 12:21:14 PM UTC 24
Finished Oct 12 12:25:09 PM UTC 24
Peak memory 301692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381769209 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_rd.381769209
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_rd_slow_flash.2023410040
Short name T309
Test name
Test status
Simulation time 23235980600 ps
CPU time 151.32 seconds
Started Oct 12 12:21:22 PM UTC 24
Finished Oct 12 12:23:56 PM UTC 24
Peak memory 303672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2023410040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 3.flash_ctrl_intr_rd_slow_flash.2023410040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr.3782471165
Short name T460
Test name
Test status
Simulation time 3857714700 ps
CPU time 66.04 seconds
Started Oct 12 12:21:19 PM UTC 24
Finished Oct 12 12:22:27 PM UTC 24
Peak memory 271056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782471165 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr.3782471165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_intr_wr_slow_flash.810485610
Short name T471
Test name
Test status
Simulation time 40517622700 ps
CPU time 234.24 seconds
Started Oct 12 12:21:24 PM UTC 24
Finished Oct 12 12:25:22 PM UTC 24
Peak memory 270900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=810485610 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 3.flash_ctrl_intr_wr_slow_flash.810485610
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_invalid_op.532866715
Short name T165
Test name
Test status
Simulation time 5964637700 ps
CPU time 63.19 seconds
Started Oct 12 12:19:43 PM UTC 24
Finished Oct 12 12:20:48 PM UTC 24
Peak memory 272848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532866715 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_invalid_op.532866715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_lcmgr_intg.2854817070
Short name T272
Test name
Test status
Simulation time 14888400 ps
CPU time 24.92 seconds
Started Oct 12 12:22:44 PM UTC 24
Finished Oct 12 12:23:10 PM UTC 24
Peak memory 272912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2854817070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_lcmgr_intg.2854817070
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mid_op_rst.140379726
Short name T91
Test name
Test status
Simulation time 3296188100 ps
CPU time 87.05 seconds
Started Oct 12 12:19:44 PM UTC 24
Finished Oct 12 12:21:13 PM UTC 24
Peak memory 270708 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=140379726 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_mid_op_rst.140379726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_mp_regions.2778251954
Short name T88
Test name
Test status
Simulation time 27125508100 ps
CPU time 338.52 seconds
Started Oct 12 12:19:17 PM UTC 24
Finished Oct 12 12:25:00 PM UTC 24
Peak memory 285192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2778251954 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_mp_regions.2778251954
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_otp_reset.63816588
Short name T187
Test name
Test status
Simulation time 70448400 ps
CPU time 210.79 seconds
Started Oct 12 12:18:59 PM UTC 24
Finished Oct 12 12:22:33 PM UTC 24
Peak memory 273160 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63816588 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_otp_reset.63816588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_oversize_error.2100312115
Short name T314
Test name
Test status
Simulation time 9665263400 ps
CPU time 211.29 seconds
Started Oct 12 12:21:03 PM UTC 24
Finished Oct 12 12:24:38 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=2100312115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 3.flash_ctrl_oversize_error.2100312115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_ack_consistency.1765214578
Short name T70
Test name
Test status
Simulation time 24081100 ps
CPU time 22.07 seconds
Started Oct 12 12:22:34 PM UTC 24
Finished Oct 12 12:22:57 PM UTC 24
Peak memory 293200 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1765214578 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_ack_consistency.1765214578
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_arb.1514916755
Short name T464
Test name
Test status
Simulation time 83109400 ps
CPU time 238.04 seconds
Started Oct 12 12:18:48 PM UTC 24
Finished Oct 12 12:22:50 PM UTC 24
Peak memory 272796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514916755 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_phy_arb.1514916755
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_phy_host_grant_err.708980977
Short name T203
Test name
Test status
Simulation time 43799000 ps
CPU time 19.42 seconds
Started Oct 12 12:22:34 PM UTC 24
Finished Oct 12 12:22:55 PM UTC 24
Peak memory 273280 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=708980977 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 3.flash_ctrl_phy_host_grant_err.708980977
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_prog_reset.1290218467
Short name T458
Test name
Test status
Simulation time 25595800 ps
CPU time 19.18 seconds
Started Oct 12 12:21:32 PM UTC 24
Finished Oct 12 12:21:52 PM UTC 24
Peak memory 270864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1290218467 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_prog_reset.1290218467
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rand_ops.229278310
Short name T531
Test name
Test status
Simulation time 6560015600 ps
CPU time 1053.53 seconds
Started Oct 12 12:18:35 PM UTC 24
Finished Oct 12 12:36:21 PM UTC 24
Peak memory 293332 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229278310 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rand_ops.229278310
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rd_buff_evict.425918330
Short name T455
Test name
Test status
Simulation time 87814800 ps
CPU time 153.14 seconds
Started Oct 12 12:18:46 PM UTC 24
Finished Oct 12 12:21:22 PM UTC 24
Peak memory 272852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425918330 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_
test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rd_buff_evict.425918330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_re_evict.3423663788
Short name T421
Test name
Test status
Simulation time 326780000 ps
CPU time 53.89 seconds
Started Oct 12 12:21:54 PM UTC 24
Finished Oct 12 12:22:50 PM UTC 24
Peak memory 287444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3423663788 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_re_evict.3423663788
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_derr.3548872039
Short name T453
Test name
Test status
Simulation time 32125400 ps
CPU time 31.09 seconds
Started Oct 12 12:20:36 PM UTC 24
Finished Oct 12 12:21:09 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3548872039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flas
h_ctrl_read_word_sweep_derr.3548872039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_read_word_sweep_serr.2405426048
Short name T451
Test name
Test status
Simulation time 23852600 ps
CPU time 43.57 seconds
Started Oct 12 12:20:00 PM UTC 24
Finished Oct 12 12:20:45 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405426048 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_read_word_sweep_serr.2405426048
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro.3033318112
Short name T302
Test name
Test status
Simulation time 1174558100 ps
CPU time 136.13 seconds
Started Oct 12 12:19:58 PM UTC 24
Finished Oct 12 12:22:17 PM UTC 24
Peak memory 291612 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3033318112 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ro.3033318112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_derr.3677949553
Short name T212
Test name
Test status
Simulation time 1287319900 ps
CPU time 166.8 seconds
Started Oct 12 12:20:46 PM UTC 24
Finished Oct 12 12:23:35 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677949553 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 3.flash_ctrl_ro_derr.3677949553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_ro_serr.2166487267
Short name T218
Test name
Test status
Simulation time 2099539300 ps
CPU time 125.98 seconds
Started Oct 12 12:20:10 PM UTC 24
Finished Oct 12 12:22:19 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2166487267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash
_ctrl_ro_serr.2166487267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw.3224196180
Short name T485
Test name
Test status
Simulation time 3415496700 ps
CPU time 479.86 seconds
Started Oct 12 12:19:58 PM UTC 24
Finished Oct 12 12:28:04 PM UTC 24
Peak memory 320204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224196180 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw.3224196180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_derr.1040917621
Short name T470
Test name
Test status
Simulation time 5773885400 ps
CPU time 251.36 seconds
Started Oct 12 12:20:49 PM UTC 24
Finished Oct 12 12:25:04 PM UTC 24
Peak memory 297668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=1040917621 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 3.flash_ctrl_rw_derr.1040917621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_evict_all_en.3307879060
Short name T461
Test name
Test status
Simulation time 31268200 ps
CPU time 40.19 seconds
Started Oct 12 12:21:52 PM UTC 24
Finished Oct 12 12:22:34 PM UTC 24
Peak memory 285380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3307879060 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ct
rl_rw_evict_all_en.3307879060
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_rw_serr.2594858538
Short name T466
Test name
Test status
Simulation time 1481174900 ps
CPU time 181.91 seconds
Started Oct 12 12:20:16 PM UTC 24
Finished Oct 12 12:23:21 PM UTC 24
Peak memory 291540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2594858538 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_rw_serr.2594858538
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_cm.1234670685
Short name T140
Test name
Test status
Simulation time 4115816300 ps
CPU time 6581.61 seconds
Started Oct 12 12:21:59 PM UTC 24
Finished Oct 12 02:12:50 PM UTC 24
Peak memory 311940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234670685 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_cm.1234670685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sec_info_access.1103243438
Short name T173
Test name
Test status
Simulation time 586823700 ps
CPU time 81.21 seconds
Started Oct 12 12:22:18 PM UTC 24
Finished Oct 12 12:23:41 PM UTC 24
Peak memory 274924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1103243438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sec_info_access.1103243438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_address.1350337927
Short name T457
Test name
Test status
Simulation time 1730274000 ps
CPU time 79.68 seconds
Started Oct 12 12:20:29 PM UTC 24
Finished Oct 12 12:21:51 PM UTC 24
Peak memory 275132 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135
0337927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_ser
r_address.1350337927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_serr_counter.2670575051
Short name T454
Test name
Test status
Simulation time 491250000 ps
CPU time 56.9 seconds
Started Oct 12 12:20:23 PM UTC 24
Finished Oct 12 12:21:22 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26
70575051 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_se
rr_counter.2670575051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke.1902583093
Short name T385
Test name
Test status
Simulation time 22585900 ps
CPU time 175.82 seconds
Started Oct 12 12:18:32 PM UTC 24
Finished Oct 12 12:21:31 PM UTC 24
Peak memory 289232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1902583093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke.1902583093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_smoke_hw.307284188
Short name T448
Test name
Test status
Simulation time 15732800 ps
CPU time 54.39 seconds
Started Oct 12 12:18:33 PM UTC 24
Finished Oct 12 12:19:29 PM UTC 24
Peak memory 270816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307284188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_smoke_hw.307284188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_stress_all.2447215112
Short name T478
Test name
Test status
Simulation time 411259000 ps
CPU time 268.82 seconds
Started Oct 12 12:22:20 PM UTC 24
Finished Oct 12 12:26:52 PM UTC 24
Peak memory 289184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447215112 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_stress_all.2447215112
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_sw_op.2992924237
Short name T446
Test name
Test status
Simulation time 44258800 ps
CPU time 43.04 seconds
Started Oct 12 12:18:37 PM UTC 24
Finished Oct 12 12:19:22 PM UTC 24
Peak memory 272736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992924237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_sw_op.2992924237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/3.flash_ctrl_wo.1578098086
Short name T462
Test name
Test status
Simulation time 4265010000 ps
CPU time 165.33 seconds
Started Oct 12 12:19:50 PM UTC 24
Finished Oct 12 12:22:38 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1578098086 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.flash_ctrl_wo.1578098086
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/3.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_alert_test.3369064508
Short name T892
Test name
Test status
Simulation time 94403100 ps
CPU time 22.27 seconds
Started Oct 12 01:14:30 PM UTC 24
Finished Oct 12 01:14:53 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369064508 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_alert_test.3369064508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_connect.3838058709
Short name T891
Test name
Test status
Simulation time 40619300 ps
CPU time 21.9 seconds
Started Oct 12 01:14:30 PM UTC 24
Finished Oct 12 01:14:53 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838058709 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_connect.3838058709
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_disable.1143390115
Short name T894
Test name
Test status
Simulation time 19362100 ps
CPU time 35.62 seconds
Started Oct 12 01:14:22 PM UTC 24
Finished Oct 12 01:14:59 PM UTC 24
Peak memory 285340 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1143390115 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_
ctrl_disable.1143390115
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_hw_sec_otp.3639716122
Short name T926
Test name
Test status
Simulation time 3837351700 ps
CPU time 152.01 seconds
Started Oct 12 01:14:00 PM UTC 24
Finished Oct 12 01:16:34 PM UTC 24
Peak memory 272800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639716122 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_hw_sec_otp.3639716122
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd.1342190621
Short name T923
Test name
Test status
Simulation time 2728468600 ps
CPU time 130.12 seconds
Started Oct 12 01:14:13 PM UTC 24
Finished Oct 12 01:16:25 PM UTC 24
Peak memory 305884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342190621 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_intr_rd.1342190621
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_intr_rd_slow_flash.3506681858
Short name T978
Test name
Test status
Simulation time 26016041400 ps
CPU time 293.07 seconds
Started Oct 12 01:14:13 PM UTC 24
Finished Oct 12 01:19:10 PM UTC 24
Peak memory 303664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3506681858 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 30.flash_ctrl_intr_rd_slow_flash.3506681858
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_otp_reset.3090465668
Short name T939
Test name
Test status
Simulation time 73484900 ps
CPU time 203.07 seconds
Started Oct 12 01:14:02 PM UTC 24
Finished Oct 12 01:17:28 PM UTC 24
Peak memory 275064 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3090465668 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_otp_reset.3090465668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict.3751182261
Short name T896
Test name
Test status
Simulation time 30521600 ps
CPU time 51.76 seconds
Started Oct 12 01:14:14 PM UTC 24
Finished Oct 12 01:15:07 PM UTC 24
Peak memory 287464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751182261 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_rw_evict.3751182261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_rw_evict_all_en.1590569675
Short name T893
Test name
Test status
Simulation time 28219900 ps
CPU time 42.32 seconds
Started Oct 12 01:14:15 PM UTC 24
Finished Oct 12 01:14:59 PM UTC 24
Peak memory 285520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1590569675 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_c
trl_rw_evict_all_en.1590569675
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_sec_info_access.1130306656
Short name T910
Test name
Test status
Simulation time 1858999800 ps
CPU time 89.86 seconds
Started Oct 12 01:14:23 PM UTC 24
Finished Oct 12 01:15:54 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130306656 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_sec_info_access.1130306656
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/30.flash_ctrl_smoke.2700418355
Short name T964
Test name
Test status
Simulation time 80739700 ps
CPU time 276.5 seconds
Started Oct 12 01:13:59 PM UTC 24
Finished Oct 12 01:18:40 PM UTC 24
Peak memory 289240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700418355 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.flash_ctrl_smoke.2700418355
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/30.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_alert_test.1459740693
Short name T902
Test name
Test status
Simulation time 35923800 ps
CPU time 22.7 seconds
Started Oct 12 01:15:00 PM UTC 24
Finished Oct 12 01:15:24 PM UTC 24
Peak memory 268928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459740693 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_alert_test.1459740693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_connect.3457535201
Short name T905
Test name
Test status
Simulation time 13669300 ps
CPU time 29.39 seconds
Started Oct 12 01:15:00 PM UTC 24
Finished Oct 12 01:15:31 PM UTC 24
Peak memory 295008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3457535201 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_connect.3457535201
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_disable.2200559442
Short name T904
Test name
Test status
Simulation time 23624100 ps
CPU time 34.34 seconds
Started Oct 12 01:14:54 PM UTC 24
Finished Oct 12 01:15:30 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2200559442 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_
ctrl_disable.2200559442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_hw_sec_otp.2445458462
Short name T951
Test name
Test status
Simulation time 4904013700 ps
CPU time 185.58 seconds
Started Oct 12 01:14:46 PM UTC 24
Finished Oct 12 01:17:55 PM UTC 24
Peak memory 274844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445458462 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_hw_sec_otp.2445458462
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd.3613780713
Short name T948
Test name
Test status
Simulation time 3204728700 ps
CPU time 172.34 seconds
Started Oct 12 01:14:47 PM UTC 24
Finished Oct 12 01:17:43 PM UTC 24
Peak memory 305876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3613780713 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_intr_rd.3613780713
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_intr_rd_slow_flash.3908288066
Short name T1003
Test name
Test status
Simulation time 147635860200 ps
CPU time 311.18 seconds
Started Oct 12 01:14:48 PM UTC 24
Finished Oct 12 01:20:04 PM UTC 24
Peak memory 301620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3908288066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 31.flash_ctrl_intr_rd_slow_flash.3908288066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_otp_reset.2666951031
Short name T932
Test name
Test status
Simulation time 76357900 ps
CPU time 138.07 seconds
Started Oct 12 01:14:46 PM UTC 24
Finished Oct 12 01:17:07 PM UTC 24
Peak memory 271056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666951031 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_otp_reset.2666951031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict.865509165
Short name T907
Test name
Test status
Simulation time 107493400 ps
CPU time 40.83 seconds
Started Oct 12 01:14:53 PM UTC 24
Finished Oct 12 01:15:36 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865509165 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_rw_evict.865509165
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_rw_evict_all_en.1254136373
Short name T903
Test name
Test status
Simulation time 81870200 ps
CPU time 34.69 seconds
Started Oct 12 01:14:53 PM UTC 24
Finished Oct 12 01:15:29 PM UTC 24
Peak memory 285520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1254136373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_c
trl_rw_evict_all_en.1254136373
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_sec_info_access.2508591561
Short name T408
Test name
Test status
Simulation time 4736271800 ps
CPU time 91.54 seconds
Started Oct 12 01:14:54 PM UTC 24
Finished Oct 12 01:16:28 PM UTC 24
Peak memory 275112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508591561 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_sec_info_access.2508591561
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/31.flash_ctrl_smoke.3122498372
Short name T942
Test name
Test status
Simulation time 34876400 ps
CPU time 163.87 seconds
Started Oct 12 01:14:42 PM UTC 24
Finished Oct 12 01:17:28 PM UTC 24
Peak memory 287260 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122498372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.flash_ctrl_smoke.3122498372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/31.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_alert_test.2272039702
Short name T911
Test name
Test status
Simulation time 110995500 ps
CPU time 23.17 seconds
Started Oct 12 01:15:31 PM UTC 24
Finished Oct 12 01:15:55 PM UTC 24
Peak memory 268820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272039702 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_alert_test.2272039702
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_connect.1258938601
Short name T915
Test name
Test status
Simulation time 20601300 ps
CPU time 30.67 seconds
Started Oct 12 01:15:31 PM UTC 24
Finished Oct 12 01:16:03 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258938601 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_connect.1258938601
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_disable.2045080263
Short name T918
Test name
Test status
Simulation time 48940600 ps
CPU time 42.89 seconds
Started Oct 12 01:15:25 PM UTC 24
Finished Oct 12 01:16:10 PM UTC 24
Peak memory 285272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2045080263 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_
ctrl_disable.2045080263
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_hw_sec_otp.3905591448
Short name T980
Test name
Test status
Simulation time 11504509500 ps
CPU time 241.29 seconds
Started Oct 12 01:15:09 PM UTC 24
Finished Oct 12 01:19:14 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3905591448 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_hw_sec_otp.3905591448
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd.1396064484
Short name T949
Test name
Test status
Simulation time 12543251400 ps
CPU time 154.3 seconds
Started Oct 12 01:15:10 PM UTC 24
Finished Oct 12 01:17:47 PM UTC 24
Peak memory 303808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396064484 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_intr_rd.1396064484
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_intr_rd_slow_flash.3941935081
Short name T961
Test name
Test status
Simulation time 34975740400 ps
CPU time 186.86 seconds
Started Oct 12 01:15:16 PM UTC 24
Finished Oct 12 01:18:26 PM UTC 24
Peak memory 303672 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3941935081 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 32.flash_ctrl_intr_rd_slow_flash.3941935081
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_otp_reset.3968958288
Short name T954
Test name
Test status
Simulation time 37680700 ps
CPU time 170.3 seconds
Started Oct 12 01:15:09 PM UTC 24
Finished Oct 12 01:18:02 PM UTC 24
Peak memory 270840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3968958288 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_otp_reset.3968958288
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict.2345706611
Short name T917
Test name
Test status
Simulation time 28897300 ps
CPU time 47.02 seconds
Started Oct 12 01:15:18 PM UTC 24
Finished Oct 12 01:16:07 PM UTC 24
Peak memory 287560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345706611 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_rw_evict.2345706611
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_rw_evict_all_en.1673227634
Short name T922
Test name
Test status
Simulation time 28560700 ps
CPU time 52.98 seconds
Started Oct 12 01:15:24 PM UTC 24
Finished Oct 12 01:16:19 PM UTC 24
Peak memory 285520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1673227634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_c
trl_rw_evict_all_en.1673227634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_sec_info_access.2985150215
Short name T933
Test name
Test status
Simulation time 2075552500 ps
CPU time 97.07 seconds
Started Oct 12 01:15:28 PM UTC 24
Finished Oct 12 01:17:08 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985150215 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_sec_info_access.2985150215
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/32.flash_ctrl_smoke.1157688832
Short name T931
Test name
Test status
Simulation time 29268400 ps
CPU time 112.1 seconds
Started Oct 12 01:15:03 PM UTC 24
Finished Oct 12 01:16:58 PM UTC 24
Peak memory 287192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157688832 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.flash_ctrl_smoke.1157688832
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/32.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_alert_test.3290840915
Short name T924
Test name
Test status
Simulation time 17816600 ps
CPU time 24.65 seconds
Started Oct 12 01:16:03 PM UTC 24
Finished Oct 12 01:16:28 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290840915 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_alert_test.3290840915
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_connect.3479926095
Short name T925
Test name
Test status
Simulation time 184405300 ps
CPU time 28.88 seconds
Started Oct 12 01:16:03 PM UTC 24
Finished Oct 12 01:16:33 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479926095 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_connect.3479926095
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_disable.2375580294
Short name T369
Test name
Test status
Simulation time 28079400 ps
CPU time 27.87 seconds
Started Oct 12 01:16:00 PM UTC 24
Finished Oct 12 01:16:29 PM UTC 24
Peak memory 285308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2375580294 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_
ctrl_disable.2375580294
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_hw_sec_otp.3647999632
Short name T941
Test name
Test status
Simulation time 5078256600 ps
CPU time 114.21 seconds
Started Oct 12 01:15:32 PM UTC 24
Finished Oct 12 01:17:28 PM UTC 24
Peak memory 274844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647999632 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_hw_sec_otp.3647999632
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd.1559905436
Short name T968
Test name
Test status
Simulation time 1490660200 ps
CPU time 187.5 seconds
Started Oct 12 01:15:38 PM UTC 24
Finished Oct 12 01:18:48 PM UTC 24
Peak memory 301852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559905436 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_intr_rd.1559905436
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_intr_rd_slow_flash.3794889901
Short name T993
Test name
Test status
Simulation time 18823180300 ps
CPU time 217.33 seconds
Started Oct 12 01:16:00 PM UTC 24
Finished Oct 12 01:19:41 PM UTC 24
Peak memory 301644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3794889901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 33.flash_ctrl_intr_rd_slow_flash.3794889901
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_otp_reset.1205737125
Short name T962
Test name
Test status
Simulation time 144800600 ps
CPU time 170.99 seconds
Started Oct 12 01:15:37 PM UTC 24
Finished Oct 12 01:18:31 PM UTC 24
Peak memory 270924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205737125 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_otp_reset.1205737125
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict.3342854382
Short name T927
Test name
Test status
Simulation time 40095800 ps
CPU time 49.97 seconds
Started Oct 12 01:16:00 PM UTC 24
Finished Oct 12 01:16:52 PM UTC 24
Peak memory 287560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342854382 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_rw_evict.3342854382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_rw_evict_all_en.380871627
Short name T928
Test name
Test status
Simulation time 30429500 ps
CPU time 52.6 seconds
Started Oct 12 01:16:00 PM UTC 24
Finished Oct 12 01:16:54 PM UTC 24
Peak memory 285384 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=380871627 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ct
rl_rw_evict_all_en.380871627
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_sec_info_access.1342430438
Short name T936
Test name
Test status
Simulation time 897404100 ps
CPU time 78.93 seconds
Started Oct 12 01:16:02 PM UTC 24
Finished Oct 12 01:17:23 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342430438 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_sec_info_access.1342430438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/33.flash_ctrl_smoke.704665409
Short name T975
Test name
Test status
Simulation time 120904900 ps
CPU time 206.75 seconds
Started Oct 12 01:15:32 PM UTC 24
Finished Oct 12 01:19:02 PM UTC 24
Peak memory 289236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704665409 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.flash_ctrl_smoke.704665409
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/33.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_alert_test.965554174
Short name T929
Test name
Test status
Simulation time 300931000 ps
CPU time 23.65 seconds
Started Oct 12 01:16:30 PM UTC 24
Finished Oct 12 01:16:55 PM UTC 24
Peak memory 274948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965554174 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_alert_test.965554174
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_connect.2047199370
Short name T930
Test name
Test status
Simulation time 20166200 ps
CPU time 26.09 seconds
Started Oct 12 01:16:29 PM UTC 24
Finished Oct 12 01:16:57 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2047199370 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_connect.2047199370
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_disable.2157258463
Short name T390
Test name
Test status
Simulation time 22760100 ps
CPU time 31.25 seconds
Started Oct 12 01:16:19 PM UTC 24
Finished Oct 12 01:16:52 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2157258463 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_
ctrl_disable.2157258463
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_hw_sec_otp.3504822051
Short name T947
Test name
Test status
Simulation time 4544293000 ps
CPU time 92.11 seconds
Started Oct 12 01:16:07 PM UTC 24
Finished Oct 12 01:17:41 PM UTC 24
Peak memory 274844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504822051 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_hw_sec_otp.3504822051
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd.3108718785
Short name T1007
Test name
Test status
Simulation time 6656657400 ps
CPU time 237.64 seconds
Started Oct 12 01:16:10 PM UTC 24
Finished Oct 12 01:20:11 PM UTC 24
Peak memory 301724 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108718785 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_intr_rd.3108718785
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_intr_rd_slow_flash.1024238924
Short name T1033
Test name
Test status
Simulation time 48719182700 ps
CPU time 287.81 seconds
Started Oct 12 01:16:14 PM UTC 24
Finished Oct 12 01:21:06 PM UTC 24
Peak memory 301684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1024238924 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 34.flash_ctrl_intr_rd_slow_flash.1024238924
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_otp_reset.3886614726
Short name T966
Test name
Test status
Simulation time 43994900 ps
CPU time 153.39 seconds
Started Oct 12 01:16:08 PM UTC 24
Finished Oct 12 01:18:44 PM UTC 24
Peak memory 270648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3886614726 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_otp_reset.3886614726
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict.666097802
Short name T934
Test name
Test status
Simulation time 75528700 ps
CPU time 58 seconds
Started Oct 12 01:16:14 PM UTC 24
Finished Oct 12 01:17:14 PM UTC 24
Peak memory 285424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666097802 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_rw_evict.666097802
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_rw_evict_all_en.1766283811
Short name T417
Test name
Test status
Simulation time 29597800 ps
CPU time 57.67 seconds
Started Oct 12 01:16:19 PM UTC 24
Finished Oct 12 01:17:19 PM UTC 24
Peak memory 287504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1766283811 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_c
trl_rw_evict_all_en.1766283811
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_sec_info_access.3202498595
Short name T950
Test name
Test status
Simulation time 1408114200 ps
CPU time 81.75 seconds
Started Oct 12 01:16:27 PM UTC 24
Finished Oct 12 01:17:51 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202498595 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_sec_info_access.3202498595
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/34.flash_ctrl_smoke.1856700913
Short name T937
Test name
Test status
Simulation time 18984700 ps
CPU time 78.71 seconds
Started Oct 12 01:16:04 PM UTC 24
Finished Oct 12 01:17:24 PM UTC 24
Peak memory 285144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856700913 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.flash_ctrl_smoke.1856700913
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/34.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_alert_test.1160556528
Short name T940
Test name
Test status
Simulation time 133144300 ps
CPU time 19.07 seconds
Started Oct 12 01:17:08 PM UTC 24
Finished Oct 12 01:17:28 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160556528 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_alert_test.1160556528
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_connect.2436929019
Short name T945
Test name
Test status
Simulation time 24367700 ps
CPU time 30.02 seconds
Started Oct 12 01:16:59 PM UTC 24
Finished Oct 12 01:17:30 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2436929019 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_connect.2436929019
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_disable.437504448
Short name T944
Test name
Test status
Simulation time 10145200 ps
CPU time 31.44 seconds
Started Oct 12 01:16:56 PM UTC 24
Finished Oct 12 01:17:29 PM UTC 24
Peak memory 285320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=437504448 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c
trl_disable.437504448
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_hw_sec_otp.1205244173
Short name T946
Test name
Test status
Simulation time 4006563700 ps
CPU time 56.21 seconds
Started Oct 12 01:16:33 PM UTC 24
Finished Oct 12 01:17:31 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205244173 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_hw_sec_otp.1205244173
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd.442309261
Short name T1010
Test name
Test status
Simulation time 3124520800 ps
CPU time 207.36 seconds
Started Oct 12 01:16:42 PM UTC 24
Finished Oct 12 01:20:13 PM UTC 24
Peak memory 301848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442309261 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_intr_rd.442309261
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_intr_rd_slow_flash.1359507079
Short name T1061
Test name
Test status
Simulation time 13372277600 ps
CPU time 322.5 seconds
Started Oct 12 01:16:52 PM UTC 24
Finished Oct 12 01:22:19 PM UTC 24
Peak memory 301648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1359507079 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 35.flash_ctrl_intr_rd_slow_flash.1359507079
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_otp_reset.3850789988
Short name T979
Test name
Test status
Simulation time 78070900 ps
CPU time 153.03 seconds
Started Oct 12 01:16:35 PM UTC 24
Finished Oct 12 01:19:11 PM UTC 24
Peak memory 270644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850789988 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_otp_reset.3850789988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict.2950431397
Short name T938
Test name
Test status
Simulation time 225700800 ps
CPU time 32.75 seconds
Started Oct 12 01:16:53 PM UTC 24
Finished Oct 12 01:17:27 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2950431397 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_rw_evict.2950431397
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_rw_evict_all_en.2705246556
Short name T423
Test name
Test status
Simulation time 47763800 ps
CPU time 48.91 seconds
Started Oct 12 01:16:55 PM UTC 24
Finished Oct 12 01:17:46 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2705246556 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_c
trl_rw_evict_all_en.2705246556
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_sec_info_access.1130830751
Short name T957
Test name
Test status
Simulation time 4998479500 ps
CPU time 76.23 seconds
Started Oct 12 01:16:58 PM UTC 24
Finished Oct 12 01:18:16 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1130830751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_sec_info_access.1130830751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/35.flash_ctrl_smoke.2720284673
Short name T977
Test name
Test status
Simulation time 31074700 ps
CPU time 151.57 seconds
Started Oct 12 01:16:30 PM UTC 24
Finished Oct 12 01:19:04 PM UTC 24
Peak memory 287192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720284673 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.flash_ctrl_smoke.2720284673
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/35.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_alert_test.4121600962
Short name T952
Test name
Test status
Simulation time 96259600 ps
CPU time 24.82 seconds
Started Oct 12 01:17:30 PM UTC 24
Finished Oct 12 01:17:56 PM UTC 24
Peak memory 268820 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4121600962 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_alert_test.4121600962
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_connect.295421797
Short name T953
Test name
Test status
Simulation time 22917700 ps
CPU time 25.65 seconds
Started Oct 12 01:17:30 PM UTC 24
Finished Oct 12 01:17:57 PM UTC 24
Peak memory 295072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295421797 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_connect.295421797
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_disable.2270761268
Short name T956
Test name
Test status
Simulation time 13508800 ps
CPU time 33.44 seconds
Started Oct 12 01:17:29 PM UTC 24
Finished Oct 12 01:18:03 PM UTC 24
Peak memory 285124 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2270761268 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_
ctrl_disable.2270761268
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_hw_sec_otp.1104227296
Short name T322
Test name
Test status
Simulation time 3202449500 ps
CPU time 99.51 seconds
Started Oct 12 01:17:15 PM UTC 24
Finished Oct 12 01:18:57 PM UTC 24
Peak memory 274844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104227296 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_hw_sec_otp.1104227296
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd.3731591710
Short name T1036
Test name
Test status
Simulation time 6546403600 ps
CPU time 222.48 seconds
Started Oct 12 01:17:24 PM UTC 24
Finished Oct 12 01:21:10 PM UTC 24
Peak memory 293504 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731591710 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_intr_rd.3731591710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_intr_rd_slow_flash.1212628722
Short name T997
Test name
Test status
Simulation time 21946875200 ps
CPU time 141.6 seconds
Started Oct 12 01:17:24 PM UTC 24
Finished Oct 12 01:19:49 PM UTC 24
Peak memory 303692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1212628722 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 36.flash_ctrl_intr_rd_slow_flash.1212628722
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_otp_reset.3229017642
Short name T1014
Test name
Test status
Simulation time 74795600 ps
CPU time 175.51 seconds
Started Oct 12 01:17:19 PM UTC 24
Finished Oct 12 01:20:17 PM UTC 24
Peak memory 270904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229017642 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_otp_reset.3229017642
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict.1151436450
Short name T955
Test name
Test status
Simulation time 128920600 ps
CPU time 35.75 seconds
Started Oct 12 01:17:25 PM UTC 24
Finished Oct 12 01:18:03 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151436450 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_rw_evict.1151436450
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_rw_evict_all_en.2850123643
Short name T958
Test name
Test status
Simulation time 73895700 ps
CPU time 47.82 seconds
Started Oct 12 01:17:29 PM UTC 24
Finished Oct 12 01:18:18 PM UTC 24
Peak memory 285388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2850123643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_c
trl_rw_evict_all_en.2850123643
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_sec_info_access.318393271
Short name T974
Test name
Test status
Simulation time 2287661800 ps
CPU time 84.86 seconds
Started Oct 12 01:17:29 PM UTC 24
Finished Oct 12 01:18:56 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=318393271 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_sec_info_access.318393271
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/36.flash_ctrl_smoke.1705339303
Short name T990
Test name
Test status
Simulation time 119871800 ps
CPU time 136.64 seconds
Started Oct 12 01:17:09 PM UTC 24
Finished Oct 12 01:19:28 PM UTC 24
Peak memory 287192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705339303 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.flash_ctrl_smoke.1705339303
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/36.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_alert_test.2226803554
Short name T959
Test name
Test status
Simulation time 104445800 ps
CPU time 21.35 seconds
Started Oct 12 01:17:58 PM UTC 24
Finished Oct 12 01:18:20 PM UTC 24
Peak memory 268996 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226803554 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_alert_test.2226803554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_connect.1822757635
Short name T960
Test name
Test status
Simulation time 46341400 ps
CPU time 26.18 seconds
Started Oct 12 01:17:55 PM UTC 24
Finished Oct 12 01:18:23 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1822757635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_connect.1822757635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_hw_sec_otp.3105101896
Short name T318
Test name
Test status
Simulation time 19354355000 ps
CPU time 128.11 seconds
Started Oct 12 01:17:30 PM UTC 24
Finished Oct 12 01:19:41 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105101896 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_hw_sec_otp.3105101896
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd.3863425559
Short name T1018
Test name
Test status
Simulation time 1665822500 ps
CPU time 176.93 seconds
Started Oct 12 01:17:33 PM UTC 24
Finished Oct 12 01:20:32 PM UTC 24
Peak memory 305844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3863425559 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_intr_rd.3863425559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_intr_rd_slow_flash.840139715
Short name T1058
Test name
Test status
Simulation time 25103393500 ps
CPU time 266.98 seconds
Started Oct 12 01:17:42 PM UTC 24
Finished Oct 12 01:22:13 PM UTC 24
Peak memory 301620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=840139715 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 37.flash_ctrl_intr_rd_slow_flash.840139715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_otp_reset.135037559
Short name T1022
Test name
Test status
Simulation time 167573100 ps
CPU time 184.61 seconds
Started Oct 12 01:17:31 PM UTC 24
Finished Oct 12 01:20:39 PM UTC 24
Peak memory 275208 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=135037559 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_otp_reset.135037559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict.2595254812
Short name T418
Test name
Test status
Simulation time 34679400 ps
CPU time 54.65 seconds
Started Oct 12 01:17:44 PM UTC 24
Finished Oct 12 01:18:40 PM UTC 24
Peak memory 287428 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595254812 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_rw_evict.2595254812
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_rw_evict_all_en.3643961626
Short name T963
Test name
Test status
Simulation time 34894600 ps
CPU time 42.81 seconds
Started Oct 12 01:17:47 PM UTC 24
Finished Oct 12 01:18:31 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3643961626 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_c
trl_rw_evict_all_en.3643961626
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_sec_info_access.3894797736
Short name T983
Test name
Test status
Simulation time 1175662300 ps
CPU time 88.71 seconds
Started Oct 12 01:17:51 PM UTC 24
Finished Oct 12 01:19:22 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894797736 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_sec_info_access.3894797736
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/37.flash_ctrl_smoke.3059947260
Short name T1001
Test name
Test status
Simulation time 34863500 ps
CPU time 146.39 seconds
Started Oct 12 01:17:30 PM UTC 24
Finished Oct 12 01:19:59 PM UTC 24
Peak memory 287320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059947260 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.flash_ctrl_smoke.3059947260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/37.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_alert_test.964397197
Short name T972
Test name
Test status
Simulation time 45839800 ps
CPU time 22.23 seconds
Started Oct 12 01:18:31 PM UTC 24
Finished Oct 12 01:18:54 PM UTC 24
Peak memory 268804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964397197 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_alert_test.964397197
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_connect.555298777
Short name T967
Test name
Test status
Simulation time 41291000 ps
CPU time 16.5 seconds
Started Oct 12 01:18:27 PM UTC 24
Finished Oct 12 01:18:44 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555298777 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_connect.555298777
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_disable.3899588180
Short name T970
Test name
Test status
Simulation time 10939300 ps
CPU time 28.03 seconds
Started Oct 12 01:18:24 PM UTC 24
Finished Oct 12 01:18:53 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3899588180 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_
ctrl_disable.3899588180
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_hw_sec_otp.3380685526
Short name T1002
Test name
Test status
Simulation time 3746645700 ps
CPU time 115.12 seconds
Started Oct 12 01:18:03 PM UTC 24
Finished Oct 12 01:20:00 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3380685526 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_hw_sec_otp.3380685526
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd.3965041222
Short name T1015
Test name
Test status
Simulation time 872377100 ps
CPU time 132.24 seconds
Started Oct 12 01:18:04 PM UTC 24
Finished Oct 12 01:20:19 PM UTC 24
Peak memory 307932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965041222 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_intr_rd.3965041222
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_intr_rd_slow_flash.3416289114
Short name T1081
Test name
Test status
Simulation time 55871501700 ps
CPU time 271.24 seconds
Started Oct 12 01:18:17 PM UTC 24
Finished Oct 12 01:22:53 PM UTC 24
Peak memory 303668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3416289114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 38.flash_ctrl_intr_rd_slow_flash.3416289114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_otp_reset.195590438
Short name T1027
Test name
Test status
Simulation time 46628800 ps
CPU time 160.52 seconds
Started Oct 12 01:18:04 PM UTC 24
Finished Oct 12 01:20:47 PM UTC 24
Peak memory 275144 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195590438 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_otp_reset.195590438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_rw_evict_all_en.3826834634
Short name T976
Test name
Test status
Simulation time 250461000 ps
CPU time 40.7 seconds
Started Oct 12 01:18:21 PM UTC 24
Finished Oct 12 01:19:04 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3826834634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_c
trl_rw_evict_all_en.3826834634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_sec_info_access.4175587176
Short name T395
Test name
Test status
Simulation time 1901685200 ps
CPU time 95.54 seconds
Started Oct 12 01:18:24 PM UTC 24
Finished Oct 12 01:20:01 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175587176 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_sec_info_access.4175587176
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/38.flash_ctrl_smoke.2041563070
Short name T143
Test name
Test status
Simulation time 50306200 ps
CPU time 225.06 seconds
Started Oct 12 01:17:58 PM UTC 24
Finished Oct 12 01:21:46 PM UTC 24
Peak memory 289232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2041563070 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.flash_ctrl_smoke.2041563070
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/38.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_alert_test.335413830
Short name T981
Test name
Test status
Simulation time 56320000 ps
CPU time 21.59 seconds
Started Oct 12 01:18:54 PM UTC 24
Finished Oct 12 01:19:17 PM UTC 24
Peak memory 268932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=335413830 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_alert_test.335413830
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_connect.3932473045
Short name T984
Test name
Test status
Simulation time 71792400 ps
CPU time 27.16 seconds
Started Oct 12 01:18:54 PM UTC 24
Finished Oct 12 01:19:23 PM UTC 24
Peak memory 295068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932473045 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_connect.3932473045
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_disable.892589412
Short name T992
Test name
Test status
Simulation time 13160200 ps
CPU time 41.84 seconds
Started Oct 12 01:18:50 PM UTC 24
Finished Oct 12 01:19:33 PM UTC 24
Peak memory 285256 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=892589412 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c
trl_disable.892589412
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_hw_sec_otp.824353059
Short name T987
Test name
Test status
Simulation time 2796102500 ps
CPU time 52.67 seconds
Started Oct 12 01:18:32 PM UTC 24
Finished Oct 12 01:19:26 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824353059 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_hw_sec_otp.824353059
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd.2928198929
Short name T1062
Test name
Test status
Simulation time 6850563500 ps
CPU time 214.61 seconds
Started Oct 12 01:18:41 PM UTC 24
Finished Oct 12 01:22:19 PM UTC 24
Peak memory 301692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2928198929 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_intr_rd.2928198929
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_intr_rd_slow_flash.2697311218
Short name T1049
Test name
Test status
Simulation time 5876557100 ps
CPU time 172.78 seconds
Started Oct 12 01:18:43 PM UTC 24
Finished Oct 12 01:21:39 PM UTC 24
Peak memory 303692 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2697311218 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 39.flash_ctrl_intr_rd_slow_flash.2697311218
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_otp_reset.3546290384
Short name T141
Test name
Test status
Simulation time 37542300 ps
CPU time 177.37 seconds
Started Oct 12 01:18:40 PM UTC 24
Finished Oct 12 01:21:40 PM UTC 24
Peak memory 270860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3546290384 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_otp_reset.3546290384
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict.846436260
Short name T991
Test name
Test status
Simulation time 66339200 ps
CPU time 42.81 seconds
Started Oct 12 01:18:45 PM UTC 24
Finished Oct 12 01:19:29 PM UTC 24
Peak memory 287600 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846436260 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_rw_evict.846436260
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_rw_evict_all_en.2957189506
Short name T988
Test name
Test status
Simulation time 34555700 ps
CPU time 40.2 seconds
Started Oct 12 01:18:46 PM UTC 24
Finished Oct 12 01:19:27 PM UTC 24
Peak memory 285584 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2957189506 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_c
trl_rw_evict_all_en.2957189506
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_sec_info_access.2296795098
Short name T1004
Test name
Test status
Simulation time 1179200500 ps
CPU time 73.18 seconds
Started Oct 12 01:18:52 PM UTC 24
Finished Oct 12 01:20:07 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296795098 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_sec_info_access.2296795098
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/39.flash_ctrl_smoke.258759007
Short name T1024
Test name
Test status
Simulation time 150318900 ps
CPU time 127.82 seconds
Started Oct 12 01:18:32 PM UTC 24
Finished Oct 12 01:20:42 PM UTC 24
Peak memory 287192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258759007 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.flash_ctrl_smoke.258759007
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/39.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_alert_test.4012912477
Short name T493
Test name
Test status
Simulation time 55921500 ps
CPU time 16.76 seconds
Started Oct 12 12:28:23 PM UTC 24
Finished Oct 12 12:28:41 PM UTC 24
Peak memory 268928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012912477 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_alert_test.4012912477
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_config_regwen.1022686575
Short name T488
Test name
Test status
Simulation time 22054500 ps
CPU time 15.11 seconds
Started Oct 12 12:28:05 PM UTC 24
Finished Oct 12 12:28:21 PM UTC 24
Peak memory 274876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022686575 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspac
es/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_config_regwen.1022686575
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_derr_detect.3797361313
Short name T438
Test name
Test status
Simulation time 4767548600 ps
CPU time 191.95 seconds
Started Oct 12 12:25:48 PM UTC 24
Finished Oct 12 12:29:03 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=4 +otf_num_rw=50 +otf_num_hr=200
+rerun=5 +otf_wr_pct=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3797361313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_derr_detect_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null
-cm_name 4.flash_ctrl_derr_detect.3797361313
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_derr_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_disable.3828246181
Short name T118
Test name
Test status
Simulation time 11124100 ps
CPU time 38.86 seconds
Started Oct 12 12:27:18 PM UTC 24
Finished Oct 12 12:27:58 PM UTC 24
Peak memory 285440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3828246181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_c
trl_disable.3828246181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_erase_suspend.1496540555
Short name T312
Test name
Test status
Simulation time 4177517100 ps
CPU time 492.38 seconds
Started Oct 12 12:23:17 PM UTC 24
Finished Oct 12 12:31:36 PM UTC 24
Peak memory 274840 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496540555 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_erase_suspend_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_erase_suspend.1496540555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_erase_suspend/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_mp.1657395206
Short name T897
Test name
Test status
Simulation time 20906771300 ps
CPU time 3021.45 seconds
Started Oct 12 12:24:15 PM UTC 24
Finished Oct 12 01:15:08 PM UTC 24
Peak memory 272968 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1657395206 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_mp.1657395206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_type.1375977965
Short name T109
Test name
Test status
Simulation time 550326800 ps
CPU time 3329.44 seconds
Started Oct 12 12:23:55 PM UTC 24
Finished Oct 12 01:19:58 PM UTC 24
Peak memory 277748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=13
75977965 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_error_prog_type_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl
_error_prog_type.1375977965
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_type/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_error_prog_win.2104842131
Short name T589
Test name
Test status
Simulation time 691442300 ps
CPU time 1274.48 seconds
Started Oct 12 12:23:57 PM UTC 24
Finished Oct 12 12:45:26 PM UTC 24
Peak memory 285164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104842131 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_error_prog_win.2104842131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fetch_code.3456678425
Short name T307
Test name
Test status
Simulation time 126799500 ps
CPU time 22.36 seconds
Started Oct 12 12:23:51 PM UTC 24
Finished Oct 12 12:24:15 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34
56678425 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_fetc
h_code.3456678425
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_fs_sup.1024281244
Short name T492
Test name
Test status
Simulation time 337931800 ps
CPU time 43.78 seconds
Started Oct 12 12:27:46 PM UTC 24
Finished Oct 12 12:28:31 PM UTC 24
Peak memory 273080 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +en_all_info_acc=1 +cdc_i
nstrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024281
244 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_filesystem_support_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_f
s_sup.1024281244
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_fs_sup/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_full_mem_access.1231050841
Short name T162
Test name
Test status
Simulation time 203560347200 ps
CPU time 2445.35 seconds
Started Oct 12 12:23:53 PM UTC 24
Finished Oct 12 01:05:04 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=500_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231050841 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_full_mem_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_full_mem_access.1231050841
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_full_mem_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_ctrl_arb.1594193630
Short name T210
Test name
Test status
Simulation time 659575992900 ps
CPU time 2281.67 seconds
Started Oct 12 12:23:36 PM UTC 24
Finished Oct 12 01:02:01 PM UTC 24
Peak memory 275040 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +test_timeout_ns=300_000_000_000 +cdc_instrumentation
_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594193630 -assert no
postproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_host_ctrl_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_ctrl_arb.1594193630
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_host_ctrl_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_host_dir_rd.1777048784
Short name T472
Test name
Test status
Simulation time 100247400 ps
CPU time 140.33 seconds
Started Oct 12 12:23:09 PM UTC 24
Finished Oct 12 12:25:32 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777048784 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_host_dir_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_host_dir_rd.1777048784
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_host_dir_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_prog_rma_wipe_err.3322208563
Short name T196
Test name
Test status
Simulation time 10012760500 ps
CPU time 131.82 seconds
Started Oct 12 12:28:17 PM UTC 24
Finished Oct 12 12:30:32 PM UTC 24
Peak memory 371388 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3322208563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 4.flash_ctrl_hw_prog_rma_wipe_err.3322208563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_read_seed_err.2184852421
Short name T267
Test name
Test status
Simulation time 46868500 ps
CPU time 21.37 seconds
Started Oct 12 12:28:12 PM UTC 24
Finished Oct 12 12:28:35 PM UTC 24
Peak memory 269012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2184852421 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
4.flash_ctrl_hw_read_seed_err.2184852421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_rma_reset.3030452875
Short name T198
Test name
Test status
Simulation time 180195738700 ps
CPU time 905.35 seconds
Started Oct 12 12:23:22 PM UTC 24
Finished Oct 12 12:38:37 PM UTC 24
Peak memory 274936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030452875
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_rma_reset.3030452875
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_hw_sec_otp.492765104
Short name T305
Test name
Test status
Simulation time 13114929900 ps
CPU time 61.06 seconds
Started Oct 12 12:23:16 PM UTC 24
Finished Oct 12 12:24:19 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492765104 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_hw_sec_otp.492765104
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_integrity.1180552624
Short name T530
Test name
Test status
Simulation time 6929842600 ps
CPU time 592.43 seconds
Started Oct 12 12:26:16 PM UTC 24
Finished Oct 12 12:36:16 PM UTC 24
Peak memory 332716 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=4 +ierr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1180552624 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_integr
ity.1180552624
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_integrity/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd.2395593146
Short name T501
Test name
Test status
Simulation time 3252201200 ps
CPU time 260.9 seconds
Started Oct 12 12:26:22 PM UTC 24
Finished Oct 12 12:30:47 PM UTC 24
Peak memory 293532 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395593146 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_rd.2395593146
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_rd_slow_flash.2510072927
Short name T507
Test name
Test status
Simulation time 12556385000 ps
CPU time 310.06 seconds
Started Oct 12 12:26:31 PM UTC 24
Finished Oct 12 12:31:46 PM UTC 24
Peak memory 293628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2510072927 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 4.flash_ctrl_intr_rd_slow_flash.2510072927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr.4285764431
Short name T489
Test name
Test status
Simulation time 5339000600 ps
CPU time 109.49 seconds
Started Oct 12 12:26:31 PM UTC 24
Finished Oct 12 12:28:23 PM UTC 24
Peak memory 270948 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285764431 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr.4285764431
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_intr_wr_slow_flash.1457496139
Short name T503
Test name
Test status
Simulation time 84937992200 ps
CPU time 263.73 seconds
Started Oct 12 12:26:40 PM UTC 24
Finished Oct 12 12:31:07 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457496139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_intr_wr_slow_flash.1457496139
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_invalid_op.1348442050
Short name T166
Test name
Test status
Simulation time 5938860900 ps
CPU time 73.34 seconds
Started Oct 12 12:24:20 PM UTC 24
Finished Oct 12 12:25:35 PM UTC 24
Peak memory 270800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348442050 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_invalid_op.1348442050
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_lcmgr_intg.3381506644
Short name T275
Test name
Test status
Simulation time 70352400 ps
CPU time 19.52 seconds
Started Oct 12 12:28:09 PM UTC 24
Finished Oct 12 12:28:30 PM UTC 24
Peak memory 270864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3381506644 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_lcmgr_intg.3381506644
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mid_op_rst.3277117852
Short name T85
Test name
Test status
Simulation time 2677590000 ps
CPU time 112.55 seconds
Started Oct 12 12:24:27 PM UTC 24
Finished Oct 12 12:26:22 PM UTC 24
Peak memory 270712 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277117852 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_mid_op_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash
_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_mid_op_rst.3277117852
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_mid_op_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_mp_regions.2869814636
Short name T159
Test name
Test status
Simulation time 30883217000 ps
CPU time 607.62 seconds
Started Oct 12 12:23:42 PM UTC 24
Finished Oct 12 12:33:57 PM UTC 24
Peak memory 283240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2869814636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 4.flash_ctrl_mp_regions.2869814636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_oversize_error.21422283
Short name T494
Test name
Test status
Simulation time 1011281100 ps
CPU time 168.05 seconds
Started Oct 12 12:25:51 PM UTC 24
Finished Oct 12 12:28:42 PM UTC 24
Peak memory 291520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=0 +otf_num_hr=1000 +otf_num_rw=1
00 +otf_wr_pct=4 +otf_rd_pct=4 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/t
ools/sim.tcl +ntb_random_seed=21422283 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_oversize_error_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.flash_ctrl_oversize_error.21422283
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_oversize_error/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_ack_consistency.3638398114
Short name T490
Test name
Test status
Simulation time 28658600 ps
CPU time 25.27 seconds
Started Oct 12 12:27:59 PM UTC 24
Finished Oct 12 12:28:26 PM UTC 24
Peak memory 293140 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +bank0_pct=8
+otf_rd_pct=4 +en_always_all=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638398114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_phy_ack_consistency_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_ack_consistency.3638398114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_phy_ack_consistency/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb.637658697
Short name T511
Test name
Test status
Simulation time 158980200 ps
CPU time 528.68 seconds
Started Oct 12 12:23:12 PM UTC 24
Finished Oct 12 12:32:07 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637658697 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_phy_arb.637658697
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_arb_redun.681503063
Short name T169
Test name
Test status
Simulation time 915537700 ps
CPU time 38.17 seconds
Started Oct 12 12:27:48 PM UTC 24
Finished Oct 12 12:28:28 PM UTC 24
Peak memory 275480 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=10 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=681503063 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_redun_vseq
+en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -c
m_log /dev/null -cm_name 4.flash_ctrl_phy_arb_redun.681503063
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_phy_arb_redun/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_phy_host_grant_err.738360517
Short name T487
Test name
Test status
Simulation time 193059200 ps
CPU time 24.45 seconds
Started Oct 12 12:27:51 PM UTC 24
Finished Oct 12 12:28:17 PM UTC 24
Peak memory 275296 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=5 +otf_num_hr=50 +ecc_mode=1 +en_always_al
l=1 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo
/hw/dv/tools/sim.tcl +ntb_random_seed=738360517 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_phy_host_grant_err_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 4.flash_ctrl_phy_host_grant_err.738360517
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_phy_host_grant_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_prog_reset.230182364
Short name T479
Test name
Test status
Simulation time 24622000 ps
CPU time 16.45 seconds
Started Oct 12 12:26:48 PM UTC 24
Finished Oct 12 12:27:05 PM UTC 24
Peak memory 275112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230182364 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_prog_reset.230182364
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rand_ops.4017354955
Short name T495
Test name
Test status
Simulation time 44629800 ps
CPU time 343.05 seconds
Started Oct 12 12:23:01 PM UTC 24
Finished Oct 12 12:28:49 PM UTC 24
Peak memory 283092 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4017354955 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rand_ops.4017354955
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rd_buff_evict.1792408991
Short name T241
Test name
Test status
Simulation time 2867529400 ps
CPU time 135.86 seconds
Started Oct 12 12:23:11 PM UTC 24
Finished Oct 12 12:25:29 PM UTC 24
Peak memory 272844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +en_cov=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBO
SITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792408991 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base
_test +UVM_TEST_SEQ=flash_ctrl_rd_buff_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rd_buff_evict.1792408991
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_rd_buff_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_re_evict.2281750183
Short name T486
Test name
Test status
Simulation time 232090800 ps
CPU time 53.97 seconds
Started Oct 12 12:27:13 PM UTC 24
Finished Oct 12 12:28:09 PM UTC 24
Peak memory 285424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2281750183 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_re_evict.2281750183
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_derr.3632505563
Short name T475
Test name
Test status
Simulation time 42108400 ps
CPU time 40.56 seconds
Started Oct 12 12:25:33 PM UTC 24
Finished Oct 12 12:26:15 PM UTC 24
Peak memory 275068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +bypass_alert_ready_to_end_che
ck=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3632505563 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flas
h_ctrl_read_word_sweep_derr.3632505563
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_read_word_sweep_serr.3073981895
Short name T474
Test name
Test status
Simulation time 34353900 ps
CPU time 43.49 seconds
Started Oct 12 12:25:05 PM UTC 24
Finished Oct 12 12:25:50 PM UTC 24
Peak memory 275068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073981895 -assert nopostproc +
UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_read_word_sweep_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/
repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_read_word_sweep_serr.3073981895
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_read_word_sweep_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro.1478240374
Short name T481
Test name
Test status
Simulation time 833401300 ps
CPU time 132.84 seconds
Started Oct 12 12:25:02 PM UTC 24
Finished Oct 12 12:27:17 PM UTC 24
Peak memory 303828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1478240374 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ro.1478240374
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_ro_serr.2310051349
Short name T482
Test name
Test status
Simulation time 7442938200 ps
CPU time 139.74 seconds
Started Oct 12 12:25:10 PM UTC 24
Finished Oct 12 12:27:32 PM UTC 24
Peak memory 291524 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2310051349 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash
_ctrl_ro_serr.2310051349
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw.2777268031
Short name T521
Test name
Test status
Simulation time 6893619600 ps
CPU time 551.84 seconds
Started Oct 12 12:25:03 PM UTC 24
Finished Oct 12 12:34:21 PM UTC 24
Peak memory 320320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2777268031 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw.2777268031
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_derr.2108347551
Short name T498
Test name
Test status
Simulation time 3979627800 ps
CPU time 245.48 seconds
Started Oct 12 12:25:36 PM UTC 24
Finished Oct 12 12:29:45 PM UTC 24
Peak memory 299732 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2108347551 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 4.flash_ctrl_rw_derr.2108347551
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict.3670048210
Short name T431
Test name
Test status
Simulation time 119818800 ps
CPU time 40.13 seconds
Started Oct 12 12:26:53 PM UTC 24
Finished Oct 12 12:27:34 PM UTC 24
Peak memory 285424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670048210 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_evict.3670048210
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_evict_all_en.1261115040
Short name T317
Test name
Test status
Simulation time 42450200 ps
CPU time 42.87 seconds
Started Oct 12 12:27:06 PM UTC 24
Finished Oct 12 12:27:50 PM UTC 24
Peak memory 285380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1261115040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ct
rl_rw_evict_all_en.1261115040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_rw_serr.4231537912
Short name T497
Test name
Test status
Simulation time 1609166600 ps
CPU time 225.14 seconds
Started Oct 12 12:25:18 PM UTC 24
Finished Oct 12 12:29:07 PM UTC 24
Peak memory 291540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=4231537912 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_rw_serr.4231537912
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sec_info_access.1784099570
Short name T174
Test name
Test status
Simulation time 2275868100 ps
CPU time 102.64 seconds
Started Oct 12 12:27:35 PM UTC 24
Finished Oct 12 12:29:20 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1784099570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sec_info_access.1784099570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_address.3664956884
Short name T477
Test name
Test status
Simulation time 931494700 ps
CPU time 74.74 seconds
Started Oct 12 12:25:30 PM UTC 24
Finished Oct 12 12:26:47 PM UTC 24
Peak memory 275152 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=5 +otf_num_hr=0 +c
dc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=366
4956884 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_address_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+as
sert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_ser
r_address.3664956884
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_serr_address/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_serr_counter.2609232749
Short name T480
Test name
Test status
Simulation time 3149576400 ps
CPU time 107.08 seconds
Started Oct 12 12:25:22 PM UTC 24
Finished Oct 12 12:27:12 PM UTC 24
Peak memory 275156 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=1 +otf_num_rw=50 +otf_num_hr=5 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26
09232749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_serr_counter_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+a
ssert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_se
rr_counter.2609232749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_serr_counter/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke.3061462284
Short name T476
Test name
Test status
Simulation time 34394600 ps
CPU time 219.63 seconds
Started Oct 12 12:22:56 PM UTC 24
Finished Oct 12 12:26:39 PM UTC 24
Peak memory 291276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061462284 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke.3061462284
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_smoke_hw.493465137
Short name T469
Test name
Test status
Simulation time 13580600 ps
CPU time 52.6 seconds
Started Oct 12 12:22:58 PM UTC 24
Finished Oct 12 12:23:52 PM UTC 24
Peak memory 270688 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=493465137 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_hw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_smoke_hw.493465137
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_smoke_hw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_stress_all.3969379758
Short name T799
Test name
Test status
Simulation time 251549600 ps
CPU time 2457.37 seconds
Started Oct 12 12:27:42 PM UTC 24
Finished Oct 12 01:09:07 PM UTC 24
Peak memory 301608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969379758 -assert nopostproc +UVM_TESTN
AME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_stress_all.3969379758
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_sw_op.1026086570
Short name T468
Test name
Test status
Simulation time 47679600 ps
CPU time 46.25 seconds
Started Oct 12 12:23:02 PM UTC 24
Finished Oct 12 12:23:50 PM UTC 24
Peak memory 270876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026086570 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_sw_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_sw_op.1026086570
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_sw_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/4.flash_ctrl_wo.4181298313
Short name T484
Test name
Test status
Simulation time 2349662700 ps
CPU time 180.97 seconds
Started Oct 12 12:24:39 PM UTC 24
Finished Oct 12 12:27:43 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=4181298313 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.flash_ctrl_wo.4181298313
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/4.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_alert_test.410589395
Short name T989
Test name
Test status
Simulation time 15747800 ps
CPU time 22.23 seconds
Started Oct 12 01:19:04 PM UTC 24
Finished Oct 12 01:19:28 PM UTC 24
Peak memory 268800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410589395 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_alert_test.410589395
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/40.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_connect.4175430325
Short name T985
Test name
Test status
Simulation time 42482900 ps
CPU time 17.93 seconds
Started Oct 12 01:19:04 PM UTC 24
Finished Oct 12 01:19:23 PM UTC 24
Peak memory 284768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175430325 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_connect.4175430325
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/40.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_disable.1720785379
Short name T986
Test name
Test status
Simulation time 20165800 ps
CPU time 26.99 seconds
Started Oct 12 01:18:58 PM UTC 24
Finished Oct 12 01:19:26 PM UTC 24
Peak memory 285508 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1720785379 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_
ctrl_disable.1720785379
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/40.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_hw_sec_otp.1029223097
Short name T1080
Test name
Test status
Simulation time 11807247000 ps
CPU time 227.76 seconds
Started Oct 12 01:18:57 PM UTC 24
Finished Oct 12 01:22:48 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029223097 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_hw_sec_otp.1029223097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/40.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_otp_reset.3704027711
Short name T1050
Test name
Test status
Simulation time 148909700 ps
CPU time 177.9 seconds
Started Oct 12 01:18:57 PM UTC 24
Finished Oct 12 01:21:57 PM UTC 24
Peak memory 271032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3704027711 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_otp_reset.3704027711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/40.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_sec_info_access.2078870066
Short name T1023
Test name
Test status
Simulation time 2090818300 ps
CPU time 96.54 seconds
Started Oct 12 01:19:02 PM UTC 24
Finished Oct 12 01:20:41 PM UTC 24
Peak memory 274916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2078870066 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_sec_info_access.2078870066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/40.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/40.flash_ctrl_smoke.824756865
Short name T1088
Test name
Test status
Simulation time 70066900 ps
CPU time 251.74 seconds
Started Oct 12 01:18:56 PM UTC 24
Finished Oct 12 01:23:11 PM UTC 24
Peak memory 287192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824756865 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-
sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.flash_ctrl_smoke.824756865
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/40.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_alert_test.1999570553
Short name T996
Test name
Test status
Simulation time 65849700 ps
CPU time 23.52 seconds
Started Oct 12 01:19:23 PM UTC 24
Finished Oct 12 01:19:48 PM UTC 24
Peak memory 274952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999570553 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_alert_test.1999570553
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/41.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_connect.3868850996
Short name T994
Test name
Test status
Simulation time 29895500 ps
CPU time 19.91 seconds
Started Oct 12 01:19:20 PM UTC 24
Finished Oct 12 01:19:42 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3868850996 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_connect.3868850996
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/41.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_disable.2814504943
Short name T995
Test name
Test status
Simulation time 26184600 ps
CPU time 30.39 seconds
Started Oct 12 01:19:15 PM UTC 24
Finished Oct 12 01:19:47 PM UTC 24
Peak memory 285444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2814504943 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_
ctrl_disable.2814504943
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/41.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_hw_sec_otp.1513472666
Short name T1032
Test name
Test status
Simulation time 4202033000 ps
CPU time 109.85 seconds
Started Oct 12 01:19:11 PM UTC 24
Finished Oct 12 01:21:03 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513472666 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_hw_sec_otp.1513472666
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/41.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_otp_reset.3595314715
Short name T1054
Test name
Test status
Simulation time 40391700 ps
CPU time 169.35 seconds
Started Oct 12 01:19:13 PM UTC 24
Finished Oct 12 01:22:05 PM UTC 24
Peak memory 270776 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3595314715 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_otp_reset.3595314715
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/41.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_sec_info_access.2707613443
Short name T1017
Test name
Test status
Simulation time 1249181100 ps
CPU time 62.09 seconds
Started Oct 12 01:19:18 PM UTC 24
Finished Oct 12 01:20:22 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707613443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_sec_info_access.2707613443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/41.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/41.flash_ctrl_smoke.3357069017
Short name T1009
Test name
Test status
Simulation time 18047400 ps
CPU time 65.22 seconds
Started Oct 12 01:19:05 PM UTC 24
Finished Oct 12 01:20:12 PM UTC 24
Peak memory 285328 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3357069017 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.flash_ctrl_smoke.3357069017
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/41.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_alert_test.2835210927
Short name T1000
Test name
Test status
Simulation time 100204500 ps
CPU time 22.35 seconds
Started Oct 12 01:19:29 PM UTC 24
Finished Oct 12 01:19:53 PM UTC 24
Peak memory 268804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2835210927 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_alert_test.2835210927
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/42.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_connect.1526820635
Short name T998
Test name
Test status
Simulation time 14401100 ps
CPU time 19.83 seconds
Started Oct 12 01:19:28 PM UTC 24
Finished Oct 12 01:19:49 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526820635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_connect.1526820635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/42.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_disable.1618358919
Short name T999
Test name
Test status
Simulation time 12761700 ps
CPU time 24.56 seconds
Started Oct 12 01:19:27 PM UTC 24
Finished Oct 12 01:19:53 PM UTC 24
Peak memory 285468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1618358919 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_
ctrl_disable.1618358919
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/42.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_hw_sec_otp.2663267967
Short name T1097
Test name
Test status
Simulation time 21566039500 ps
CPU time 257.31 seconds
Started Oct 12 01:19:25 PM UTC 24
Finished Oct 12 01:23:46 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663267967 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_hw_sec_otp.2663267967
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/42.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_otp_reset.1919949496
Short name T1090
Test name
Test status
Simulation time 39254100 ps
CPU time 225.66 seconds
Started Oct 12 01:19:27 PM UTC 24
Finished Oct 12 01:23:16 PM UTC 24
Peak memory 274956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1919949496 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_otp_reset.1919949496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/42.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_sec_info_access.297827166
Short name T407
Test name
Test status
Simulation time 14299477400 ps
CPU time 81.91 seconds
Started Oct 12 01:19:28 PM UTC 24
Finished Oct 12 01:20:52 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297827166 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_sec_info_access.297827166
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/42.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/42.flash_ctrl_smoke.3295886798
Short name T1096
Test name
Test status
Simulation time 108988700 ps
CPU time 258.56 seconds
Started Oct 12 01:19:24 PM UTC 24
Finished Oct 12 01:23:46 PM UTC 24
Peak memory 291264 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295886798 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.flash_ctrl_smoke.3295886798
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/42.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_alert_test.2723166705
Short name T1008
Test name
Test status
Simulation time 78761400 ps
CPU time 27.63 seconds
Started Oct 12 01:19:42 PM UTC 24
Finished Oct 12 01:20:11 PM UTC 24
Peak memory 268932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2723166705 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_alert_test.2723166705
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/43.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_connect.3321523296
Short name T1011
Test name
Test status
Simulation time 30180600 ps
CPU time 30.79 seconds
Started Oct 12 01:19:42 PM UTC 24
Finished Oct 12 01:20:14 PM UTC 24
Peak memory 294944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321523296 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_connect.3321523296
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/43.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_disable.3837787664
Short name T1005
Test name
Test status
Simulation time 16009900 ps
CPU time 35.06 seconds
Started Oct 12 01:19:34 PM UTC 24
Finished Oct 12 01:20:10 PM UTC 24
Peak memory 285308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3837787664 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_
ctrl_disable.3837787664
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/43.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_hw_sec_otp.2300846853
Short name T1034
Test name
Test status
Simulation time 5121902000 ps
CPU time 94.71 seconds
Started Oct 12 01:19:30 PM UTC 24
Finished Oct 12 01:21:06 PM UTC 24
Peak memory 274852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300846853 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_hw_sec_otp.2300846853
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/43.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_otp_reset.1141090888
Short name T1013
Test name
Test status
Simulation time 37492900 ps
CPU time 152.95 seconds
Started Oct 12 01:19:34 PM UTC 24
Finished Oct 12 01:22:09 PM UTC 24
Peak memory 272888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141090888 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_otp_reset.1141090888
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/43.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_sec_info_access.3946710485
Short name T1028
Test name
Test status
Simulation time 419107400 ps
CPU time 68.93 seconds
Started Oct 12 01:19:42 PM UTC 24
Finished Oct 12 01:20:53 PM UTC 24
Peak memory 275112 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946710485 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_sec_info_access.3946710485
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/43.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/43.flash_ctrl_smoke.2821062925
Short name T1055
Test name
Test status
Simulation time 22515500 ps
CPU time 154.02 seconds
Started Oct 12 01:19:29 PM UTC 24
Finished Oct 12 01:22:06 PM UTC 24
Peak memory 289240 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821062925 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.flash_ctrl_smoke.2821062925
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/43.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_alert_test.2798526988
Short name T1016
Test name
Test status
Simulation time 38887800 ps
CPU time 19.28 seconds
Started Oct 12 01:19:59 PM UTC 24
Finished Oct 12 01:20:20 PM UTC 24
Peak memory 275076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798526988 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_alert_test.2798526988
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/44.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_connect.1342744810
Short name T1006
Test name
Test status
Simulation time 24486400 ps
CPU time 15.97 seconds
Started Oct 12 01:19:54 PM UTC 24
Finished Oct 12 01:20:11 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1342744810 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_connect.1342744810
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/44.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_disable.3130050470
Short name T373
Test name
Test status
Simulation time 11219300 ps
CPU time 36.13 seconds
Started Oct 12 01:19:50 PM UTC 24
Finished Oct 12 01:20:27 PM UTC 24
Peak memory 285244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3130050470 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_
ctrl_disable.3130050470
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/44.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_hw_sec_otp.3621698303
Short name T1042
Test name
Test status
Simulation time 2727446200 ps
CPU time 92.81 seconds
Started Oct 12 01:19:50 PM UTC 24
Finished Oct 12 01:21:24 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3621698303 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_hw_sec_otp.3621698303
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/44.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_otp_reset.2183523782
Short name T1065
Test name
Test status
Simulation time 39868100 ps
CPU time 150.45 seconds
Started Oct 12 01:19:50 PM UTC 24
Finished Oct 12 01:22:23 PM UTC 24
Peak memory 271052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183523782 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_otp_reset.2183523782
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/44.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_sec_info_access.376687269
Short name T1035
Test name
Test status
Simulation time 399126900 ps
CPU time 72.28 seconds
Started Oct 12 01:19:54 PM UTC 24
Finished Oct 12 01:21:08 PM UTC 24
Peak memory 274924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=376687269 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_sec_info_access.376687269
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/44.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/44.flash_ctrl_smoke.3220936972
Short name T1101
Test name
Test status
Simulation time 698047300 ps
CPU time 256.92 seconds
Started Oct 12 01:19:47 PM UTC 24
Finished Oct 12 01:24:08 PM UTC 24
Peak memory 291284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220936972 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.flash_ctrl_smoke.3220936972
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/44.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_alert_test.3657515513
Short name T1021
Test name
Test status
Simulation time 69364100 ps
CPU time 22.11 seconds
Started Oct 12 01:20:12 PM UTC 24
Finished Oct 12 01:20:35 PM UTC 24
Peak memory 268800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657515513 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_alert_test.3657515513
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/45.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_connect.748608747
Short name T1020
Test name
Test status
Simulation time 22272100 ps
CPU time 21.22 seconds
Started Oct 12 01:20:11 PM UTC 24
Finished Oct 12 01:20:33 PM UTC 24
Peak memory 295008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748608747 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_connect.748608747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/45.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_disable.3460390834
Short name T1019
Test name
Test status
Simulation time 26256100 ps
CPU time 27.34 seconds
Started Oct 12 01:20:05 PM UTC 24
Finished Oct 12 01:20:33 PM UTC 24
Peak memory 285308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3460390834 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_
ctrl_disable.3460390834
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/45.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_hw_sec_otp.437290705
Short name T1095
Test name
Test status
Simulation time 7608660000 ps
CPU time 218.63 seconds
Started Oct 12 01:20:01 PM UTC 24
Finished Oct 12 01:23:44 PM UTC 24
Peak memory 272804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437290705 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_hw_sec_otp.437290705
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/45.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_otp_reset.3116301131
Short name T176
Test name
Test status
Simulation time 126316100 ps
CPU time 144.74 seconds
Started Oct 12 01:20:03 PM UTC 24
Finished Oct 12 01:22:30 PM UTC 24
Peak memory 274808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116301131 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_otp_reset.3116301131
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/45.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_sec_info_access.3437957979
Short name T1047
Test name
Test status
Simulation time 1384319000 ps
CPU time 88.03 seconds
Started Oct 12 01:20:08 PM UTC 24
Finished Oct 12 01:21:38 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437957979 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_sec_info_access.3437957979
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/45.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/45.flash_ctrl_smoke.2164015647
Short name T1031
Test name
Test status
Simulation time 43028400 ps
CPU time 58.62 seconds
Started Oct 12 01:20:00 PM UTC 24
Finished Oct 12 01:21:01 PM UTC 24
Peak memory 276952 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164015647 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.flash_ctrl_smoke.2164015647
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/45.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_alert_test.2045139545
Short name T1026
Test name
Test status
Simulation time 50535400 ps
CPU time 24.32 seconds
Started Oct 12 01:20:19 PM UTC 24
Finished Oct 12 01:20:45 PM UTC 24
Peak memory 268880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2045139545 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_alert_test.2045139545
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/46.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_connect.570168369
Short name T1025
Test name
Test status
Simulation time 16979000 ps
CPU time 24.5 seconds
Started Oct 12 01:20:17 PM UTC 24
Finished Oct 12 01:20:42 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570168369 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_connect.570168369
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/46.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_disable.3957266539
Short name T374
Test name
Test status
Simulation time 27807600 ps
CPU time 29.44 seconds
Started Oct 12 01:20:13 PM UTC 24
Finished Oct 12 01:20:44 PM UTC 24
Peak memory 285308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3957266539 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_
ctrl_disable.3957266539
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/46.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_hw_sec_otp.828288381
Short name T144
Test name
Test status
Simulation time 10898640200 ps
CPU time 92.59 seconds
Started Oct 12 01:20:12 PM UTC 24
Finished Oct 12 01:21:47 PM UTC 24
Peak memory 274844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=828288381 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_hw_sec_otp.828288381
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/46.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_otp_reset.1384583132
Short name T1091
Test name
Test status
Simulation time 73671000 ps
CPU time 187.02 seconds
Started Oct 12 01:20:13 PM UTC 24
Finished Oct 12 01:23:23 PM UTC 24
Peak memory 271048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384583132 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_otp_reset.1384583132
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/46.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_sec_info_access.3812771978
Short name T405
Test name
Test status
Simulation time 2921331600 ps
CPU time 64.93 seconds
Started Oct 12 01:20:16 PM UTC 24
Finished Oct 12 01:21:22 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812771978 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_sec_info_access.3812771978
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/46.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/46.flash_ctrl_smoke.3108232415
Short name T1071
Test name
Test status
Simulation time 17224900 ps
CPU time 136.36 seconds
Started Oct 12 01:20:12 PM UTC 24
Finished Oct 12 01:22:31 PM UTC 24
Peak memory 289360 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108232415 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.flash_ctrl_smoke.3108232415
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/46.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_alert_test.1174613058
Short name T1030
Test name
Test status
Simulation time 95047500 ps
CPU time 20.23 seconds
Started Oct 12 01:20:35 PM UTC 24
Finished Oct 12 01:20:56 PM UTC 24
Peak memory 274604 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174613058 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_alert_test.1174613058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/47.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_connect.896133058
Short name T1029
Test name
Test status
Simulation time 40232000 ps
CPU time 19.05 seconds
Started Oct 12 01:20:35 PM UTC 24
Finished Oct 12 01:20:55 PM UTC 24
Peak memory 284424 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896133058 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_connect.896133058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/47.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_disable.1985177910
Short name T1038
Test name
Test status
Simulation time 10898100 ps
CPU time 41.26 seconds
Started Oct 12 01:20:28 PM UTC 24
Finished Oct 12 01:21:11 PM UTC 24
Peak memory 285272 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1985177910 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_
ctrl_disable.1985177910
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/47.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_hw_sec_otp.253329501
Short name T1067
Test name
Test status
Simulation time 5417670300 ps
CPU time 120.44 seconds
Started Oct 12 01:20:21 PM UTC 24
Finished Oct 12 01:22:24 PM UTC 24
Peak memory 272804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253329501 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_hw_sec_otp.253329501
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/47.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_otp_reset.1832965816
Short name T1092
Test name
Test status
Simulation time 61166200 ps
CPU time 181.27 seconds
Started Oct 12 01:20:23 PM UTC 24
Finished Oct 12 01:23:27 PM UTC 24
Peak memory 270648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832965816 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_otp_reset.1832965816
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/47.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_sec_info_access.2024138335
Short name T147
Test name
Test status
Simulation time 1741324600 ps
CPU time 77.93 seconds
Started Oct 12 01:20:33 PM UTC 24
Finished Oct 12 01:21:53 PM UTC 24
Peak memory 275108 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2024138335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_sec_info_access.2024138335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/47.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/47.flash_ctrl_smoke.3407769786
Short name T1094
Test name
Test status
Simulation time 58638700 ps
CPU time 192 seconds
Started Oct 12 01:20:20 PM UTC 24
Finished Oct 12 01:23:35 PM UTC 24
Peak memory 287320 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407769786 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.flash_ctrl_smoke.3407769786
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/47.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_alert_test.2478579003
Short name T1039
Test name
Test status
Simulation time 45879800 ps
CPU time 24.65 seconds
Started Oct 12 01:20:45 PM UTC 24
Finished Oct 12 01:21:11 PM UTC 24
Peak memory 268932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478579003 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_alert_test.2478579003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/48.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_connect.3547546808
Short name T1037
Test name
Test status
Simulation time 14740300 ps
CPU time 24.47 seconds
Started Oct 12 01:20:45 PM UTC 24
Finished Oct 12 01:21:11 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547546808 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_connect.3547546808
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/48.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_disable.3916552765
Short name T1044
Test name
Test status
Simulation time 36031200 ps
CPU time 41.14 seconds
Started Oct 12 01:20:43 PM UTC 24
Finished Oct 12 01:21:26 PM UTC 24
Peak memory 285244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3916552765 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_
ctrl_disable.3916552765
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/48.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_hw_sec_otp.3336595860
Short name T1077
Test name
Test status
Simulation time 3359821400 ps
CPU time 122.1 seconds
Started Oct 12 01:20:40 PM UTC 24
Finished Oct 12 01:22:44 PM UTC 24
Peak memory 272928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336595860 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_hw_sec_otp.3336595860
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/48.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_otp_reset.242640432
Short name T1098
Test name
Test status
Simulation time 39516400 ps
CPU time 191.68 seconds
Started Oct 12 01:20:42 PM UTC 24
Finished Oct 12 01:23:57 PM UTC 24
Peak memory 270984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242640432 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_otp_reset.242640432
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/48.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_sec_info_access.263737273
Short name T149
Test name
Test status
Simulation time 1630520300 ps
CPU time 70.4 seconds
Started Oct 12 01:20:43 PM UTC 24
Finished Oct 12 01:21:55 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=263737273 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_sec_info_access.263737273
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/48.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/48.flash_ctrl_smoke.1844598496
Short name T1069
Test name
Test status
Simulation time 66845000 ps
CPU time 108.16 seconds
Started Oct 12 01:20:37 PM UTC 24
Finished Oct 12 01:22:27 PM UTC 24
Peak memory 287180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844598496 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.flash_ctrl_smoke.1844598496
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/48.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_alert_test.2634908330
Short name T1040
Test name
Test status
Simulation time 165285900 ps
CPU time 16.95 seconds
Started Oct 12 01:21:03 PM UTC 24
Finished Oct 12 01:21:21 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634908330 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_alert_test.2634908330
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/49.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_connect.2599566743
Short name T1041
Test name
Test status
Simulation time 16121100 ps
CPU time 21.62 seconds
Started Oct 12 01:21:01 PM UTC 24
Finished Oct 12 01:21:24 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2599566743 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_connect.2599566743
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/49.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_disable.2762913036
Short name T1043
Test name
Test status
Simulation time 15451400 ps
CPU time 28.43 seconds
Started Oct 12 01:20:56 PM UTC 24
Finished Oct 12 01:21:26 PM UTC 24
Peak memory 285444 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2762913036 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_
ctrl_disable.2762913036
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/49.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_hw_sec_otp.1026168936
Short name T1056
Test name
Test status
Simulation time 5118914800 ps
CPU time 72.34 seconds
Started Oct 12 01:20:53 PM UTC 24
Finished Oct 12 01:22:07 PM UTC 24
Peak memory 270884 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026168936 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_hw_sec_otp.1026168936
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/49.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_otp_reset.734334931
Short name T177
Test name
Test status
Simulation time 427496900 ps
CPU time 153.19 seconds
Started Oct 12 01:20:54 PM UTC 24
Finished Oct 12 01:23:30 PM UTC 24
Peak memory 270984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734334931 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_otp_reset.734334931
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/49.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_sec_info_access.2540619387
Short name T1051
Test name
Test status
Simulation time 1426592200 ps
CPU time 59.39 seconds
Started Oct 12 01:20:57 PM UTC 24
Finished Oct 12 01:21:58 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540619387 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_sec_info_access.2540619387
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/49.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/49.flash_ctrl_smoke.2171351901
Short name T1093
Test name
Test status
Simulation time 22398800 ps
CPU time 159.48 seconds
Started Oct 12 01:20:49 PM UTC 24
Finished Oct 12 01:23:31 PM UTC 24
Peak memory 289236 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171351901 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.flash_ctrl_smoke.2171351901
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/49.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_alert_test.1333354845
Short name T513
Test name
Test status
Simulation time 142554000 ps
CPU time 16.27 seconds
Started Oct 12 12:32:04 PM UTC 24
Finished Oct 12 12:32:22 PM UTC 24
Peak memory 268800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333354845 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_alert_test.1333354845
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_connect.484337108
Short name T512
Test name
Test status
Simulation time 16684500 ps
CPU time 32.34 seconds
Started Oct 12 12:31:37 PM UTC 24
Finished Oct 12 12:32:10 PM UTC 24
Peak memory 295004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484337108 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_connect.484337108
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_disable.431002089
Short name T391
Test name
Test status
Simulation time 17790600 ps
CPU time 34.93 seconds
Started Oct 12 12:31:27 PM UTC 24
Finished Oct 12 12:32:03 PM UTC 24
Peak memory 285312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=431002089 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_disable.431002089
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_mp.3292792653
Short name T1118
Test name
Test status
Simulation time 43144155800 ps
CPU time 3355.24 seconds
Started Oct 12 12:28:43 PM UTC 24
Finished Oct 12 01:25:14 PM UTC 24
Peak memory 277684 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292792653 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_mp.3292792653
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_error_prog_win.2187140668
Short name T625
Test name
Test status
Simulation time 1352564900 ps
CPU time 1251.23 seconds
Started Oct 12 12:28:41 PM UTC 24
Finished Oct 12 12:49:47 PM UTC 24
Peak memory 285164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2187140668 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_error_prog_win.2187140668
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_fetch_code.2757807975
Short name T73
Test name
Test status
Simulation time 264686100 ps
CPU time 40.74 seconds
Started Oct 12 12:28:36 PM UTC 24
Finished Oct 12 12:29:19 PM UTC 24
Peak memory 272848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=27
57807975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_fetc
h_code.2757807975
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_prog_rma_wipe_err.2775889923
Short name T106
Test name
Test status
Simulation time 10012494100 ps
CPU time 292.77 seconds
Started Oct 12 12:31:59 PM UTC 24
Finished Oct 12 12:36:56 PM UTC 24
Peak memory 328212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=2775889923 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 5.flash_ctrl_hw_prog_rma_wipe_err.2775889923
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_read_seed_err.4253498616
Short name T346
Test name
Test status
Simulation time 46426800 ps
CPU time 24.21 seconds
Started Oct 12 12:31:46 PM UTC 24
Finished Oct 12 12:32:12 PM UTC 24
Peak memory 270860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4253498616 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
5.flash_ctrl_hw_read_seed_err.4253498616
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_rma_reset.1291623588
Short name T199
Test name
Test status
Simulation time 160165464400 ps
CPU time 797.92 seconds
Started Oct 12 12:28:30 PM UTC 24
Finished Oct 12 12:41:58 PM UTC 24
Peak memory 274744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291623588
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_rma_reset.1291623588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_hw_sec_otp.1991581878
Short name T504
Test name
Test status
Simulation time 24420938900 ps
CPU time 173.05 seconds
Started Oct 12 12:28:29 PM UTC 24
Finished Oct 12 12:31:25 PM UTC 24
Peak memory 272804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991581878 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_hw_sec_otp.1991581878
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd.3350126510
Short name T343
Test name
Test status
Simulation time 9712168600 ps
CPU time 210.69 seconds
Started Oct 12 12:30:20 PM UTC 24
Finished Oct 12 12:33:54 PM UTC 24
Peak memory 301696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350126510 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_rd.3350126510
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_rd_slow_flash.2691149909
Short name T344
Test name
Test status
Simulation time 22322103800 ps
CPU time 336.88 seconds
Started Oct 12 12:30:48 PM UTC 24
Finished Oct 12 12:36:30 PM UTC 24
Peak memory 301640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=2691149909 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 5.flash_ctrl_intr_rd_slow_flash.2691149909
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr.3403835331
Short name T508
Test name
Test status
Simulation time 14203854900 ps
CPU time 84.3 seconds
Started Oct 12 12:30:32 PM UTC 24
Finished Oct 12 12:31:58 PM UTC 24
Peak memory 275028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403835331 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr.3403835331
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_intr_wr_slow_flash.1459835139
Short name T538
Test name
Test status
Simulation time 80795950000 ps
CPU time 355.11 seconds
Started Oct 12 12:31:00 PM UTC 24
Finished Oct 12 12:37:00 PM UTC 24
Peak memory 275028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459835139 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 5.flash_ctrl_intr_wr_slow_flash.1459835139
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_invalid_op.55901815
Short name T500
Test name
Test status
Simulation time 1831874400 ps
CPU time 87.12 seconds
Started Oct 12 12:28:50 PM UTC 24
Finished Oct 12 12:30:19 PM UTC 24
Peak memory 270796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55901815 -assert nopostproc +UVM_TESTNAME=flash_
ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_invalid_op.55901815
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_lcmgr_intg.2733334659
Short name T273
Test name
Test status
Simulation time 44892100 ps
CPU time 23.5 seconds
Started Oct 12 12:31:44 PM UTC 24
Finished Oct 12 12:32:09 PM UTC 24
Peak memory 275120 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2733334659 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flas
h_ctrl_lcmgr_intg.2733334659
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_otp_reset.1268454075
Short name T95
Test name
Test status
Simulation time 134252700 ps
CPU time 167.57 seconds
Started Oct 12 12:28:31 PM UTC 24
Finished Oct 12 12:31:22 PM UTC 24
Peak memory 270832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1268454075 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_otp_reset.1268454075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_phy_arb.922077552
Short name T499
Test name
Test status
Simulation time 102599700 ps
CPU time 106.2 seconds
Started Oct 12 12:28:27 PM UTC 24
Finished Oct 12 12:30:15 PM UTC 24
Peak memory 274848 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922077552 -assert nopostproc +UVM_TESTNAME=flash_ctrl_
base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_phy_arb.922077552
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_prog_reset.930149275
Short name T505
Test name
Test status
Simulation time 20566400 ps
CPU time 23.11 seconds
Started Oct 12 12:31:02 PM UTC 24
Finished Oct 12 12:31:26 PM UTC 24
Peak memory 268764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930149275 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_prog_reset.930149275
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rand_ops.3535179634
Short name T522
Test name
Test status
Simulation time 101646300 ps
CPU time 375.47 seconds
Started Oct 12 12:28:25 PM UTC 24
Finished Oct 12 12:34:45 PM UTC 24
Peak memory 291284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535179634 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rand_ops.3535179634
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro.1979787657
Short name T502
Test name
Test status
Simulation time 430241700 ps
CPU time 114.73 seconds
Started Oct 12 12:29:04 PM UTC 24
Finished Oct 12 12:31:01 PM UTC 24
Peak memory 291540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1979787657 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_ro.1979787657
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_derr.912649960
Short name T510
Test name
Test status
Simulation time 2612119500 ps
CPU time 138.33 seconds
Started Oct 12 12:29:46 PM UTC 24
Finished Oct 12 12:32:06 PM UTC 24
Peak memory 291668 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=912649960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 5.flash_ctrl_ro_derr.912649960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_ro_serr.3028265022
Short name T509
Test name
Test status
Simulation time 2666557900 ps
CPU time 161.51 seconds
Started Oct 12 12:29:20 PM UTC 24
Finished Oct 12 12:32:05 PM UTC 24
Peak memory 305860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=3028265022 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash
_ctrl_ro_serr.3028265022
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw.3045239175
Short name T429
Test name
Test status
Simulation time 13760259500 ps
CPU time 460.72 seconds
Started Oct 12 12:29:08 PM UTC 24
Finished Oct 12 12:36:55 PM UTC 24
Peak memory 330400 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045239175 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw.3045239175
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_derr.2953221367
Short name T517
Test name
Test status
Simulation time 3918205800 ps
CPU time 212.99 seconds
Started Oct 12 12:30:17 PM UTC 24
Finished Oct 12 12:33:53 PM UTC 24
Peak memory 295640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2953221367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 5.flash_ctrl_rw_derr.2953221367
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict.1753792274
Short name T506
Test name
Test status
Simulation time 124577100 ps
CPU time 34.06 seconds
Started Oct 12 12:31:08 PM UTC 24
Finished Oct 12 12:31:43 PM UTC 24
Peak memory 287664 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753792274 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_evict.1753792274
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_evict_all_en.2720126960
Short name T436
Test name
Test status
Simulation time 37114700 ps
CPU time 51.23 seconds
Started Oct 12 12:31:23 PM UTC 24
Finished Oct 12 12:32:16 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2720126960 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ct
rl_rw_evict_all_en.2720126960
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_rw_serr.1245242418
Short name T519
Test name
Test status
Simulation time 5740077200 ps
CPU time 284.98 seconds
Started Oct 12 12:29:21 PM UTC 24
Finished Oct 12 12:34:11 PM UTC 24
Peak memory 305860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1245242418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_rw_serr.1245242418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_sec_info_access.1584308559
Short name T303
Test name
Test status
Simulation time 4421234100 ps
CPU time 61.3 seconds
Started Oct 12 12:31:37 PM UTC 24
Finished Oct 12 12:32:40 PM UTC 24
Peak memory 274984 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1584308559 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_sec_info_access.1584308559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_smoke.2020856670
Short name T516
Test name
Test status
Simulation time 1182818700 ps
CPU time 273.11 seconds
Started Oct 12 12:28:24 PM UTC 24
Finished Oct 12 12:33:00 PM UTC 24
Peak memory 291284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020856670 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_smoke.2020856670
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/5.flash_ctrl_wo.3451888189
Short name T491
Test name
Test status
Simulation time 1871346700 ps
CPU time 124.13 seconds
Started Oct 12 12:28:53 PM UTC 24
Finished Oct 12 12:30:59 PM UTC 24
Peak memory 275216 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3451888189 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.flash_ctrl_wo.3451888189
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/5.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_connect.1175779598
Short name T1045
Test name
Test status
Simulation time 17394600 ps
CPU time 20.79 seconds
Started Oct 12 01:21:07 PM UTC 24
Finished Oct 12 01:21:30 PM UTC 24
Peak memory 295008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1175779598 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_connect.1175779598
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/50.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/50.flash_ctrl_otp_reset.2077992935
Short name T1100
Test name
Test status
Simulation time 41665200 ps
CPU time 178.14 seconds
Started Oct 12 01:21:06 PM UTC 24
Finished Oct 12 01:24:07 PM UTC 24
Peak memory 271052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077992935 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.flash_ctrl_otp_reset.2077992935
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/50.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_connect.3190474040
Short name T1046
Test name
Test status
Simulation time 17507900 ps
CPU time 21.91 seconds
Started Oct 12 01:21:11 PM UTC 24
Finished Oct 12 01:21:34 PM UTC 24
Peak memory 294936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190474040 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_connect.3190474040
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/51.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/51.flash_ctrl_otp_reset.2631902058
Short name T1102
Test name
Test status
Simulation time 77585500 ps
CPU time 178.25 seconds
Started Oct 12 01:21:09 PM UTC 24
Finished Oct 12 01:24:10 PM UTC 24
Peak memory 273100 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631902058 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.flash_ctrl_otp_reset.2631902058
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/51.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_connect.1138964479
Short name T1048
Test name
Test status
Simulation time 52841400 ps
CPU time 25.1 seconds
Started Oct 12 01:21:12 PM UTC 24
Finished Oct 12 01:21:38 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1138964479 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_connect.1138964479
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/52.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/52.flash_ctrl_otp_reset.3664758377
Short name T1105
Test name
Test status
Simulation time 81176100 ps
CPU time 184.03 seconds
Started Oct 12 01:21:12 PM UTC 24
Finished Oct 12 01:24:19 PM UTC 24
Peak memory 270860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664758377 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.flash_ctrl_otp_reset.3664758377
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/52.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_connect.2478820795
Short name T146
Test name
Test status
Simulation time 13147000 ps
CPU time 27.86 seconds
Started Oct 12 01:21:22 PM UTC 24
Finished Oct 12 01:21:51 PM UTC 24
Peak memory 294944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478820795 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_connect.2478820795
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/53.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/53.flash_ctrl_otp_reset.2882119404
Short name T1111
Test name
Test status
Simulation time 40648900 ps
CPU time 198.23 seconds
Started Oct 12 01:21:12 PM UTC 24
Finished Oct 12 01:24:33 PM UTC 24
Peak memory 273292 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2882119404 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.flash_ctrl_otp_reset.2882119404
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/53.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_connect.1424373876
Short name T142
Test name
Test status
Simulation time 23016200 ps
CPU time 20.08 seconds
Started Oct 12 01:21:24 PM UTC 24
Finished Oct 12 01:21:46 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424373876 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_connect.1424373876
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/54.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/54.flash_ctrl_otp_reset.904916255
Short name T1109
Test name
Test status
Simulation time 59170900 ps
CPU time 181.78 seconds
Started Oct 12 01:21:23 PM UTC 24
Finished Oct 12 01:24:28 PM UTC 24
Peak memory 271024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=904916255 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.flash_ctrl_otp_reset.904916255
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/54.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_connect.1650281629
Short name T145
Test name
Test status
Simulation time 16809100 ps
CPU time 21.97 seconds
Started Oct 12 01:21:27 PM UTC 24
Finished Oct 12 01:21:50 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650281629 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_connect.1650281629
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/55.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/55.flash_ctrl_otp_reset.3189904421
Short name T1113
Test name
Test status
Simulation time 46234100 ps
CPU time 202.98 seconds
Started Oct 12 01:21:26 PM UTC 24
Finished Oct 12 01:24:52 PM UTC 24
Peak memory 271116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189904421 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.flash_ctrl_otp_reset.3189904421
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/55.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_connect.1516591133
Short name T148
Test name
Test status
Simulation time 24884600 ps
CPU time 22.36 seconds
Started Oct 12 01:21:30 PM UTC 24
Finished Oct 12 01:21:54 PM UTC 24
Peak memory 294936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516591133 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_connect.1516591133
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/56.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/56.flash_ctrl_otp_reset.3568686588
Short name T1099
Test name
Test status
Simulation time 34693400 ps
CPU time 151.41 seconds
Started Oct 12 01:21:27 PM UTC 24
Finished Oct 12 01:24:01 PM UTC 24
Peak memory 270904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568686588 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.flash_ctrl_otp_reset.3568686588
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/56.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_connect.1309600446
Short name T1052
Test name
Test status
Simulation time 15324100 ps
CPU time 22.21 seconds
Started Oct 12 01:21:38 PM UTC 24
Finished Oct 12 01:22:02 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309600446 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_connect.1309600446
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/57.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/57.flash_ctrl_otp_reset.2912117711
Short name T1108
Test name
Test status
Simulation time 37466800 ps
CPU time 167.04 seconds
Started Oct 12 01:21:35 PM UTC 24
Finished Oct 12 01:24:25 PM UTC 24
Peak memory 271116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912117711 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.flash_ctrl_otp_reset.2912117711
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/57.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_connect.4077119302
Short name T1053
Test name
Test status
Simulation time 62064900 ps
CPU time 21.03 seconds
Started Oct 12 01:21:41 PM UTC 24
Finished Oct 12 01:22:03 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4077119302 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_connect.4077119302
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/58.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/58.flash_ctrl_otp_reset.3167144262
Short name T1104
Test name
Test status
Simulation time 143128300 ps
CPU time 154.78 seconds
Started Oct 12 01:21:39 PM UTC 24
Finished Oct 12 01:24:17 PM UTC 24
Peak memory 275004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3167144262 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.flash_ctrl_otp_reset.3167144262
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/58.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_connect.2837588735
Short name T1057
Test name
Test status
Simulation time 39623300 ps
CPU time 20.07 seconds
Started Oct 12 01:21:47 PM UTC 24
Finished Oct 12 01:22:08 PM UTC 24
Peak memory 294816 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837588735 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_connect.2837588735
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/59.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/59.flash_ctrl_otp_reset.188648639
Short name T1114
Test name
Test status
Simulation time 33615300 ps
CPU time 188.3 seconds
Started Oct 12 01:21:42 PM UTC 24
Finished Oct 12 01:24:54 PM UTC 24
Peak memory 270896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=188648639 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.flash_ctrl_otp_reset.188648639
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/59.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_alert_test.1065203706
Short name T534
Test name
Test status
Simulation time 45125100 ps
CPU time 15.58 seconds
Started Oct 12 12:36:12 PM UTC 24
Finished Oct 12 12:36:29 PM UTC 24
Peak memory 268796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065203706 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_alert_test.1065203706
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_connect.2171089636
Short name T532
Test name
Test status
Simulation time 14433600 ps
CPU time 21.11 seconds
Started Oct 12 12:36:00 PM UTC 24
Finished Oct 12 12:36:23 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171089636 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_connect.2171089636
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_disable.2398306662
Short name T119
Test name
Test status
Simulation time 10407900 ps
CPU time 30.36 seconds
Started Oct 12 12:35:41 PM UTC 24
Finished Oct 12 12:36:13 PM UTC 24
Peak memory 285304 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2398306662 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_c
trl_disable.2398306662
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_mp.280592511
Short name T973
Test name
Test status
Simulation time 26994541000 ps
CPU time 2763.1 seconds
Started Oct 12 12:32:23 PM UTC 24
Finished Oct 12 01:18:55 PM UTC 24
Peak memory 272852 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280592511 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fla
sh_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/c
overage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_mp.280592511
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_error_prog_win.1785623796
Short name T626
Test name
Test status
Simulation time 575600500 ps
CPU time 1041.58 seconds
Started Oct 12 12:32:22 PM UTC 24
Finished Oct 12 12:49:55 PM UTC 24
Peak memory 283116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785623796 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_error_prog_win.1785623796
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_fetch_code.2809162348
Short name T515
Test name
Test status
Simulation time 622762100 ps
CPU time 35.71 seconds
Started Oct 12 12:32:17 PM UTC 24
Finished Oct 12 12:32:54 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28
09162348 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_fetc
h_code.2809162348
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_prog_rma_wipe_err.688510499
Short name T107
Test name
Test status
Simulation time 10019973900 ps
CPU time 200.97 seconds
Started Oct 12 12:36:11 PM UTC 24
Finished Oct 12 12:39:35 PM UTC 24
Peak memory 299540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=688510499 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_hw_prog_rma_wipe_err.688510499
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_read_seed_err.4161974339
Short name T533
Test name
Test status
Simulation time 26672200 ps
CPU time 15.83 seconds
Started Oct 12 12:36:08 PM UTC 24
Finished Oct 12 12:36:25 PM UTC 24
Peak memory 270836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4161974339 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
6.flash_ctrl_hw_read_seed_err.4161974339
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_rma_reset.3606175370
Short name T179
Test name
Test status
Simulation time 270194386800 ps
CPU time 851.8 seconds
Started Oct 12 12:32:11 PM UTC 24
Finished Oct 12 12:46:32 PM UTC 24
Peak memory 274876 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3606175370
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_rma_reset.3606175370
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_hw_sec_otp.2671149100
Short name T523
Test name
Test status
Simulation time 15544290900 ps
CPU time 168.79 seconds
Started Oct 12 12:32:10 PM UTC 24
Finished Oct 12 12:35:01 PM UTC 24
Peak memory 272804 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671149100 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_hw_sec_otp.2671149100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd.2955666152
Short name T341
Test name
Test status
Simulation time 1757356900 ps
CPU time 207.9 seconds
Started Oct 12 12:34:17 PM UTC 24
Finished Oct 12 12:37:49 PM UTC 24
Peak memory 301696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2955666152 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_rd.2955666152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_rd_slow_flash.1344132148
Short name T339
Test name
Test status
Simulation time 50684313600 ps
CPU time 320.17 seconds
Started Oct 12 12:34:45 PM UTC 24
Finished Oct 12 12:40:10 PM UTC 24
Peak memory 301636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1344132148 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 6.flash_ctrl_intr_rd_slow_flash.1344132148
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr.315779102
Short name T528
Test name
Test status
Simulation time 2325832800 ps
CPU time 97.65 seconds
Started Oct 12 12:34:22 PM UTC 24
Finished Oct 12 12:36:02 PM UTC 24
Peak memory 270940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315779102 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wor
kspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr.315779102
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_intr_wr_slow_flash.4210226069
Short name T542
Test name
Test status
Simulation time 36768066100 ps
CPU time 157.46 seconds
Started Oct 12 12:35:03 PM UTC 24
Finished Oct 12 12:37:42 PM UTC 24
Peak memory 275012 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210226069 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 6.flash_ctrl_intr_wr_slow_flash.4210226069
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_invalid_op.719040002
Short name T520
Test name
Test status
Simulation time 3114522100 ps
CPU time 92.74 seconds
Started Oct 12 12:32:40 PM UTC 24
Finished Oct 12 12:34:16 PM UTC 24
Peak memory 270800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=719040002 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_invalid_op.719040002
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_lcmgr_intg.1547326039
Short name T274
Test name
Test status
Simulation time 15312900 ps
CPU time 25.68 seconds
Started Oct 12 12:36:02 PM UTC 24
Finished Oct 12 12:36:29 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1547326039 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flas
h_ctrl_lcmgr_intg.1547326039
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_mp_regions.1266427392
Short name T150
Test name
Test status
Simulation time 26358638300 ps
CPU time 473.15 seconds
Started Oct 12 12:32:13 PM UTC 24
Finished Oct 12 12:40:12 PM UTC 24
Peak memory 283284 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1266427392 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 6.flash_ctrl_mp_regions.1266427392
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_otp_reset.3014432964
Short name T525
Test name
Test status
Simulation time 78257300 ps
CPU time 189.82 seconds
Started Oct 12 12:32:13 PM UTC 24
Finished Oct 12 12:35:26 PM UTC 24
Peak memory 270464 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014432964 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_otp_reset.3014432964
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_phy_arb.3096702066
Short name T526
Test name
Test status
Simulation time 169342800 ps
CPU time 224.79 seconds
Started Oct 12 12:32:09 PM UTC 24
Finished Oct 12 12:35:57 PM UTC 24
Peak memory 274836 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3096702066 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_phy_arb.3096702066
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_prog_reset.3896411067
Short name T311
Test name
Test status
Simulation time 24774400 ps
CPU time 29.82 seconds
Started Oct 12 12:35:09 PM UTC 24
Finished Oct 12 12:35:40 PM UTC 24
Peak memory 270864 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896411067 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_prog_reset.3896411067
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rand_ops.3280655186
Short name T540
Test name
Test status
Simulation time 88596100 ps
CPU time 322.88 seconds
Started Oct 12 12:32:07 PM UTC 24
Finished Oct 12 12:37:35 PM UTC 24
Peak memory 281044 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280655186 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rand_ops.3280655186
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_re_evict.633660301
Short name T535
Test name
Test status
Simulation time 61642000 ps
CPU time 52.12 seconds
Started Oct 12 12:35:41 PM UTC 24
Finished Oct 12 12:36:35 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=633660301 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_re_evict.633660301
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro.3838040778
Short name T524
Test name
Test status
Simulation time 2544861700 ps
CPU time 142.24 seconds
Started Oct 12 12:33:01 PM UTC 24
Finished Oct 12 12:35:26 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3838040778 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_ro.3838040778
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_derr.2892368897
Short name T539
Test name
Test status
Simulation time 2299288000 ps
CPU time 173.72 seconds
Started Oct 12 12:34:06 PM UTC 24
Finished Oct 12 12:37:02 PM UTC 24
Peak memory 291520 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892368897 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 6.flash_ctrl_ro_derr.2892368897
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_ro_serr.1632480170
Short name T527
Test name
Test status
Simulation time 2827797900 ps
CPU time 122.43 seconds
Started Oct 12 12:33:55 PM UTC 24
Finished Oct 12 12:36:00 PM UTC 24
Peak memory 305872 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1632480170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash
_ctrl_ro_serr.1632480170
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw.640107272
Short name T577
Test name
Test status
Simulation time 5212232200 ps
CPU time 565.41 seconds
Started Oct 12 12:33:54 PM UTC 24
Finished Oct 12 12:43:27 PM UTC 24
Peak memory 324288 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640107272 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw.640107272
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_derr.2828064225
Short name T209
Test name
Test status
Simulation time 4288912300 ps
CPU time 192.06 seconds
Started Oct 12 12:34:12 PM UTC 24
Finished Oct 12 12:37:27 PM UTC 24
Peak memory 295620 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=2828064225 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 6.flash_ctrl_rw_derr.2828064225
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict.3970640898
Short name T529
Test name
Test status
Simulation time 45021100 ps
CPU time 42.15 seconds
Started Oct 12 12:35:27 PM UTC 24
Finished Oct 12 12:36:10 PM UTC 24
Peak memory 287468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970640898 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_evict.3970640898
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_evict_all_en.2312029110
Short name T432
Test name
Test status
Simulation time 26671000 ps
CPU time 39 seconds
Started Oct 12 12:35:27 PM UTC 24
Finished Oct 12 12:36:07 PM UTC 24
Peak memory 287624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=2312029110 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ct
rl_rw_evict_all_en.2312029110
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_rw_serr.1154426554
Short name T536
Test name
Test status
Simulation time 1119822000 ps
CPU time 159.87 seconds
Started Oct 12 12:33:59 PM UTC 24
Finished Oct 12 12:36:41 PM UTC 24
Peak memory 301780 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1154426554 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_rw_serr.1154426554
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_sec_info_access.513999430
Short name T541
Test name
Test status
Simulation time 23401633700 ps
CPU time 98.89 seconds
Started Oct 12 12:35:57 PM UTC 24
Finished Oct 12 12:37:38 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513999430 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_sec_info_access.513999430
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_smoke.3851240043
Short name T518
Test name
Test status
Simulation time 19159400 ps
CPU time 117.23 seconds
Started Oct 12 12:32:05 PM UTC 24
Finished Oct 12 12:34:05 PM UTC 24
Peak memory 287180 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851240043 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_smoke.3851240043
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/6.flash_ctrl_wo.3264917741
Short name T537
Test name
Test status
Simulation time 2210221600 ps
CPU time 226.9 seconds
Started Oct 12 12:32:55 PM UTC 24
Finished Oct 12 12:36:45 PM UTC 24
Peak memory 270920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=3264917741 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.flash_ctrl_wo.3264917741
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/6.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_connect.4002332762
Short name T1059
Test name
Test status
Simulation time 21906100 ps
CPU time 24.32 seconds
Started Oct 12 01:21:48 PM UTC 24
Finished Oct 12 01:22:14 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002332762 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_connect.4002332762
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/60.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/60.flash_ctrl_otp_reset.2409320559
Short name T1103
Test name
Test status
Simulation time 120038700 ps
CPU time 143.41 seconds
Started Oct 12 01:21:47 PM UTC 24
Finished Oct 12 01:24:13 PM UTC 24
Peak memory 270652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409320559 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.flash_ctrl_otp_reset.2409320559
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/60.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_connect.1884606451
Short name T1060
Test name
Test status
Simulation time 14131300 ps
CPU time 23.67 seconds
Started Oct 12 01:21:52 PM UTC 24
Finished Oct 12 01:22:17 PM UTC 24
Peak memory 294936 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884606451 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_connect.1884606451
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/61.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/61.flash_ctrl_otp_reset.396028111
Short name T1106
Test name
Test status
Simulation time 282208600 ps
CPU time 147.03 seconds
Started Oct 12 01:21:51 PM UTC 24
Finished Oct 12 01:24:21 PM UTC 24
Peak memory 270856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396028111 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.flash_ctrl_otp_reset.396028111
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/61.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_connect.1220221335
Short name T1064
Test name
Test status
Simulation time 21558700 ps
CPU time 24.86 seconds
Started Oct 12 01:21:55 PM UTC 24
Finished Oct 12 01:22:21 PM UTC 24
Peak memory 284828 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220221335 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_connect.1220221335
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/62.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/62.flash_ctrl_otp_reset.2960488160
Short name T1110
Test name
Test status
Simulation time 72581000 ps
CPU time 154.01 seconds
Started Oct 12 01:21:55 PM UTC 24
Finished Oct 12 01:24:31 PM UTC 24
Peak memory 274956 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2960488160 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.flash_ctrl_otp_reset.2960488160
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/62.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_connect.1265048957
Short name T1068
Test name
Test status
Simulation time 24245600 ps
CPU time 25.03 seconds
Started Oct 12 01:21:59 PM UTC 24
Finished Oct 12 01:22:25 PM UTC 24
Peak memory 295004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1265048957 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_connect.1265048957
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/63.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/63.flash_ctrl_otp_reset.1333937254
Short name T1107
Test name
Test status
Simulation time 43753500 ps
CPU time 143.64 seconds
Started Oct 12 01:21:56 PM UTC 24
Finished Oct 12 01:24:22 PM UTC 24
Peak memory 275148 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1333937254 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.flash_ctrl_otp_reset.1333937254
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/63.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_connect.990898085
Short name T1063
Test name
Test status
Simulation time 38382600 ps
CPU time 15.47 seconds
Started Oct 12 01:22:03 PM UTC 24
Finished Oct 12 01:22:20 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990898085 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_connect.990898085
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/64.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/64.flash_ctrl_otp_reset.3975827233
Short name T1112
Test name
Test status
Simulation time 627396600 ps
CPU time 163.6 seconds
Started Oct 12 01:21:59 PM UTC 24
Finished Oct 12 01:24:45 PM UTC 24
Peak memory 271032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975827233 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.flash_ctrl_otp_reset.3975827233
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/64.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_connect.2998594643
Short name T1066
Test name
Test status
Simulation time 27608200 ps
CPU time 17.5 seconds
Started Oct 12 01:22:05 PM UTC 24
Finished Oct 12 01:22:24 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998594643 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_connect.2998594643
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/65.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/65.flash_ctrl_otp_reset.3291084366
Short name T1116
Test name
Test status
Simulation time 37420100 ps
CPU time 175.96 seconds
Started Oct 12 01:22:04 PM UTC 24
Finished Oct 12 01:25:03 PM UTC 24
Peak memory 270904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291084366 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.flash_ctrl_otp_reset.3291084366
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/65.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_connect.2872016373
Short name T1070
Test name
Test status
Simulation time 13487500 ps
CPU time 19.55 seconds
Started Oct 12 01:22:07 PM UTC 24
Finished Oct 12 01:22:28 PM UTC 24
Peak memory 294944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2872016373 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_connect.2872016373
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/66.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/66.flash_ctrl_otp_reset.2938263710
Short name T1124
Test name
Test status
Simulation time 162062100 ps
CPU time 200.02 seconds
Started Oct 12 01:22:07 PM UTC 24
Finished Oct 12 01:25:31 PM UTC 24
Peak memory 271048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938263710 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.flash_ctrl_otp_reset.2938263710
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/66.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_connect.2031591083
Short name T1072
Test name
Test status
Simulation time 14324100 ps
CPU time 24.32 seconds
Started Oct 12 01:22:10 PM UTC 24
Finished Oct 12 01:22:35 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031591083 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_connect.2031591083
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/67.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/67.flash_ctrl_otp_reset.2997391144
Short name T1115
Test name
Test status
Simulation time 75457700 ps
CPU time 169.57 seconds
Started Oct 12 01:22:10 PM UTC 24
Finished Oct 12 01:25:02 PM UTC 24
Peak memory 275020 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997391144 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.flash_ctrl_otp_reset.2997391144
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/67.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_connect.3843216056
Short name T1074
Test name
Test status
Simulation time 43420900 ps
CPU time 21.03 seconds
Started Oct 12 01:22:15 PM UTC 24
Finished Oct 12 01:22:37 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843216056 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_connect.3843216056
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/68.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/68.flash_ctrl_otp_reset.1519230442
Short name T1120
Test name
Test status
Simulation time 81337000 ps
CPU time 184.68 seconds
Started Oct 12 01:22:14 PM UTC 24
Finished Oct 12 01:25:22 PM UTC 24
Peak memory 274808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519230442 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.flash_ctrl_otp_reset.1519230442
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/68.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_connect.2111673413
Short name T1073
Test name
Test status
Simulation time 15636900 ps
CPU time 15.19 seconds
Started Oct 12 01:22:20 PM UTC 24
Finished Oct 12 01:22:37 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111673413 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_connect.2111673413
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/69.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/69.flash_ctrl_otp_reset.2880697270
Short name T1126
Test name
Test status
Simulation time 259139200 ps
CPU time 191.14 seconds
Started Oct 12 01:22:18 PM UTC 24
Finished Oct 12 01:25:32 PM UTC 24
Peak memory 270988 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880697270 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.flash_ctrl_otp_reset.2880697270
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/69.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_alert_test.1807043382
Short name T553
Test name
Test status
Simulation time 350071700 ps
CPU time 24.81 seconds
Started Oct 12 12:39:19 PM UTC 24
Finished Oct 12 12:39:45 PM UTC 24
Peak memory 275072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1807043382 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_alert_test.1807043382
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_connect.4098719170
Short name T549
Test name
Test status
Simulation time 47856200 ps
CPU time 24.59 seconds
Started Oct 12 12:38:59 PM UTC 24
Finished Oct 12 12:39:25 PM UTC 24
Peak memory 295004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098719170 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_connect.4098719170
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_disable.2678541292
Short name T193
Test name
Test status
Simulation time 27857100 ps
CPU time 37.67 seconds
Started Oct 12 12:38:38 PM UTC 24
Finished Oct 12 12:39:17 PM UTC 24
Peak memory 285336 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2678541292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_c
trl_disable.2678541292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_mp.1301706105
Short name T1117
Test name
Test status
Simulation time 37200311000 ps
CPU time 2877.16 seconds
Started Oct 12 12:36:42 PM UTC 24
Finished Oct 12 01:25:09 PM UTC 24
Peak memory 277736 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1301706105 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_mp.1301706105
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_error_prog_win.2820354207
Short name T664
Test name
Test status
Simulation time 344014600 ps
CPU time 1130.27 seconds
Started Oct 12 12:36:36 PM UTC 24
Finished Oct 12 12:55:39 PM UTC 24
Peak memory 285164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820354207 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_error_prog_win.2820354207
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_fetch_code.2299002555
Short name T63
Test name
Test status
Simulation time 470809900 ps
CPU time 35.51 seconds
Started Oct 12 12:36:31 PM UTC 24
Finished Oct 12 12:37:08 PM UTC 24
Peak memory 272844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22
99002555 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_fetc
h_code.2299002555
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_prog_rma_wipe_err.4072530980
Short name T557
Test name
Test status
Simulation time 10064244200 ps
CPU time 71.83 seconds
Started Oct 12 12:39:15 PM UTC 24
Finished Oct 12 12:40:28 PM UTC 24
Peak memory 275072 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=4072530980 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 7.flash_ctrl_hw_prog_rma_wipe_err.4072530980
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_read_seed_err.3146147754
Short name T551
Test name
Test status
Simulation time 25780200 ps
CPU time 26.52 seconds
Started Oct 12 12:39:14 PM UTC 24
Finished Oct 12 12:39:41 PM UTC 24
Peak memory 270844 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3146147754 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
7.flash_ctrl_hw_read_seed_err.3146147754
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_rma_reset.3890831164
Short name T619
Test name
Test status
Simulation time 90144012600 ps
CPU time 746.56 seconds
Started Oct 12 12:36:25 PM UTC 24
Finished Oct 12 12:49:01 PM UTC 24
Peak memory 274744 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3890831164
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_rma_reset.3890831164
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_hw_sec_otp.3032385692
Short name T310
Test name
Test status
Simulation time 9560051000 ps
CPU time 91.81 seconds
Started Oct 12 12:36:23 PM UTC 24
Finished Oct 12 12:37:57 PM UTC 24
Peak memory 274856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3032385692 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_hw_sec_otp.3032385692
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd.202319475
Short name T41
Test name
Test status
Simulation time 4740137600 ps
CPU time 169.88 seconds
Started Oct 12 12:37:39 PM UTC 24
Finished Oct 12 12:40:32 PM UTC 24
Peak memory 306008 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202319475 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_rd.202319475
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_rd_slow_flash.1761918975
Short name T567
Test name
Test status
Simulation time 43429475200 ps
CPU time 276.39 seconds
Started Oct 12 12:37:49 PM UTC 24
Finished Oct 12 12:42:29 PM UTC 24
Peak memory 303796 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=1761918975 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 7.flash_ctrl_intr_rd_slow_flash.1761918975
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr.1908792416
Short name T552
Test name
Test status
Simulation time 9305798500 ps
CPU time 118.88 seconds
Started Oct 12 12:37:43 PM UTC 24
Finished Oct 12 12:39:44 PM UTC 24
Peak memory 275028 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908792416 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr.1908792416
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_intr_wr_slow_flash.1992790613
Short name T566
Test name
Test status
Simulation time 80868717500 ps
CPU time 240.43 seconds
Started Oct 12 12:37:53 PM UTC 24
Finished Oct 12 12:41:57 PM UTC 24
Peak memory 270916 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992790613 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 7.flash_ctrl_intr_wr_slow_flash.1992790613
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_invalid_op.3335634027
Short name T545
Test name
Test status
Simulation time 11532222400 ps
CPU time 77.06 seconds
Started Oct 12 12:36:46 PM UTC 24
Finished Oct 12 12:38:05 PM UTC 24
Peak memory 275024 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3335634027 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_invalid_op.3335634027
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_lcmgr_intg.4135731245
Short name T550
Test name
Test status
Simulation time 73578300 ps
CPU time 24.12 seconds
Started Oct 12 12:39:05 PM UTC 24
Finished Oct 12 12:39:31 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4135731245 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flas
h_ctrl_lcmgr_intg.4135731245
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_mp_regions.1468082869
Short name T410
Test name
Test status
Simulation time 23809837300 ps
CPU time 205.06 seconds
Started Oct 12 12:36:31 PM UTC 24
Finished Oct 12 12:39:59 PM UTC 24
Peak memory 274960 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1468082869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 7.flash_ctrl_mp_regions.1468082869
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_otp_reset.410855560
Short name T96
Test name
Test status
Simulation time 86531700 ps
CPU time 160.42 seconds
Started Oct 12 12:36:29 PM UTC 24
Finished Oct 12 12:39:13 PM UTC 24
Peak memory 270652 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410855560 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_otp_reset.410855560
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_phy_arb.1932282443
Short name T573
Test name
Test status
Simulation time 46060200 ps
CPU time 387.54 seconds
Started Oct 12 12:36:22 PM UTC 24
Finished Oct 12 12:42:55 PM UTC 24
Peak memory 274972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932282443 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_phy_arb.1932282443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_prog_reset.49878367
Short name T547
Test name
Test status
Simulation time 68207100 ps
CPU time 22.06 seconds
Started Oct 12 12:37:57 PM UTC 24
Finished Oct 12 12:38:21 PM UTC 24
Peak memory 274892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49878367 -asse
rt nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /w
orkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_prog_reset.49878367
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rand_ops.3937895719
Short name T658
Test name
Test status
Simulation time 113277100 ps
CPU time 1085.81 seconds
Started Oct 12 12:36:17 PM UTC 24
Finished Oct 12 12:54:34 PM UTC 24
Peak memory 295380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937895719 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rand_ops.3937895719
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_re_evict.86482743
Short name T548
Test name
Test status
Simulation time 263365300 ps
CPU time 49.71 seconds
Started Oct 12 12:38:22 PM UTC 24
Finished Oct 12 12:39:14 PM UTC 24
Peak memory 287436 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86482743 -assert nopostpr
oc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_re_evict.86482743
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro.1526812843
Short name T543
Test name
Test status
Simulation time 490028300 ps
CPU time 143.14 seconds
Started Oct 12 12:36:57 PM UTC 24
Finished Oct 12 12:39:23 PM UTC 24
Peak memory 291468 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1526812843 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_ro.1526812843
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_derr.2683270274
Short name T558
Test name
Test status
Simulation time 817272500 ps
CPU time 178.82 seconds
Started Oct 12 12:37:28 PM UTC 24
Finished Oct 12 12:40:29 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683270274 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 7.flash_ctrl_ro_derr.2683270274
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_ro_serr.1207171181
Short name T555
Test name
Test status
Simulation time 1383146400 ps
CPU time 169.88 seconds
Started Oct 12 12:37:03 PM UTC 24
Finished Oct 12 12:39:56 PM UTC 24
Peak memory 291588 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=1207171181 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash
_ctrl_ro_serr.1207171181
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw.935451747
Short name T602
Test name
Test status
Simulation time 18219079900 ps
CPU time 582.82 seconds
Started Oct 12 12:37:01 PM UTC 24
Finished Oct 12 12:46:51 PM UTC 24
Peak memory 324308 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935451747 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw.935451747
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_derr.3078307685
Short name T560
Test name
Test status
Simulation time 1578502000 ps
CPU time 188.99 seconds
Started Oct 12 12:37:36 PM UTC 24
Finished Oct 12 12:40:48 PM UTC 24
Peak memory 295640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3078307685 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 7.flash_ctrl_rw_derr.3078307685
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict.460291809
Short name T325
Test name
Test status
Simulation time 40764800 ps
CPU time 56.84 seconds
Started Oct 12 12:38:06 PM UTC 24
Finished Oct 12 12:39:04 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460291809 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_evict.460291809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_evict_all_en.3908604094
Short name T424
Test name
Test status
Simulation time 80992900 ps
CPU time 47.06 seconds
Started Oct 12 12:38:10 PM UTC 24
Finished Oct 12 12:38:59 PM UTC 24
Peak memory 287432 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=3908604094 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ct
rl_rw_evict_all_en.3908604094
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_rw_serr.1661884674
Short name T559
Test name
Test status
Simulation time 28728787700 ps
CPU time 202.39 seconds
Started Oct 12 12:37:09 PM UTC 24
Finished Oct 12 12:40:34 PM UTC 24
Peak memory 301892 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1661884674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_rw_serr.1661884674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_sec_info_access.647017091
Short name T401
Test name
Test status
Simulation time 1304421200 ps
CPU time 77.62 seconds
Started Oct 12 12:38:54 PM UTC 24
Finished Oct 12 12:40:14 PM UTC 24
Peak memory 275116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647017091 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/
flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_sec_info_access.647017091
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_smoke.3029237372
Short name T546
Test name
Test status
Simulation time 111974200 ps
CPU time 112.69 seconds
Started Oct 12 12:36:14 PM UTC 24
Finished Oct 12 12:38:09 PM UTC 24
Peak memory 287184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3029237372 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_smoke.3029237372
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/7.flash_ctrl_wo.700739333
Short name T554
Test name
Test status
Simulation time 2049140900 ps
CPU time 173.81 seconds
Started Oct 12 12:36:55 PM UTC 24
Finished Oct 12 12:39:52 PM UTC 24
Peak memory 270944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=700739333 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.flash_ctrl_wo.700739333
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/7.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_connect.2116829292
Short name T1075
Test name
Test status
Simulation time 14983800 ps
CPU time 18.72 seconds
Started Oct 12 01:22:20 PM UTC 24
Finished Oct 12 01:22:40 PM UTC 24
Peak memory 295004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116829292 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_connect.2116829292
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/70.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/70.flash_ctrl_otp_reset.340519872
Short name T1122
Test name
Test status
Simulation time 73158200 ps
CPU time 184.99 seconds
Started Oct 12 01:22:20 PM UTC 24
Finished Oct 12 01:25:28 PM UTC 24
Peak memory 270832 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340519872 -assert nopostproc +UVM_TE
STNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.flash_ctrl_otp_reset.340519872
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/70.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_connect.3475440869
Short name T1079
Test name
Test status
Simulation time 15389300 ps
CPU time 21.77 seconds
Started Oct 12 01:22:24 PM UTC 24
Finished Oct 12 01:22:47 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475440869 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_connect.3475440869
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/71.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/71.flash_ctrl_otp_reset.3368693265
Short name T1127
Test name
Test status
Simulation time 163236400 ps
CPU time 189.14 seconds
Started Oct 12 01:22:21 PM UTC 24
Finished Oct 12 01:25:34 PM UTC 24
Peak memory 275276 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3368693265 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.flash_ctrl_otp_reset.3368693265
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/71.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_connect.929200752
Short name T1078
Test name
Test status
Simulation time 33073700 ps
CPU time 19.79 seconds
Started Oct 12 01:22:25 PM UTC 24
Finished Oct 12 01:22:46 PM UTC 24
Peak memory 284768 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929200752 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_connect.929200752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/72.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/72.flash_ctrl_otp_reset.2483622100
Short name T1121
Test name
Test status
Simulation time 144941700 ps
CPU time 179.19 seconds
Started Oct 12 01:22:25 PM UTC 24
Finished Oct 12 01:25:27 PM UTC 24
Peak memory 271244 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483622100 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.flash_ctrl_otp_reset.2483622100
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/72.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_connect.1378575092
Short name T1082
Test name
Test status
Simulation time 61827500 ps
CPU time 25.85 seconds
Started Oct 12 01:22:28 PM UTC 24
Finished Oct 12 01:22:56 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378575092 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_connect.1378575092
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/73.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/73.flash_ctrl_otp_reset.3534881687
Short name T1123
Test name
Test status
Simulation time 71207600 ps
CPU time 179.97 seconds
Started Oct 12 01:22:26 PM UTC 24
Finished Oct 12 01:25:29 PM UTC 24
Peak memory 275192 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534881687 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.flash_ctrl_otp_reset.3534881687
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/73.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_connect.1942747873
Short name T1084
Test name
Test status
Simulation time 23281000 ps
CPU time 27.88 seconds
Started Oct 12 01:22:31 PM UTC 24
Finished Oct 12 01:23:01 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942747873 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_connect.1942747873
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/74.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/74.flash_ctrl_otp_reset.3103345404
Short name T1125
Test name
Test status
Simulation time 36732800 ps
CPU time 179.29 seconds
Started Oct 12 01:22:29 PM UTC 24
Finished Oct 12 01:25:32 PM UTC 24
Peak memory 270648 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103345404 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.flash_ctrl_otp_reset.3103345404
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/74.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_connect.2623749461
Short name T1083
Test name
Test status
Simulation time 13237200 ps
CPU time 21.8 seconds
Started Oct 12 01:22:36 PM UTC 24
Finished Oct 12 01:22:59 PM UTC 24
Peak memory 294940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623749461 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_connect.2623749461
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/75.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/75.flash_ctrl_otp_reset.3082132142
Short name T86
Test name
Test status
Simulation time 38445300 ps
CPU time 144.94 seconds
Started Oct 12 01:22:32 PM UTC 24
Finished Oct 12 01:24:59 PM UTC 24
Peak memory 271032 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082132142 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.flash_ctrl_otp_reset.3082132142
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/75.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_connect.1341438809
Short name T1085
Test name
Test status
Simulation time 47398400 ps
CPU time 23.29 seconds
Started Oct 12 01:22:38 PM UTC 24
Finished Oct 12 01:23:02 PM UTC 24
Peak memory 295004 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341438809 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_connect.1341438809
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/76.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/76.flash_ctrl_otp_reset.3582064285
Short name T1128
Test name
Test status
Simulation time 60709900 ps
CPU time 174.3 seconds
Started Oct 12 01:22:38 PM UTC 24
Finished Oct 12 01:25:35 PM UTC 24
Peak memory 271116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582064285 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.flash_ctrl_otp_reset.3582064285
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/76.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_connect.814316751
Short name T1086
Test name
Test status
Simulation time 14293700 ps
CPU time 23.6 seconds
Started Oct 12 01:22:43 PM UTC 24
Finished Oct 12 01:23:08 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=814316751 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_
TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_connect.814316751
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/77.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/77.flash_ctrl_otp_reset.3922977577
Short name T1129
Test name
Test status
Simulation time 150393500 ps
CPU time 179.63 seconds
Started Oct 12 01:22:41 PM UTC 24
Finished Oct 12 01:25:44 PM UTC 24
Peak memory 271052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922977577 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.flash_ctrl_otp_reset.3922977577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/77.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_connect.1810934202
Short name T1087
Test name
Test status
Simulation time 47044500 ps
CPU time 20.04 seconds
Started Oct 12 01:22:47 PM UTC 24
Finished Oct 12 01:23:09 PM UTC 24
Peak memory 284696 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810934202 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_connect.1810934202
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/78.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/78.flash_ctrl_otp_reset.4216390314
Short name T1131
Test name
Test status
Simulation time 71855200 ps
CPU time 184.68 seconds
Started Oct 12 01:22:45 PM UTC 24
Finished Oct 12 01:25:53 PM UTC 24
Peak memory 272888 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216390314 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.flash_ctrl_otp_reset.4216390314
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/78.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_connect.1507310232
Short name T1089
Test name
Test status
Simulation time 14739700 ps
CPU time 25.78 seconds
Started Oct 12 01:22:49 PM UTC 24
Finished Oct 12 01:23:16 PM UTC 24
Peak memory 284704 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507310232 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_connect.1507310232
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/79.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/79.flash_ctrl_otp_reset.1526775487
Short name T1130
Test name
Test status
Simulation time 146017100 ps
CPU time 179.41 seconds
Started Oct 12 01:22:47 PM UTC 24
Finished Oct 12 01:25:50 PM UTC 24
Peak memory 271116 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526775487 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.flash_ctrl_otp_reset.1526775487
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/79.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_alert_test.1140812464
Short name T576
Test name
Test status
Simulation time 89359700 ps
CPU time 18.85 seconds
Started Oct 12 12:42:50 PM UTC 24
Finished Oct 12 12:43:10 PM UTC 24
Peak memory 274940 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140812464 -assert nopostproc +UVM_TESTNAME
=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_alert_test.1140812464
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_connect.3680595075
Short name T375
Test name
Test status
Simulation time 17334100 ps
CPU time 23.15 seconds
Started Oct 12 12:42:33 PM UTC 24
Finished Oct 12 12:42:58 PM UTC 24
Peak memory 284700 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680595075 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_connect.3680595075
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_disable.988460439
Short name T392
Test name
Test status
Simulation time 14435500 ps
CPU time 39.71 seconds
Started Oct 12 12:41:59 PM UTC 24
Finished Oct 12 12:42:40 PM UTC 24
Peak memory 285316 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=988460439 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ct
rl_disable.988460439
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_mp.3882805939
Short name T1132
Test name
Test status
Simulation time 21476134400 ps
CPU time 2936.67 seconds
Started Oct 12 12:40:01 PM UTC 24
Finished Oct 12 01:29:30 PM UTC 24
Peak memory 275640 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882805939 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_mp.3882805939
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_error_prog_win.3378687691
Short name T698
Test name
Test status
Simulation time 2413802700 ps
CPU time 1199.47 seconds
Started Oct 12 12:39:58 PM UTC 24
Finished Oct 12 01:00:11 PM UTC 24
Peak memory 285164 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378687691 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_error_prog_win.3378687691
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_fetch_code.3043655347
Short name T556
Test name
Test status
Simulation time 674859900 ps
CPU time 27.85 seconds
Started Oct 12 12:39:53 PM UTC 24
Finished Oct 12 12:40:22 PM UTC 24
Peak memory 272924 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=30
43655347 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_fetc
h_code.3043655347
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_prog_rma_wipe_err.1153222237
Short name T587
Test name
Test status
Simulation time 10033553500 ps
CPU time 139.56 seconds
Started Oct 12 12:42:45 PM UTC 24
Finished Oct 12 12:45:07 PM UTC 24
Peak memory 281088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1153222237 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 8.flash_ctrl_hw_prog_rma_wipe_err.1153222237
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_read_seed_err.3009815674
Short name T575
Test name
Test status
Simulation time 15111600 ps
CPU time 25.01 seconds
Started Oct 12 12:42:41 PM UTC 24
Finished Oct 12 12:43:08 PM UTC 24
Peak memory 275068 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3009815674 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name
8.flash_ctrl_hw_read_seed_err.3009815674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_rma_reset.3490430003
Short name T180
Test name
Test status
Simulation time 420326253500 ps
CPU time 1212.98 seconds
Started Oct 12 12:39:42 PM UTC 24
Finished Oct 12 01:00:09 PM UTC 24
Peak memory 274880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490430003
-assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_rma_reset.3490430003
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_hw_sec_otp.41833760
Short name T319
Test name
Test status
Simulation time 4112934300 ps
CPU time 79.15 seconds
Started Oct 12 12:39:35 PM UTC 24
Finished Oct 12 12:40:56 PM UTC 24
Peak memory 274980 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41833760 -assert nopostproc +UVM_TES
TNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_hw_sec_otp.41833760
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd.4012475577
Short name T42
Test name
Test status
Simulation time 1472156000 ps
CPU time 147.02 seconds
Started Oct 12 12:40:49 PM UTC 24
Finished Oct 12 12:43:18 PM UTC 24
Peak memory 305856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012475577 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_rd.4012475577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_rd_slow_flash.3179874067
Short name T340
Test name
Test status
Simulation time 19047997900 ps
CPU time 350.23 seconds
Started Oct 12 12:40:57 PM UTC 24
Finished Oct 12 12:46:52 PM UTC 24
Peak memory 301624 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=3179874067 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm
_name 8.flash_ctrl_intr_rd_slow_flash.3179874067
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr.1106959211
Short name T569
Test name
Test status
Simulation time 2135434100 ps
CPU time 101.6 seconds
Started Oct 12 12:40:52 PM UTC 24
Finished Oct 12 12:42:36 PM UTC 24
Peak memory 275016 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1106959211 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr.1106959211
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_intr_wr_slow_flash.2394064635
Short name T584
Test name
Test status
Simulation time 52817131300 ps
CPU time 185.79 seconds
Started Oct 12 12:41:29 PM UTC 24
Finished Oct 12 12:44:38 PM UTC 24
Peak memory 270912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394064635 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 8.flash_ctrl_intr_wr_slow_flash.2394064635
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_invalid_op.3876969896
Short name T563
Test name
Test status
Simulation time 3064374200 ps
CPU time 76.48 seconds
Started Oct 12 12:40:10 PM UTC 24
Finished Oct 12 12:41:29 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3876969896 -assert nopostproc +UVM_TESTNAME=flas
h_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_invalid_op.3876969896
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_lcmgr_intg.1986158262
Short name T574
Test name
Test status
Simulation time 25255000 ps
CPU time 23.21 seconds
Started Oct 12 12:42:36 PM UTC 24
Finished Oct 12 12:43:01 PM UTC 24
Peak memory 272912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1986158262 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flas
h_ctrl_lcmgr_intg.1986158262
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_mp_regions.1981657881
Short name T578
Test name
Test status
Simulation time 24581367600 ps
CPU time 218.45 seconds
Started Oct 12 12:39:45 PM UTC 24
Finished Oct 12 12:43:27 PM UTC 24
Peak memory 274964 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=1981657881 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log
/dev/null -cm_name 8.flash_ctrl_mp_regions.1981657881
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_otp_reset.1097052242
Short name T580
Test name
Test status
Simulation time 136821100 ps
CPU time 236.3 seconds
Started Oct 12 12:39:45 PM UTC 24
Finished Oct 12 12:43:45 PM UTC 24
Peak memory 274932 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1097052242 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_otp_reset.1097052242
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_phy_arb.3577971780
Short name T588
Test name
Test status
Simulation time 105117800 ps
CPU time 348.91 seconds
Started Oct 12 12:39:32 PM UTC 24
Finished Oct 12 12:45:26 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577971780 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_phy_arb.3577971780
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_prog_reset.3341783417
Short name T565
Test name
Test status
Simulation time 65397100 ps
CPU time 23.16 seconds
Started Oct 12 12:41:31 PM UTC 24
Finished Oct 12 12:41:55 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341783417 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_prog_reset.3341783417
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rand_ops.2310556748
Short name T606
Test name
Test status
Simulation time 152989200 ps
CPU time 490.2 seconds
Started Oct 12 12:39:26 PM UTC 24
Finished Oct 12 12:47:42 PM UTC 24
Peak memory 287312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310556748 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rand_ops.2310556748
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_re_evict.2381005572
Short name T413
Test name
Test status
Simulation time 203658800 ps
CPU time 51.54 seconds
Started Oct 12 12:41:58 PM UTC 24
Finished Oct 12 12:42:51 PM UTC 24
Peak memory 285552 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381005572 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_re_evict.2381005572
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro.1590415076
Short name T564
Test name
Test status
Simulation time 1010271500 ps
CPU time 96.63 seconds
Started Oct 12 12:40:14 PM UTC 24
Finished Oct 12 12:41:53 PM UTC 24
Peak memory 301660 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1590415076 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_ro.1590415076
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_derr.274628188
Short name T579
Test name
Test status
Simulation time 3433277900 ps
CPU time 182.56 seconds
Started Oct 12 12:40:33 PM UTC 24
Finished Oct 12 12:43:38 PM UTC 24
Peak memory 291516 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274628188 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vse
q +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 8.flash_ctrl_ro_derr.274628188
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_ro_serr.4281829690
Short name T572
Test name
Test status
Simulation time 424324500 ps
CPU time 139.93 seconds
Started Oct 12 12:40:29 PM UTC 24
Finished Oct 12 12:42:52 PM UTC 24
Peak memory 291540 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=4281829690 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash
_ctrl_ro_serr.4281829690
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw.2077488326
Short name T609
Test name
Test status
Simulation time 13660744100 ps
CPU time 454.77 seconds
Started Oct 12 12:40:22 PM UTC 24
Finished Oct 12 12:48:03 PM UTC 24
Peak memory 336608 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077488326 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /works
paces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw.2077488326
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_derr.279280012
Short name T585
Test name
Test status
Simulation time 4806877900 ps
CPU time 243.82 seconds
Started Oct 12 12:40:35 PM UTC 24
Finished Oct 12 12:44:42 PM UTC 24
Peak memory 297880 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=279280012 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/n
ull -cm_name 8.flash_ctrl_rw_derr.279280012
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict.3654308445
Short name T568
Test name
Test status
Simulation time 60278200 ps
CPU time 36.81 seconds
Started Oct 12 12:41:54 PM UTC 24
Finished Oct 12 12:42:32 PM UTC 24
Peak memory 287440 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654308445 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_evict.3654308445
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_evict_all_en.64309774
Short name T571
Test name
Test status
Simulation time 29255700 ps
CPU time 51.74 seconds
Started Oct 12 12:41:56 PM UTC 24
Finished Oct 12 12:42:49 PM UTC 24
Peak memory 285380 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=64309774 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl
_rw_evict_all_en.64309774
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_rw_serr.1226951622
Short name T590
Test name
Test status
Simulation time 7830064400 ps
CPU time 295.24 seconds
Started Oct 12 12:40:30 PM UTC 24
Finished Oct 12 12:45:30 PM UTC 24
Peak memory 305860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=1226951622 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_rw_serr.1226951622
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_sec_info_access.1834696440
Short name T583
Test name
Test status
Simulation time 3981510600 ps
CPU time 84.92 seconds
Started Oct 12 12:42:30 PM UTC 24
Finished Oct 12 12:43:57 PM UTC 24
Peak memory 274920 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1834696440 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_sec_info_access.1834696440
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_smoke.2952310367
Short name T562
Test name
Test status
Simulation time 35638100 ps
CPU time 122.63 seconds
Started Oct 12 12:39:24 PM UTC 24
Finished Oct 12 12:41:29 PM UTC 24
Peak memory 287184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952310367 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_smoke.2952310367
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/8.flash_ctrl_wo.1848577359
Short name T582
Test name
Test status
Simulation time 4436312400 ps
CPU time 214.15 seconds
Started Oct 12 12:40:13 PM UTC 24
Finished Oct 12 12:43:51 PM UTC 24
Peak memory 272972 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1848577359 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.flash_ctrl_wo.1848577359
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/8.flash_ctrl_wo/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_alert_test.687233680
Short name T604
Test name
Test status
Simulation time 101649400 ps
CPU time 25.61 seconds
Started Oct 12 12:46:35 PM UTC 24
Finished Oct 12 12:47:02 PM UTC 24
Peak memory 268944 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687233680 -assert nopostproc +UVM_TESTNAME=
flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_alert_test.687233680
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_connect.3846246099
Short name T102
Test name
Test status
Simulation time 21172900 ps
CPU time 22.99 seconds
Started Oct 12 12:46:18 PM UTC 24
Finished Oct 12 12:46:43 PM UTC 24
Peak memory 284764 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846246099 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_connect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_connect.3846246099
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_connect/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_disable.3135385749
Short name T121
Test name
Test status
Simulation time 11305300 ps
CPU time 41.65 seconds
Started Oct 12 12:46:08 PM UTC 24
Finished Oct 12 12:46:51 PM UTC 24
Peak memory 285312 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3135385749 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_c
trl_disable.3135385749
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_mp.3995742028
Short name T1133
Test name
Test status
Simulation time 5146153100 ps
CPU time 3075.86 seconds
Started Oct 12 12:43:28 PM UTC 24
Finished Oct 12 01:35:18 PM UTC 24
Peak memory 275636 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +op_readonly_on_info_partition=0 +o
p_readonly_on_info1_partition=0 +op_readonly_on_info2_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995742028 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=fl
ash_ctrl_error_mp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/
coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_mp.3995742028
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_error_mp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_error_prog_win.2947721304
Short name T688
Test name
Test status
Simulation time 646038600 ps
CPU time 936.46 seconds
Started Oct 12 12:43:28 PM UTC 24
Finished Oct 12 12:59:14 PM UTC 24
Peak memory 285352 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2947721304 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_error_prog_win_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/f
lash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_error_prog_win.2947721304
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_error_prog_win/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_fetch_code.1519913956
Short name T581
Test name
Test status
Simulation time 120397700 ps
CPU time 26.44 seconds
Started Oct 12 12:43:19 PM UTC 24
Finished Oct 12 12:43:47 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +op_readonly_on_info_partition=1 +op_readonly_on_info1_partition=1 +
cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15
19913956 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_fetch_code_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+ass
ert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_fetc
h_code.1519913956
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_fetch_code/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_prog_rma_wipe_err.3128731093
Short name T269
Test name
Test status
Simulation time 10022088400 ps
CPU time 96.05 seconds
Started Oct 12 12:46:35 PM UTC 24
Finished Oct 12 12:48:13 PM UTC 24
Peak memory 295644 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +flash_program_latency=5 +en_always_all=1
+bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=3128731093 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_prog_rma_wipe_err_v
seq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vd
b -cm_log /dev/null -cm_name 9.flash_ctrl_hw_prog_rma_wipe_err.3128731093
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_hw_prog_rma_wipe_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_read_seed_err.225466147
Short name T603
Test name
Test status
Simulation time 47709300 ps
CPU time 18.85 seconds
Started Oct 12 12:46:33 PM UTC 24
Finished Oct 12 12:46:53 PM UTC 24
Peak memory 271088 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=225466147 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_read_seed_err_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9
.flash_ctrl_hw_read_seed_err.225466147
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_hw_read_seed_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_rma_reset.992691577
Short name T696
Test name
Test status
Simulation time 80134448500 ps
CPU time 986.08 seconds
Started Oct 12 12:43:02 PM UTC 24
Finished Oct 12 12:59:40 PM UTC 24
Peak memory 274748 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +flash_program_latency=5 +test_timeout_ns=300_000_000_000 +cdc_instr
umentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992691577 -
assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_rma_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_
dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_rma_reset.992691577
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_hw_rma_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_hw_sec_otp.3858036438
Short name T315
Test name
Test status
Simulation time 4766935700 ps
CPU time 132.18 seconds
Started Oct 12 12:42:59 PM UTC 24
Finished Oct 12 12:45:14 PM UTC 24
Peak memory 274856 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3858036438 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_hw_sec_otp_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat
ch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_hw_sec_otp.3858036438
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_hw_sec_otp/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd.3721656502
Short name T607
Test name
Test status
Simulation time 4100398500 ps
CPU time 181.23 seconds
Started Oct 12 12:44:44 PM UTC 24
Finished Oct 12 12:47:49 PM UTC 24
Peak memory 306076 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721656502 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_rd.3721656502
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_rd_slow_flash.670536152
Short name T337
Test name
Test status
Simulation time 11795245800 ps
CPU time 238.51 seconds
Started Oct 12 12:45:15 PM UTC 24
Finished Oct 12 12:49:17 PM UTC 24
Peak memory 301628 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +tes
t_timeout_ns=500_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/s
im.tcl +ntb_random_seed=670536152 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_rd_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_
name 9.flash_ctrl_intr_rd_slow_flash.670536152
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_intr_rd_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr.1558203097
Short name T601
Test name
Test status
Simulation time 2670589600 ps
CPU time 99.48 seconds
Started Oct 12 12:45:07 PM UTC 24
Finished Oct 12 12:46:49 PM UTC 24
Peak memory 270928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558203097 -as
sert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /wo
rkspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr.1558203097
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_intr_wr_slow_flash.2147945418
Short name T622
Test name
Test status
Simulation time 18391239800 ps
CPU time 224.67 seconds
Started Oct 12 12:45:27 PM UTC 24
Finished Oct 12 12:49:15 PM UTC 24
Peak memory 275204 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +flash_read_latency=50 +flash_program_latency=500 +rd_
buf_en_to=500_000 +test_timeout_ns=1_000_000_000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /works
paces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147945418 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_intr_wr_
vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.v
db -cm_log /dev/null -cm_name 9.flash_ctrl_intr_wr_slow_flash.2147945418
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_intr_wr_slow_flash/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_invalid_op.779327640
Short name T586
Test name
Test status
Simulation time 4320288800 ps
CPU time 62.54 seconds
Started Oct 12 12:43:39 PM UTC 24
Finished Oct 12 12:44:44 PM UTC 24
Peak memory 275084 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +fast_rcvr_recov_err +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=779327640 -assert nopostproc +UVM_TESTNAME=flash
_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_invalid_op_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_invalid_op.779327640
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_invalid_op/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_lcmgr_intg.3312484443
Short name T599
Test name
Test status
Simulation time 47569300 ps
CPU time 25.55 seconds
Started Oct 12 12:46:20 PM UTC 24
Finished Oct 12 12:46:47 PM UTC 24
Peak memory 272912 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_all=1 +bypass_alert_ready_to_en
d_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3312484443 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_lcmgr_intg_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flas
h_ctrl_lcmgr_intg.3312484443
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_lcmgr_intg/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_mp_regions.411696068
Short name T595
Test name
Test status
Simulation time 6571524700 ps
CPU time 185.57 seconds
Started Oct 12 12:43:10 PM UTC 24
Finished Oct 12 12:46:19 PM UTC 24
Peak memory 272904 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +multi_alert=1 +test_timeout_ns=300_000_000_000 +fast_rcvr_recov_err
+op_readonly_on_info1_partition=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/
dv/tools/sim.tcl +ntb_random_seed=411696068 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_mp_regions_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /
dev/null -cm_name 9.flash_ctrl_mp_regions.411696068
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_mp_regions/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_otp_reset.3466278206
Short name T593
Test name
Test status
Simulation time 92986000 ps
CPU time 175.79 seconds
Started Oct 12 12:43:09 PM UTC 24
Finished Oct 12 12:46:08 PM UTC 24
Peak memory 270900 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +test_timeout_ns=300_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466278206 -assert nopostproc +UVM_T
ESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_otp_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_otp_reset.3466278206
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_otp_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_phy_arb.2946413474
Short name T613
Test name
Test status
Simulation time 2730616900 ps
CPU time 338.38 seconds
Started Oct 12 12:42:56 PM UTC 24
Finished Oct 12 12:48:39 PM UTC 24
Peak memory 274896 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +zero_delays=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_
VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946413474 -assert nopostproc +UVM_TESTNAME=flash_ctrl
_base_test +UVM_TEST_SEQ=flash_ctrl_phy_arb_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_phy_arb.2946413474
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_phy_arb/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_prog_reset.317618674
Short name T591
Test name
Test status
Simulation time 67316300 ps
CPU time 23.29 seconds
Started Oct 12 12:45:27 PM UTC 24
Finished Oct 12 12:45:51 PM UTC 24
Peak memory 270800 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +test_timeout_ns=500_000_000 +cdc_instrume
ntation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317618674 -ass
ert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_prog_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_prog_reset.317618674
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_prog_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rand_ops.3667542877
Short name T610
Test name
Test status
Simulation time 46401700 ps
CPU time 318.96 seconds
Started Oct 12 12:42:53 PM UTC 24
Finished Oct 12 12:48:17 PM UTC 24
Peak memory 289232 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3667542877 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_rand_ops_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rand_ops.3667542877
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_rand_ops/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_re_evict.326995821
Short name T600
Test name
Test status
Simulation time 64733800 ps
CPU time 40.51 seconds
Started Oct 12 12:46:06 PM UTC 24
Finished Oct 12 12:46:48 PM UTC 24
Peak memory 287560 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326995821 -assert nopostp
roc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_re_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_re_evict.326995821
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_re_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro.1077578352
Short name T110
Test name
Test status
Simulation time 1136417400 ps
CPU time 144.73 seconds
Started Oct 12 12:43:48 PM UTC 24
Finished Oct 12 12:46:16 PM UTC 24
Peak memory 303808 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=1000 +otf_wr_pct=0 +ecc_mo
de=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1077578352 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_ro.1077578352
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_ro/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_derr.2722313693
Short name T596
Test name
Test status
Simulation time 512313700 ps
CPU time 113.38 seconds
Started Oct 12 12:44:39 PM UTC 24
Finished Oct 12 12:46:35 PM UTC 24
Peak memory 291536 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /wo
rkspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722313693 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vs
eq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb
-cm_log /dev/null -cm_name 9.flash_ctrl_ro_derr.2722313693
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_ro_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_ro_serr.2875793267
Short name T597
Test name
Test status
Simulation time 812851400 ps
CPU time 154.3 seconds
Started Oct 12 12:43:58 PM UTC 24
Finished Oct 12 12:46:35 PM UTC 24
Peak memory 306052 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +otf_wr_pct=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +
ntb_random_seed=2875793267 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+
branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash
_ctrl_ro_serr.2875793267
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_ro_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw.770495752
Short name T629
Test name
Test status
Simulation time 12640813300 ps
CPU time 404.72 seconds
Started Oct 12 12:43:52 PM UTC 24
Finished Oct 12 12:50:41 PM UTC 24
Peak memory 320212 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +test_timeout_ns=5_000_000_000 +ecc_mode=1 +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770495752 -a
ssert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /worksp
aces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw.770495752
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_derr.3841697114
Short name T615
Test name
Test status
Simulation time 2302741800 ps
CPU time 245.76 seconds
Started Oct 12 12:44:43 PM UTC 24
Finished Oct 12 12:48:52 PM UTC 24
Peak memory 299928 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=3 +derr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +bypass_alert_ready_to_end_check=1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/
hw/dv/tools/sim.tcl +ntb_random_seed=3841697114 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 9.flash_ctrl_rw_derr.3841697114
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_rw_derr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict.2363183417
Short name T594
Test name
Test status
Simulation time 49808700 ps
CPU time 45.53 seconds
Started Oct 12 12:45:31 PM UTC 24
Finished Oct 12 12:46:18 PM UTC 24
Peak memory 287632 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +cdc_instrumentation_ena
bled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363183417 -assert nopost
proc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/r
epo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_evict.2363183417
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_evict_all_en.1711771508
Short name T598
Test name
Test status
Simulation time 168087800 ps
CPU time 45.89 seconds
Started Oct 12 12:45:52 PM UTC 24
Finished Oct 12 12:46:39 PM UTC 24
Peak memory 287456 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=1 +en_always_read=1 +en_always_prog=1 en_rnd
_data=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_rando
m_seed=1711771508 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_evict_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ct
rl_rw_evict_all_en.1711771508
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_rw_evict_all_en/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_rw_serr.2634226593
Short name T605
Test name
Test status
Simulation time 5208139800 ps
CPU time 195.99 seconds
Started Oct 12 12:44:04 PM UTC 24
Finished Oct 12 12:47:23 PM UTC 24
Peak memory 305860 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +ecc_mode=2 +serr_pct=3 +otf_num_rw=100 +otf_num_hr=10
00 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_see
d=2634226593 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_rw_serr.2634226593
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_rw_serr/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_sec_info_access.2878620814
Short name T398
Test name
Test status
Simulation time 2067951000 ps
CPU time 74.33 seconds
Started Oct 12 12:46:16 PM UTC 24
Finished Oct 12 12:47:32 PM UTC 24
Peak memory 275048 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2878620814 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_info_part_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11
/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_sec_info_access.2878620814
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_sec_info_access/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_smoke.2546336121
Short name T608
Test name
Test status
Simulation time 125481000 ps
CPU time 304.6 seconds
Started Oct 12 12:42:52 PM UTC 24
Finished Oct 12 12:48:01 PM UTC 24
Peak memory 289184 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_L
OW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546336121 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM
_TEST_SEQ=flash_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl
-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_smoke.2546336121
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default/9.flash_ctrl_wo.1805185677
Short name T592
Test name
Test status
Simulation time 3676664300 ps
CPU time 136.04 seconds
Started Oct 12 12:43:46 PM UTC 24
Finished Oct 12 12:46:05 PM UTC 24
Peak memory 271056 kb
Host riverbear.us-west1-a.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/default/simv +scb_otf_en=1 +otf_num_rw=100 +otf_num_hr=0 +otf_rd_pct=0 +ecc_mode=
1 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed
=1805185677 -assert nopostproc +UVM_TESTNAME=flash_ctrl_base_test +UVM_TEST_SEQ=flash_ctrl_rw_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -
cm_dir /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.flash_ctrl_wo.1805185677
Directory /workspaces/repo/scratch/os_regression_2024_10_11/flash_ctrl-sim-vcs/9.flash_ctrl_wo/latest
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