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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.WreadyKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	391176692	51529862	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	391176692	13126715	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DataKnown_AKnownEnable	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	391176692	13126715	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	391176692	3604407	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	391176692	3604413	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	391176692	8965155	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	390994669	13993652	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DataKnown_AKnownEnable	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390994669	13993652	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	390994669	51529862	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DataKnown_AKnownEnable	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390994669	51529862	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	391176692	2579774	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	391176692	2579774	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	391176692	2579774	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	391176692	269714767	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	391176692	2579774	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	391176692	2579774	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	391176692	115185371	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs.AssertConnected_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_state_regs_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_A	0	0	390994669	2581725	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DataKnown_AKnownEnable	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.DepthKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.RvalidKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.WreadyKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[0].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390994669	2581725	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.ArbCntMax_A	0	0	391176692	1202477	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.CtrlPrio_A	0	0	391176692	1202477	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.HostTransIdleChk_A	0	0	391176692	21855068	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.NoRemainder_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.OneHotReqs_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.Pow2Multiple_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.RdTxnCheck_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.OneDonePerTxn_A	0	0	391176692	1157393	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PostPackRule_A	0	0	391176692	883	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.PrePackRule_A	0	0	391176692	615	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.WidthCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs.AssertConnected_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.gen_prog_data.u_prog.u_state_regs_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.OutputsKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	391176692	90706219	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	391176692	90706219	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	391176692	90706219	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	391176692	40876153	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.Priority_A	0	0	391176692	96833439	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	391176692	90706219	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	391176692	90706219	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	391176692	96833439	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[0].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckHotOne_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.CheckNGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesReady_A	0	0	391176692	90706137	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GntImpliesValid_A	0	0	391176692	90706137	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.GrantKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IdxKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.IndexIsCorrect_A	0	0	391176692	90706137	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	391176692	40876153	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.Priority_A	0	0	391176692	96833357	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	391176692	90706137	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	391176692	90706137	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ReqImpliesValid_A	0	0	391176692	96833357	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_host_arb.gen_input_bufs[1].gen_fixed_arbiter.u_arb.ValidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.BufferMatchEcc_A	0	0	391176692	609999	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveOps_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveProgHazard_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ExclusiveState_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.ForwardCheck_A	0	0	391176692	1808517	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.IdleCheck_A	0	0	391176692	47612945	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.MaxBufs_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotAlloc_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotMatch_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotRspMatch_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.OneHotUpdate_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.AllocCheck_A	0	0	391176692	585829	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[0].u_rd_buf.UpdateCheck_A	0	0	391176692	585826	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.AllocCheck_A	0	0	391176692	585597	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[1].u_rd_buf.UpdateCheck_A	0	0	391176692	585595	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.AllocCheck_A	0	0	391176692	585418	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[2].u_rd_buf.UpdateCheck_A	0	0	391176692	585417	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.AllocCheck_A	0	0	391176692	585000	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.gen_bufs[3].u_rd_buf.UpdateCheck_A	0	0	391176692	584998	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.DataKnown_A	0	0	391176692	47609119	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.DataKnown_AKnownEnable	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.DepthKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.RvalidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.WreadyKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_addr_xor_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	391176692	47609119	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_A	0	0	391176692	11546280	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DataKnown_AKnownEnable	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.DepthKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.RvalidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.WreadyKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_mask_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	391176692	11546280	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDecrUnderRun_A	0	0	391176692	2951835	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferDepRsp_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.BufferIncrOverFlow_A	0	0	391176692	2951843	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_buf_dep.DepBufferRspOrder_A	0	0	391176694	7499204	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_A	0	0	390994669	12428925	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DataKnown_AKnownEnable	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.DepthKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.RvalidKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.WreadyKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rd_storage.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390994669	12428925	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_A	0	0	390994669	47609119	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DataKnown_AKnownEnable	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.DepthKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.RvalidKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.WreadyKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_rsp_order_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390994669	47609119	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckHotOne_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.CheckNGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesReady_A	0	0	391176692	2287241	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GntImpliesValid_A	0	0	391176692	2287241	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.GrantKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IdxKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.IndexIsCorrect_A	0	0	391176692	2287241	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.NoReadyValidNoGrant_A	0	0	391176692	277642324	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReadyAndValidImplyGrant_A	0	0	391176692	2287241	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqAndReadyImplyGrant_A	0	0	391176692	2287241	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ReqImpliesValid_A	0	0	391176692	108119882	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.ValidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs.AssertConnected_A	0	0	1051	1051	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_state_regs_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_A	0	0	390994669	2432114	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DataKnown_AKnownEnable	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.DepthKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.RvalidKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.WreadyKnown_A	0	0	390994669	390182147	0	0
tb.dut.u_eflash.gen_flash_cores[1].u_host_rsp_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	390994669	2432114	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_A	0	0	391176692	32107824	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DataKnown_AKnownEnable	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.DepthKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.RvalidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.WreadyKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_bank_sequence_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	391176692	32107824	0	0
tb.dut.u_eflash.u_disable_buf.NumCopiesMustBeGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_disable_buf.OutputsKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_disable_buf.gen_no_flops.OutputDelay_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	391176692	16855623	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	391176692	6723328	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	391176692	7014452	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	391176692	90503341	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DataKnown_AKnownEnable	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	391176692	90503341	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[0].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	391176692	60330618	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[0].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	391176692	6979886	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[1].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	391176692	5793280	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.gen_info_types[2].u_info_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	391176692	5949442	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_A	0	0	391176692	74590652	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DataKnown_AKnownEnable	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.DepthKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.RvalidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.WreadyKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_cmd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	391176692	74590652	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.DataBitsPerMaskCheck_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.gen_prim_flash_banks[1].u_prim_flash_bank.u_mem.gen_generic.u_impl_generic.gen_wmask[0].MaskCheck_A	0	0	391176692	55644408	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.en2addrHit	0	0	393570196	51067	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.reAfterRv	0	0	393570196	51067	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.rePulse	0	0	393570196	36117	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_chk.PayLoadWidthCheck	0	0	1266	1266	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.AllowedLatency_A	0	0	1266	1266	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.MatchedWidthAssert	0	0	1266	1266	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_err.dataWidthOnly32_A	0	0	1266	1266	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1266	1266	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1266	1266	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.DataWidthCheck_A	0	0	1266	1266	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1266	1266	0	0
tb.dut.u_eflash.u_flash.gen_generic.u_impl_generic.u_reg_top.wePulse	0	0	393570196	14950	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.OutputsKnown_A	0	0	384600752	383788230	0	0
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	384600752	383756307	0	2751
tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult.IntegerLoops_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_scramble.gen_gf_mult.u_mult.StagePow2_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckHotOne_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckNGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesReady_A	0	0	391176692	17043590	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesValid_A	0	0	391176692	17043590	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.GrantKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.IdxKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.IndexIsCorrect_A	0	0	391176692	17043590	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.LockArbDecision_A	0	0	391176539	17043588	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	391176692	356276886	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	391176692	17043590	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	391176692	17043590	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqImpliesValid_A	0	0	391176692	34087192	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M	0	0	391107693	17043368	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.ValidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A	0	0	391176692	17043590	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckHotOne_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckNGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesReady_A	0	0	391176692	17043664	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A	0	0	391176692	17043664	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A	0	0	391176692	17043664	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A	0	0	391176539	17043588	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A	0	0	391176692	356276812	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A	0	0	391176692	17043664	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A	0	0	391176692	17043664	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A	0	0	391176692	34087340	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M	0	0	391107693	17043368	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A	0	0	391176692	17043664	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckHotOne_A	0	0	391176692	390364170	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.CheckNGreaterZero_A	0	0	1051	1051	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesReady_A	0	0	391176692	15204174	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GntImpliesValid_A	0	0	391176692	15204174	0	0
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.GrantKnown_A	0	0	391176692	390364170	0	0

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	ASSERT	PROPERTIES	SEQUENCES
Total	1053	0	10
Category 0	1053	0	10

	ASSERT	PROPERTIES	SEQUENCES
Total	1053	0	10
Severity 0	1053	0	10

	NUMBER	PERCENT
Total Number	1053	100.00
Uncovered	29	2.75
Success	1024	97.25
Failure	0	0.00
Incomplete	15	1.42
Without Attempts	0	0.00

	NUMBER	PERCENT
Total Number	10	100.00
Uncovered	3	30.00
All Matches	7	70.00
First Matches	7	70.00