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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A	0	0	377741524	376900515	0	0
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_flash_mp.BankEraseData_A	0	0	383420262	8062196	0	0
tb.dut.u_flash_mp.BankEraseInfo_A	0	0	383420262	10421018	0	0
tb.dut.u_flash_mp.DataReqToInfo_A	0	0	383420262	236100395	0	0
tb.dut.u_flash_mp.InReqOutReq_A	0	0	383420262	264266919	0	0
tb.dut.u_flash_mp.InfoReqToData_A	0	0	383420262	28166524	0	0
tb.dut.u_flash_mp.NoReqWhenErr_A	0	0	378046490	127790	0	0
tb.dut.u_flash_mp.bkEraseEnOnehot_A	0	0	383420262	18483214	0	0
tb.dut.u_flash_mp.hwInfoRuleOnehot_A	0	0	383420262	154640043	0	0
tb.dut.u_flash_mp.invalidReqOnehot_A	0	0	383420262	264139094	0	0
tb.dut.u_flash_mp.requestTypesOnehot_A	0	0	383420262	264139094	0	0
tb.dut.u_intr_corr_err.IntrTKind_A	0	0	1058	1058	0	0
tb.dut.u_intr_op_done.IntrTKind_A	0	0	1058	1058	0	0
tb.dut.u_intr_prog_empty.IntrTKind_A	0	0	1058	1058	0	0
tb.dut.u_intr_prog_lvl.IntrTKind_A	0	0	1058	1058	0	0
tb.dut.u_intr_rd_full.IntrTKind_A	0	0	1058	1058	0	0
tb.dut.u_intr_rd_lvl.IntrTKind_A	0	0	1058	1058	0	0
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A	0	0	377718875	376877866	0	0
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	377718875	376845019	0	2619
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A	0	0	377741524	376900515	0	0
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_prog_fifo.DataKnown_A	0	0	383420193	165639076	0	0
tb.dut.u_prog_fifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_prog_fifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_prog_fifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	165639076	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	377741455	376900446	0	0
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	377741455	376900446	0	0
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A	0	0	1058	1058	0	0
tb.dut.u_prog_tl_gate.u_state_regs_A	0	0	383420193	382579184	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1058	1058	0	0
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1058	1058	0	0
tb.dut.u_reg_core.en2addrHit	0	0	385925382	27713367	0	0
tb.dut.u_reg_core.reAfterRv	0	0	385925382	27713347	0	0
tb.dut.u_reg_core.rePulse	0	0	385925382	25321410	0	0
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A	0	0	385925382	385008271	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A	0	0	385925382	385008271	0	0
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.NotOverflowed_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A	0	0	385925313	34119604	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A	0	0	385925313	44864746	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A	0	0	385925313	2178867	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A	0	0	385925313	3648360	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A	0	0	385925313	3765154	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A	0	0	385925313	5028498	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A	0	0	385925313	28113201	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A	0	0	385925313	36187888	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A	0	0	385925313	385008202	0	0
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1273	1273	0	0
tb.dut.u_reg_core.u_socket.maxN	0	0	1273	1273	0	0
tb.dut.u_reg_core.wePulse	0	0	385925382	2391937	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A	0	0	383420262	382579253	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A	0	0	377741524	376900515	0	0
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A	0	0	377741524	376900515	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A	0	0	377741524	376900515	0	0
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A	0	0	377741524	376900515	0	0
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_sw_rd_fifo.DataKnown_A	0	0	383420193	40909607	0	0
tb.dut.u_sw_rd_fifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_sw_rd_fifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_sw_rd_fifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	40909607	0	0
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.TlOutKnownIfFifoKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.TlOutValidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.WeOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DataKnown_A	0	0	383420193	32277222	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	32277222	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty	0	0	383420193	4077604	0	0
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull	0	0	383420193	4077604	0	0
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A	0	0	383420193	33399005	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	33399005	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A	0	0	383420193	5195078	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	5195078	0	0
tb.dut.u_tl_adapter_eflash.u_sram_byte.SramReadbackAndIntg	0	0	1058	1058	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A	0	0	383420193	32277222	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	32277222	0	0
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A	0	0	1058	1058	0	0
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A	0	0	377741455	376900446	0	0
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A	0	0	377741455	376900446	0	0
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A	0	0	1058	1058	0	0
tb.dut.u_tl_gate.u_state_regs_A	0	0	383420193	382579184	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A	0	0	1058	1058	0	0
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.AddrOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.DataIntgOptions_A	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.ReqOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.TlOutKnownIfFifoKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.TlOutValidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.WdataOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.WeOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.WmaskOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A	0	0	383420193	3622784	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	3622784	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1058	1058	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.AddrOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.DataIntgOptions_A	0	0	1058	1058	0	0
tb.dut.u_to_rd_fifo.ReqOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A	0	0	1058	1058	0	0
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A	0	0	1058	1058	0	0
tb.dut.u_to_rd_fifo.TlOutKnownIfFifoKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.TlOutValidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1058	1058	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	383420193	3094268	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	382750936	3088379	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1058	1058	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	383420193	5022283	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	5022283	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1058	1058	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1058	1058	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	383204207	5016290	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	5028394	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1058	1058	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	383420193	3094268	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	383420193	382579184	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	383420193	3094268	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	383420193	0	0	1053
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	383420193	0	0	1053
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	377741455	376867464	0	2769
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	383420193	0	0	1053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	383420193	0	0	1053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	383420193	0	0	1053
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	383420193	0	0	1053
tb.dut.u_flash_hw_if.DisableChk_A	0	0	369098771	5488209	0	43
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	377718875	376845019	0	2619
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	377741524	376867518	0	2769

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	385926029	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	385926029	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	385926029	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	385926029	81703	81703	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	385926029	17	17	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	385926029	7	7	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	385926029	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	385926029	12497	12497	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	385926029	294974	294974	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	385926029	16797920	16797920	1248

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	385926029	81703	81703	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	385926029	17	17	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	385926029	7	7	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	385926029	12	12	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	385926029	12497	12497	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	385926029	294974	294974	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	385926029	16797920	16797920	1248