Assertions
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Assertions by Category
ASSERTPROPERTIESSEQUENCES
Total1055010
Category 01055010

Assertions by Severity
ASSERTPROPERTIESSEQUENCES
Total1055010
Severity 01055010

Summary for Assertions
NUMBERPERCENT
Total Number1055100.00
Uncovered292.75
Success102697.25
Failure00.00
Incomplete151.42
Without Attempts00.00

Summary for Cover Sequences
NUMBERPERCENT
Total Number10100.00
Uncovered330.00
All Matches770.00
First Matches770.00
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ASSERTIONSCATEGORYSEVERITYATTEMPTSREAL SUCCESSESFAILURESINCOMPLETE
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.IdxKnown_A 0036190926736104751000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.IndexIsCorrect_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.LockArbDecision_A 003618886161528284500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0036190926733048166800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqImpliesValid_A 003619092673056584200
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 003618886161528284500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.ValidKnown_A 0036190926736104751000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckHotOne_A 0036190926736104751000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.CheckNGreaterZero_A 001048104800
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesReady_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GntImpliesValid_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.GrantKnown_A 0036190926736104751000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IdxKnown_A 0036190926736104751000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.IndexIsCorrect_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.LockArbDecision_A 003618886161528284500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.NoReadyValidNoGrant_A 0036190926733048174100
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReadyAndValidImplyGrant_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqAndReadyImplyGrant_A 003619092671528288000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqImpliesValid_A 003619092673056576900
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ReqStaysHighUntilGranted0_M 003618886161528284500
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.ValidKnown_A 0036190926736104751000
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.gen_data_port_assertion.DataFlow_A 003619092671528288000
tb.dut.u_flash_hw_if.DisableChk_A 003451806815310034044
tb.dut.u_flash_hw_if.ProgRdVerify_A 00344319397197761700
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckAckNeedsReq 00361909303957100
tb.dut.u_flash_hw_if.u_addr_sync_reqack.SyncReqAckHoldReq 00361816942924200
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckAckNeedsReq 00361909303953200
tb.dut.u_flash_hw_if.u_data_sync_reqack.SyncReqAckHoldReq 00352694296924500
tb.dut.u_flash_hw_if.u_rma_state_regs.AssertConnected_A 001048104800
tb.dut.u_flash_hw_if.u_rma_state_regs_A 0036190930336104754600
tb.dut.u_flash_hw_if.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_flash_hw_if.u_state_regs_A 0036190930336104754600
tb.dut.u_flash_hw_if.u_sync_rma_req.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_flash_hw_if.u_sync_rma_req.OutputsKnown_A 0035562583035476407300
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A 0035562583035473016102745
tb.dut.u_flash_mp.BankEraseData_A 00361909303747267700
tb.dut.u_flash_mp.BankEraseInfo_A 00361909303943776000
tb.dut.u_flash_mp.DataReqToInfo_A 0036190930322136880700
tb.dut.u_flash_mp.InReqOutReq_A 0036190930324764534300
tb.dut.u_flash_mp.InfoReqToData_A 003619093032627653600
tb.dut.u_flash_mp.NoReqWhenErr_A 0035675440413342600
tb.dut.u_flash_mp.bkEraseEnOnehot_A 003619093031691043700
tb.dut.u_flash_mp.hwInfoRuleOnehot_A 0036190930314488285400
tb.dut.u_flash_mp.invalidReqOnehot_A 0036190930324751187100
tb.dut.u_flash_mp.requestTypesOnehot_A 0036190930324751187100
tb.dut.u_intr_corr_err.IntrTKind_A 001048104800
tb.dut.u_intr_op_done.IntrTKind_A 001048104800
tb.dut.u_intr_prog_empty.IntrTKind_A 001048104800
tb.dut.u_intr_prog_lvl.IntrTKind_A 001048104800
tb.dut.u_intr_rd_full.IntrTKind_A 001048104800
tb.dut.u_intr_rd_lvl.IntrTKind_A 001048104800
tb.dut.u_lc_escalation_en_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_lc_escalation_en_sync.OutputsKnown_A 0035560068135473892400
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A 0035560068135470516202595
tb.dut.u_lc_seed_hw_rd_en_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_lc_seed_hw_rd_en_sync.OutputsKnown_A 0035562583035476407300
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A 0035562583035473016102745
tb.dut.u_prog_fifo.DataKnown_A 0036190926715484254800
tb.dut.u_prog_fifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_prog_fifo.DepthKnown_A 0036190926736104751000
tb.dut.u_prog_fifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_prog_fifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_prog_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 0036190926715484254800
tb.dut.u_prog_tl_gate.SizeOutstandingTxn_A 0036190926736104751000
tb.dut.u_prog_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_prog_tl_gate.u_err_en_sync.OutputsKnown_A 0035562579435476403700
tb.dut.u_prog_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0035562579435476403700
tb.dut.u_prog_tl_gate.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_prog_tl_gate.u_state_regs_A 0036190926736104751000
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001048104800
tb.dut.u_prog_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001048104800
tb.dut.u_reg_core.en2addrHit 003645966652631350400
tb.dut.u_reg_core.reAfterRv 003645966652631348300
tb.dut.u_reg_core.rePulse 003645966652391005500
tb.dut.u_reg_core.u_chk.PayLoadWidthCheck 001263126300
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_0.MubiIsNotYetSupported_A 0036459666536364107100
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.CheckSwAccessIsLegal_A 001263126300
tb.dut.u_reg_core.u_mp_bank_cfg_shadowed_erase_en_1.MubiIsNotYetSupported_A 0036459666536364107100
tb.dut.u_reg_core.u_reg_if.AllowedLatency_A 001263126300
tb.dut.u_reg_core.u_reg_if.MatchedWidthAssert 001263126300
tb.dut.u_reg_core.u_reg_if.u_err.dataWidthOnly32_A 001263126300
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.DataWidthCheck_A 001263126300
tb.dut.u_reg_core.u_reg_if.u_rsp_intg_gen.PayLoadWidthCheck 001263126300
tb.dut.u_reg_core.u_rsp_intg_gen.DataWidthCheck_A 001263126300
tb.dut.u_reg_core.u_rsp_intg_gen.PayLoadWidthCheck 001263126300
tb.dut.u_reg_core.u_socket.NotOverflowed_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_A 003645966293266144200
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DataKnown_AKnownEnable 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.DepthKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.RvalidKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.WreadyKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.reqfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_A 003645966294191712700
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DataKnown_AKnownEnable 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.DepthKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.RvalidKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.WreadyKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.fifo_h.rspfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_A 00364596629215779000
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DataKnown_AKnownEnable 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.DepthKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.RvalidKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.WreadyKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_A 00364596629333509700
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DataKnown_AKnownEnable 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.DepthKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.RvalidKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.WreadyKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[0].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_A 00364596629374267100
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DataKnown_AKnownEnable 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.DepthKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.RvalidKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.WreadyKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_A 00364596629469403400
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DataKnown_AKnownEnable 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.DepthKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.RvalidKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.WreadyKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[1].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_A 003645966292669597900
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DataKnown_AKnownEnable 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.DepthKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.RvalidKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.WreadyKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.reqfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_A 003645966293388799600
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DataKnown_AKnownEnable 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.DepthKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.RvalidKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.WreadyKnown_A 0036459662936364103500
tb.dut.u_reg_core.u_socket.gen_dfifo[2].fifo_d.rspfifo.gen_passthru_fifo.paramCheckPass 001263126300
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.DataWidthCheck_A 001263126300
tb.dut.u_reg_core.u_socket.gen_err_resp.err_resp.u_intg_gen.PayLoadWidthCheck 001263126300
tb.dut.u_reg_core.u_socket.maxN 001263126300
tb.dut.u_reg_core.wePulse 00364596665240342800
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A 001048104800
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A 001048104800
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A 001048104800
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[0].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.InfoNoBiggerThanData_A 001048104800
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[0].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.InfoNoBiggerThanData_A 001048104800
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[1].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.InfoNoBiggerThanData_A 001048104800
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_creator_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.gen_info_priv_bank[1].gen_info_priv_type[2].u_info_cfg.u_owner_mubi.OutputsKnown_A 0036190930336104754600
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.OutputsKnown_A 0035562583035476407300
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0035562583035473016102745
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.OutputsKnown_A 0035562583035476407300
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A 0035562583035473016102745
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.OutputsKnown_A 0035562583035476407300
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A 0035562583035473016102745
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.OutputsKnown_A 0035562583035476407300
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A 0035562583035473016102745
tb.dut.u_sw_rd_fifo.DataKnown_A 003619092673816805600
tb.dut.u_sw_rd_fifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_sw_rd_fifo.DepthKnown_A 0036190926736104751000
tb.dut.u_sw_rd_fifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_sw_rd_fifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_sw_rd_fifo.gen_normal_fifo.depthShallNotExceedParamDepth 003619092673816805600
tb.dut.u_tl_adapter_eflash.AddrOutKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.DataIntgOptions_A 001048104800
tb.dut.u_tl_adapter_eflash.ReqOutKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.SramDwHasByteGranularity_A 001048104800
tb.dut.u_tl_adapter_eflash.SramDwIsMultipleOfTlulWidth_A 001048104800
tb.dut.u_tl_adapter_eflash.TlOutKnownIfFifoKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.TlOutValidKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.WdataOutKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.WeOutKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.WmaskOutKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.adapterNoReadOrWrite 001048104800
tb.dut.u_tl_adapter_eflash.gen_cmd_intg_check.u_cmd_intg_chk.PayLoadWidthCheck 001048104800
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DataKnown_A 003619092673188516200
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.DepthKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.gen_data_xor_addr_fifo.u_sramreqaddrfifo.gen_normal_fifo.depthShallNotExceedParamDepth 003619092673188516200
tb.dut.u_tl_adapter_eflash.rvalidHighReqFifoEmpty 00361909267401932300
tb.dut.u_tl_adapter_eflash.rvalidHighWhenRspFifoFull 00361909267401932300
tb.dut.u_tl_adapter_eflash.u_err.dataWidthOnly32_A 001048104800
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_A 003619092673313293200
tb.dut.u_tl_adapter_eflash.u_reqfifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_reqfifo.DepthKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_reqfifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_reqfifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 003619092673313293200
tb.dut.u_tl_adapter_eflash.u_rsp_gen.DataWidthCheck_A 001048104800
tb.dut.u_tl_adapter_eflash.u_rsp_gen.PayLoadWidthCheck 001048104800
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_A 00361909267526247300
tb.dut.u_tl_adapter_eflash.u_rspfifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_rspfifo.DepthKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_rspfifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_rspfifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00361909267526247300
tb.dut.u_tl_adapter_eflash.u_sram_byte.SramReadbackAndIntg 001048104800
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_A 003619092673188516200
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.DepthKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_tl_adapter_eflash.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 003619092673188516200
tb.dut.u_tl_gate.SizeOutstandingTxn_A 0036190926736104751000
tb.dut.u_tl_gate.u_err_en_sync.NumCopiesMustBeGreaterZero_A 001048104800
tb.dut.u_tl_gate.u_err_en_sync.OutputsKnown_A 0035562579435476403700
tb.dut.u_tl_gate.u_err_en_sync.gen_no_flops.OutputDelay_A 0035562579435476403700
tb.dut.u_tl_gate.u_state_regs.AssertConnected_A 001048104800
tb.dut.u_tl_gate.u_state_regs_A 0036190926736104751000
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.DataWidthCheck_A 001048104800
tb.dut.u_tl_gate.u_tlul_err_resp.u_intg_gen.PayLoadWidthCheck 001048104800
tb.dut.u_to_prog_fifo.AddrOutKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.DataIntgOptions_A 001048104800
tb.dut.u_to_prog_fifo.ReqOutKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.SramDwHasByteGranularity_A 001048104800
tb.dut.u_to_prog_fifo.SramDwIsMultipleOfTlulWidth_A 001048104800
tb.dut.u_to_prog_fifo.TlOutKnownIfFifoKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.TlOutValidKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.WdataOutKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.WeOutKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.WmaskOutKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.adapterNoReadOrWrite 001048104800
tb.dut.u_to_prog_fifo.u_err.dataWidthOnly32_A 001048104800
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_A 00361909267328624000
tb.dut.u_to_prog_fifo.u_reqfifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_to_prog_fifo.u_reqfifo.DepthKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.u_reqfifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.u_reqfifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth 00361909267328624000
tb.dut.u_to_prog_fifo.u_rsp_gen.DataWidthCheck_A 001048104800
tb.dut.u_to_prog_fifo.u_rsp_gen.PayLoadWidthCheck 001048104800
tb.dut.u_to_prog_fifo.u_rspfifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_to_prog_fifo.u_rspfifo.DepthKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.u_rspfifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.u_rspfifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.u_sram_byte.SramReadbackAndIntg 001048104800
tb.dut.u_to_prog_fifo.u_sramreqfifo.DataKnown_AKnownEnable 0036190926736104751000
tb.dut.u_to_prog_fifo.u_sramreqfifo.DepthKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.u_sramreqfifo.RvalidKnown_A 0036190926736104751000
tb.dut.u_to_prog_fifo.u_sramreqfifo.WreadyKnown_A 0036190926736104751000
tb.dut.u_to_rd_fifo.AddrOutKnown_A 0036190926736104751000
tb.dut.u_to_rd_fifo.DataIntgOptions_A 001048104800
tb.dut.u_to_rd_fifo.ReqOutKnown_A 0036190926736104751000
tb.dut.u_to_rd_fifo.SramDwHasByteGranularity_A 001048104800
tb.dut.u_to_rd_fifo.SramDwIsMultipleOfTlulWidth_A 001048104800
tb.dut.u_to_rd_fifo.TlOutKnownIfFifoKnown_A 0036190926736104751000
tb.dut.u_to_rd_fifo.TlOutValidKnown_A 0036190926736104751000
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