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ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE
tb.dut.u_to_rd_fifo.WdataOutKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.WeOutKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.WmaskOutKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.adapterNoReadOrWrite	0	0	1048	1048	0	0
tb.dut.u_to_rd_fifo.rvalidHighReqFifoEmpty	0	0	361909267	3113131	0	0
tb.dut.u_to_rd_fifo.rvalidHighWhenRspFifoFull	0	0	361184231	3106667	0	0
tb.dut.u_to_rd_fifo.u_err.dataWidthOnly32_A	0	0	1048	1048	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_A	0	0	361909267	4687481	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DataKnown_AKnownEnable	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.DepthKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.RvalidKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.WreadyKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_reqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361909267	4687481	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.DataWidthCheck_A	0	0	1048	1048	0	0
tb.dut.u_to_rd_fifo.u_rsp_gen.PayLoadWidthCheck	0	0	1048	1048	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_A	0	0	361651110	4671701	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DataKnown_AKnownEnable	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.DepthKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.RvalidKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.WreadyKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_rspfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361909267	4687481	0	0
tb.dut.u_to_rd_fifo.u_sram_byte.SramReadbackAndIntg	0	0	1048	1048	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_A	0	0	361909267	3113131	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DataKnown_AKnownEnable	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.DepthKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.RvalidKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.WreadyKnown_A	0	0	361909267	361047510	0	0
tb.dut.u_to_rd_fifo.u_sramreqfifo.gen_normal_fifo.depthShallNotExceedParamDepth	0	0	361909267	3113131	0	0

Assertions Incomplete:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_eflash.gen_flash_cores[0].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	361909267	0	0	1045
tb.dut.u_eflash.gen_flash_cores[1].u_core.u_rd.u_valid_random.RoundRobin_A	0	0	361909267	0	0	1045
tb.dut.u_eflash.u_lc_nvm_debug_en_sync.gen_flops.OutputDelay_A	0	0	355625794	354730134	0	2745
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	361909267	0	0	1045
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_calc.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	361909267	0	0	1045
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[0].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	361909267	0	0	1045
tb.dut.u_eflash.u_scramble.u_prim_arbiter_tree_op.gen_input_bufs[1].gen_rr_arbiter.u_arb.RoundRobin_A	0	0	361909267	0	0	1045
tb.dut.u_flash_hw_if.DisableChk_A	0	0	345180681	5310034	0	44
tb.dut.u_flash_hw_if.u_sync_rma_req.gen_flops.OutputDelay_A	0	0	355625830	354730161	0	2745
tb.dut.u_lc_escalation_en_sync.gen_flops.OutputDelay_A	0	0	355600681	354705162	0	2595
tb.dut.u_lc_seed_hw_rd_en_sync.gen_flops.OutputDelay_A	0	0	355625830	354730161	0	2745
tb.dut.u_region_cfg.u_lc_creator_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	355625830	354730161	0	2745
tb.dut.u_region_cfg.u_lc_iso_part_sw_rd_en_sync.gen_flops.OutputDelay_A	0	0	355625830	354730161	0	2745
tb.dut.u_region_cfg.u_lc_iso_part_sw_wr_en_sync.gen_flops.OutputDelay_A	0	0	355625830	354730161	0	2745
tb.dut.u_region_cfg.u_lc_owner_seed_sw_rw_en_sync.gen_flops.OutputDelay_A	0	0	355625830	354730161	0	2745

---

Detail Report for Cover Sequences

Cover Sequences Uncovered:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C	0	0	364597328	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C	0	0	364597328	0	0	0
tb.dut.tlul_assert_device.gen_device_cov.a_sizeChangedNotAccepted_C	0	0	364597328	0	0	0

Cover Sequences All Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	364597328	65355	65355	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	364597328	10	10	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	364597328	3	3	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	364597328	3	3	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	364597328	11230	11230	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	364597328	264905	264905	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	364597328	19312302	19312302	1240

Cover Sequences First Matches:

COVER SEQUENCES	CATEGORY	SEVERITY	ATTEMPTS	ALL MATCHES	FIRST MATCHES	INCOMPLETE	SRC
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C	0	0	364597328	65355	65355	0
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C	0	0	364597328	10	10	0
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C	0	0	364597328	3	3	0
tb.dut.tlul_assert_device.gen_device_cov.a_sourceChangedNotAccepted_C	0	0	364597328	3	3	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReqWithSameAddr_C	0	0	364597328	11230	11230	0
tb.dut.tlul_assert_device.gen_device_cov.b2bReq_C	0	0	364597328	264905	264905	0
tb.dut.tlul_assert_device.gen_device_cov.b2bSameSource_C	0	0	364597328	19312302	19312302	1240