PWRMGR Simulation Results

Wednesday December 27 2023 20:02:24 UTC

GitHub Revision: 0c759b93ab

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 85416116840666724748485424200434981761468351851988553961117902923833034512693

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.730s	62.406us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.630s	22.923us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.750s	19.653us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.380s	290.341us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.010s	51.753us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.340s	72.471us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.750s	19.653us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	51.753us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	1.580s	262.533us	50	50	100.00
V2	control_clks	pwrmgr_wakeup	1.580s	262.533us	50	50	100.00
V2	aborted_low_power	pwrmgr_aborted_low_power	0.800s	110.410us	50	50	100.00
		pwrmgr_lowpower_invalid	0.750s	53.959us	49	50	98.00
V2	reset	pwrmgr_reset	1.340s	82.791us	50	50	100.00
		pwrmgr_reset_invalid	1.050s	100.900us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	1.340s	82.791us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	1.600s	240.112us	50	50	100.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	1.670s	281.313us	50	50	100.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.930s	68.527us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	10.560s	2.584ms	50	50	100.00
V2	intr_test	pwrmgr_intr_test	0.640s	18.873us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	2.490s	136.562us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	2.490s	136.562us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.630s	22.923us	5	5	100.00
		pwrmgr_csr_rw	0.750s	19.653us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	51.753us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	44.192us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.630s	22.923us	5	5	100.00
		pwrmgr_csr_rw	0.750s	19.653us	20	20	100.00
		pwrmgr_csr_aliasing	1.010s	51.753us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.990s	44.192us	20	20	100.00
V2		TOTAL			539	540	99.81
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.710s	212.798us	20	20	100.00
		pwrmgr_sec_cm	2.020s	669.570us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.020s	669.570us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.020s	669.570us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.710s	212.798us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	4.100s	784.893us	50	50	100.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	4.120s	860.495us	50	50	100.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.950s	67.363us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.700s	29.875us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.020s	669.570us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.020s	669.570us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.020s	669.570us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	43.550us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.780s	54.149us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	1.690s	272.802us	50	50	100.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.750s	19.653us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.750s	19.653us	20	20	100.00
V2S		TOTAL			375	375	100.00
V3	escalation_timeout	pwrmgr_escalation_timeout	1.720s	1.385ms	2	50	4.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	48.390s	14.732ms	49	50	98.00
V3		TOTAL			51	100	51.00
		TOTAL			1070	1120	95.54

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	11	91.67
V2S	9	9	9	100.00
V3	2	2	0	0.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.94	98.22	96.58	99.44	96.00	96.32	100.00	99.02

Failure Buckets

• UVM_ERROR (cip_base_scoreboard.sv:287) scoreboard [scoreboard] alert fatal_fault did not trigger max_delay:* has 36 failures:

  • Test pwrmgr_escalation_timeout has 36 failures.

    • 2.pwrmgr_escalation_timeout.41834778420218322556610818649993985865483073202546845056262013932256435713396
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @  13792743 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
        UVM_INFO @  13792743 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 3.pwrmgr_escalation_timeout.28907822747517316544192366482064864004696042772946711504783483634618408396700
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest/run.log

        UVM_ERROR @  43763430 ps: (cip_base_scoreboard.sv:287) uvm_test_top.env.scoreboard [uvm_test_top.env.scoreboard] alert fatal_fault did not trigger max_delay:500
        UVM_INFO @  43763430 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 34 more failures.

• UVM_FATAL (pwrmgr_escalation_timeout_vseq.sv:30) [pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable has 12 failures:

  • Test pwrmgr_escalation_timeout has 12 failures.

    • 0.pwrmgr_escalation_timeout.61481900010376186598593974343963992215518469903319532682281596438426404741413
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 842552990 ps: (pwrmgr_escalation_timeout_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 842552990 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.pwrmgr_escalation_timeout.62390574420434902892070603378929711732902325639610583775910341061310559421149
      Line 248, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest/run.log

        UVM_FATAL @ 2515425276 ps: (pwrmgr_escalation_timeout_vseq.sv:30) [uvm_test_top.env.virtual_sequencer.pwrmgr_escalation_timeout_vseq] Timeout waiting for cpu fetch disable
        UVM_INFO @ 2515425276 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 10 more failures.

• UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:

  • Test pwrmgr_lowpower_invalid has 1 failures.

    • 3.pwrmgr_lowpower_invalid.91137660188339608439358870997571445416828400997671686726029561122127803448000
      Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest/run.log

        UVM_FATAL @  34161546 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
        UVM_INFO @  34161546 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (* [*] vs * [*]) Regname: pwrmgr_reg_block.wake_status reset value: * wake_status has 1 failures:

  • Test pwrmgr_stress_all_with_rand_reset has 1 failures.

    • 23.pwrmgr_stress_all_with_rand_reset.45041053669528306687954410638616470349180366990924714941323012445389373010538
      Line 1070, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest/run.log

        UVM_ERROR @ 3377253492 ps: (csr_utils_pkg.sv:457) [csr_utils::csr_rd_check] Check failed obs == exp (1 [0x1] vs 3 [0x3]) Regname: pwrmgr_reg_block.wake_status reset value: 0x0 wake_status
        UVM_INFO @ 3377253492 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

Past Results

• Latest
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• dv
• 2023.12.25_01.42.52
• 2023.12.21_00.37.45
• 2023.11.23_02.28.43
• 2023.11.02_04.00.32
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