Unified Coverage Report :: Module :: prim_sec_anchor_buf

Module : prim_sec_anchor_buf

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_sec_anchor_0.1/rtl/prim_sec_anchor_buf.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf
tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf
tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sync_rom_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sync_rom_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sync_rom_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl.gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_sync_rom_ctrl

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_prim_lc_sync_dft_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_prim_lc_sync_dft_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_prim_lc_sync_dft_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync_dft_en.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_prim_lc_sync_dft_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[0].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_prim_lc_sync_hw_debug_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[1].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_prim_lc_sync_hw_debug_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[2].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_prim_lc_sync_hw_debug_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00

---

Module Instance : tb.dut.u_prim_lc_sync_hw_debug_en.gen_buffs[0].gen_bits[3].u_prim_buf

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00						u_prim_lc_sync_hw_debug_en

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_secure_anchor_buf	0.00	0.00