Unified Coverage Report :: Module :: prim_mubi4_sync

Module : prim_mubi4_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_cdc.u_sync_rom_ctrl	0.00	0.00	0.00			0.00

---

Module Instance : tb.dut.u_cdc.u_sync_rom_ctrl

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
0.00	0.00	0.00			0.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
0.00	0.00	0.00			0.00		u_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_buffs[0].gen_bits[0].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[1].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[2].u_prim_buf	0.00	0.00
gen_buffs[0].gen_bits[3].u_prim_buf	0.00	0.00
gen_flops.gen_stable_chks.gen_bufs_muxes[0].u_sig_unstable_buf	0.00	0.00
gen_flops.gen_stable_chks.gen_bufs_muxes[1].u_sig_unstable_buf	0.00	0.00
gen_flops.gen_stable_chks.gen_bufs_muxes[2].u_sig_unstable_buf	0.00	0.00
gen_flops.gen_stable_chks.gen_bufs_muxes[3].u_sig_unstable_buf	0.00	0.00
gen_flops.gen_stable_chks.u_mubi_xor	0.00	0.00
gen_flops.gen_stable_chks.u_prim_flop_3rd_stage	0.00	0.00				0.00
gen_flops.u_prim_flop_2sync	0.00	0.00				0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
TOTAL		6	0	0.00
CONT_ASSIGN	96	1	0	0.00
CONT_ASSIGN	96	1	0	0.00
CONT_ASSIGN	96	1	0	0.00
CONT_ASSIGN	96	1	0	0.00
ALWAYS	117	1	0	0.00
CONT_ASSIGN	168	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
96	0	4
117	0	1
168	0	1

---

Cond Coverage for Module : prim_mubi4_sync

	Total	Covered	Percent
Conditions	8	0	0.00
Logical	8	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[0] : gen_flops.gen_stable_chks.mubi_q[0])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[1] : gen_flops.gen_stable_chks.mubi_q[1])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[2] : gen_flops.gen_stable_chks.mubi_q[2])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       96
 EXPRESSION (((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? gen_flops.gen_stable_chks.reset_value[3] : gen_flops.gen_stable_chks.mubi_q[3])
             --------------------------------1--------------------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

---

Branch Coverage for Module : prim_mubi4_sync

	Line No.	Total	Covered	Percent
Branches		8	0	0.00
TERNARY	96	2	0	0.00
TERNARY	96	2	0	0.00
TERNARY	96	2	0	0.00
TERNARY	96	2	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv' or '../src/lowrisc_prim_mubi_0.1/rtl/prim_mubi4_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[0].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[1].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[2].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered

	LineNo.	Expression
-1-:	96	((|gen_flops.gen_stable_chks.gen_bufs_muxes[3].sig_unstable_buf)) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Not Covered