Unified Coverage Report :: Module :: pwrmgr_csr_assert_fpv

Module : pwrmgr_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_pwrmgr_csr_assert_0/pwrmgr_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.pwrmgr_csr_assert	100.00						100.00

---

Module Instance : tb.dut.pwrmgr_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
20.42	0.00	0.00	81.69		0.00		dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : pwrmgr_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	7	7	100.00	7	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	7	7	100.00	7	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	589627	14758	0	0
intr_enable_rd_A	589627	1669	0	0
reset_en_rd_A	589627	1594	0	0
reset_en_regwen_rd_A	589627	1449	0	0
wake_info_capture_dis_rd_A	589627	1590	0	0
wakeup_en_rd_A	589627	1993	0	0
wakeup_en_regwen_rd_A	589627	1550	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589627	14758	0	0
T2	5301	417	0	0
T3	888	0	0	0
T4	4766	6	0	0
T5	3280	62	0	0
T6	0	4	0	0
T7	5044	294	0	0
T8	2118	0	0	0
T9	1611	0	0	0
T12	1092	0	0	0
T13	1442	0	0	0
T14	0	894	0	0
T15	0	126	0	0
T16	0	588	0	0
T17	0	56	0	0
T18	0	135	0	0
T21	1329	0	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589627	1669	0	0
T1	1075	15	0	0
T2	5301	0	0	0
T3	888	0	0	0
T4	4766	0	0	0
T5	3280	0	0	0
T7	5044	0	0	0
T8	2118	0	0	0
T9	1611	0	0	0
T10	0	7	0	0
T12	1092	0	0	0
T13	1442	13	0	0
T17	0	13	0	0
T19	0	9	0	0
T24	0	7	0	0
T43	0	441	0	0
T44	0	1	0	0
T50	0	7	0	0
T59	0	5	0	0

reset_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589627	1594	0	0
T1	1075	7	0	0
T2	5301	0	0	0
T3	888	0	0	0
T4	4766	0	0	0
T5	3280	0	0	0
T7	5044	0	0	0
T8	2118	0	0	0
T9	1611	0	0	0
T12	1092	0	0	0
T13	1442	8	0	0
T17	0	30	0	0
T19	0	5	0	0
T24	0	6	0	0
T29	0	160	0	0
T43	0	414	0	0
T50	0	29	0	0
T60	0	8	0	0
T61	0	4	0	0

reset_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589627	1449	0	0
T1	1075	5	0	0
T2	5301	0	0	0
T3	888	0	0	0
T4	4766	0	0	0
T5	3280	0	0	0
T7	5044	0	0	0
T8	2118	0	0	0
T9	1611	0	0	0
T12	1092	0	0	0
T13	1442	0	0	0
T17	0	23	0	0
T19	0	8	0	0
T29	0	112	0	0
T43	0	407	0	0
T50	0	18	0	0
T60	0	30	0	0
T62	0	9	0	0
T63	0	8	0	0
T64	0	17	0	0

wake_info_capture_dis_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589627	1590	0	0
T1	1075	5	0	0
T2	5301	0	0	0
T3	888	0	0	0
T4	4766	0	0	0
T5	3280	0	0	0
T7	5044	0	0	0
T8	2118	0	0	0
T9	1611	0	0	0
T12	1092	0	0	0
T13	1442	8	0	0
T17	0	28	0	0
T24	0	4	0	0
T29	0	115	0	0
T43	0	437	0	0
T50	0	37	0	0
T60	0	37	0	0
T61	0	3	0	0
T62	0	9	0	0

wakeup_en_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589627	1993	0	0
T6	8430	0	0	0
T10	1580	0	0	0
T11	1338	0	0	0
T13	1442	28	0	0
T14	4134	0	0	0
T15	1436	0	0	0
T17	0	47	0	0
T19	0	4	0	0
T21	1329	0	0	0
T24	0	2	0	0
T29	0	146	0	0
T43	0	447	0	0
T45	1366	0	0	0
T48	757	0	0	0
T49	681	0	0	0
T50	0	25	0	0
T61	0	2	0	0
T62	0	16	0	0
T63	0	25	0	0

wakeup_en_regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	589627	1550	0	0
T1	1075	1	0	0
T2	5301	0	0	0
T3	888	0	0	0
T4	4766	0	0	0
T5	3280	0	0	0
T7	5044	0	0	0
T8	2118	0	0	0
T9	1611	0	0	0
T12	1092	0	0	0
T13	1442	8	0	0
T17	0	7	0	0
T29	0	127	0	0
T43	0	471	0	0
T50	0	39	0	0
T60	0	12	0	0
T61	0	5	0	0
T62	0	7	0	0
T63	0	22	0	0