Unified Coverage Report :: Module :: pwrmgr

Module : pwrmgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
20.42	0.00	0.00	81.69		0.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut	20.42	0.00	0.00	81.69		0.00

---

Module Instance : tb.dut

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
20.42	0.00	0.00	81.69		0.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
54.40	42.44	64.05	77.73	0.00	42.18	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
							tb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	100.00			100.00
i_wake_info	0.00	0.00	0.00			0.00
intr_wakeup	0.00	0.00	0.00			0.00
pwrmgr_clock_enables_sva_if	0.00	0.00	0.00
pwrmgr_csr_assert	100.00						100.00
pwrmgr_rstmgr_sva_if	0.00	0.00	0.00
pwrmgr_sec_cm_checker_assert	0.00	0.00	0.00
tlul_assert_device	33.33	0.00				0.00	100.00
u_cdc	0.00	0.00	0.00			0.00
u_esc_clk_buf	0.00	0.00
u_esc_rst_buf	0.00	0.00
u_esc_rx	0.00			0.00
u_esc_timeout	0.00	0.00	0.00			0.00
u_esc_timeout_sync	0.00	0.00				0.00
u_fsm	0.00	0.00	0.00		0.00	0.00
u_ndm_sync	0.00	0.00				0.00
u_prim_lc_sync_dft_en	0.00	0.00				0.00
u_prim_lc_sync_hw_debug_en	0.00	0.00				0.00
u_reg	95.31	95.83	96.56	92.45		91.70	100.00
u_slow_fsm	0.00	0.00	0.00		0.00	0.00
u_sw_req_buf	0.00	0.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : pwrmgr

	Line No.	Total	Covered	Percent
TOTAL		46	0	0.00
CONT_ASSIGN	108	1	0	0.00
CONT_ASSIGN	116	1	0	0.00
CONT_ASSIGN	117	1	0	0.00
ALWAYS	178	4	0	0.00
ALWAYS	213	4	0	0.00
CONT_ASSIGN	228	1	0	0.00
CONT_ASSIGN	229	1	0	0.00
CONT_ASSIGN	230	1	0	0.00
CONT_ASSIGN	232	1	0	0.00
CONT_ASSIGN	233	1	0	0.00
CONT_ASSIGN	246	1	0	0.00
CONT_ASSIGN	334	1	0	0.00
ALWAYS	337	6	0	0.00
CONT_ASSIGN	346	1	0	0.00
CONT_ASSIGN	348	1	0	0.00
CONT_ASSIGN	350	1	0	0.00
CONT_ASSIGN	357	1	0	0.00
CONT_ASSIGN	358	1	0	0.00
CONT_ASSIGN	372	1	0	0.00
CONT_ASSIGN	377	1	0	0.00
CONT_ASSIGN	475	1	0	0.00
CONT_ASSIGN	500	1	0	0.00
CONT_ASSIGN	504	1	0	0.00
CONT_ASSIGN	512	1	0	0.00
CONT_ASSIGN	512	1	0	0.00
CONT_ASSIGN	512	1	0	0.00
CONT_ASSIGN	512	1	0	0.00
CONT_ASSIGN	512	1	0	0.00
CONT_ASSIGN	512	1	0	0.00
CONT_ASSIGN	517	1	0	0.00
CONT_ASSIGN	517	1	0	0.00
CONT_ASSIGN	521	1	0	0.00
CONT_ASSIGN	578	1	0	0.00
CONT_ASSIGN	651	1	0	0.00
CONT_ASSIGN	655	1	0	0.00
CONT_ASSIGN	712	0	0
ALWAYS	716	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
108	0	1
116	0	1
117	0	1
178	0	1
179	0	1
180	0	1
182	0	1
			==> MISSING_ELSE
213	0	1
214	0	1
215	0	1
217	0	1
			==> MISSING_ELSE
228	0	1
229	0	1
230	0	1
232	0	1
233	0	1
246	0	1
334	0	1
337	0	1
338	0	1
339	0	1
340	0	1
341	0	1
342	0	1
			==> MISSING_ELSE
346	0	1
348	0	1
350	0	1
357	0	1
358	0	1
372	0	1
377	0	1
475	0	1
500	0	1
504	0	1
512	0	6
517	0	2
521	0	1
578	0	1
651	0	1
655	0	1
712		unreachable
716		unreachable
717		unreachable
719		unreachable

---

Cond Coverage for Module : pwrmgr

	Total	Covered	Percent
Conditions	31	0	0.00
Logical	31	0	0.00
Non-Logical	0	0
Event	0	0

 LINE       232
 EXPRESSION (esc_rst_req_q | esc_timeout_lc_q)
             ------1------   --------2-------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       339
 EXPRESSION (((!lowpwr_cfg_wen)) && (clr_cfg_lock || wkup))
             ---------1---------    -----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       339
 SUB-EXPRESSION (clr_cfg_lock || wkup)
                 ------1-----    --2-

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       358
 EXPRESSION (peri_reqs_masked.rstreqs[pwrmgr_reg_pkg::ResetMainPwrIdx] | reg2hw.fault_status.main_pd_glitch.q)
             ----------------------------1----------------------------   ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Not Covered
0	1	Not Covered
1	0	Not Covered

 LINE       372
 SUB-EXPRESSION (reg2hw.alert_test.q & reg2hw.alert_test.qe)
                 ---------1---------   ----------2---------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       377
 EXPRESSION (reg2hw.fault_status.reg_intg_err.q | reg2hw.fault_status.esc_timeout.q | reg2hw.fault_status.main_pd_glitch.q)
             -----------------1----------------   ----------------2----------------   ------------------3-----------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

 LINE       401
 EXPRESSION (reg2hw.cfg_cdc_sync.qe & reg2hw.cfg_cdc_sync.q)
             -----------1----------   ----------2----------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       578
 EXPRESSION (reg2hw.control.low_power_hint.q == LowPower)
            ----------------------1----------------------

-1-	Status	Tests
0	Not Covered
1	Not Covered

 LINE       580
 EXPRESSION (core_sleeping & low_power_hint)
             ------1------   -------2------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Not Covered
1	1	Not Covered

 LINE       651
 EXPRESSION (reg2hw.wake_info.abort.qe | reg2hw.wake_info.fall_through.qe | reg2hw.wake_info.reasons.qe)
             ------------1------------   ----------------2---------------   -------------3-------------

-1-	-2-	-3-	Status	Tests
0	0	0	Not Covered
0	0	1	Not Covered
0	1	0	Not Covered
1	0	0	Not Covered

---

Toggle Coverage for Module : pwrmgr

	Total	Covered	Percent
Totals	81	59	72.84
Total Bits	508	415	81.69
Total Bits 0->1	254	208	81.89
Total Bits 1->0	254	207	81.50

Ports	81	59	72.84
Port Bits	508	415	81.69
Port Bits 0->1	254	208	81.89
Port Bits 1->0	254	207	81.50

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_slow_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_slow_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
rst_main_ni	No	No		No		INPUT
clk_lc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_lc_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
clk_esc_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_esc_ni	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T7	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31:0]	Yes	Yes	T1,T2,T7	Yes	T1,T2,T7	INPUT
tl_i.a_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	Yes	Yes	T2,T7,T4	Yes	T2,T7,T4	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T1,T3,T8	Yes	T1,T3,T8	OUTPUT
tl_o.d_user.rsp_intg[5:0]	Yes	Yes	*T1,T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_source[7:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T3,T8,T4	Yes	T3,T8,T4	INPUT
alert_rx_i[0].ping_n	Unreachable	Unreachable		Unreachable		INPUT
alert_rx_i[0].ping_p	Unreachable	Unreachable		Unreachable		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T3,T8,T4	Yes	T3,T8,T4	OUTPUT
pwr_ast_i.main_pok	No	No		Yes	T1,T2,T3	INPUT
pwr_ast_i.usb_clk_val	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_ast_i.io_clk_val	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_ast_i.core_clk_val	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_ast_i.slow_clk_val	No	No		No		INPUT
pwr_ast_o.usb_clk_en	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.io_clk_en	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.core_clk_en	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
pwr_ast_o.slow_clk_en	No	No		No		OUTPUT
pwr_ast_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwr_ast_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwr_ast_o.main_pd_n	No	No		No		OUTPUT
pwr_rst_i.rst_sys_src_n[1:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_rst_i.rst_lc_src_n[1:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_rst_o.reset_cause[1:0]	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwr_rst_o.rstreqs[4:0]	No	No		No		OUTPUT
pwr_rst_o.rst_sys_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwr_rst_o.rst_lc_req[1:0]	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwr_clk_o.usb_ip_clk_en	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.io_ip_clk_en	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
pwr_clk_o.main_ip_clk_en	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
pwr_clk_i.usb_status	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_clk_i.io_status	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_clk_i.main_status	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwr_otp_i.otp_idle	No	No		No		INPUT
pwr_otp_i.otp_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_otp_o.otp_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_lc_i.lc_idle	No	No		No		INPUT
pwr_lc_i.lc_done	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pwr_lc_o.lc_init	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
pwr_flash_i.flash_idle	No	No		No		INPUT
pwr_cpu_i.core_sleeping	No	No		No		INPUT
fetch_en_o[3:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
lc_hw_debug_en_i[3:0]	No	No		No		INPUT
lc_dft_en_i[3:0]	No	No		No		INPUT
wakeups_i[5:0]	No	No		No		INPUT
rstreqs_i[1:0]	No	No		No		INPUT
ndmreset_req_i	No	No		No		INPUT
strap_o	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
low_power_o	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
rom_ctrl_i.good[3:0]	No	No		No		INPUT
rom_ctrl_i.done[3:0]	No	No		No		INPUT
sw_rst_req_i[3:0]	No	No		No		INPUT
esc_rst_tx_i.esc_n	No	No		No		INPUT
esc_rst_tx_i.esc_p	No	No		No		INPUT
esc_rst_rx_o.resp_n	No	No		No		OUTPUT
esc_rst_rx_o.resp_p	No	No		No		OUTPUT
intr_wakeup_o	Yes	Yes	T9,T10,T11	Yes	T9,T10,T11	OUTPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Module : pwrmgr

	Line No.	Total	Covered	Percent
Branches		10	0	0.00
IF	178	3	0	0.00
IF	213	3	0	0.00
IF	337	4	0	0.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv' or '../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	178	if ((!rst_lc_n))
-2-:	180	if (esc_rst_req_d)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	213	if ((!rst_lc_n))
-2-:	215	if (esc_timeout_lc_d)

Branches:

-1-	-2-	Status	Tests
1	-	Not Covered
0	1	Not Covered
0	0	Not Covered

	LineNo.	Expression
-1-:	337	if ((!rst_ni))
-2-:	339	if (((!lowpwr_cfg_wen) && (clr_cfg_lock || wkup)))
-3-:	341	if (low_power_hint)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Not Covered
0	0	0	Not Covered