c8985d6745| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.720s | 33.228us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.700s | 34.731us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.750s | 21.064us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.250s | 282.477us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 1.000s | 42.474us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.430s | 51.496us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.750s | 21.064us | 20 | 20 | 100.00 |
| pwrmgr_csr_aliasing | 1.000s | 42.474us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | wakeup | pwrmgr_wakeup | 0.820s | 95.308us | 6 | 50 | 12.00 |
| V2 | control_clks | pwrmgr_wakeup | 0.820s | 95.308us | 6 | 50 | 12.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 1.150s | 36.803us | 50 | 50 | 100.00 |
| pwrmgr_lowpower_invalid | 0.770s | 45.113us | 48 | 50 | 96.00 | ||
| V2 | reset | pwrmgr_reset | 0.910s | 82.924us | 50 | 50 | 100.00 |
| pwrmgr_reset_invalid | 1.090s | 108.996us | 50 | 50 | 100.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 0.910s | 82.924us | 50 | 50 | 100.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 0.700s | 40.591us | 1 | 50 | 2.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 0.990s | 109.250us | 6 | 50 | 12.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.850s | 58.564us | 50 | 50 | 100.00 |
| V2 | stress_all | pwrmgr_stress_all | 1.440s | 200.632us | 5 | 50 | 10.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.670s | 20.274us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.560s | 121.706us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.560s | 121.706us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.700s | 34.731us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.750s | 21.064us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.000s | 42.474us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.890s | 45.974us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.700s | 34.731us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.750s | 21.064us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.000s | 42.474us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.890s | 45.974us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 356 | 540 | 65.93 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.660s | 199.188us | 20 | 20 | 100.00 |
| pwrmgr_sec_cm | 1.490s | 341.407us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 1.490s | 341.407us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 1.490s | 341.407us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.660s | 199.188us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 0.800s | 86.968us | 0 | 50 | 0.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 0.820s | 87.715us | 0 | 50 | 0.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.960s | 71.625us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.700s | 37.518us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 1.490s | 341.407us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 1.490s | 341.407us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 1.490s | 341.407us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.680s | 302.052us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.710s | 63.099us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 0.780s | 56.387us | 5 | 50 | 10.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.750s | 21.064us | 20 | 20 | 100.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.750s | 21.064us | 20 | 20 | 100.00 |
| V2S | TOTAL | 230 | 375 | 61.33 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.020s | 1.852ms | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 2.080s | 256.105us | 0 | 50 | 0.00 |
| V3 | TOTAL | 50 | 100 | 50.00 | |||
| TOTAL | 741 | 1120 | 66.16 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 12 | 12 | 7 | 58.33 |
| V2S | 9 | 9 | 6 | 66.67 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.39 | 98.23 | 96.15 | 99.44 | 96.00 | 96.18 | 100.00 | 95.74 |
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 100 failures:
0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.103611153443889854684507764645921172806401421058982233523849784880444852843022
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 21847601 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21847601 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.13746004267578081503155362978779941485542014057227909093480357014249230268403
Line 271, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 19834281 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 19834281 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.18250567357483318670632667738160221113484946406034210787054528808573125431
Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 25157239 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25157239 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.80569456764571928581685687440708889852937401809810454999930833772548590658414
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 19642275 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 19642275 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 84 failures:
0.pwrmgr_wakeup_reset.63905134649556202104301627930315133930216520173615515333782889166674701380091
Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 32976222 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 32976222 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_wakeup_reset.65620743787010204742307271222945387956779051616943537196608418894948380265416
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 33448655 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33448655 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
0.pwrmgr_stress_all_with_rand_reset.38660079645823343921557978353056006168005960978626277590177968627420943737840
Line 288, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 178400176 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 178400176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_stress_all_with_rand_reset.93133427037228437692725206414359641902181801312370751016821367097551904981877
Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 129400662 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 129400662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
0.pwrmgr_stress_all.57892196713178901360333037298785116556475945715977741373080809829249630308123
Line 721, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 82019247 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 82019247 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.pwrmgr_stress_all.74628229120498284846292865126460601976655826826445280526892897901516012748983
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 28599487 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28599487 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 19 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 50 failures:
0.pwrmgr_wakeup.94422808109591117743732176554154184818085107399320591756423848440277981067533
Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 39769116 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 39769116 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_wakeup.73133599689390271491403131331429747474872557664200377301866559461017396524848
Line 257, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 27784488 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 27784488 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 29 more failures.
3.pwrmgr_stress_all.42095802888820702881554879130825857815195879230640768599949965989983598024024
Line 256, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 33737402 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33737402 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.pwrmgr_stress_all.28526971331500842995169796230542968809661319074818271600245368939411506790262
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 27841257 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 27841257 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
5.pwrmgr_stress_all_with_rand_reset.3120449850743676184267964333717184616875220876637404921108456560259839719498
Line 522, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 236086335 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 236086335 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.pwrmgr_stress_all_with_rand_reset.88250975413492605960695372123632606998316821343256673585056743965090431784314
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 51480495 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 51480495 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 48 failures:
1.pwrmgr_lowpower_wakeup_race.51078295105401628947657610640925630127461687923892597949290912996647298843387
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 25917693 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 25917693 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_lowpower_wakeup_race.45616715641460568477027166590371117142038187299380975588858589791854807389122
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 61409528 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 61409528 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 25 more failures.
2.pwrmgr_stress_all_with_rand_reset.2037012505085049716032792824143631036062987004316929285770653467471539532924
Line 284, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 105948481 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 105948481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
8.pwrmgr_stress_all_with_rand_reset.10619633484750644394456485313606376121356497393411182478551427498195950021014
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 80922121 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 80922121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
11.pwrmgr_stress_all.64638857201240224666545661858211512490495857054251267378110397662026360978903
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 107006627 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 107006627 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pwrmgr_stress_all.103450259247727637977589994439274381503037948811778880807125415794617725984919
Line 358, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 122085068 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 122085068 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 32 failures:
0.pwrmgr_sec_cm_ctrl_config_regwen.3783784143175005039986384021208410542704458152106403002779835446571825799308
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 41913734 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 41913734 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_sec_cm_ctrl_config_regwen.105628948993352414501082531249784569629950802175584817483772993422081866218123
Line 356, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 54599956 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 54599956 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 26 failures:
1.pwrmgr_stress_all_with_rand_reset.84877467113252068139060414630196653645390318686995902728478313812444771962674
Line 425, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 374965806 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 374965806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
13.pwrmgr_stress_all_with_rand_reset.37837994426115127010553267441475087010060800790083196023543209640794015464688
Line 380, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 352078320 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 352078320 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 4 more failures.
2.pwrmgr_stress_all.85815837059086494244337631074152508947516432739194574865252208545080901150675
Line 297, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 86913716 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hf}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 86913716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_stress_all.31928181694070224263886705123741388925275161251188023556595327739785405867843
Line 377, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 189080918 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 189080918 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
6.pwrmgr_wakeup.88135668401558764498715208263168047598152413605007318362918472374030090208538
Line 273, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 54407566 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h30}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 54407566 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.pwrmgr_wakeup.22576436994035426858608736051115592570751941301947260903553806416258929969652
Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 74320093 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h30}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 74320093 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 24 failures:
2.pwrmgr_lowpower_wakeup_race.20971731749898906746043146947614110572866557907062635027184343552141511492160
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 66823314 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h15}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 66823314 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_lowpower_wakeup_race.114195955732391535389262492946894629636356892833618029494565908610674248138626
Line 274, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 63988529 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h30}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 63988529 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
6.pwrmgr_stress_all_with_rand_reset.4697748865287882540304470114280245843043072092566570380471278614289201813906
Line 397, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 259247087 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h21}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 259247087 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
17.pwrmgr_stress_all_with_rand_reset.46083741080783951737388214582126599023665728499834124150081517010249789502981
Line 572, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 344800806 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h37}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 344800806 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
35.pwrmgr_stress_all.85532055156199172565878809959074685295792033565397923544904068658973156463737
Line 269, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 71541341 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1d}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 71541341 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
43.pwrmgr_stress_all.1290624355209531888796214713551803461294768419202788169052084784296411764388
Line 273, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 56433301 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h22}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 56433301 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 13 failures:
10.pwrmgr_sec_cm_ctrl_config_regwen.81871698277253959716698803745103991427480517617364507830758859809045547704062
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 117884128 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 117884128 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.pwrmgr_sec_cm_ctrl_config_regwen.43102751221472837669385132981717205970071076228888628663223745482391229265522
Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 47180662 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h23}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 47180662 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 2 failures:
42.pwrmgr_lowpower_invalid.98782776356075936557026649833390320573165272750837783249610983635503811927217
Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/42.pwrmgr_lowpower_invalid/latest/run.log
UVM_FATAL @ 36822367 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
UVM_INFO @ 36822367 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
49.pwrmgr_lowpower_invalid.7419069233305740223643448671121548559536834058031949381225336197933060212629
Line 249, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/49.pwrmgr_lowpower_invalid/latest/run.log
UVM_FATAL @ 42543830 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
UVM_INFO @ 42543830 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---