e4c5daa580| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.760s | 36.825us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.720s | 27.657us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.770s | 22.660us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 3.390s | 272.010us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 1.060s | 96.186us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.360s | 48.666us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.770s | 22.660us | 20 | 20 | 100.00 |
| pwrmgr_csr_aliasing | 1.060s | 96.186us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | wakeup | pwrmgr_wakeup | 0.970s | 89.109us | 2 | 50 | 4.00 |
| V2 | control_clks | pwrmgr_wakeup | 0.970s | 89.109us | 2 | 50 | 4.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 1.090s | 31.662us | 50 | 50 | 100.00 |
| pwrmgr_lowpower_invalid | 0.780s | 87.003us | 49 | 50 | 98.00 | ||
| V2 | reset | pwrmgr_reset | 0.940s | 76.798us | 50 | 50 | 100.00 |
| pwrmgr_reset_invalid | 1.170s | 98.650us | 50 | 50 | 100.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 0.940s | 76.798us | 50 | 50 | 100.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 0.800s | 115.847us | 1 | 50 | 2.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 0.800s | 65.480us | 4 | 50 | 8.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.900s | 65.483us | 50 | 50 | 100.00 |
| V2 | stress_all | pwrmgr_stress_all | 1.330s | 714.764us | 2 | 50 | 4.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.670s | 51.209us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 2.680s | 140.533us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 2.680s | 140.533us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.720s | 27.657us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.770s | 22.660us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.060s | 96.186us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.950s | 42.004us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.720s | 27.657us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.770s | 22.660us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.060s | 96.186us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.950s | 42.004us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 348 | 540 | 64.44 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.810s | 461.481us | 20 | 20 | 100.00 |
| pwrmgr_sec_cm | 1.400s | 802.636us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 1.400s | 802.636us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 1.400s | 802.636us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.810s | 461.481us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 0.870s | 96.141us | 0 | 50 | 0.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 0.830s | 58.101us | 0 | 50 | 0.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 1.010s | 63.397us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.740s | 37.444us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 1.400s | 802.636us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 1.400s | 802.636us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 1.400s | 802.636us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.700s | 45.258us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.760s | 54.985us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 0.860s | 158.210us | 3 | 50 | 6.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.770s | 22.660us | 20 | 20 | 100.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.770s | 22.660us | 20 | 20 | 100.00 |
| V2S | TOTAL | 228 | 375 | 60.80 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.120s | 310.732us | 49 | 50 | 98.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 1.730s | 275.015us | 0 | 50 | 0.00 |
| V3 | TOTAL | 49 | 100 | 49.00 | |||
| TOTAL | 730 | 1120 | 65.18 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 12 | 12 | 7 | 58.33 |
| V2S | 9 | 9 | 6 | 66.67 |
| V3 | 2 | 2 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.39 | 98.23 | 96.15 | 99.44 | 96.00 | 96.18 | 100.00 | 95.74 |
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 100 failures:
0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.74251203260694599390436160835337315152864063085479853501809337127731271959063
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 21326163 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 21326163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.225851573715535481462719369472376933446700397990166148348209331800937274497
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 22538491 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 22538491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.52579479508612054119253626967106888039508470660941896631983578108654230788425
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 28396168 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 28396168 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.115266735515877241395464207321392564136124505296361098908704300319324468235332
Line 310, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 70794372 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 70794372 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 86 failures:
0.pwrmgr_wakeup_reset.8389885669205860055665470522111057657584821375164338226949012706447931412815
Line 283, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 36495584 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 36495584 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_wakeup_reset.45911551078594856781284673288008507976006815015227228326297825870288641499741
Line 260, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 33748924 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 33748924 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
6.pwrmgr_stress_all_with_rand_reset.82198501717025717118446149521843457180334210334805240582138565483221162693798
Line 361, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 57765736 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 57765736 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.pwrmgr_stress_all_with_rand_reset.86221398132252933190533285809727318877635609254330629937219934928913386597619
Line 766, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 167433438 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 167433438 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
6.pwrmgr_stress_all.94425185538811916059713761176356883233061695238146532701281522118776985481600
Line 292, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 63038814 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 63038814 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
14.pwrmgr_stress_all.83854410920142662102155422820326463607166023397536121724137766760800806129196
Line 377, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 123081820 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 123081820 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 15 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 61 failures:
0.pwrmgr_wakeup.84704131485671132736817704187502191597363852035905113468150740367536969953108
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 145650832 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 145650832 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_wakeup.102236548786565943419036066860959872850894469832116463048463227127829652041560
Line 255, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 29187816 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 29187816 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 36 more failures.
1.pwrmgr_stress_all_with_rand_reset.26153957944247041532684815424186978360529484867015491913017330294421918747950
Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 30455094 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 30455094 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_stress_all_with_rand_reset.62334552933413794568481030909368832318932641454191178009181612823742147316224
Line 289, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 53323490 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 53323490 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
1.pwrmgr_stress_all.9907335760451449093715377005136892020565097626126197827545621427468728990304
Line 273, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 40959892 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 40959892 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_stress_all.109777762754579822625904704917484156050008096587419118077694220033803382625463
Line 395, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 231520615 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 231520615 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 51 failures:
0.pwrmgr_lowpower_wakeup_race.60301215212620904689896237008784509327763366603228274142488633384369376596448
Line 285, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 57549452 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 57549452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_lowpower_wakeup_race.19254846333222680216645476938994967321648124410284482469775350925494505220915
Line 273, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 86231370 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 86231370 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 30 more failures.
0.pwrmgr_stress_all_with_rand_reset.12730663866989894918706830746478668392930335347752566847268645909364556653724
Line 272, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 76836761 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 76836761 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_stress_all_with_rand_reset.75381963480404752875854270009136672358542008884675798364976373711390219103922
Line 276, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 54647451 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 54647451 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
3.pwrmgr_stress_all.54887477778892763049192634014546658509310940664823163408506622878122009529041
Line 318, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 205799904 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 205799904 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
11.pwrmgr_stress_all.88191926289863856156945472112017906078662142036064413604308047133038311800252
Line 256, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 27685121 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 27685121 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 35 failures:
0.pwrmgr_sec_cm_ctrl_config_regwen.36282083162817854226302969226161741262112419935560771562187893093240378582941
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 27249609 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 27249609 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_ctrl_config_regwen.69711339501158927347983154846762866414797485260398445843930231361635778476003
Line 260, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 59276545 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 59276545 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 23 failures:
2.pwrmgr_stress_all_with_rand_reset.55623561938744225505942882972698075244938109434282594181327518221988819538874
Line 291, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 85762865 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hc}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 85762865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_stress_all_with_rand_reset.40084901010739584169373811189189821409003942092990148076101930007013845801474
Line 273, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 76347048 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h34}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 76347048 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 3 more failures.
3.pwrmgr_lowpower_wakeup_race.6051728130376566025722128900660948135238478353009364647664104288518050802593
Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 66099413 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3e}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 66099413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
9.pwrmgr_lowpower_wakeup_race.96128629533505557101859202885033341719401449169106127728973413727229453720268
Line 259, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 57321049 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 57321049 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
16.pwrmgr_stress_all.90428557928178918682921824712682977891046516696899001466320121010440011682077
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 141836899 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h2f}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 141836899 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
18.pwrmgr_stress_all.108161561990324364390828013243582971327789593941532989798049583355929182239273
Line 299, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 83704441 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h34}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 83704441 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 20 failures:
4.pwrmgr_stress_all.8167008758469020701598734754159464830235649178411469656972288438963251282461
Line 372, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 129686792 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h2f}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 129686792 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
7.pwrmgr_stress_all.17557158136818843005093481136731673388873663218334819372920796647136735286382
Line 335, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 92093954 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h32}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 92093954 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 5 more failures.
9.pwrmgr_wakeup.60643917777849467804922458384543910207149717186407421522748455810260919514958
Line 337, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 67057690 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h24}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 67057690 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
12.pwrmgr_wakeup.78014064401275061645288685251552943524293100522338655923224300163734525323435
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 48456359 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'hc}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 48456359 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
18.pwrmgr_stress_all_with_rand_reset.97316928723336047396637449047212684411288359636380970714679067611675083417396
Line 290, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 114999671 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h4}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 114999671 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.pwrmgr_stress_all_with_rand_reset.98633444744518208741523526822528793687906092618065924536494841503604803670915
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 72238955 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 72238955 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 12 failures:
3.pwrmgr_sec_cm_ctrl_config_regwen.31803134976718113411667179114041606676069535586934303812422685097218134892865
Line 288, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 78324670 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3b}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 78324670 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_sec_cm_ctrl_config_regwen.109005211498087334081314791589061155620352041988224812542175099021712105195720
Line 359, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 149632056 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 149632056 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.
Offending '(pwr_rst_o.rst_lc_req == *'b11)' has 1 failures:
40.pwrmgr_escalation_timeout.61305496213439026386503698754789969959742269329566048363464584067762550172586
Line 250, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest/run.log
Offending '(pwr_rst_o.rst_lc_req == 2'b11)'
UVM_ERROR @ 94451210 ps: (pwrmgr.sv:174) [ASSERT FAILED] PwrmgrSecCmEscToLCReset_A
UVM_INFO @ 94451210 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_FATAL (pwrmgr_lowpower_invalid_vseq.sv:61) [pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough has 1 failures:
47.pwrmgr_lowpower_invalid.2463033006915822358448135421871664046940926645946662826280177827718862605884
Line 251, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/47.pwrmgr_lowpower_invalid/latest/run.log
UVM_FATAL @ 37205413 ps: (pwrmgr_lowpower_invalid_vseq.sv:61) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_invalid_vseq] Timed out waiting for state DVWaitFallThrough
UVM_INFO @ 37205413 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---