PWRMGR Simulation Results

Saturday August 03 2024 23:02:32 UTC

GitHub Revision: `c8985d6745`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 108668412464624965510474525856307009670790505545344576298908689226672042444441

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	smoke	pwrmgr_smoke	0.760s	58.685us	50	50	100.00
V1	csr_hw_reset	pwrmgr_csr_hw_reset	0.680s	37.883us	5	5	100.00
V1	csr_rw	pwrmgr_csr_rw	0.690s	18.734us	20	20	100.00
V1	csr_bit_bash	pwrmgr_csr_bit_bash	3.210s	862.255us	5	5	100.00
V1	csr_aliasing	pwrmgr_csr_aliasing	1.040s	54.871us	5	5	100.00
V1	csr_mem_rw_with_rand_reset	pwrmgr_csr_mem_rw_with_rand_reset	1.510s	51.951us	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	pwrmgr_csr_rw	0.690s	18.734us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	54.871us	5	5	100.00
V1		TOTAL			105	105	100.00
V2	wakeup	pwrmgr_wakeup	0.900s	98.544us	9	50	18.00
V2	control_clks	pwrmgr_wakeup	0.900s	98.544us	9	50	18.00
V2	aborted_low_power	pwrmgr_aborted_low_power	1.090s	31.586us	50	50	100.00
		pwrmgr_lowpower_invalid	0.770s	42.371us	50	50	100.00
V2	reset	pwrmgr_reset	0.900s	80.296us	50	50	100.00
		pwrmgr_reset_invalid	1.130s	108.792us	50	50	100.00
V2	main_power_glitch_reset	pwrmgr_reset	0.900s	80.296us	50	50	100.00
V2	reset_wakeup_race	pwrmgr_wakeup_reset	0.730s	57.461us	3	50	6.00
V2	lowpower_wakeup_race	pwrmgr_lowpower_wakeup_race	0.850s	82.537us	5	50	10.00
V2	disable_rom_integrity_check	pwrmgr_disable_rom_integrity_check	0.850s	54.684us	50	50	100.00
V2	stress_all	pwrmgr_stress_all	1.680s	286.281us	5	50	10.00
V2	intr_test	pwrmgr_intr_test	0.680s	46.818us	50	50	100.00
V2	tl_d_oob_addr_access	pwrmgr_tl_errors	3.130s	251.367us	20	20	100.00
V2	tl_d_illegal_access	pwrmgr_tl_errors	3.130s	251.367us	20	20	100.00
V2	tl_d_outstanding_access	pwrmgr_csr_hw_reset	0.680s	37.883us	5	5	100.00
		pwrmgr_csr_rw	0.690s	18.734us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	54.871us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	140.622us	20	20	100.00
V2	tl_d_partial_access	pwrmgr_csr_hw_reset	0.680s	37.883us	5	5	100.00
		pwrmgr_csr_rw	0.690s	18.734us	20	20	100.00
		pwrmgr_csr_aliasing	1.040s	54.871us	5	5	100.00
		pwrmgr_same_csr_outstanding	0.900s	140.622us	20	20	100.00
V2		TOTAL			362	540	67.04
V2S	tl_intg_err	pwrmgr_tl_intg_err	1.680s	192.513us	20	20	100.00
		pwrmgr_sec_cm	2.110s	688.915us	5	5	100.00
V2S	prim_count_check	pwrmgr_sec_cm	2.110s	688.915us	5	5	100.00
V2S	prim_fsm_check	pwrmgr_sec_cm	2.110s	688.915us	5	5	100.00
V2S	sec_cm_bus_integrity	pwrmgr_tl_intg_err	1.680s	192.513us	20	20	100.00
V2S	sec_cm_lc_ctrl_intersig_mubi	pwrmgr_sec_cm_lc_ctrl_intersig_mubi	0.740s	30.828us	0	50	0.00
V2S	sec_cm_rom_ctrl_intersig_mubi	pwrmgr_sec_cm_rom_ctrl_intersig_mubi	0.910s	63.678us	0	50	0.00
V2S	sec_cm_rstmgr_intersig_mubi	pwrmgr_sec_cm_rstmgr_intersig_mubi	0.970s	63.251us	50	50	100.00
V2S	sec_cm_esc_rx_clk_bkgn_chk	pwrmgr_esc_clk_rst_malfunc	0.690s	31.041us	50	50	100.00
V2S	sec_cm_esc_rx_clk_local_esc	pwrmgr_sec_cm	2.110s	688.915us	5	5	100.00
V2S	sec_cm_fsm_sparse	pwrmgr_sec_cm	2.110s	688.915us	5	5	100.00
V2S	sec_cm_fsm_terminal	pwrmgr_sec_cm	2.110s	688.915us	5	5	100.00
V2S	sec_cm_ctrl_flow_global_esc	pwrmgr_global_esc	0.710s	44.317us	50	50	100.00
V2S	sec_cm_main_pd_rst_local_esc	pwrmgr_glitch	0.720s	59.754us	50	50	100.00
V2S	sec_cm_ctrl_config_regwen	pwrmgr_sec_cm_ctrl_config_regwen	0.820s	85.684us	5	50	10.00
V2S	sec_cm_wakeup_config_regwen	pwrmgr_csr_rw	0.690s	18.734us	20	20	100.00
V2S	sec_cm_reset_config_regwen	pwrmgr_csr_rw	0.690s	18.734us	20	20	100.00
V2S		TOTAL			230	375	61.33
V3	escalation_timeout	pwrmgr_escalation_timeout	1.070s	158.509us	50	50	100.00
V3	stress_all_with_rand_reset	pwrmgr_stress_all_with_rand_reset	2.000s	288.402us	0	50	0.00
V3		TOTAL			50	100	50.00
		TOTAL			747	1120	66.70

Testplan Progress

Items	Total	Written	Passing	Progress
V1	6	6	6	100.00
V2	12	12	8	66.67
V2S	9	9	6	66.67
V3	2	2	1	50.00

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
97.46	98.23	96.15	99.44	96.00	96.18	100.00	96.24

Failure Buckets

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])

has 100 failures:

Test pwrmgr_sec_cm_lc_ctrl_intersig_mubi has 50 failures.

0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.96849183419239601463200176321254668156515680591852618538147952433367193075932
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  39992377 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  39992377 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.76012734629775823633528078660905218192071472945557343625991469047824201401880
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  23527176 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  23527176 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

Test pwrmgr_sec_cm_rom_ctrl_intersig_mubi has 50 failures.

0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.86219031836694806233674242440587852117967233733332926091738274249970941192752
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  34126224 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  34126224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.37712573957299548620217014441208143642059550173371116588430923247297449964568
Line 276, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log

  UVM_ERROR @  41054388 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  41054388 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 48 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])

has 77 failures:

Test pwrmgr_wakeup_reset has 47 failures.

0.pwrmgr_wakeup_reset.25313800558553177503445900899455814392824881679444236913950553221780878197505
Line 272, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log

  UVM_ERROR @  46326637 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  46326637 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_wakeup_reset.9480072065556907720672465327312064916361413809651058702796040014470097458795
Line 276, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log

  UVM_ERROR @  37011261 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  37011261 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 45 more failures.

Test pwrmgr_stress_all_with_rand_reset has 13 failures.

0.pwrmgr_stress_all_with_rand_reset.21786465444480477862472552838936354723455451040043918418248228159778745221912
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  31482687 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  31482687 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_stress_all_with_rand_reset.109990483082827331532810191267353281374390307756368149841895400695202068688857
Line 492, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  69774072 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  69774072 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 11 more failures.

Test pwrmgr_stress_all has 17 failures.

3.pwrmgr_stress_all.46988356711716884714082697230071644633075624285636154836609016376418936152075
Line 438, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @ 381374979 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 381374979 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_stress_all.51519230590038259354375288263195971207752071828648879049607641489490583809532
Line 352, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  97641283 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  97641283 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 15 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])

has 58 failures:

Test pwrmgr_wakeup has 26 failures.

0.pwrmgr_wakeup.55320041849732773754489584759583897433748361868157837452460315346591747097644
Line 298, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  80082306 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  80082306 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.pwrmgr_wakeup.82665290524514548981233817981138415982810824366213217282238493155200746790350
Line 280, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest/run.log

  UVM_ERROR @  65827078 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  65827078 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 24 more failures.

Test pwrmgr_stress_all_with_rand_reset has 20 failures.

1.pwrmgr_stress_all_with_rand_reset.32382669745876065430771157931903766903438701127322666186602791846037816271135
Line 278, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  82224633 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  82224633 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_stress_all_with_rand_reset.102839234784296761140923537558974484816587015581175786484187110590267085529249
Line 359, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 133375656 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 133375656 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 18 more failures.

Test pwrmgr_stress_all has 12 failures.

6.pwrmgr_stress_all.23469340354918629126638760171210431200838651514744281869889973974560009831882
Line 260, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  37138269 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  37138269 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

9.pwrmgr_stress_all.64526844161260488544962494084587552310735822697060815313127574791588130312774
Line 510, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  72647661 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  72647661 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 10 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*])

has 49 failures:

Test pwrmgr_lowpower_wakeup_race has 31 failures.

0.pwrmgr_lowpower_wakeup_race.36752594195139291973179134907570147674989891481982296020150299287087149971162
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_ERROR @  36373961 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  36373961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.pwrmgr_lowpower_wakeup_race.103389551506705785614611081160088879576108907887037616197829612172741500402209
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_ERROR @  57736337 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  57736337 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 29 more failures.

Test pwrmgr_stress_all has 7 failures.

1.pwrmgr_stress_all.50226748293419532141933510218093066252039142394288014289138875819076289639185
Line 257, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  67785460 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  67785460 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

5.pwrmgr_stress_all.21301685248457396744113675010028121029093433007479138378850566260568655323941
Line 271, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest/run.log

  UVM_ERROR @  66516026 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  66516026 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 5 more failures.

Test pwrmgr_stress_all_with_rand_reset has 11 failures.

3.pwrmgr_stress_all_with_rand_reset.4411638067960382391223942478765654294949526130919978725134275898564111917043
Line 356, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @  57630696 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  57630696 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

11.pwrmgr_stress_all_with_rand_reset.112133038364752488682561001852003285857400984494761820621448706727211889249041
Line 432, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_ERROR @ 117124513 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @ 117124513 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 9 more failures.

UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 35 failures:
- Test pwrmgr_sec_cm_ctrl_config_regwen has 35 failures.
  - 0.pwrmgr_sec_cm_ctrl_config_regwen.103577546023442580207267144153276000551772408419688179902959769855221828733304
    Line 300, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  55843928 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  55843928 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.pwrmgr_sec_cm_ctrl_config_regwen.88242638254498871430288926616865605274372537696827592272963388106834651300595
    Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
```
  UVM_ERROR @  35251470 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
  UVM_INFO @  35251470 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 33 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}}

has 24 failures:

Test pwrmgr_wakeup has 15 failures.

1.pwrmgr_wakeup.26652554153826397988409302829977701147972083268429406147046820347616195428361
Line 302, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest/run.log

  UVM_FATAL @  60356961 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h20}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  60356961 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

7.pwrmgr_wakeup.20054428784517992660984677318542895059164644668523665401179362338535940364219
Line 263, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest/run.log

  UVM_FATAL @  52437205 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  52437205 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 13 more failures.

Test pwrmgr_stress_all has 5 failures.

4.pwrmgr_stress_all.5146253308211423476974160943474711268557713250852321948210951676716106542300
Line 271, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 210068226 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 210068226 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

8.pwrmgr_stress_all.87047589448538876338445468312065994882856775936214863448136140294293338858196
Line 344, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 355296150 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h11}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 355296150 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 3 more failures.

Test pwrmgr_stress_all_with_rand_reset has 4 failures.

19.pwrmgr_stress_all_with_rand_reset.90711365849020652380460945884162480968190007444210828151326391920468001084272
Line 350, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 147520452 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h2a}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 147520452 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

21.pwrmgr_stress_all_with_rand_reset.43010947773411971214221764349345276177464004758842280813683404533234820281927
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  55663482 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h8}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  55663482 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}}

has 20 failures:

Test pwrmgr_lowpower_wakeup_race has 14 failures.

4.pwrmgr_lowpower_wakeup_race.15003704464323940040823134021156653894010633582155562812035667589021492814110
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_FATAL @  75186595 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h16}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  75186595 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

6.pwrmgr_lowpower_wakeup_race.32882485093970788575516469424698820289523319586551766782139471278966217140012
Line 275, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest/run.log

  UVM_FATAL @  77433267 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h30}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  77433267 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 12 more failures.

Test pwrmgr_stress_all_with_rand_reset has 2 failures.

6.pwrmgr_stress_all_with_rand_reset.86693555981697079777513844406567897170621745921005046905473893999526628272032
Line 289, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @  86710547 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3a}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  86710547 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

12.pwrmgr_stress_all_with_rand_reset.61049196278930086113640394098883823642567245133843142592278608413123885863835
Line 361, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest/run.log

  UVM_FATAL @ 153978610 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 153978610 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test pwrmgr_stress_all has 4 failures.

23.pwrmgr_stress_all.79396635048376526214885503350374585972630791067438359022409495053936145100499
Line 311, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @  71726426 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  71726426 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

33.pwrmgr_stress_all.12570026725800086916555818282776663022182910849467159206216223586454159416857
Line 401, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest/run.log

  UVM_FATAL @ 115021603 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @ 115021603 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 2 more failures.

UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}}

has 10 failures:

Test pwrmgr_sec_cm_ctrl_config_regwen has 10 failures.

6.pwrmgr_sec_cm_ctrl_config_regwen.36471022925493601931901660361840997539901056350696401813382242173132990034000
Line 265, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_FATAL @  52665322 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h36}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  52665322 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

18.pwrmgr_sec_cm_ctrl_config_regwen.14646869031714523841654960229639766000143280145664368737057901927113943109768
Line 291, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log

  UVM_FATAL @  49214514 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h0}, fall_through:'{d:'h0}, abort:'{d:'h0}}
  UVM_INFO @  49214514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 8 more failures.