PWRMGR Simulation Results

Thursday August 08 2024 23:02:08 UTC

GitHub Revision: 3707c48f56

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 96859198578252641766218135484681220968075710602306197013001824903089223290045

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.760s 28.475us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.650s 24.567us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.740s 21.163us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.130s 828.592us 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 1.050s 42.215us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.660s 353.793us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.740s 21.163us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 42.215us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.330s 313.820us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.330s 313.820us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.120s 36.291us 50 50 100.00
pwrmgr_lowpower_invalid 0.810s 41.258us 50 50 100.00
V2 reset pwrmgr_reset 1.050s 89.299us 50 50 100.00
pwrmgr_reset_invalid 1.160s 110.993us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 1.050s 89.299us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.460s 277.508us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.360s 270.259us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.920s 75.309us 50 50 100.00
V2 stress_all pwrmgr_stress_all 7.930s 2.346ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.670s 32.978us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.520s 151.306us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.520s 151.306us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.650s 24.567us 5 5 100.00
pwrmgr_csr_rw 0.740s 21.163us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 42.215us 5 5 100.00
pwrmgr_same_csr_outstanding 0.930s 46.425us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.650s 24.567us 5 5 100.00
pwrmgr_csr_rw 0.740s 21.163us 20 20 100.00
pwrmgr_csr_aliasing 1.050s 42.215us 5 5 100.00
pwrmgr_same_csr_outstanding 0.930s 46.425us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.710s 185.375us 20 20 100.00
pwrmgr_sec_cm 1.620s 326.538us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 1.620s 326.538us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 1.620s 326.538us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.710s 185.375us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.400s 916.045us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.530s 882.788us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 0.980s 69.187us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.670s 28.402us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 1.620s 326.538us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 1.620s 326.538us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 1.620s 326.538us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.690s 47.474us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.710s 54.820us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.390s 302.212us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.740s 21.163us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.740s 21.163us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.060s 567.870us 49 50 98.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 45.970s 12.812ms 50 50 100.00
V3 TOTAL 99 100 99.00
TOTAL 1119 1120 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.92 98.23 96.58 99.44 96.00 96.37 100.00 98.85

Failure Buckets

Past Results