5fd4ecc0fc| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | pwrmgr_smoke | 0.730s | 30.336us | 50 | 50 | 100.00 |
| V1 | csr_hw_reset | pwrmgr_csr_hw_reset | 0.700s | 32.950us | 5 | 5 | 100.00 |
| V1 | csr_rw | pwrmgr_csr_rw | 0.700s | 34.620us | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | pwrmgr_csr_bit_bash | 2.060s | 161.613us | 5 | 5 | 100.00 |
| V1 | csr_aliasing | pwrmgr_csr_aliasing | 1.020s | 47.715us | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | pwrmgr_csr_mem_rw_with_rand_reset | 1.240s | 60.056us | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | pwrmgr_csr_rw | 0.700s | 34.620us | 20 | 20 | 100.00 |
| pwrmgr_csr_aliasing | 1.020s | 47.715us | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 105 | 105 | 100.00 | |||
| V2 | wakeup | pwrmgr_wakeup | 0.840s | 72.419us | 7 | 50 | 14.00 |
| V2 | control_clks | pwrmgr_wakeup | 0.840s | 72.419us | 7 | 50 | 14.00 |
| V2 | aborted_low_power | pwrmgr_aborted_low_power | 1.010s | 53.141us | 50 | 50 | 100.00 |
| pwrmgr_lowpower_invalid | 0.790s | 44.380us | 50 | 50 | 100.00 | ||
| V2 | reset | pwrmgr_reset | 0.930s | 73.875us | 50 | 50 | 100.00 |
| pwrmgr_reset_invalid | 1.210s | 110.227us | 50 | 50 | 100.00 | ||
| V2 | main_power_glitch_reset | pwrmgr_reset | 0.930s | 73.875us | 50 | 50 | 100.00 |
| V2 | reset_wakeup_race | pwrmgr_wakeup_reset | 0.810s | 44.075us | 1 | 50 | 2.00 |
| V2 | lowpower_wakeup_race | pwrmgr_lowpower_wakeup_race | 0.800s | 52.978us | 2 | 50 | 4.00 |
| V2 | disable_rom_integrity_check | pwrmgr_disable_rom_integrity_check | 0.880s | 59.988us | 50 | 50 | 100.00 |
| V2 | stress_all | pwrmgr_stress_all | 1.220s | 145.422us | 2 | 50 | 4.00 |
| V2 | intr_test | pwrmgr_intr_test | 0.660s | 33.075us | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | pwrmgr_tl_errors | 3.000s | 628.053us | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | pwrmgr_tl_errors | 3.000s | 628.053us | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | pwrmgr_csr_hw_reset | 0.700s | 32.950us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.700s | 34.620us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.020s | 47.715us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.940s | 42.421us | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | pwrmgr_csr_hw_reset | 0.700s | 32.950us | 5 | 5 | 100.00 |
| pwrmgr_csr_rw | 0.700s | 34.620us | 20 | 20 | 100.00 | ||
| pwrmgr_csr_aliasing | 1.020s | 47.715us | 5 | 5 | 100.00 | ||
| pwrmgr_same_csr_outstanding | 0.940s | 42.421us | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 352 | 540 | 65.19 | |||
| V2S | tl_intg_err | pwrmgr_tl_intg_err | 1.910s | 349.710us | 20 | 20 | 100.00 |
| pwrmgr_sec_cm | 2.230s | 691.080us | 5 | 5 | 100.00 | ||
| V2S | prim_count_check | pwrmgr_sec_cm | 2.230s | 691.080us | 5 | 5 | 100.00 |
| V2S | prim_fsm_check | pwrmgr_sec_cm | 2.230s | 691.080us | 5 | 5 | 100.00 |
| V2S | sec_cm_bus_integrity | pwrmgr_tl_intg_err | 1.910s | 349.710us | 20 | 20 | 100.00 |
| V2S | sec_cm_lc_ctrl_intersig_mubi | pwrmgr_sec_cm_lc_ctrl_intersig_mubi | 0.920s | 71.947us | 0 | 50 | 0.00 |
| V2S | sec_cm_rom_ctrl_intersig_mubi | pwrmgr_sec_cm_rom_ctrl_intersig_mubi | 0.790s | 56.709us | 0 | 50 | 0.00 |
| V2S | sec_cm_rstmgr_intersig_mubi | pwrmgr_sec_cm_rstmgr_intersig_mubi | 0.930s | 51.825us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_bkgn_chk | pwrmgr_esc_clk_rst_malfunc | 0.700s | 30.366us | 50 | 50 | 100.00 |
| V2S | sec_cm_esc_rx_clk_local_esc | pwrmgr_sec_cm | 2.230s | 691.080us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_sparse | pwrmgr_sec_cm | 2.230s | 691.080us | 5 | 5 | 100.00 |
| V2S | sec_cm_fsm_terminal | pwrmgr_sec_cm | 2.230s | 691.080us | 5 | 5 | 100.00 |
| V2S | sec_cm_ctrl_flow_global_esc | pwrmgr_global_esc | 0.660s | 56.460us | 50 | 50 | 100.00 |
| V2S | sec_cm_main_pd_rst_local_esc | pwrmgr_glitch | 0.720s | 55.912us | 50 | 50 | 100.00 |
| V2S | sec_cm_ctrl_config_regwen | pwrmgr_sec_cm_ctrl_config_regwen | 0.880s | 96.762us | 4 | 50 | 8.00 |
| V2S | sec_cm_wakeup_config_regwen | pwrmgr_csr_rw | 0.700s | 34.620us | 20 | 20 | 100.00 |
| V2S | sec_cm_reset_config_regwen | pwrmgr_csr_rw | 0.700s | 34.620us | 20 | 20 | 100.00 |
| V2S | TOTAL | 229 | 375 | 61.07 | |||
| V3 | escalation_timeout | pwrmgr_escalation_timeout | 1.080s | 167.210us | 50 | 50 | 100.00 |
| V3 | stress_all_with_rand_reset | pwrmgr_stress_all_with_rand_reset | 2.560s | 369.344us | 0 | 50 | 0.00 |
| V3 | TOTAL | 50 | 100 | 50.00 | |||
| TOTAL | 736 | 1120 | 65.71 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 6 | 6 | 6 | 100.00 |
| V2 | 12 | 12 | 8 | 66.67 |
| V2S | 9 | 9 | 6 | 66.67 |
| V3 | 2 | 2 | 1 | 50.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 97.39 | 98.23 | 96.15 | 99.44 | 96.00 | 96.18 | 100.00 | 95.74 |
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 100 failures:
0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.770123952491983862036364879457191007002296252302563461880634648893307756268
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 24627574 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 24627574 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.64907597008413648316656925262036704352265840626131997045365218899955677475663
Line 332, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 45331117 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45331117 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.93687140335852989901795241978079720539826426022166862739820513256161840419109
Line 270, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 23169203 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 23169203 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.66836163443127834047327719816220917107915775699202891512732542981255864977157
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest/run.log
UVM_ERROR @ 22321634 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_repeat_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 22321634 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 48 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 80 failures:
0.pwrmgr_wakeup_reset.21768361967186956929757599909603740103114951270230836051605146522031966184328
Line 260, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 29220163 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 29220163 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_wakeup_reset.3314484781507668866496222609170841177997031785373517133010384603271715828834
Line 274, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest/run.log
UVM_ERROR @ 38790415 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 38790415 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 47 more failures.
0.pwrmgr_stress_all_with_rand_reset.74503742296873818084955877567434211338753486250447836220450758180485386436339
Line 296, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 44268819 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 44268819 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_stress_all_with_rand_reset.44870840471639792613456775185640618519323482124031393821507958836047695319708
Line 274, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 45564937 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45564937 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 18 more failures.
0.pwrmgr_stress_all.85308735229922556721446831033546440378623237608258687193035265145871452828326
Line 313, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 67786755 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 67786755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_stress_all.38193104188295659632305009231442998114171611208288111308325015899237454948644
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 83178509 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_reset_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 83178509 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 62 failures:
0.pwrmgr_lowpower_wakeup_race.26529244150797581751184731188323077949852261463523818644752910949845705355043
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 46314754 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 46314754 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
1.pwrmgr_lowpower_wakeup_race.100568312111818945470753602808572401015555845886570030576404676522630555367523
Line 270, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_ERROR @ 26830514 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 26830514 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 33 more failures.
1.pwrmgr_stress_all_with_rand_reset.30735592943182966642343007198989759657677739293454618415780698147492888051261
Line 270, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 69340066 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 69340066 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_stress_all_with_rand_reset.35967648687377307639468705128917857707075963318641164421124228198776044122391
Line 291, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 59091870 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 59091870 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
7.pwrmgr_stress_all.108493191455914752271633578314886408331494727923911428087330917815336215456603
Line 456, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 107389520 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 107389520 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.pwrmgr_stress_all.109584603003799731540054630353983438458432041016975476252428081902830174565174
Line 290, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 85587815 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 85587815 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 12 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 51 failures:
1.pwrmgr_wakeup.86908210412932101926630201630922854805861852246179029386503203071399708309359
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 45692399 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45692399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_wakeup.80301270239313330227460376396564596073480159425073795203546016215052426964878
Line 279, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest/run.log
UVM_ERROR @ 72395407 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 72395407 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 28 more failures.
2.pwrmgr_stress_all_with_rand_reset.34125320078116673570629861187942950827990151580872703924325713504195996008673
Line 266, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 44721716 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 44721716 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_stress_all_with_rand_reset.3496843476834419451283014530507408658208723192560878797263124903104542595926
Line 358, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 82120570 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 82120570 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 8 more failures.
2.pwrmgr_stress_all.114312806616821663877704296591754144569513048020361804769915158864202471560004
Line 299, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 75676155 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 75676155 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
5.pwrmgr_stress_all.65823316221740145967418512691186298115368322856420251761793888784940483551222
Line 436, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest/run.log
UVM_ERROR @ 499652865 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 499652865 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 9 more failures.
UVM_ERROR (pwrmgr_base_vseq.sv:269) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (* [*] vs * [*]) has 34 failures:
5.pwrmgr_sec_cm_ctrl_config_regwen.47937892475754675486659170603280683842168393671309211952026980224571315260384
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 45117119 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 45117119 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
6.pwrmgr_sec_cm_ctrl_config_regwen.13843655528072657798691699430789249110405620279947195149384326343728057318649
Line 264, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_ERROR @ 23011491 ps: (pwrmgr_base_vseq.sv:269) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] Check failed cfg.pwrmgr_vif.intr_wakeup == expected && enable (0 [0x0] vs 1 [0x1])
UVM_INFO @ 23011491 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 32 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 24 failures:
0.pwrmgr_wakeup.110317029243477391891038866729188921327548475053685994850081917268081094029694
Line 267, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 53879329 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h5}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 53879329 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
3.pwrmgr_wakeup.77823992872151816898192755908643137088990880371237370188742071194407681219420
Line 272, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest/run.log
UVM_FATAL @ 78960643 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h20}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 78960643 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
3.pwrmgr_stress_all.54287962911939079919465474120560508207061175610688894439994042513161542472384
Line 277, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 61749095 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h36}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 61749095 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
4.pwrmgr_stress_all.21086462433102441099116391545251140293804507388127862482680219267260124953067
Line 262, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 70421849 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1b}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 70421849 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 6 more failures.
25.pwrmgr_stress_all_with_rand_reset.51493062352564522226887359146181551240466103028974098406937784709424400944159
Line 269, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 71808481 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3f}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 71808481 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
38.pwrmgr_stress_all_with_rand_reset.40820526072974556081618064810872377314678756257520662424523243697116881159132
Line 551, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 386414572 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_wakeup_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h8}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 386414572 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 21 failures:
8.pwrmgr_lowpower_wakeup_race.46322177847296424075331347588754736245864647113482254006036358583431671607883
Line 287, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 112821399 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h33}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 112821399 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
10.pwrmgr_lowpower_wakeup_race.89922193445767506739719793257606786919339425074740328807171134267614158747259
Line 282, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest/run.log
UVM_FATAL @ 74372263 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h1c}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 74372263 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 11 more failures.
9.pwrmgr_stress_all.64697347653349220097351447657463249711701132473851260059087278434700903184787
Line 363, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 279380052 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h29}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 279380052 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
15.pwrmgr_stress_all.53222108296494059451910793966582088318519985915710414059271389782371689546824
Line 443, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest/run.log
UVM_FATAL @ 170742137 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3f}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 170742137 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
17.pwrmgr_stress_all_with_rand_reset.3176486814027963494936428979433869675504162631417020801900873508534491617745
Line 714, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 120971567 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h3e}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 120971567 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
24.pwrmgr_stress_all_with_rand_reset.42023653247785504742438449618927894934808751335554045945406862729161652064780
Line 315, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest/run.log
UVM_FATAL @ 105999224 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_lowpower_wakeup_race_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h28}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 105999224 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 2 more failures.
UVM_FATAL (pwrmgr_base_vseq.sv:721) [pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} actual:'{reasons:'{d:*}, fall_through:'{d:*}, abort:'{d:*}} has 12 failures:
1.pwrmgr_sec_cm_ctrl_config_regwen.81269402531806517323692821234288293559552589590106762850799563029128869991211
Line 268, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 56399458 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h38}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 56399458 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
2.pwrmgr_sec_cm_ctrl_config_regwen.21276711855468549566961415915085865916240701167668242237004003675100568666158
Line 261, in log /container/opentitan-public/scratch/os_regression/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest/run.log
UVM_FATAL @ 51794969 ps: (pwrmgr_base_vseq.sv:721) [uvm_test_top.env.virtual_sequencer.pwrmgr_sec_cm_ctrl_config_regwen_vseq] wake info wait timeout exp:'{reasons:'{d:'h3f}, fall_through:'{d:'h1}, abort:'{d:'h1}} actual:'{reasons:'{d:'h4}, fall_through:'{d:'h0}, abort:'{d:'h0}}
UVM_INFO @ 51794969 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 10 more failures.