PWRMGR Simulation Results

Friday August 09 2024 23:02:07 UTC

GitHub Revision: 07b417ef03

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 39866585070056138360117926942905553094756411441088058786676399955088054585836

Test Results

Stage Name Tests Max Job Runtime Simulated Time Passing Total Pass Rate
V1 smoke pwrmgr_smoke 0.760s 28.544us 50 50 100.00
V1 csr_hw_reset pwrmgr_csr_hw_reset 0.690s 36.273us 5 5 100.00
V1 csr_rw pwrmgr_csr_rw 0.720s 35.411us 20 20 100.00
V1 csr_bit_bash pwrmgr_csr_bit_bash 3.450s 1.192ms 5 5 100.00
V1 csr_aliasing pwrmgr_csr_aliasing 0.970s 310.718us 5 5 100.00
V1 csr_mem_rw_with_rand_reset pwrmgr_csr_mem_rw_with_rand_reset 1.650s 54.955us 20 20 100.00
V1 regwen_csr_and_corresponding_lockable_csr pwrmgr_csr_rw 0.720s 35.411us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 310.718us 5 5 100.00
V1 TOTAL 105 105 100.00
V2 wakeup pwrmgr_wakeup 1.300s 270.355us 50 50 100.00
V2 control_clks pwrmgr_wakeup 1.300s 270.355us 50 50 100.00
V2 aborted_low_power pwrmgr_aborted_low_power 1.110s 31.981us 50 50 100.00
pwrmgr_lowpower_invalid 0.790s 42.122us 50 50 100.00
V2 reset pwrmgr_reset 0.990s 78.766us 50 50 100.00
pwrmgr_reset_invalid 1.140s 94.371us 50 50 100.00
V2 main_power_glitch_reset pwrmgr_reset 0.990s 78.766us 50 50 100.00
V2 reset_wakeup_race pwrmgr_wakeup_reset 1.570s 330.560us 50 50 100.00
V2 lowpower_wakeup_race pwrmgr_lowpower_wakeup_race 1.340s 287.281us 50 50 100.00
V2 disable_rom_integrity_check pwrmgr_disable_rom_integrity_check 0.910s 64.024us 50 50 100.00
V2 stress_all pwrmgr_stress_all 7.730s 2.323ms 50 50 100.00
V2 intr_test pwrmgr_intr_test 0.690s 69.730us 50 50 100.00
V2 tl_d_oob_addr_access pwrmgr_tl_errors 2.430s 134.777us 20 20 100.00
V2 tl_d_illegal_access pwrmgr_tl_errors 2.430s 134.777us 20 20 100.00
V2 tl_d_outstanding_access pwrmgr_csr_hw_reset 0.690s 36.273us 5 5 100.00
pwrmgr_csr_rw 0.720s 35.411us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 310.718us 5 5 100.00
pwrmgr_same_csr_outstanding 0.960s 37.056us 20 20 100.00
V2 tl_d_partial_access pwrmgr_csr_hw_reset 0.690s 36.273us 5 5 100.00
pwrmgr_csr_rw 0.720s 35.411us 20 20 100.00
pwrmgr_csr_aliasing 0.970s 310.718us 5 5 100.00
pwrmgr_same_csr_outstanding 0.960s 37.056us 20 20 100.00
V2 TOTAL 540 540 100.00
V2S tl_intg_err pwrmgr_tl_intg_err 1.660s 222.463us 20 20 100.00
pwrmgr_sec_cm 2.120s 599.586us 5 5 100.00
V2S prim_count_check pwrmgr_sec_cm 2.120s 599.586us 5 5 100.00
V2S prim_fsm_check pwrmgr_sec_cm 2.120s 599.586us 5 5 100.00
V2S sec_cm_bus_integrity pwrmgr_tl_intg_err 1.660s 222.463us 20 20 100.00
V2S sec_cm_lc_ctrl_intersig_mubi pwrmgr_sec_cm_lc_ctrl_intersig_mubi 3.300s 837.296us 50 50 100.00
V2S sec_cm_rom_ctrl_intersig_mubi pwrmgr_sec_cm_rom_ctrl_intersig_mubi 3.460s 761.493us 50 50 100.00
V2S sec_cm_rstmgr_intersig_mubi pwrmgr_sec_cm_rstmgr_intersig_mubi 1.060s 64.388us 50 50 100.00
V2S sec_cm_esc_rx_clk_bkgn_chk pwrmgr_esc_clk_rst_malfunc 0.690s 30.639us 50 50 100.00
V2S sec_cm_esc_rx_clk_local_esc pwrmgr_sec_cm 2.120s 599.586us 5 5 100.00
V2S sec_cm_fsm_sparse pwrmgr_sec_cm 2.120s 599.586us 5 5 100.00
V2S sec_cm_fsm_terminal pwrmgr_sec_cm 2.120s 599.586us 5 5 100.00
V2S sec_cm_ctrl_flow_global_esc pwrmgr_global_esc 0.670s 49.081us 50 50 100.00
V2S sec_cm_main_pd_rst_local_esc pwrmgr_glitch 0.720s 63.283us 50 50 100.00
V2S sec_cm_ctrl_config_regwen pwrmgr_sec_cm_ctrl_config_regwen 1.390s 313.175us 50 50 100.00
V2S sec_cm_wakeup_config_regwen pwrmgr_csr_rw 0.720s 35.411us 20 20 100.00
V2S sec_cm_reset_config_regwen pwrmgr_csr_rw 0.720s 35.411us 20 20 100.00
V2S TOTAL 375 375 100.00
V3 escalation_timeout pwrmgr_escalation_timeout 1.070s 166.646us 49 50 98.00
V3 stress_all_with_rand_reset pwrmgr_stress_all_with_rand_reset 37.160s 9.566ms 50 50 100.00
V3 TOTAL 99 100 99.00
TOTAL 1119 1120 99.91

Testplan Progress

Items Total Written Passing Progress
V1 6 6 6 100.00
V2 12 12 12 100.00
V2S 9 9 9 100.00
V3 2 2 1 50.00

Coverage Results

Coverage Dashboard

SCORE LINE COND TOGGLE FSM BRANCH ASSERT GROUP
97.95 98.23 96.58 99.44 96.00 96.37 100.00 99.02

Failure Buckets

Past Results