| T805 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.1108603213 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
22775921 ps |
| T806 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.1343968362 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
74552823 ps |
| T807 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.3106486569 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
100110812 ps |
| T808 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1734392396 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
45629946 ps |
| T809 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.1445856600 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
97646595 ps |
| T810 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2224513532 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
136727272 ps |
| T811 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.1221324026 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
180602831 ps |
| T812 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.2454731626 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
37085823 ps |
| T813 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.2567747931 |
|
|
Aug 25 06:47:56 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
1731785450 ps |
| T814 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.4191921673 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
59825846 ps |
| T815 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.264442343 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
111682699 ps |
| T816 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4247117005 |
|
|
Aug 25 06:48:03 AM UTC 24 |
Aug 25 06:48:16 AM UTC 24 |
52437735 ps |
| T817 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.1178007566 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
49388167 ps |
| T818 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.3776074026 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
36917570 ps |
| T819 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.3371543302 |
|
|
Aug 25 06:48:03 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
37028643 ps |
| T820 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.3455245398 |
|
|
Aug 25 06:48:01 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
124854856 ps |
| T821 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1280251638 |
|
|
Aug 25 06:48:01 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
188909276 ps |
| T822 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.3686086504 |
|
|
Aug 25 06:48:04 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
24569535 ps |
| T823 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2690902363 |
|
|
Aug 25 06:48:01 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
84043516 ps |
| T824 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.2204266071 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
124826998 ps |
| T825 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.758017526 |
|
|
Aug 25 06:48:01 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
31831457 ps |
| T826 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.1548163024 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
225668859 ps |
| T827 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.2883653063 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
186866583 ps |
| T828 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.3809018110 |
|
|
Aug 25 06:48:03 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
2866436520 ps |
| T829 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.3195713032 |
|
|
Aug 25 06:48:03 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
232358041 ps |
| T830 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.3901595704 |
|
|
Aug 25 06:48:01 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
378176614 ps |
| T831 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.559036761 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:17 AM UTC 24 |
85859393 ps |
| T832 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.611257016 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:18 AM UTC 24 |
335979725 ps |
| T833 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.992755542 |
|
|
Aug 25 06:48:03 AM UTC 24 |
Aug 25 06:48:18 AM UTC 24 |
1257291369 ps |
| T834 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4094618331 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:18 AM UTC 24 |
872341554 ps |
| T835 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3782427675 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:18 AM UTC 24 |
769844991 ps |
| T836 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2582618822 |
|
|
Aug 25 06:48:01 AM UTC 24 |
Aug 25 06:48:19 AM UTC 24 |
1356938469 ps |
| T837 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2798583748 |
|
|
Aug 25 06:48:01 AM UTC 24 |
Aug 25 06:48:19 AM UTC 24 |
884458646 ps |
| T838 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4152310277 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:19 AM UTC 24 |
969763284 ps |
| T839 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.402777382 |
|
|
Aug 25 06:48:13 AM UTC 24 |
Aug 25 06:48:20 AM UTC 24 |
163483077 ps |
| T840 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2720832759 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:20 AM UTC 24 |
39886393 ps |
| T841 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.3849454927 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:20 AM UTC 24 |
1354142849 ps |
| T842 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.3599012400 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:25 AM UTC 24 |
50682334 ps |
| T843 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2328890169 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:20 AM UTC 24 |
30216628 ps |
| T844 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.1159163616 |
|
|
Aug 25 06:48:11 AM UTC 24 |
Aug 25 06:48:20 AM UTC 24 |
64494259 ps |
| T845 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3388971224 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:20 AM UTC 24 |
90167320 ps |
| T846 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.1393527998 |
|
|
Aug 25 06:48:11 AM UTC 24 |
Aug 25 06:48:20 AM UTC 24 |
54408150 ps |
| T847 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.872624800 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
64022447 ps |
| T848 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.1897991441 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
381819046 ps |
| T849 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.454316613 |
|
|
Aug 25 06:48:11 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
105828689 ps |
| T850 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2356914681 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
303531914 ps |
| T851 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3476922419 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
133084170 ps |
| T852 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.3453028314 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
32226904 ps |
| T853 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.495607312 |
|
|
Aug 25 06:48:11 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
77115402 ps |
| T854 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.2365607965 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
120747466 ps |
| T855 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.2240535452 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
43125789 ps |
| T856 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.716445993 |
|
|
Aug 25 06:48:03 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
6755311599 ps |
| T857 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.4084710070 |
|
|
Aug 25 06:48:19 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
37506884 ps |
| T858 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.920508292 |
|
|
Aug 25 06:48:11 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
145801401 ps |
| T859 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.2518990350 |
|
|
Aug 25 06:48:15 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
131395021 ps |
| T860 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.764311668 |
|
|
Aug 25 06:48:19 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
108949140 ps |
| T861 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.2524662679 |
|
|
Aug 25 06:47:56 AM UTC 24 |
Aug 25 06:48:21 AM UTC 24 |
3961728177 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.3832590147 |
|
|
Aug 25 06:48:14 AM UTC 24 |
Aug 25 06:48:23 AM UTC 24 |
2281324587 ps |
| T862 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.3954023394 |
|
|
Aug 25 06:48:19 AM UTC 24 |
Aug 25 06:48:25 AM UTC 24 |
154497345 ps |
| T863 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3285353693 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:25 AM UTC 24 |
91926017 ps |
| T864 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.1628488998 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:25 AM UTC 24 |
94082126 ps |
| T865 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3960316695 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:25 AM UTC 24 |
30209179 ps |
| T866 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.2242304995 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:25 AM UTC 24 |
35407718 ps |
| T867 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.1806079895 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:25 AM UTC 24 |
73818014 ps |
| T868 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.2891082164 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:25 AM UTC 24 |
272120647 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.70858437 |
|
|
Aug 25 06:48:05 AM UTC 24 |
Aug 25 06:48:27 AM UTC 24 |
11121879409 ps |
| T869 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.3791726454 |
|
|
Aug 25 06:47:58 AM UTC 24 |
Aug 25 06:48:28 AM UTC 24 |
13262804423 ps |
| T870 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.166131502 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:29 AM UTC 24 |
1803093414 ps |
| T53 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.4164918183 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:33 AM UTC 24 |
2332806718 ps |
| T871 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.1026029154 |
|
|
Aug 25 06:48:20 AM UTC 24 |
Aug 25 06:48:35 AM UTC 24 |
74122070 ps |
| T872 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.822110736 |
|
|
Aug 25 06:48:20 AM UTC 24 |
Aug 25 06:48:36 AM UTC 24 |
74527935 ps |
| T873 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1459827217 |
|
|
Aug 25 06:48:33 AM UTC 24 |
Aug 25 06:48:36 AM UTC 24 |
51639266 ps |
| T874 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.872506934 |
|
|
Aug 25 06:48:37 AM UTC 24 |
Aug 25 06:48:45 AM UTC 24 |
41911242 ps |
| T875 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.3153777473 |
|
|
Aug 25 06:48:20 AM UTC 24 |
Aug 25 06:48:45 AM UTC 24 |
68876910 ps |
| T54 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.3473926893 |
|
|
Aug 25 06:48:37 AM UTC 24 |
Aug 25 06:48:53 AM UTC 24 |
2050102080 ps |
| T876 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.1171075203 |
|
|
Aug 25 06:48:20 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
175128994 ps |
| T877 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.1490634208 |
|
|
Aug 25 06:48:54 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
45948899 ps |
| T878 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.2223722747 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
56468210 ps |
| T879 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.1719020530 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
76315334 ps |
| T880 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.328897805 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
206792796 ps |
| T881 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3066788905 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
20003903 ps |
| T882 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.1824118260 |
|
|
Aug 25 06:48:24 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
28793266 ps |
| T883 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.917905214 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
74078166 ps |
| T884 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.436925744 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
171145043 ps |
| T885 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.1779460903 |
|
|
Aug 25 06:48:27 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
53834400 ps |
| T886 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.387591938 |
|
|
Aug 25 06:48:34 AM UTC 24 |
Aug 25 06:48:56 AM UTC 24 |
151195338 ps |
| T887 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.1154809495 |
|
|
Aug 25 06:48:59 AM UTC 24 |
Aug 25 06:49:52 AM UTC 24 |
185963204 ps |
| T888 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.1890037350 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:57 AM UTC 24 |
197806677 ps |
| T889 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.166018430 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:57 AM UTC 24 |
57041083 ps |
| T890 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2375402424 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:57 AM UTC 24 |
1413144645 ps |
| T891 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.2169002245 |
|
|
Aug 25 06:48:19 AM UTC 24 |
Aug 25 06:48:57 AM UTC 24 |
42404245 ps |
| T892 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3973130439 |
|
|
Aug 25 06:48:42 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
29821647 ps |
| T893 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.2227404282 |
|
|
Aug 25 06:48:19 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
90217249 ps |
| T894 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.682225883 |
|
|
Aug 25 06:48:26 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
31349243 ps |
| T895 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.4278140522 |
|
|
Aug 25 06:48:26 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
198687656 ps |
| T896 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3938948229 |
|
|
Aug 25 06:48:54 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
754223646 ps |
| T897 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.1221916764 |
|
|
Aug 25 06:48:29 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
35665524 ps |
| T898 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.591254836 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
1064849347 ps |
| T899 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1876255335 |
|
|
Aug 25 06:48:17 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
867191623 ps |
| T900 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.3569744418 |
|
|
Aug 25 06:48:21 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
3684561083 ps |
| T901 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.3524084393 |
|
|
Aug 25 06:48:29 AM UTC 24 |
Aug 25 06:48:58 AM UTC 24 |
392674580 ps |
| T902 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3327452697 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:48:59 AM UTC 24 |
831411301 ps |
| T903 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.536143597 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:01 AM UTC 24 |
43289045 ps |
| T904 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.322420584 |
|
|
Aug 25 06:48:16 AM UTC 24 |
Aug 25 06:49:01 AM UTC 24 |
1355576093 ps |
| T905 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.3248242717 |
|
|
Aug 25 06:48:37 AM UTC 24 |
Aug 25 06:49:02 AM UTC 24 |
2186186649 ps |
| T906 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1120992365 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:04 AM UTC 24 |
3461535278 ps |
| T907 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2042761811 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:05 AM UTC 24 |
39424066 ps |
| T908 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.717130719 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:05 AM UTC 24 |
48308844 ps |
| T909 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.2353136625 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:05 AM UTC 24 |
76325530 ps |
| T910 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3475496505 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:05 AM UTC 24 |
53488174 ps |
| T911 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1497041791 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:05 AM UTC 24 |
91093383 ps |
| T912 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.4207656132 |
|
|
Aug 25 06:48:19 AM UTC 24 |
Aug 25 06:49:05 AM UTC 24 |
1826588385 ps |
| T913 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1537084206 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:06 AM UTC 24 |
196947433 ps |
| T914 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.315773632 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:06 AM UTC 24 |
173917991 ps |
| T915 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.891240745 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:06 AM UTC 24 |
104309489 ps |
| T916 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.489640508 |
|
|
Aug 25 06:48:56 AM UTC 24 |
Aug 25 06:49:07 AM UTC 24 |
1237477437 ps |
| T917 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.2404746203 |
|
|
Aug 25 06:48:16 AM UTC 24 |
Aug 25 06:49:09 AM UTC 24 |
3800612837 ps |
| T918 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.1900551453 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:10 AM UTC 24 |
7662347231 ps |
| T919 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.4107371580 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:11 AM UTC 24 |
37654042 ps |
| T920 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.1367002645 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:11 AM UTC 24 |
106671565 ps |
| T921 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.908845708 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:11 AM UTC 24 |
240168969 ps |
| T922 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.2437350968 |
|
|
Aug 25 06:48:46 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
63215382 ps |
| T923 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.436673804 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
279592179 ps |
| T924 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.3838385195 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
199519793 ps |
| T925 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.1280325807 |
|
|
Aug 25 06:48:46 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
96760035 ps |
| T926 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2770725223 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
31520490 ps |
| T927 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.1150274799 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
22997022 ps |
| T928 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.4023893731 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
132246356 ps |
| T929 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.3048540169 |
|
|
Aug 25 06:48:59 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
72171417 ps |
| T930 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3215884894 |
|
|
Aug 25 06:48:26 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
164128081 ps |
| T931 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1284752612 |
|
|
Aug 25 06:48:59 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
53581520 ps |
| T932 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.1010053382 |
|
|
Aug 25 06:48:46 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
224471417 ps |
| T933 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.3748864352 |
|
|
Aug 25 06:48:46 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
362583754 ps |
| T934 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2937377 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:22 AM UTC 24 |
1112312524 ps |
| T935 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2753437559 |
|
|
Aug 25 06:48:58 AM UTC 24 |
Aug 25 06:49:23 AM UTC 24 |
1033533426 ps |
| T936 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.4256567149 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:49:24 AM UTC 24 |
812505971 ps |
| T937 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.109960015 |
|
|
Aug 25 06:48:28 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
73047634 ps |
| T938 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.1534688208 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
461842805 ps |
| T939 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.76523098 |
|
|
Aug 25 06:48:22 AM UTC 24 |
Aug 25 06:49:29 AM UTC 24 |
477824830 ps |
| T940 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.3538957384 |
|
|
Aug 25 06:48:59 AM UTC 24 |
Aug 25 06:49:59 AM UTC 24 |
194793815 ps |
| T941 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.3791918914 |
|
|
Aug 25 06:48:59 AM UTC 24 |
Aug 25 06:50:06 AM UTC 24 |
3495092544 ps |
| T55 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.2594815337 |
|
|
Aug 25 06:49:03 AM UTC 24 |
Aug 25 06:49:05 AM UTC 24 |
173910370 ps |
| T58 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.894427466 |
|
|
Aug 25 06:49:05 AM UTC 24 |
Aug 25 06:49:11 AM UTC 24 |
202666479 ps |
| T73 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1278229800 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:16 AM UTC 24 |
45763104 ps |
| T68 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.383761529 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:16 AM UTC 24 |
92444513 ps |
| T69 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3083428712 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:17 AM UTC 24 |
150031750 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3488996969 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:18 AM UTC 24 |
184883182 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3500191322 |
|
|
Aug 25 06:49:19 AM UTC 24 |
Aug 25 06:49:20 AM UTC 24 |
56015991 ps |
| T61 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.694247471 |
|
|
Aug 25 06:49:08 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
95441619 ps |
| T62 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.1306643964 |
|
|
Aug 25 06:49:17 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
24800595 ps |
| T70 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4048288085 |
|
|
Aug 25 06:49:17 AM UTC 24 |
Aug 25 06:49:21 AM UTC 24 |
57372346 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.4162824570 |
|
|
Aug 25 06:49:18 AM UTC 24 |
Aug 25 06:49:23 AM UTC 24 |
1187287788 ps |
| T79 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1730607457 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:24 AM UTC 24 |
169794363 ps |
| T118 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2135560730 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:40 AM UTC 24 |
31938057 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.2482463901 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:25 AM UTC 24 |
61028025 ps |
| T163 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.1533822 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:25 AM UTC 24 |
43239142 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.825490659 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:25 AM UTC 24 |
21782546 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.2066439689 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:25 AM UTC 24 |
28491163 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.1083992720 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:25 AM UTC 24 |
74126881 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.666831324 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:25 AM UTC 24 |
24176101 ps |
| T80 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2049294711 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:25 AM UTC 24 |
59449894 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1014742287 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
57348465 ps |
| T65 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1741999765 |
|
|
Aug 25 06:49:13 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
161453959 ps |
| T942 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3792415889 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
40726216 ps |
| T943 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3859225151 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
55926592 ps |
| T59 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3104134684 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:31 AM UTC 24 |
117702914 ps |
| T60 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.75351656 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
339827246 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.1500758856 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
67330893 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.947027899 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
38977909 ps |
| T74 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2240792411 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:31 AM UTC 24 |
67179051 ps |
| T944 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.1853780537 |
|
|
Aug 25 06:49:24 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
29714997 ps |
| T162 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.474618327 |
|
|
Aug 25 06:49:23 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
141321340 ps |
| T75 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.187300031 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
82103521 ps |
| T945 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.724909297 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
68308164 ps |
| T946 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.3750580928 |
|
|
Aug 25 06:49:24 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
33467162 ps |
| T947 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.636748733 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
103486234 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.342710832 |
|
|
Aug 25 06:49:24 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
320611238 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.2113287237 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
103022391 ps |
| T948 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4167978940 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
88803252 ps |
| T949 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.849391284 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
55931128 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2097351384 |
|
|
Aug 25 06:49:21 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
29147933 ps |
| T77 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2139232038 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:31 AM UTC 24 |
54056272 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2369980055 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
26167307 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3898531920 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
61677360 ps |
| T950 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3076162127 |
|
|
Aug 25 06:49:21 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
69227447 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3955857807 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
39930815 ps |
| T951 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.3007121725 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
34053486 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.303953198 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
20329831 ps |
| T952 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.680425662 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
191875675 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.4005041233 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
20991159 ps |
| T953 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.1845534377 |
|
|
Aug 25 06:49:21 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
34468043 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.2953059200 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
37519800 ps |
| T954 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.261385432 |
|
|
Aug 25 06:49:11 AM UTC 24 |
Aug 25 06:49:26 AM UTC 24 |
50189527 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.2369712376 |
|
|
Aug 25 06:49:21 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
18468411 ps |
| T955 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2970540716 |
|
|
Aug 25 06:49:21 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
111351525 ps |
| T83 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1603495194 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
135541647 ps |
| T956 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2390629715 |
|
|
Aug 25 06:49:21 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
325985883 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1838513051 |
|
|
Aug 25 06:49:11 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
107767131 ps |
| T78 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3095233782 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
102817962 ps |
| T82 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.1424944182 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
157512966 ps |
| T957 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2986739790 |
|
|
Aug 25 06:49:24 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
54488171 ps |
| T958 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3341540338 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
233446663 ps |
| T959 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.329419301 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
181320947 ps |
| T960 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2755357428 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
330784612 ps |
| T961 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.850112066 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
56148164 ps |
| T962 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3099904656 |
|
|
Aug 25 06:49:21 AM UTC 24 |
Aug 25 06:49:27 AM UTC 24 |
142355061 ps |
| T963 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1174504012 |
|
|
Aug 25 06:49:11 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
684124406 ps |
| T964 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3517809770 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
76018915 ps |
| T965 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.410046984 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
17545938 ps |
| T81 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3285633230 |
|
|
Aug 25 06:49:25 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
235919816 ps |
| T966 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.439380805 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
24392751 ps |
| T967 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2501265018 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
58218113 ps |
| T968 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2880248702 |
|
|
Aug 25 06:49:22 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
282429085 ps |
| T969 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.3499949341 |
|
|
Aug 25 06:49:25 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
44260403 ps |
| T84 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2260049158 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
105889954 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3229169335 |
|
|
Aug 25 06:49:07 AM UTC 24 |
Aug 25 06:49:28 AM UTC 24 |
1884106190 ps |
| T970 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2705291672 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:29 AM UTC 24 |
48372958 ps |
| T971 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3001469459 |
|
|
Aug 25 06:49:01 AM UTC 24 |
Aug 25 06:49:29 AM UTC 24 |
443002447 ps |
| T972 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2416861968 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:29 AM UTC 24 |
128450848 ps |
| T973 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.89775083 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:30 AM UTC 24 |
44239820 ps |
| T974 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.770904670 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:30 AM UTC 24 |
34641102 ps |
| T975 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1735918192 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:30 AM UTC 24 |
23020062 ps |
| T976 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2791007532 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:30 AM UTC 24 |
96135899 ps |
| T977 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3663670796 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:30 AM UTC 24 |
149420114 ps |
| T978 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1525493070 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:31 AM UTC 24 |
97919665 ps |
| T979 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.71569895 |
|
|
Aug 25 06:49:17 AM UTC 24 |
Aug 25 06:49:34 AM UTC 24 |
26903243 ps |
| T980 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.575464576 |
|
|
Aug 25 06:49:32 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
23723301 ps |
| T981 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.409774830 |
|
|
Aug 25 06:49:31 AM UTC 24 |
Aug 25 06:49:56 AM UTC 24 |
75415612 ps |
| T982 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.4185258971 |
|
|
Aug 25 06:49:32 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
124860990 ps |
| T983 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.1983924486 |
|
|
Aug 25 06:49:32 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
29194613 ps |
| T984 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1977970897 |
|
|
Aug 25 06:49:26 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
32662280 ps |
| T985 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.4228098117 |
|
|
Aug 25 06:49:32 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
211704760 ps |
| T986 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2709478871 |
|
|
Aug 25 06:49:32 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
20722326 ps |
| T987 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.861354755 |
|
|
Aug 25 06:49:32 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
43007111 ps |
| T988 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1392098327 |
|
|
Aug 25 06:49:33 AM UTC 24 |
Aug 25 06:49:36 AM UTC 24 |
46901263 ps |
| T989 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3362476835 |
|
|
Aug 25 06:49:32 AM UTC 24 |
Aug 25 06:49:36 AM UTC 24 |
21836279 ps |
| T990 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.1731835374 |
|
|
Aug 25 06:49:33 AM UTC 24 |
Aug 25 06:49:36 AM UTC 24 |
22036496 ps |
| T991 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2942124136 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:40 AM UTC 24 |
41591730 ps |
| T992 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.2669805664 |
|
|
Aug 25 06:49:37 AM UTC 24 |
Aug 25 06:49:40 AM UTC 24 |
18454480 ps |
| T993 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2528947989 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:40 AM UTC 24 |
86926897 ps |
| T994 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.4010352369 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:40 AM UTC 24 |
89695223 ps |
| T995 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.3304299688 |
|
|
Aug 25 06:49:29 AM UTC 24 |
Aug 25 06:49:40 AM UTC 24 |
36863386 ps |
| T996 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.3182719781 |
|
|
Aug 25 06:49:29 AM UTC 24 |
Aug 25 06:49:40 AM UTC 24 |
22494825 ps |
| T997 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3786759241 |
|
|
Aug 25 06:49:28 AM UTC 24 |
Aug 25 06:49:41 AM UTC 24 |
124814949 ps |
| T998 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1907561480 |
|
|
Aug 25 06:49:29 AM UTC 24 |
Aug 25 06:49:41 AM UTC 24 |
68324261 ps |
| T161 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2323484520 |
|
|
Aug 25 06:49:29 AM UTC 24 |
Aug 25 06:49:41 AM UTC 24 |
261156041 ps |
| T999 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.583715203 |
|
|
Aug 25 06:49:29 AM UTC 24 |
Aug 25 06:49:42 AM UTC 24 |
98639769 ps |
| T1000 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.1999088339 |
|
|
Aug 25 06:49:36 AM UTC 24 |
Aug 25 06:49:45 AM UTC 24 |
22587744 ps |
| T1001 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.3620272793 |
|
|
Aug 25 06:49:41 AM UTC 24 |
Aug 25 06:49:45 AM UTC 24 |
55720706 ps |
| T1002 |
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1707664520 |
|
|
Aug 25 06:49:31 AM UTC 24 |
Aug 25 06:49:57 AM UTC 24 |
150490380 ps |