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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.97 98.23 96.58 99.62 96.00 96.37 100.00 99.02


Total test records in report: 1054
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html
T1003 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.2521226066 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 19637626 ps
T1004 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.4049007196 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 42649936 ps
T1005 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.3709538355 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 26118242 ps
T1006 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1615067569 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 51985037 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.858313506 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 36537175 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.2606341609 Aug 25 06:49:35 AM UTC 24 Aug 25 06:49:57 AM UTC 24 17984819 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.308612436 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:51 AM UTC 24 29378271 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.165526930 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 62994554 ps
T1011 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3928222064 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 53574444 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.635754271 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 49088029 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2083153542 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:57 AM UTC 24 197825018 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1680528261 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:51 AM UTC 24 21333023 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.649164768 Aug 25 06:49:28 AM UTC 24 Aug 25 06:49:51 AM UTC 24 53359247 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.3073982649 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:51 AM UTC 24 19110802 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.3839567159 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:51 AM UTC 24 22411935 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.2367280395 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:51 AM UTC 24 70528904 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.2309989567 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:51 AM UTC 24 18924401 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.715447510 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:52 AM UTC 24 16655237 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.3197759829 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:52 AM UTC 24 35324564 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2179770470 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:52 AM UTC 24 41582998 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.798363209 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:52 AM UTC 24 35126495 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3275423234 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:52 AM UTC 24 16390466 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2839447829 Aug 25 06:49:12 AM UTC 24 Aug 25 06:49:52 AM UTC 24 54089239 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.396011432 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:52 AM UTC 24 101910907 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.1871792476 Aug 25 06:49:36 AM UTC 24 Aug 25 06:49:52 AM UTC 24 19852525 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3099424590 Aug 25 06:49:28 AM UTC 24 Aug 25 06:49:52 AM UTC 24 143859320 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.897498438 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:52 AM UTC 24 84137959 ps
T85 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2497143071 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:52 AM UTC 24 378184342 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1422534681 Aug 25 06:49:28 AM UTC 24 Aug 25 06:49:52 AM UTC 24 141470391 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.2662418124 Aug 25 06:49:28 AM UTC 24 Aug 25 06:49:53 AM UTC 24 81951986 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1328582395 Aug 25 06:49:29 AM UTC 24 Aug 25 06:49:53 AM UTC 24 104387822 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.89707551 Aug 25 06:49:12 AM UTC 24 Aug 25 06:49:53 AM UTC 24 127450628 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.3429586822 Aug 25 06:49:10 AM UTC 24 Aug 25 06:49:55 AM UTC 24 50189637 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.1561271465 Aug 25 06:49:41 AM UTC 24 Aug 25 06:49:56 AM UTC 24 21647102 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.2771632125 Aug 25 06:49:41 AM UTC 24 Aug 25 06:49:56 AM UTC 24 46515281 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.2669517904 Aug 25 06:49:41 AM UTC 24 Aug 25 06:49:56 AM UTC 24 36403208 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.2153901799 Aug 25 06:49:41 AM UTC 24 Aug 25 06:49:56 AM UTC 24 20289697 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.3329903203 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 21777605 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.579759466 Aug 25 06:49:41 AM UTC 24 Aug 25 06:49:56 AM UTC 24 17365255 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2169545950 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 341374196 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2935119492 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 53140204 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3922379587 Aug 25 06:49:33 AM UTC 24 Aug 25 06:49:56 AM UTC 24 87410792 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.879110325 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 83679724 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.170037044 Aug 25 06:49:33 AM UTC 24 Aug 25 06:49:56 AM UTC 24 26514750 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3367145386 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 77484178 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.42655208 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 21227745 ps
T124 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.764369286 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 18093186 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1809238709 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 49793487 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.3512879076 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 154087937 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.19943861 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:57 AM UTC 24 111261219 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.2786663864 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 17609880 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3954002243 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:56 AM UTC 24 686843178 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3043181056 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:57 AM UTC 24 172015308 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.387273273 Aug 25 06:49:31 AM UTC 24 Aug 25 06:49:58 AM UTC 24 277277624 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.2997437921
Short name T9
Test name
Test status
Simulation time 365125651 ps
CPU time 1.91 seconds
Started Aug 25 06:45:23 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997437921 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.2997437921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.3449009095
Short name T38
Test name
Test status
Simulation time 100067166 ps
CPU time 1.47 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:28 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449009095 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3449009095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.2900892021
Short name T48
Test name
Test status
Simulation time 2931428135 ps
CPU time 7.05 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 211612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2900892021 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.2900892021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.3662341977
Short name T29
Test name
Test status
Simulation time 623135051 ps
CPU time 3.45 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 238816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662341977 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.3662341977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.651614145
Short name T56
Test name
Test status
Simulation time 3554761014 ps
CPU time 16.77 seconds
Started Aug 25 06:45:50 AM UTC 24
Finished Aug 25 06:46:08 AM UTC 24
Peak memory 211692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=651614145 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_
stress_all_with_rand_reset.651614145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4164489231
Short name T14
Test name
Test status
Simulation time 1000585540 ps
CPU time 4.07 seconds
Started Aug 25 06:45:23 AM UTC 24
Finished Aug 25 06:45:28 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4164489231 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.4164489231
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.894427466
Short name T58
Test name
Test status
Simulation time 202666479 ps
CPU time 1.53 seconds
Started Aug 25 06:49:05 AM UTC 24
Finished Aug 25 06:49:11 AM UTC 24
Peak memory 211360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894427466 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.894427466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.396400852
Short name T44
Test name
Test status
Simulation time 151643210 ps
CPU time 0.91 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:28 AM UTC 24
Peak memory 210916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396400852 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid.396400852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2505724542
Short name T67
Test name
Test status
Simulation time 246277108 ps
CPU time 1.42 seconds
Started Aug 25 06:45:31 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505724542 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.2505724542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.947027899
Short name T167
Test name
Test status
Simulation time 38977909 ps
CPU time 0.6 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 206656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947027899 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.947027899
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.2031835336
Short name T11
Test name
Test status
Simulation time 111912850 ps
CPU time 1.36 seconds
Started Aug 25 06:45:24 AM UTC 24
Finished Aug 25 06:45:27 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2031835336 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.2031835336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2135560730
Short name T118
Test name
Test status
Simulation time 31938057 ps
CPU time 0.66 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:40 AM UTC 24
Peak memory 209168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135560730 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2135560730
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.1424944182
Short name T82
Test name
Test status
Simulation time 157512966 ps
CPU time 2.25 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1424944182 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.1424944182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.735166814
Short name T107
Test name
Test status
Simulation time 58881068 ps
CPU time 1.22 seconds
Started Aug 25 06:45:49 AM UTC 24
Finished Aug 25 06:45:51 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=735166814 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.735166814
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.4169201680
Short name T291
Test name
Test status
Simulation time 63907843 ps
CPU time 1.16 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 210720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169201680 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.4169201680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.3104134684
Short name T59
Test name
Test status
Simulation time 117702914 ps
CPU time 1.13 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:31 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3104134684 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.3104134684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.3747083496
Short name T24
Test name
Test status
Simulation time 10399532342 ps
CPU time 22.15 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:50 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3747083496 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr
_stress_all_with_rand_reset.3747083496
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.3955857807
Short name T121
Test name
Test status
Simulation time 39930815 ps
CPU time 0.63 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 208384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955857807 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.3955857807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.1500758856
Short name T166
Test name
Test status
Simulation time 67330893 ps
CPU time 0.6 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 206808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1500758856 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.1500758856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2831791298
Short name T177
Test name
Test status
Simulation time 78683844 ps
CPU time 0.65 seconds
Started Aug 25 06:46:41 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831791298 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.2831791298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3539760689
Short name T175
Test name
Test status
Simulation time 50729639 ps
CPU time 0.91 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 210696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539760689 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.3539760689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.1603495194
Short name T83
Test name
Test status
Simulation time 135541647 ps
CPU time 1.06 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603495194 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.1603495194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.860858392
Short name T282
Test name
Test status
Simulation time 76216811 ps
CPU time 0.82 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=860858392 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.860858392
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.4167978940
Short name T948
Test name
Test status
Simulation time 88803252 ps
CPU time 0.79 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167978940 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.4167978940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.3083428712
Short name T69
Test name
Test status
Simulation time 150031750 ps
CPU time 1.84 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:17 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083428712 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.3083428712
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3859225151
Short name T943
Test name
Test status
Simulation time 55926592 ps
CPU time 0.59 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 206664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859225151 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3859225151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.1278229800
Short name T73
Test name
Test status
Simulation time 45763104 ps
CPU time 0.89 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:16 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1278229800 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_w
ith_rand_reset.1278229800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.724909297
Short name T945
Test name
Test status
Simulation time 68308164 ps
CPU time 0.67 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 206780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=724909297 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.724909297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.2369980055
Short name T131
Test name
Test status
Simulation time 26167307 ps
CPU time 0.96 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369980055 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_same_csr_outstanding.2369980055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3095233782
Short name T78
Test name
Test status
Simulation time 102817962 ps
CPU time 1.58 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095233782 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3095233782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.680425662
Short name T952
Test name
Test status
Simulation time 191875675 ps
CPU time 1.1 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680425662 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.680425662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.383761529
Short name T68
Test name
Test status
Simulation time 92444513 ps
CPU time 0.71 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:16 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383761529 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.383761529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.3001469459
Short name T971
Test name
Test status
Simulation time 443002447 ps
CPU time 3.11 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:29 AM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3001469459 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.3001469459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.2953059200
Short name T133
Test name
Test status
Simulation time 37519800 ps
CPU time 0.71 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 209412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953059200 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.2953059200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.4005041233
Short name T169
Test name
Test status
Simulation time 20991159 ps
CPU time 0.73 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 207148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005041233 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.4005041233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2755357428
Short name T960
Test name
Test status
Simulation time 330784612 ps
CPU time 1.95 seconds
Started Aug 25 06:49:01 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755357428 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2755357428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.2705291672
Short name T970
Test name
Test status
Simulation time 48372958 ps
CPU time 1.2 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:29 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2705291672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_
with_rand_reset.2705291672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.3898531920
Short name T132
Test name
Test status
Simulation time 61677360 ps
CPU time 0.59 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 209204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898531920 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.3898531920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.1977970897
Short name T984
Test name
Test status
Simulation time 32662280 ps
CPU time 0.76 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 209360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977970897 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.1977970897
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.2416861968
Short name T972
Test name
Test status
Simulation time 128450848 ps
CPU time 2.17 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:29 AM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416861968 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.2416861968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.2260049158
Short name T84
Test name
Test status
Simulation time 105889954 ps
CPU time 1.12 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260049158 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.2260049158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.2528947989
Short name T993
Test name
Test status
Simulation time 86926897 ps
CPU time 0.99 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:40 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2528947989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_
with_rand_reset.2528947989
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3099424590
Short name T1028
Test name
Test status
Simulation time 143859320 ps
CPU time 0.82 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099424590 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3099424590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.649164768
Short name T1015
Test name
Test status
Simulation time 53359247 ps
CPU time 0.69 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=649164768 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.649164768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2942124136
Short name T991
Test name
Test status
Simulation time 41591730 ps
CPU time 0.78 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:40 AM UTC 24
Peak memory 210548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942124136 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.2942124136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.2662418124
Short name T1031
Test name
Test status
Simulation time 81951986 ps
CPU time 1.95 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:53 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2662418124 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.2662418124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1422534681
Short name T1030
Test name
Test status
Simulation time 141470391 ps
CPU time 1.18 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422534681 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.1422534681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.3663670796
Short name T977
Test name
Test status
Simulation time 149420114 ps
CPU time 0.75 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:30 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3663670796 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_
with_rand_reset.3663670796
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.89775083
Short name T973
Test name
Test status
Simulation time 44239820 ps
CPU time 0.56 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:30 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89775083 -assert nopostproc +UVM_TESTNAME=pwrmgr_
base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.89775083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.770904670
Short name T974
Test name
Test status
Simulation time 34641102 ps
CPU time 0.69 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:30 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770904670 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.770904670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.2791007532
Short name T976
Test name
Test status
Simulation time 96135899 ps
CPU time 0.74 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:30 AM UTC 24
Peak memory 210188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791007532 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.2791007532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.2240792411
Short name T74
Test name
Test status
Simulation time 67179051 ps
CPU time 1.41 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:31 AM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240792411 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.2240792411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1525493070
Short name T978
Test name
Test status
Simulation time 97919665 ps
CPU time 1.06 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:31 AM UTC 24
Peak memory 211248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1525493070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_
with_rand_reset.1525493070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.1735918192
Short name T975
Test name
Test status
Simulation time 23020062 ps
CPU time 0.56 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:30 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735918192 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.1735918192
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.4010352369
Short name T994
Test name
Test status
Simulation time 89695223 ps
CPU time 0.66 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:40 AM UTC 24
Peak memory 209096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010352369 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.4010352369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2139232038
Short name T77
Test name
Test status
Simulation time 54056272 ps
CPU time 1.73 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:31 AM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139232038 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2139232038
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3786759241
Short name T997
Test name
Test status
Simulation time 124814949 ps
CPU time 0.97 seconds
Started Aug 25 06:49:28 AM UTC 24
Finished Aug 25 06:49:41 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786759241 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.3786759241
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.3928222064
Short name T1011
Test name
Test status
Simulation time 53574444 ps
CPU time 1.03 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 209712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3928222064 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_
with_rand_reset.3928222064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.3182719781
Short name T996
Test name
Test status
Simulation time 22494825 ps
CPU time 0.62 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:40 AM UTC 24
Peak memory 209408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3182719781 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3182719781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.3304299688
Short name T995
Test name
Test status
Simulation time 36863386 ps
CPU time 0.54 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:40 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304299688 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.3304299688
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.1907561480
Short name T998
Test name
Test status
Simulation time 68324261 ps
CPU time 0.75 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:41 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907561480 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.1907561480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.583715203
Short name T999
Test name
Test status
Simulation time 98639769 ps
CPU time 1.96 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:42 AM UTC 24
Peak memory 210712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583715203 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.583715203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.2323484520
Short name T161
Test name
Test status
Simulation time 261156041 ps
CPU time 1.42 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:41 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323484520 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.2323484520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.897498438
Short name T1029
Test name
Test status
Simulation time 84137959 ps
CPU time 1.36 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=897498438 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_w
ith_rand_reset.897498438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.2521226066
Short name T1003
Test name
Test status
Simulation time 19637626 ps
CPU time 0.58 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 208388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521226066 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.2521226066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.4049007196
Short name T1004
Test name
Test status
Simulation time 42649936 ps
CPU time 0.61 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049007196 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.4049007196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.858313506
Short name T1007
Test name
Test status
Simulation time 36537175 ps
CPU time 0.84 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 209672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=858313506 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.858313506
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.635754271
Short name T1012
Test name
Test status
Simulation time 49088029 ps
CPU time 1.27 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=635754271 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.635754271
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.396011432
Short name T1026
Test name
Test status
Simulation time 101910907 ps
CPU time 1.27 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396011432 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.396011432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.1615067569
Short name T1006
Test name
Test status
Simulation time 51985037 ps
CPU time 0.81 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1615067569 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_
with_rand_reset.1615067569
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1680528261
Short name T1014
Test name
Test status
Simulation time 21333023 ps
CPU time 0.66 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 208500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680528261 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1680528261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.3709538355
Short name T1005
Test name
Test status
Simulation time 26118242 ps
CPU time 0.59 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709538355 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.3709538355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.165526930
Short name T1010
Test name
Test status
Simulation time 62994554 ps
CPU time 0.83 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165526930 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.165526930
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1328582395
Short name T1032
Test name
Test status
Simulation time 104387822 ps
CPU time 2.44 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:53 AM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328582395 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1328582395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2497143071
Short name T85
Test name
Test status
Simulation time 378184342 ps
CPU time 1.36 seconds
Started Aug 25 06:49:29 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497143071 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.2497143071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.409774830
Short name T981
Test name
Test status
Simulation time 75415612 ps
CPU time 1.06 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 209836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=409774830 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_w
ith_rand_reset.409774830
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.3329903203
Short name T1039
Test name
Test status
Simulation time 21777605 ps
CPU time 0.62 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329903203 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.3329903203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2935119492
Short name T1042
Test name
Test status
Simulation time 53140204 ps
CPU time 0.65 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 206936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935119492 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2935119492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2169545950
Short name T1041
Test name
Test status
Simulation time 341374196 ps
CPU time 0.86 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 209988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169545950 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.2169545950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.3512879076
Short name T1049
Test name
Test status
Simulation time 154087937 ps
CPU time 1.12 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512879076 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.3512879076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.3954002243
Short name T1052
Test name
Test status
Simulation time 686843178 ps
CPU time 1.17 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 208284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954002243 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.3954002243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3043181056
Short name T1053
Test name
Test status
Simulation time 172015308 ps
CPU time 0.89 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3043181056 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_
with_rand_reset.3043181056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.764369286
Short name T124
Test name
Test status
Simulation time 18093186 ps
CPU time 0.6 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 208320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764369286 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.764369286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.42655208
Short name T1047
Test name
Test status
Simulation time 21227745 ps
CPU time 0.71 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42655208 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.42655208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.3367145386
Short name T1046
Test name
Test status
Simulation time 77484178 ps
CPU time 0.8 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367145386 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.3367145386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.19943861
Short name T1050
Test name
Test status
Simulation time 111261219 ps
CPU time 1.82 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=19943861 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.19943861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.2083153542
Short name T1013
Test name
Test status
Simulation time 197825018 ps
CPU time 1.66 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 211184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2083153542 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.2083153542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.4228098117
Short name T985
Test name
Test status
Simulation time 211704760 ps
CPU time 0.65 seconds
Started Aug 25 06:49:32 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4228098117 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_
with_rand_reset.4228098117
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.879110325
Short name T1044
Test name
Test status
Simulation time 83679724 ps
CPU time 0.55 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 208548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=879110325 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.879110325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.2786663864
Short name T1051
Test name
Test status
Simulation time 17609880 ps
CPU time 0.6 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2786663864 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.2786663864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1809238709
Short name T1048
Test name
Test status
Simulation time 49793487 ps
CPU time 0.65 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 209364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1809238709 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.1809238709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.387273273
Short name T1054
Test name
Test status
Simulation time 277277624 ps
CPU time 1.75 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:58 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387273273 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.387273273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.1707664520
Short name T1002
Test name
Test status
Simulation time 150490380 ps
CPU time 1.23 seconds
Started Aug 25 06:49:31 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 209820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707664520 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.1707664520
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.636748733
Short name T947
Test name
Test status
Simulation time 103486234 ps
CPU time 0.72 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 209256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636748733 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.636748733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.3229169335
Short name T125
Test name
Test status
Simulation time 1884106190 ps
CPU time 3.11 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229169335 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.3229169335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1730607457
Short name T79
Test name
Test status
Simulation time 169794363 ps
CPU time 0.61 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:24 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730607457 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1730607457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.849391284
Short name T949
Test name
Test status
Simulation time 55931128 ps
CPU time 0.78 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=849391284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_wi
th_rand_reset.849391284
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.2113287237
Short name T120
Test name
Test status
Simulation time 103022391 ps
CPU time 0.61 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113287237 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2113287237
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.666831324
Short name T165
Test name
Test status
Simulation time 24176101 ps
CPU time 0.54 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:25 AM UTC 24
Peak memory 206928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666831324 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.666831324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3488996969
Short name T126
Test name
Test status
Simulation time 184883182 ps
CPU time 0.79 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:18 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3488996969 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.3488996969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.2594815337
Short name T55
Test name
Test status
Simulation time 173910370 ps
CPU time 1.05 seconds
Started Aug 25 06:49:03 AM UTC 24
Finished Aug 25 06:49:05 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594815337 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.2594815337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.575464576
Short name T980
Test name
Test status
Simulation time 23723301 ps
CPU time 0.55 seconds
Started Aug 25 06:49:32 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575464576 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.575464576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.1983924486
Short name T983
Test name
Test status
Simulation time 29194613 ps
CPU time 0.54 seconds
Started Aug 25 06:49:32 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983924486 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.1983924486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.4185258971
Short name T982
Test name
Test status
Simulation time 124860990 ps
CPU time 0.57 seconds
Started Aug 25 06:49:32 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4185258971 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.4185258971
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.861354755
Short name T987
Test name
Test status
Simulation time 43007111 ps
CPU time 0.5 seconds
Started Aug 25 06:49:32 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861354755 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.861354755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2709478871
Short name T986
Test name
Test status
Simulation time 20722326 ps
CPU time 0.57 seconds
Started Aug 25 06:49:32 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709478871 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2709478871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.3362476835
Short name T989
Test name
Test status
Simulation time 21836279 ps
CPU time 0.58 seconds
Started Aug 25 06:49:32 AM UTC 24
Finished Aug 25 06:49:36 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362476835 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.3362476835
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.1392098327
Short name T988
Test name
Test status
Simulation time 46901263 ps
CPU time 0.55 seconds
Started Aug 25 06:49:33 AM UTC 24
Finished Aug 25 06:49:36 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392098327 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.1392098327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.170037044
Short name T1045
Test name
Test status
Simulation time 26514750 ps
CPU time 0.78 seconds
Started Aug 25 06:49:33 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170037044 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.170037044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.3922379587
Short name T1043
Test name
Test status
Simulation time 87410792 ps
CPU time 0.7 seconds
Started Aug 25 06:49:33 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 206952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922379587 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.3922379587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.1731835374
Short name T990
Test name
Test status
Simulation time 22036496 ps
CPU time 0.53 seconds
Started Aug 25 06:49:33 AM UTC 24
Finished Aug 25 06:49:36 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731835374 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.1731835374
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.1838513051
Short name T123
Test name
Test status
Simulation time 107767131 ps
CPU time 0.93 seconds
Started Aug 25 06:49:11 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 209824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838513051 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.1838513051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1174504012
Short name T963
Test name
Test status
Simulation time 684124406 ps
CPU time 1.79 seconds
Started Aug 25 06:49:11 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 208740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174504012 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1174504012
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.694247471
Short name T61
Test name
Test status
Simulation time 95441619 ps
CPU time 0.58 seconds
Started Aug 25 06:49:08 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=694247471 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.694247471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.2839447829
Short name T1025
Test name
Test status
Simulation time 54089239 ps
CPU time 0.93 seconds
Started Aug 25 06:49:12 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2839447829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_w
ith_rand_reset.2839447829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.3429586822
Short name T1034
Test name
Test status
Simulation time 50189637 ps
CPU time 0.55 seconds
Started Aug 25 06:49:10 AM UTC 24
Finished Aug 25 06:49:55 AM UTC 24
Peak memory 208456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429586822 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.3429586822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.303953198
Short name T168
Test name
Test status
Simulation time 20329831 ps
CPU time 0.71 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303953198 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.303953198
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.261385432
Short name T954
Test name
Test status
Simulation time 50189527 ps
CPU time 0.68 seconds
Started Aug 25 06:49:11 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261385432 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.261385432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3341540338
Short name T958
Test name
Test status
Simulation time 233446663 ps
CPU time 1.7 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341540338 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3341540338
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.329419301
Short name T959
Test name
Test status
Simulation time 181320947 ps
CPU time 1.67 seconds
Started Aug 25 06:49:07 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=329419301 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.329419301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.2606341609
Short name T1008
Test name
Test status
Simulation time 17984819 ps
CPU time 0.56 seconds
Started Aug 25 06:49:35 AM UTC 24
Finished Aug 25 06:49:57 AM UTC 24
Peak memory 207076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2606341609 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.2606341609
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.3073982649
Short name T1016
Test name
Test status
Simulation time 19110802 ps
CPU time 0.73 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3073982649 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.3073982649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.308612436
Short name T1009
Test name
Test status
Simulation time 29378271 ps
CPU time 0.6 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 206992 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308612436 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.308612436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.798363209
Short name T1023
Test name
Test status
Simulation time 35126495 ps
CPU time 0.71 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798363209 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.798363209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.2309989567
Short name T1019
Test name
Test status
Simulation time 18924401 ps
CPU time 0.67 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309989567 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.2309989567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.3197759829
Short name T1021
Test name
Test status
Simulation time 35324564 ps
CPU time 0.77 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197759829 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3197759829
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.2367280395
Short name T1018
Test name
Test status
Simulation time 70528904 ps
CPU time 0.58 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367280395 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.2367280395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.3839567159
Short name T1017
Test name
Test status
Simulation time 22411935 ps
CPU time 0.72 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:51 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3839567159 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.3839567159
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.1871792476
Short name T1027
Test name
Test status
Simulation time 19852525 ps
CPU time 0.68 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871792476 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.1871792476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.2179770470
Short name T1022
Test name
Test status
Simulation time 41582998 ps
CPU time 0.6 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2179770470 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.2179770470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.3500191322
Short name T117
Test name
Test status
Simulation time 56015991 ps
CPU time 0.69 seconds
Started Aug 25 06:49:19 AM UTC 24
Finished Aug 25 06:49:20 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500191322 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.3500191322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.4162824570
Short name T170
Test name
Test status
Simulation time 1187287788 ps
CPU time 3.22 seconds
Started Aug 25 06:49:18 AM UTC 24
Finished Aug 25 06:49:23 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162824570 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.4162824570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.71569895
Short name T979
Test name
Test status
Simulation time 26903243 ps
CPU time 0.6 seconds
Started Aug 25 06:49:17 AM UTC 24
Finished Aug 25 06:49:34 AM UTC 24
Peak memory 209044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71569895 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.71569895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.3076162127
Short name T950
Test name
Test status
Simulation time 69227447 ps
CPU time 0.98 seconds
Started Aug 25 06:49:21 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 209832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3076162127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_w
ith_rand_reset.3076162127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.4048288085
Short name T70
Test name
Test status
Simulation time 57372346 ps
CPU time 0.57 seconds
Started Aug 25 06:49:17 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048288085 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.4048288085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.1306643964
Short name T62
Test name
Test status
Simulation time 24800595 ps
CPU time 0.54 seconds
Started Aug 25 06:49:17 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1306643964 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.1306643964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.2097351384
Short name T130
Test name
Test status
Simulation time 29147933 ps
CPU time 0.76 seconds
Started Aug 25 06:49:21 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 208836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097351384 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.2097351384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.89707551
Short name T1033
Test name
Test status
Simulation time 127450628 ps
CPU time 2.32 seconds
Started Aug 25 06:49:12 AM UTC 24
Finished Aug 25 06:49:53 AM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=89707551 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.89707551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.1741999765
Short name T65
Test name
Test status
Simulation time 161453959 ps
CPU time 1 seconds
Started Aug 25 06:49:13 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1741999765 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.1741999765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3275423234
Short name T1024
Test name
Test status
Simulation time 16390466 ps
CPU time 0.58 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275423234 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3275423234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.715447510
Short name T1020
Test name
Test status
Simulation time 16655237 ps
CPU time 0.71 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715447510 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.715447510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.1999088339
Short name T1000
Test name
Test status
Simulation time 22587744 ps
CPU time 0.56 seconds
Started Aug 25 06:49:36 AM UTC 24
Finished Aug 25 06:49:45 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1999088339 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.1999088339
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.2669805664
Short name T992
Test name
Test status
Simulation time 18454480 ps
CPU time 0.55 seconds
Started Aug 25 06:49:37 AM UTC 24
Finished Aug 25 06:49:40 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669805664 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2669805664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.1561271465
Short name T1035
Test name
Test status
Simulation time 21647102 ps
CPU time 0.75 seconds
Started Aug 25 06:49:41 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561271465 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1561271465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.3620272793
Short name T1001
Test name
Test status
Simulation time 55720706 ps
CPU time 0.59 seconds
Started Aug 25 06:49:41 AM UTC 24
Finished Aug 25 06:49:45 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3620272793 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.3620272793
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.2153901799
Short name T1038
Test name
Test status
Simulation time 20289697 ps
CPU time 0.64 seconds
Started Aug 25 06:49:41 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 206876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153901799 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.2153901799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.579759466
Short name T1040
Test name
Test status
Simulation time 17365255 ps
CPU time 0.58 seconds
Started Aug 25 06:49:41 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=579759466 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.579759466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.2771632125
Short name T1036
Test name
Test status
Simulation time 46515281 ps
CPU time 0.56 seconds
Started Aug 25 06:49:41 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771632125 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.2771632125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.2669517904
Short name T1037
Test name
Test status
Simulation time 36403208 ps
CPU time 0.54 seconds
Started Aug 25 06:49:41 AM UTC 24
Finished Aug 25 06:49:56 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2669517904 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2669517904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.850112066
Short name T961
Test name
Test status
Simulation time 56148164 ps
CPU time 0.93 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=850112066 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_wi
th_rand_reset.850112066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.2369712376
Short name T122
Test name
Test status
Simulation time 18468411 ps
CPU time 0.74 seconds
Started Aug 25 06:49:21 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369712376 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.2369712376
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.1845534377
Short name T953
Test name
Test status
Simulation time 34468043 ps
CPU time 0.72 seconds
Started Aug 25 06:49:21 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 206884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845534377 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.1845534377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2970540716
Short name T955
Test name
Test status
Simulation time 111351525 ps
CPU time 0.98 seconds
Started Aug 25 06:49:21 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2970540716 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.2970540716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3099904656
Short name T962
Test name
Test status
Simulation time 142355061 ps
CPU time 1.75 seconds
Started Aug 25 06:49:21 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 210980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099904656 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3099904656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2390629715
Short name T956
Test name
Test status
Simulation time 325985883 ps
CPU time 1.12 seconds
Started Aug 25 06:49:21 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390629715 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.2390629715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2049294711
Short name T80
Test name
Test status
Simulation time 59449894 ps
CPU time 0.97 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:25 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2049294711 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_w
ith_rand_reset.2049294711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.2482463901
Short name T171
Test name
Test status
Simulation time 61028025 ps
CPU time 0.6 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:25 AM UTC 24
Peak memory 209012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482463901 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.2482463901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.1533822
Short name T163
Test name
Test status
Simulation time 43239142 ps
CPU time 0.63 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:25 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base
_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwr
mgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.1533822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.825490659
Short name T127
Test name
Test status
Simulation time 21782546 ps
CPU time 0.7 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:25 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=825490659 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.825490659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.187300031
Short name T75
Test name
Test status
Simulation time 82103521 ps
CPU time 1.61 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=187300031 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.187300031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.2880248702
Short name T968
Test name
Test status
Simulation time 282429085 ps
CPU time 1.54 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880248702 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.2880248702
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.3792415889
Short name T942
Test name
Test status
Simulation time 40726216 ps
CPU time 0.77 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3792415889 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_w
ith_rand_reset.3792415889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.2066439689
Short name T119
Test name
Test status
Simulation time 28491163 ps
CPU time 0.6 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:25 AM UTC 24
Peak memory 206628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066439689 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.2066439689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.1083992720
Short name T164
Test name
Test status
Simulation time 74126881 ps
CPU time 0.61 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:25 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083992720 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1083992720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.1014742287
Short name T128
Test name
Test status
Simulation time 57348465 ps
CPU time 0.79 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014742287 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.1014742287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.75351656
Short name T60
Test name
Test status
Simulation time 339827246 ps
CPU time 1.01 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 210372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=75351656 -assert nopostproc +UVM_TESTNAM
E=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.75351656
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.2986739790
Short name T957
Test name
Test status
Simulation time 54488171 ps
CPU time 1.48 seconds
Started Aug 25 06:49:24 AM UTC 24
Finished Aug 25 06:49:27 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2986739790 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_w
ith_rand_reset.2986739790
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.3750580928
Short name T946
Test name
Test status
Simulation time 33467162 ps
CPU time 0.67 seconds
Started Aug 25 06:49:24 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 208384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750580928 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.3750580928
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.1853780537
Short name T944
Test name
Test status
Simulation time 29714997 ps
CPU time 0.56 seconds
Started Aug 25 06:49:24 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 206940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853780537 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.1853780537
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.342710832
Short name T129
Test name
Test status
Simulation time 320611238 ps
CPU time 0.86 seconds
Started Aug 25 06:49:24 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342710832 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.342710832
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.3007121725
Short name T951
Test name
Test status
Simulation time 34053486 ps
CPU time 1.46 seconds
Started Aug 25 06:49:22 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007121725 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.3007121725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.474618327
Short name T162
Test name
Test status
Simulation time 141321340 ps
CPU time 1 seconds
Started Aug 25 06:49:23 AM UTC 24
Finished Aug 25 06:49:26 AM UTC 24
Peak memory 211136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=474618327 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.474618327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2501265018
Short name T967
Test name
Test status
Simulation time 58218113 ps
CPU time 0.84 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2501265018 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_w
ith_rand_reset.2501265018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.439380805
Short name T966
Test name
Test status
Simulation time 24392751 ps
CPU time 0.74 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 209844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439380805 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.439380805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.410046984
Short name T965
Test name
Test status
Simulation time 17545938 ps
CPU time 0.7 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410046984 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.410046984
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.3517809770
Short name T964
Test name
Test status
Simulation time 76018915 ps
CPU time 0.64 seconds
Started Aug 25 06:49:26 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 209364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517809770 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.3517809770
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.3499949341
Short name T969
Test name
Test status
Simulation time 44260403 ps
CPU time 2.02 seconds
Started Aug 25 06:49:25 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3499949341 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.3499949341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.3285633230
Short name T81
Test name
Test status
Simulation time 235919816 ps
CPU time 1.47 seconds
Started Aug 25 06:49:25 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285633230 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.3285633230
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.2727572142
Short name T6
Test name
Test status
Simulation time 29842558 ps
CPU time 1.28 seconds
Started Aug 25 06:45:23 AM UTC 24
Finished Aug 25 06:45:25 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2727572142 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.2727572142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.4129319356
Short name T13
Test name
Test status
Simulation time 50948719 ps
CPU time 0.95 seconds
Started Aug 25 06:45:24 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4129319356 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.4129319356
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3507111994
Short name T5
Test name
Test status
Simulation time 30353874 ps
CPU time 0.95 seconds
Started Aug 25 06:45:23 AM UTC 24
Finished Aug 25 06:45:25 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3507111994 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.3507111994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.4045784683
Short name T41
Test name
Test status
Simulation time 38811951 ps
CPU time 0.84 seconds
Started Aug 25 06:45:24 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4045784683 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.4045784683
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2175876324
Short name T10
Test name
Test status
Simulation time 59293308 ps
CPU time 0.88 seconds
Started Aug 25 06:45:24 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2175876324 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.2175876324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.2784403481
Short name T4
Test name
Test status
Simulation time 339305591 ps
CPU time 1.5 seconds
Started Aug 25 06:45:21 AM UTC 24
Finished Aug 25 06:45:24 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784403481 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.2784403481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.2620708021
Short name T2
Test name
Test status
Simulation time 39073296 ps
CPU time 0.94 seconds
Started Aug 25 06:45:21 AM UTC 24
Finished Aug 25 06:45:24 AM UTC 24
Peak memory 211032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620708021 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.2620708021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2279273401
Short name T20
Test name
Test status
Simulation time 1484997232 ps
CPU time 2.97 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 238876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279273401 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2279273401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3626907005
Short name T42
Test name
Test status
Simulation time 246044716 ps
CPU time 1.23 seconds
Started Aug 25 06:45:24 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3626907005 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.3626907005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.500097495
Short name T39
Test name
Test status
Simulation time 855263936 ps
CPU time 5.11 seconds
Started Aug 25 06:45:23 AM UTC 24
Finished Aug 25 06:45:29 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500097495 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.500097495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3000978167
Short name T7
Test name
Test status
Simulation time 188046957 ps
CPU time 1.24 seconds
Started Aug 25 06:45:23 AM UTC 24
Finished Aug 25 06:45:25 AM UTC 24
Peak memory 208216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3000978167 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.3000978167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1386509033
Short name T1
Test name
Test status
Simulation time 56731507 ps
CPU time 0.94 seconds
Started Aug 25 06:45:20 AM UTC 24
Finished Aug 25 06:45:23 AM UTC 24
Peak memory 210424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386509033 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1386509033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.3081161259
Short name T3
Test name
Test status
Simulation time 318506570 ps
CPU time 1.34 seconds
Started Aug 25 06:45:21 AM UTC 24
Finished Aug 25 06:45:24 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081161259 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.3081161259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.1155842462
Short name T16
Test name
Test status
Simulation time 23144266 ps
CPU time 1.01 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1155842462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.1155842462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.984777858
Short name T26
Test name
Test status
Simulation time 50563615 ps
CPU time 1.05 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=984777858 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.984777858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1496738909
Short name T12
Test name
Test status
Simulation time 32232359 ps
CPU time 0.87 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1496738909 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.1496738909
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.1092171270
Short name T31
Test name
Test status
Simulation time 201748902 ps
CPU time 1.32 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092171270 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1092171270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.2076426916
Short name T180
Test name
Test status
Simulation time 97094377 ps
CPU time 0.88 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076426916 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.2076426916
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.1838277599
Short name T43
Test name
Test status
Simulation time 57471104 ps
CPU time 0.9 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838277599 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.1838277599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3219889328
Short name T33
Test name
Test status
Simulation time 198951102 ps
CPU time 0.95 seconds
Started Aug 25 06:45:29 AM UTC 24
Finished Aug 25 06:45:31 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219889328 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid.3219889328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.2844132281
Short name T71
Test name
Test status
Simulation time 178755753 ps
CPU time 1.21 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:29 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844132281 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.2844132281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.2832997318
Short name T27
Test name
Test status
Simulation time 195648271 ps
CPU time 1 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:28 AM UTC 24
Peak memory 211032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2832997318 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.2832997318
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.463951318
Short name T35
Test name
Test status
Simulation time 107910124 ps
CPU time 1.33 seconds
Started Aug 25 06:45:29 AM UTC 24
Finished Aug 25 06:45:32 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463951318 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.463951318
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.4066431114
Short name T21
Test name
Test status
Simulation time 620592310 ps
CPU time 3.6 seconds
Started Aug 25 06:45:29 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 238984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066431114 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.4066431114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.2094510457
Short name T32
Test name
Test status
Simulation time 232933122 ps
CPU time 1.96 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:31 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2094510457 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.2094510457
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3750156326
Short name T159
Test name
Test status
Simulation time 824234364 ps
CPU time 4.43 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:33 AM UTC 24
Peak memory 211388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750156326 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3750156326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2846683203
Short name T137
Test name
Test status
Simulation time 1013715797 ps
CPU time 4.26 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:33 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846683203 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2846683203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387042995
Short name T30
Test name
Test status
Simulation time 64974019 ps
CPU time 1.36 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387042995 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387042995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.2296190973
Short name T45
Test name
Test status
Simulation time 41310968 ps
CPU time 0.94 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:28 AM UTC 24
Peak memory 208200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296190973 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.2296190973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.3730109297
Short name T46
Test name
Test status
Simulation time 1803433371 ps
CPU time 10.95 seconds
Started Aug 25 06:45:30 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3730109297 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.3730109297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.4051131044
Short name T23
Test name
Test status
Simulation time 5062457470 ps
CPU time 17.63 seconds
Started Aug 25 06:45:29 AM UTC 24
Finished Aug 25 06:45:49 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4051131044 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr
_stress_all_with_rand_reset.4051131044
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1159319447
Short name T87
Test name
Test status
Simulation time 44992994 ps
CPU time 1.02 seconds
Started Aug 25 06:45:26 AM UTC 24
Finished Aug 25 06:45:28 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159319447 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1159319447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.4031930546
Short name T86
Test name
Test status
Simulation time 163149310 ps
CPU time 1.09 seconds
Started Aug 25 06:45:28 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031930546 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.4031930546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.3260114690
Short name T112
Test name
Test status
Simulation time 28249762 ps
CPU time 0.87 seconds
Started Aug 25 06:45:56 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260114690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3260114690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.3129118068
Short name T281
Test name
Test status
Simulation time 50885922 ps
CPU time 0.76 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129118068 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.3129118068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.465917217
Short name T289
Test name
Test status
Simulation time 109961625 ps
CPU time 1.02 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 208172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465917217 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.465917217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.3740195681
Short name T284
Test name
Test status
Simulation time 38742582 ps
CPU time 0.88 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 206164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740195681 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.3740195681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.4036503619
Short name T290
Test name
Test status
Simulation time 152381740 ps
CPU time 0.93 seconds
Started Aug 25 06:45:58 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036503619 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invalid.4036503619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.2590625926
Short name T279
Test name
Test status
Simulation time 298437597 ps
CPU time 2.2 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590625926 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.2590625926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.2449294224
Short name T275
Test name
Test status
Simulation time 80605588 ps
CPU time 1.06 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:58 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449294224 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.2449294224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.2914892173
Short name T296
Test name
Test status
Simulation time 108688559 ps
CPU time 1.68 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914892173 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.2914892173
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.1965114739
Short name T288
Test name
Test status
Simulation time 168445305 ps
CPU time 1.23 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1965114739 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.1965114739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2985008651
Short name T287
Test name
Test status
Simulation time 1030443970 ps
CPU time 2.74 seconds
Started Aug 25 06:45:56 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985008651 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2985008651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.593043581
Short name T310
Test name
Test status
Simulation time 816256454 ps
CPU time 4.9 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:46:03 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593043581 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.593043581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1916338399
Short name T286
Test name
Test status
Simulation time 94882034 ps
CPU time 1.21 seconds
Started Aug 25 06:45:57 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916338399 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.1916338399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.441050644
Short name T268
Test name
Test status
Simulation time 55857776 ps
CPU time 0.95 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=441050644 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.441050644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.655985223
Short name T114
Test name
Test status
Simulation time 1172197620 ps
CPU time 6.17 seconds
Started Aug 25 06:45:58 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655985223 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.655985223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.3593239519
Short name T94
Test name
Test status
Simulation time 10423920276 ps
CPU time 27.66 seconds
Started Aug 25 06:45:58 AM UTC 24
Finished Aug 25 06:46:27 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3593239519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmg
r_stress_all_with_rand_reset.3593239519
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.2365510363
Short name T276
Test name
Test status
Simulation time 118576810 ps
CPU time 1.39 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:58 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365510363 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.2365510363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.2678052684
Short name T274
Test name
Test status
Simulation time 92159904 ps
CPU time 0.96 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2678052684 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.2678052684
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.1925038407
Short name T298
Test name
Test status
Simulation time 33510981 ps
CPU time 1.11 seconds
Started Aug 25 06:45:59 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1925038407 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.1925038407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.2255191210
Short name T303
Test name
Test status
Simulation time 81948897 ps
CPU time 0.96 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 210232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255191210 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.2255191210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.145176794
Short name T299
Test name
Test status
Simulation time 33686695 ps
CPU time 0.9 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145176794 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.145176794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2236697
Short name T308
Test name
Test status
Simulation time 111649853 ps
CPU time 1.33 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=p
wrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2236697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.2680091239
Short name T305
Test name
Test status
Simulation time 61032922 ps
CPU time 1.11 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680091239 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2680091239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.4281076767
Short name T300
Test name
Test status
Simulation time 28419285 ps
CPU time 0.92 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281076767 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.4281076767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.2754529738
Short name T304
Test name
Test status
Simulation time 42523511 ps
CPU time 1.01 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754529738 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invalid.2754529738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2123813760
Short name T297
Test name
Test status
Simulation time 338272300 ps
CPU time 1.89 seconds
Started Aug 25 06:45:58 AM UTC 24
Finished Aug 25 06:46:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123813760 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.2123813760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1404625706
Short name T292
Test name
Test status
Simulation time 26544273 ps
CPU time 1.03 seconds
Started Aug 25 06:45:58 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1404625706 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1404625706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.4135618077
Short name T307
Test name
Test status
Simulation time 168039660 ps
CPU time 1.12 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 220076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135618077 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.4135618077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2028229244
Short name T301
Test name
Test status
Simulation time 325865123 ps
CPU time 1.18 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 208220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028229244 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.2028229244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.679149422
Short name T311
Test name
Test status
Simulation time 862915097 ps
CPU time 3.1 seconds
Started Aug 25 06:45:59 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679149422 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.679149422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1227897030
Short name T325
Test name
Test status
Simulation time 822955713 ps
CPU time 5.22 seconds
Started Aug 25 06:45:59 AM UTC 24
Finished Aug 25 06:46:06 AM UTC 24
Peak memory 211052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227897030 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1227897030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2153294734
Short name T302
Test name
Test status
Simulation time 147357561 ps
CPU time 1.29 seconds
Started Aug 25 06:45:59 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153294734 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.2153294734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.3959239204
Short name T293
Test name
Test status
Simulation time 30303026 ps
CPU time 1 seconds
Started Aug 25 06:45:58 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959239204 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.3959239204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.2596032891
Short name T342
Test name
Test status
Simulation time 3467682189 ps
CPU time 6.67 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:08 AM UTC 24
Peak memory 211448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596032891 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.2596032891
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.2422807755
Short name T136
Test name
Test status
Simulation time 2334145636 ps
CPU time 5.52 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2422807755 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmg
r_stress_all_with_rand_reset.2422807755
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.426163360
Short name T295
Test name
Test status
Simulation time 194596752 ps
CPU time 1.25 seconds
Started Aug 25 06:45:58 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426163360 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.426163360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.3816741998
Short name T294
Test name
Test status
Simulation time 106765509 ps
CPU time 1.04 seconds
Started Aug 25 06:45:58 AM UTC 24
Finished Aug 25 06:46:00 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3816741998 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.3816741998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.1446095070
Short name T113
Test name
Test status
Simulation time 43893580 ps
CPU time 0.94 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1446095070 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.1446095070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.4090166259
Short name T318
Test name
Test status
Simulation time 55342753 ps
CPU time 1.13 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090166259 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.4090166259
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1580223655
Short name T313
Test name
Test status
Simulation time 38003114 ps
CPU time 0.83 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580223655 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.1580223655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.1536405517
Short name T320
Test name
Test status
Simulation time 202375510 ps
CPU time 1.39 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536405517 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.1536405517
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1991219087
Short name T270
Test name
Test status
Simulation time 79183723 ps
CPU time 0.83 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991219087 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1991219087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.3807216351
Short name T251
Test name
Test status
Simulation time 33295370 ps
CPU time 0.82 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3807216351 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3807216351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.4149980614
Short name T317
Test name
Test status
Simulation time 78206264 ps
CPU time 0.96 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4149980614 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.4149980614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2433964767
Short name T269
Test name
Test status
Simulation time 452628397 ps
CPU time 1.22 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433964767 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.2433964767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.3437572783
Short name T309
Test name
Test status
Simulation time 49544702 ps
CPU time 1.02 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 210964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437572783 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.3437572783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.2710751837
Short name T322
Test name
Test status
Simulation time 99333847 ps
CPU time 1.38 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2710751837 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.2710751837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.520471709
Short name T314
Test name
Test status
Simulation time 104919654 ps
CPU time 0.94 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520471709 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.520471709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2755943744
Short name T324
Test name
Test status
Simulation time 1909374440 ps
CPU time 2.67 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:06 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755943744 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2755943744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2922085849
Short name T343
Test name
Test status
Simulation time 923824217 ps
CPU time 5.69 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922085849 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2922085849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.4167196634
Short name T316
Test name
Test status
Simulation time 55128592 ps
CPU time 1.34 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 208200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167196634 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.4167196634
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.1744100605
Short name T306
Test name
Test status
Simulation time 59379097 ps
CPU time 0.92 seconds
Started Aug 25 06:46:00 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744100605 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.1744100605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.430403381
Short name T115
Test name
Test status
Simulation time 1947332283 ps
CPU time 5.09 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430403381 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.430403381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.30510433
Short name T140
Test name
Test status
Simulation time 12584626650 ps
CPU time 20.94 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:25 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=30510433 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_
stress_all_with_rand_reset.30510433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.2747843660
Short name T249
Test name
Test status
Simulation time 120453102 ps
CPU time 1.29 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747843660 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.2747843660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.741317614
Short name T315
Test name
Test status
Simulation time 117842876 ps
CPU time 1.34 seconds
Started Aug 25 06:46:02 AM UTC 24
Finished Aug 25 06:46:04 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=741317614 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.741317614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.3113499662
Short name T327
Test name
Test status
Simulation time 225752345 ps
CPU time 1.05 seconds
Started Aug 25 06:46:04 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 208220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113499662 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.3113499662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.4106565140
Short name T173
Test name
Test status
Simulation time 63753709 ps
CPU time 1.34 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4106565140 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.4106565140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.448998815
Short name T329
Test name
Test status
Simulation time 29853017 ps
CPU time 0.95 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 206208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448998815 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.448998815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.1216025391
Short name T335
Test name
Test status
Simulation time 1536545559 ps
CPU time 1.35 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216025391 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.1216025391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.537415791
Short name T330
Test name
Test status
Simulation time 73191608 ps
CPU time 0.89 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537415791 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.537415791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.565880687
Short name T328
Test name
Test status
Simulation time 107314218 ps
CPU time 0.88 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565880687 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.565880687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.2076116274
Short name T334
Test name
Test status
Simulation time 40830611 ps
CPU time 1.03 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076116274 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invalid.2076116274
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.1318403218
Short name T321
Test name
Test status
Simulation time 59057460 ps
CPU time 1.08 seconds
Started Aug 25 06:46:03 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1318403218 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.1318403218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.667985004
Short name T323
Test name
Test status
Simulation time 68759555 ps
CPU time 1.48 seconds
Started Aug 25 06:46:03 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667985004 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.667985004
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.500894695
Short name T336
Test name
Test status
Simulation time 108862089 ps
CPU time 1.39 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=500894695 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.500894695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.2848750488
Short name T331
Test name
Test status
Simulation time 62144340 ps
CPU time 1.1 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848750488 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.2848750488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3322914026
Short name T345
Test name
Test status
Simulation time 976549824 ps
CPU time 3.19 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3322914026 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3322914026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3290522733
Short name T358
Test name
Test status
Simulation time 1030339483 ps
CPU time 4.1 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290522733 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3290522733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.578544848
Short name T332
Test name
Test status
Simulation time 54946643 ps
CPU time 1.34 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578544848 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.578544848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.2305877300
Short name T319
Test name
Test status
Simulation time 52001909 ps
CPU time 0.94 seconds
Started Aug 25 06:46:03 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305877300 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2305877300
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.2026645573
Short name T341
Test name
Test status
Simulation time 335844174 ps
CPU time 1.69 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:08 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2026645573 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.2026645573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.3398397738
Short name T395
Test name
Test status
Simulation time 2971661507 ps
CPU time 8.79 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:15 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3398397738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmg
r_stress_all_with_rand_reset.3398397738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.3196479570
Short name T285
Test name
Test status
Simulation time 90298182 ps
CPU time 0.76 seconds
Started Aug 25 06:46:03 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196479570 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.3196479570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.3196167524
Short name T340
Test name
Test status
Simulation time 325044622 ps
CPU time 2.35 seconds
Started Aug 25 06:46:04 AM UTC 24
Finished Aug 25 06:46:08 AM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196167524 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.3196167524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.4906723
Short name T116
Test name
Test status
Simulation time 28888330 ps
CPU time 0.96 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4906723 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=p
wrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.4906723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.2002519351
Short name T174
Test name
Test status
Simulation time 65203465 ps
CPU time 1.29 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002519351 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.2002519351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.2620494750
Short name T347
Test name
Test status
Simulation time 31483458 ps
CPU time 0.94 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620494750 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.2620494750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.1853495141
Short name T357
Test name
Test status
Simulation time 109735578 ps
CPU time 1.42 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853495141 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.1853495141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.382459305
Short name T346
Test name
Test status
Simulation time 55803907 ps
CPU time 0.77 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=382459305 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.382459305
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.4255900152
Short name T349
Test name
Test status
Simulation time 47915251 ps
CPU time 0.86 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 206096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255900152 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.4255900152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.621356546
Short name T353
Test name
Test status
Simulation time 109646822 ps
CPU time 1.01 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621356546 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid.621356546
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.503999733
Short name T339
Test name
Test status
Simulation time 263548664 ps
CPU time 1.4 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:08 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503999733 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.503999733
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.3493331200
Short name T337
Test name
Test status
Simulation time 64392213 ps
CPU time 1.2 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493331200 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.3493331200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.515589010
Short name T355
Test name
Test status
Simulation time 227832943 ps
CPU time 1.23 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=515589010 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.515589010
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.2410460476
Short name T348
Test name
Test status
Simulation time 51957168 ps
CPU time 0.94 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2410460476 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.2410460476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1223451277
Short name T359
Test name
Test status
Simulation time 1486220534 ps
CPU time 2.8 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:11 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1223451277 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1223451277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.437520554
Short name T364
Test name
Test status
Simulation time 817294423 ps
CPU time 3.38 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:11 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=437520554 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.437520554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2817984997
Short name T352
Test name
Test status
Simulation time 52551652 ps
CPU time 1.41 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817984997 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2817984997
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.2414295024
Short name T333
Test name
Test status
Simulation time 49601709 ps
CPU time 0.86 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:07 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414295024 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.2414295024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.4259859115
Short name T360
Test name
Test status
Simulation time 314210995 ps
CPU time 2.09 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:11 AM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4259859115 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.4259859115
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.1877192147
Short name T66
Test name
Test status
Simulation time 4160005624 ps
CPU time 22.11 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:31 AM UTC 24
Peak memory 211684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1877192147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmg
r_stress_all_with_rand_reset.1877192147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.171033550
Short name T338
Test name
Test status
Simulation time 119528935 ps
CPU time 1.14 seconds
Started Aug 25 06:46:05 AM UTC 24
Finished Aug 25 06:46:08 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171033550 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.171033550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.518193163
Short name T350
Test name
Test status
Simulation time 101092474 ps
CPU time 1.26 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 210996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518193163 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.518193163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.1354828645
Short name T366
Test name
Test status
Simulation time 45222915 ps
CPU time 1.1 seconds
Started Aug 25 06:46:09 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354828645 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.1354828645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.541034307
Short name T372
Test name
Test status
Simulation time 63035700 ps
CPU time 0.96 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 210416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=541034307 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.541034307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.794912587
Short name T362
Test name
Test status
Simulation time 31124888 ps
CPU time 0.9 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:11 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794912587 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.794912587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.1415533454
Short name T363
Test name
Test status
Simulation time 593437621 ps
CPU time 1.35 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1415533454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.1415533454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.3437218318
Short name T368
Test name
Test status
Simulation time 54739138 ps
CPU time 0.94 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437218318 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.3437218318
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.3640110070
Short name T367
Test name
Test status
Simulation time 111283545 ps
CPU time 0.9 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640110070 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.3640110070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.4064808175
Short name T373
Test name
Test status
Simulation time 56977211 ps
CPU time 1 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064808175 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invalid.4064808175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.3786540873
Short name T356
Test name
Test status
Simulation time 46081461 ps
CPU time 1.06 seconds
Started Aug 25 06:46:08 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786540873 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.3786540873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.3270440922
Short name T351
Test name
Test status
Simulation time 21109543 ps
CPU time 0.91 seconds
Started Aug 25 06:46:08 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270440922 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.3270440922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.2105217748
Short name T344
Test name
Test status
Simulation time 150553422 ps
CPU time 1.11 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2105217748 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2105217748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.2724301639
Short name T369
Test name
Test status
Simulation time 88749489 ps
CPU time 1.03 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724301639 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.2724301639
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3036743043
Short name T374
Test name
Test status
Simulation time 1069795686 ps
CPU time 2.81 seconds
Started Aug 25 06:46:09 AM UTC 24
Finished Aug 25 06:46:13 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036743043 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3036743043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1118039111
Short name T384
Test name
Test status
Simulation time 787897532 ps
CPU time 3.72 seconds
Started Aug 25 06:46:09 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118039111 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1118039111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.1252643530
Short name T371
Test name
Test status
Simulation time 214527742 ps
CPU time 1.14 seconds
Started Aug 25 06:46:09 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252643530 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.1252643530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.2111323966
Short name T354
Test name
Test status
Simulation time 57052829 ps
CPU time 0.89 seconds
Started Aug 25 06:46:07 AM UTC 24
Finished Aug 25 06:46:10 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2111323966 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.2111323966
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.3521690523
Short name T407
Test name
Test status
Simulation time 2504506260 ps
CPU time 5.5 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:17 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521690523 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.3521690523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.3067644272
Short name T139
Test name
Test status
Simulation time 3998437175 ps
CPU time 5.95 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:17 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3067644272 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmg
r_stress_all_with_rand_reset.3067644272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.2660601696
Short name T361
Test name
Test status
Simulation time 567693426 ps
CPU time 1.09 seconds
Started Aug 25 06:46:09 AM UTC 24
Finished Aug 25 06:46:11 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660601696 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.2660601696
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.1801504433
Short name T365
Test name
Test status
Simulation time 143212291 ps
CPU time 1.04 seconds
Started Aug 25 06:46:09 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1801504433 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.1801504433
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.1874545636
Short name T377
Test name
Test status
Simulation time 93078022 ps
CPU time 1.13 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 210928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1874545636 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.1874545636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.2123398209
Short name T385
Test name
Test status
Simulation time 59680443 ps
CPU time 0.99 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123398209 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.2123398209
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.796032867
Short name T376
Test name
Test status
Simulation time 38379049 ps
CPU time 0.85 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=796032867 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.796032867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.1892518738
Short name T391
Test name
Test status
Simulation time 110179946 ps
CPU time 1.42 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:15 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892518738 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.1892518738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.3326638396
Short name T378
Test name
Test status
Simulation time 53429439 ps
CPU time 0.8 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326638396 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3326638396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.4194887764
Short name T379
Test name
Test status
Simulation time 35637002 ps
CPU time 0.93 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194887764 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.4194887764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.1123090994
Short name T388
Test name
Test status
Simulation time 42623799 ps
CPU time 1.02 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123090994 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invalid.1123090994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.4210662949
Short name T381
Test name
Test status
Simulation time 838022754 ps
CPU time 1.4 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4210662949 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.4210662949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.70464844
Short name T370
Test name
Test status
Simulation time 140194028 ps
CPU time 0.75 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70464844 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.70464844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.3871482261
Short name T392
Test name
Test status
Simulation time 99882229 ps
CPU time 1.47 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:15 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871482261 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3871482261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.3891303700
Short name T386
Test name
Test status
Simulation time 194749726 ps
CPU time 1.12 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891303700 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.3891303700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.641478669
Short name T399
Test name
Test status
Simulation time 2127740453 ps
CPU time 2.76 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:16 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641478669 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.641478669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2433982295
Short name T396
Test name
Test status
Simulation time 1127326312 ps
CPU time 2.17 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:15 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433982295 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2433982295
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2562334179
Short name T383
Test name
Test status
Simulation time 423062839 ps
CPU time 1.2 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562334179 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.2562334179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3719003664
Short name T312
Test name
Test status
Simulation time 32063959 ps
CPU time 0.94 seconds
Started Aug 25 06:46:10 AM UTC 24
Finished Aug 25 06:46:12 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719003664 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3719003664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.467704966
Short name T398
Test name
Test status
Simulation time 444912104 ps
CPU time 2.17 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:16 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=467704966 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.467704966
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.756195583
Short name T76
Test name
Test status
Simulation time 11797911473 ps
CPU time 19.23 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:33 AM UTC 24
Peak memory 211600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=756195583 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr
_stress_all_with_rand_reset.756195583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.2684727094
Short name T326
Test name
Test status
Simulation time 92004916 ps
CPU time 0.95 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2684727094 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.2684727094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.2396107305
Short name T380
Test name
Test status
Simulation time 281095218 ps
CPU time 1.35 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 210916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2396107305 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.2396107305
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.2923861087
Short name T400
Test name
Test status
Simulation time 197392031 ps
CPU time 0.91 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:16 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923861087 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.2923861087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.1674033901
Short name T406
Test name
Test status
Simulation time 157920371 ps
CPU time 0.96 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:16 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674033901 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.1674033901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.2826839170
Short name T402
Test name
Test status
Simulation time 34487233 ps
CPU time 0.89 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826839170 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.2826839170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.4188143468
Short name T413
Test name
Test status
Simulation time 116596809 ps
CPU time 1.53 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:17 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188143468 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.4188143468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.2904437147
Short name T404
Test name
Test status
Simulation time 68958259 ps
CPU time 0.76 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:16 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904437147 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.2904437147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.4248098502
Short name T403
Test name
Test status
Simulation time 43767978 ps
CPU time 0.86 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248098502 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.4248098502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.1507288121
Short name T408
Test name
Test status
Simulation time 42347355 ps
CPU time 1.04 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:17 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1507288121 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.1507288121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.545289568
Short name T397
Test name
Test status
Simulation time 298158524 ps
CPU time 1.7 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:15 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545289568 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.545289568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.1629754131
Short name T390
Test name
Test status
Simulation time 54172412 ps
CPU time 1.03 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:15 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629754131 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.1629754131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2843629568
Short name T411
Test name
Test status
Simulation time 133277044 ps
CPU time 1.18 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:17 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2843629568 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2843629568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.1216837715
Short name T409
Test name
Test status
Simulation time 284932188 ps
CPU time 1.35 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:17 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216837715 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.1216837715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.256265938
Short name T416
Test name
Test status
Simulation time 733395886 ps
CPU time 3.55 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:19 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256265938 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.256265938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2240345161
Short name T415
Test name
Test status
Simulation time 725351875 ps
CPU time 3.39 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:19 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240345161 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2240345161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1539743725
Short name T405
Test name
Test status
Simulation time 145086565 ps
CPU time 1.2 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:16 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539743725 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.1539743725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.2927283461
Short name T389
Test name
Test status
Simulation time 31249943 ps
CPU time 0.89 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:14 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2927283461 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2927283461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.2227940283
Short name T419
Test name
Test status
Simulation time 1853502063 ps
CPU time 3.97 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:20 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227940283 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.2227940283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.3593186492
Short name T57
Test name
Test status
Simulation time 7129748055 ps
CPU time 7.05 seconds
Started Aug 25 06:46:14 AM UTC 24
Finished Aug 25 06:46:23 AM UTC 24
Peak memory 211492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3593186492 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmg
r_stress_all_with_rand_reset.3593186492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.2002315665
Short name T393
Test name
Test status
Simulation time 339216805 ps
CPU time 1.22 seconds
Started Aug 25 06:46:12 AM UTC 24
Finished Aug 25 06:46:15 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002315665 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.2002315665
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.424429645
Short name T394
Test name
Test status
Simulation time 481737264 ps
CPU time 1.29 seconds
Started Aug 25 06:46:13 AM UTC 24
Finished Aug 25 06:46:15 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424429645 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.424429645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.2687670174
Short name T439
Test name
Test status
Simulation time 21168073 ps
CPU time 0.82 seconds
Started Aug 25 06:46:16 AM UTC 24
Finished Aug 25 06:46:45 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2687670174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.2687670174
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1854939527
Short name T418
Test name
Test status
Simulation time 30536511 ps
CPU time 0.95 seconds
Started Aug 25 06:46:16 AM UTC 24
Finished Aug 25 06:46:20 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1854939527 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.1854939527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.3617272805
Short name T422
Test name
Test status
Simulation time 108470002 ps
CPU time 1.51 seconds
Started Aug 25 06:46:17 AM UTC 24
Finished Aug 25 06:46:20 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617272805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.3617272805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.365881848
Short name T414
Test name
Test status
Simulation time 244562608 ps
CPU time 1 seconds
Started Aug 25 06:46:16 AM UTC 24
Finished Aug 25 06:46:18 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=365881848 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.365881848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.22107018
Short name T412
Test name
Test status
Simulation time 54341859 ps
CPU time 0.99 seconds
Started Aug 25 06:46:15 AM UTC 24
Finished Aug 25 06:46:17 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22107018 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.22107018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.3552882947
Short name T420
Test name
Test status
Simulation time 160165368 ps
CPU time 1.16 seconds
Started Aug 25 06:46:17 AM UTC 24
Finished Aug 25 06:46:20 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552882947 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3552882947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3872371276
Short name T417
Test name
Test status
Simulation time 49565522 ps
CPU time 0.97 seconds
Started Aug 25 06:46:17 AM UTC 24
Finished Aug 25 06:46:20 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3872371276 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.3872371276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4244123550
Short name T427
Test name
Test status
Simulation time 1598351482 ps
CPU time 2.23 seconds
Started Aug 25 06:46:16 AM UTC 24
Finished Aug 25 06:46:27 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4244123550 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4244123550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1379058097
Short name T428
Test name
Test status
Simulation time 918213043 ps
CPU time 2.52 seconds
Started Aug 25 06:46:16 AM UTC 24
Finished Aug 25 06:46:27 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379058097 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1379058097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3838456982
Short name T421
Test name
Test status
Simulation time 76806710 ps
CPU time 1.32 seconds
Started Aug 25 06:46:16 AM UTC 24
Finished Aug 25 06:46:20 AM UTC 24
Peak memory 208156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838456982 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3838456982
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.3867310368
Short name T410
Test name
Test status
Simulation time 31506597 ps
CPU time 1.01 seconds
Started Aug 25 06:46:15 AM UTC 24
Finished Aug 25 06:46:17 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867310368 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3867310368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.2306635852
Short name T426
Test name
Test status
Simulation time 104972014 ps
CPU time 1.02 seconds
Started Aug 25 06:46:16 AM UTC 24
Finished Aug 25 06:46:25 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306635852 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.2306635852
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.652843758
Short name T425
Test name
Test status
Simulation time 37651329 ps
CPU time 0.76 seconds
Started Aug 25 06:46:16 AM UTC 24
Finished Aug 25 06:46:25 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652843758 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.652843758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.3131555979
Short name T446
Test name
Test status
Simulation time 88949669 ps
CPU time 0.82 seconds
Started Aug 25 06:46:19 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131555979 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3131555979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.1928711215
Short name T497
Test name
Test status
Simulation time 62211619 ps
CPU time 0.96 seconds
Started Aug 25 06:46:19 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928711215 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.1928711215
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.1939925007
Short name T514
Test name
Test status
Simulation time 71334332 ps
CPU time 0.9 seconds
Started Aug 25 06:46:19 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 210748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1939925007 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invalid.1939925007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.2673845461
Short name T423
Test name
Test status
Simulation time 272529529 ps
CPU time 1.36 seconds
Started Aug 25 06:46:17 AM UTC 24
Finished Aug 25 06:46:20 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673845461 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.2673845461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.1848616242
Short name T468
Test name
Test status
Simulation time 149719347 ps
CPU time 0.93 seconds
Started Aug 25 06:46:19 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1848616242 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1848616242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.10164610
Short name T541
Test name
Test status
Simulation time 2537711885 ps
CPU time 7.01 seconds
Started Aug 25 06:46:19 AM UTC 24
Finished Aug 25 06:47:28 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10164610 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.10164610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.676532131
Short name T580
Test name
Test status
Simulation time 4661849724 ps
CPU time 18.45 seconds
Started Aug 25 06:46:19 AM UTC 24
Finished Aug 25 06:47:39 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=676532131 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr
_stress_all_with_rand_reset.676532131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.1124161263
Short name T424
Test name
Test status
Simulation time 290561507 ps
CPU time 1.49 seconds
Started Aug 25 06:46:17 AM UTC 24
Finished Aug 25 06:46:21 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1124161263 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.1124161263
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.1991409304
Short name T37
Test name
Test status
Simulation time 29255243 ps
CPU time 1.03 seconds
Started Aug 25 06:45:30 AM UTC 24
Finished Aug 25 06:45:32 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1991409304 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.1991409304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.1529281183
Short name T52
Test name
Test status
Simulation time 82617841 ps
CPU time 1.04 seconds
Started Aug 25 06:45:32 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529281183 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.1529281183
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3089432421
Short name T144
Test name
Test status
Simulation time 38837913 ps
CPU time 0.85 seconds
Started Aug 25 06:45:31 AM UTC 24
Finished Aug 25 06:45:33 AM UTC 24
Peak memory 205980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089432421 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.3089432421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.1534081797
Short name T145
Test name
Test status
Simulation time 404488085 ps
CPU time 1.36 seconds
Started Aug 25 06:45:31 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534081797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.1534081797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.114999102
Short name T17
Test name
Test status
Simulation time 56130348 ps
CPU time 1.14 seconds
Started Aug 25 06:45:31 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=114999102 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.114999102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.3234196240
Short name T183
Test name
Test status
Simulation time 76575306 ps
CPU time 0.95 seconds
Started Aug 25 06:45:31 AM UTC 24
Finished Aug 25 06:45:33 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234196240 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.3234196240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.3969353389
Short name T51
Test name
Test status
Simulation time 48641205 ps
CPU time 1.08 seconds
Started Aug 25 06:45:32 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969353389 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.3969353389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.1525363290
Short name T36
Test name
Test status
Simulation time 197899525 ps
CPU time 1.11 seconds
Started Aug 25 06:45:30 AM UTC 24
Finished Aug 25 06:45:32 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525363290 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.1525363290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.1251703788
Short name T181
Test name
Test status
Simulation time 65583415 ps
CPU time 1.32 seconds
Started Aug 25 06:45:30 AM UTC 24
Finished Aug 25 06:45:32 AM UTC 24
Peak memory 210372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251703788 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1251703788
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2760297169
Short name T50
Test name
Test status
Simulation time 122843397 ps
CPU time 1.27 seconds
Started Aug 25 06:45:32 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760297169 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2760297169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.648310660
Short name T22
Test name
Test status
Simulation time 366544884 ps
CPU time 1.94 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:36 AM UTC 24
Peak memory 236700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=648310660 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.648310660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.631757545
Short name T138
Test name
Test status
Simulation time 981661362 ps
CPU time 4.33 seconds
Started Aug 25 06:45:31 AM UTC 24
Finished Aug 25 06:45:37 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631757545 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.631757545
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.614883821
Short name T40
Test name
Test status
Simulation time 801321170 ps
CPU time 5.03 seconds
Started Aug 25 06:45:31 AM UTC 24
Finished Aug 25 06:45:37 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614883821 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.614883821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3696013079
Short name T184
Test name
Test status
Simulation time 53859233 ps
CPU time 1.32 seconds
Started Aug 25 06:45:31 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696013079 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.3696013079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.1604787659
Short name T34
Test name
Test status
Simulation time 40085758 ps
CPU time 0.97 seconds
Started Aug 25 06:45:30 AM UTC 24
Finished Aug 25 06:45:32 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604787659 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.1604787659
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1231491542
Short name T194
Test name
Test status
Simulation time 637003920 ps
CPU time 4.31 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:39 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231491542 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.1231491542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.2567522638
Short name T90
Test name
Test status
Simulation time 5335654242 ps
CPU time 18.62 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2567522638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr
_stress_all_with_rand_reset.2567522638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.1508279510
Short name T182
Test name
Test status
Simulation time 253448461 ps
CPU time 1.29 seconds
Started Aug 25 06:45:30 AM UTC 24
Finished Aug 25 06:45:32 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1508279510 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1508279510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.1368818772
Short name T72
Test name
Test status
Simulation time 154965345 ps
CPU time 1.58 seconds
Started Aug 25 06:45:30 AM UTC 24
Finished Aug 25 06:45:33 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1368818772 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.1368818772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.2538829567
Short name T443
Test name
Test status
Simulation time 61724597 ps
CPU time 0.99 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:50 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538829567 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.2538829567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.1827093151
Short name T449
Test name
Test status
Simulation time 49721573 ps
CPU time 0.93 seconds
Started Aug 25 06:46:22 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827093151 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.1827093151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.980403311
Short name T445
Test name
Test status
Simulation time 37289139 ps
CPU time 0.79 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 206128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980403311 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.980403311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.2332636279
Short name T448
Test name
Test status
Simulation time 338525868 ps
CPU time 0.97 seconds
Started Aug 25 06:46:22 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 206180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332636279 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2332636279
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.2150460320
Short name T441
Test name
Test status
Simulation time 33606082 ps
CPU time 0.93 seconds
Started Aug 25 06:46:22 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150460320 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.2150460320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.4228664292
Short name T387
Test name
Test status
Simulation time 87301699 ps
CPU time 0.78 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 206172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4228664292 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.4228664292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.1252405623
Short name T429
Test name
Test status
Simulation time 85125376 ps
CPU time 0.77 seconds
Started Aug 25 06:46:26 AM UTC 24
Finished Aug 25 06:46:35 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252405623 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invalid.1252405623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.3430594381
Short name T465
Test name
Test status
Simulation time 40619083 ps
CPU time 0.61 seconds
Started Aug 25 06:46:19 AM UTC 24
Finished Aug 25 06:47:04 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3430594381 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3430594381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.1151071847
Short name T401
Test name
Test status
Simulation time 162391708 ps
CPU time 0.73 seconds
Started Aug 25 06:46:24 AM UTC 24
Finished Aug 25 06:46:46 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1151071847 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1151071847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.2861713934
Short name T447
Test name
Test status
Simulation time 435988940 ps
CPU time 1.08 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861713934 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.2861713934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3137674234
Short name T452
Test name
Test status
Simulation time 868499641 ps
CPU time 2.29 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:52 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137674234 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3137674234
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.420158882
Short name T436
Test name
Test status
Simulation time 824995205 ps
CPU time 3.39 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:43 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420158882 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.420158882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.297695078
Short name T444
Test name
Test status
Simulation time 52661226 ps
CPU time 0.97 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=297695078 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.297695078
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.1243736593
Short name T506
Test name
Test status
Simulation time 39407027 ps
CPU time 0.69 seconds
Started Aug 25 06:46:19 AM UTC 24
Finished Aug 25 06:47:24 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243736593 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.1243736593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.2834552223
Short name T431
Test name
Test status
Simulation time 2459763137 ps
CPU time 3.7 seconds
Started Aug 25 06:46:26 AM UTC 24
Finished Aug 25 06:46:38 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834552223 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.2834552223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.3217233419
Short name T442
Test name
Test status
Simulation time 3740022684 ps
CPU time 12.08 seconds
Started Aug 25 06:46:26 AM UTC 24
Finished Aug 25 06:46:47 AM UTC 24
Peak memory 211592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3217233419 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmg
r_stress_all_with_rand_reset.3217233419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.2651104108
Short name T434
Test name
Test status
Simulation time 214866706 ps
CPU time 1.36 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:41 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651104108 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.2651104108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.109534962
Short name T433
Test name
Test status
Simulation time 385695719 ps
CPU time 1.03 seconds
Started Aug 25 06:46:21 AM UTC 24
Finished Aug 25 06:46:40 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109534962 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.109534962
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/20.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.3374463718
Short name T440
Test name
Test status
Simulation time 21405945 ps
CPU time 0.68 seconds
Started Aug 25 06:46:34 AM UTC 24
Finished Aug 25 06:46:45 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374463718 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.3374463718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.272832403
Short name T512
Test name
Test status
Simulation time 44785538 ps
CPU time 0.66 seconds
Started Aug 25 06:46:39 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272832403 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.272832403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.105759203
Short name T487
Test name
Test status
Simulation time 62682567 ps
CPU time 0.61 seconds
Started Aug 25 06:46:41 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105759203 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.105759203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.577300043
Short name T485
Test name
Test status
Simulation time 99227302 ps
CPU time 0.65 seconds
Started Aug 25 06:46:41 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577300043 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.577300043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.3888487762
Short name T437
Test name
Test status
Simulation time 75133947 ps
CPU time 0.62 seconds
Started Aug 25 06:46:43 AM UTC 24
Finished Aug 25 06:46:45 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888487762 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid.3888487762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.715940194
Short name T435
Test name
Test status
Simulation time 239076596 ps
CPU time 1.13 seconds
Started Aug 25 06:46:27 AM UTC 24
Finished Aug 25 06:46:41 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=715940194 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.715940194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.3559576200
Short name T375
Test name
Test status
Simulation time 52479638 ps
CPU time 0.78 seconds
Started Aug 25 06:46:27 AM UTC 24
Finished Aug 25 06:46:50 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559576200 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3559576200
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.1046118935
Short name T438
Test name
Test status
Simulation time 145793889 ps
CPU time 0.76 seconds
Started Aug 25 06:46:43 AM UTC 24
Finished Aug 25 06:46:45 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1046118935 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1046118935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.2535972880
Short name T495
Test name
Test status
Simulation time 158823411 ps
CPU time 0.72 seconds
Started Aug 25 06:46:39 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2535972880 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.2535972880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.174272554
Short name T453
Test name
Test status
Simulation time 1236327036 ps
CPU time 2.07 seconds
Started Aug 25 06:46:36 AM UTC 24
Finished Aug 25 06:46:52 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=174272554 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.174272554
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3224177112
Short name T454
Test name
Test status
Simulation time 2538629930 ps
CPU time 2.17 seconds
Started Aug 25 06:46:36 AM UTC 24
Finished Aug 25 06:46:52 AM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224177112 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3224177112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.911697742
Short name T463
Test name
Test status
Simulation time 52507196 ps
CPU time 0.85 seconds
Started Aug 25 06:46:36 AM UTC 24
Finished Aug 25 06:47:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911697742 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.911697742
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.4286285434
Short name T430
Test name
Test status
Simulation time 44678806 ps
CPU time 0.96 seconds
Started Aug 25 06:46:26 AM UTC 24
Finished Aug 25 06:46:35 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4286285434 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.4286285434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1422567913
Short name T456
Test name
Test status
Simulation time 1429150915 ps
CPU time 5.12 seconds
Started Aug 25 06:46:45 AM UTC 24
Finished Aug 25 06:46:55 AM UTC 24
Peak memory 211540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422567913 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.1422567913
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.2409039675
Short name T432
Test name
Test status
Simulation time 79780367 ps
CPU time 0.68 seconds
Started Aug 25 06:46:27 AM UTC 24
Finished Aug 25 06:46:40 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2409039675 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.2409039675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.2670498482
Short name T451
Test name
Test status
Simulation time 399487533 ps
CPU time 1.16 seconds
Started Aug 25 06:46:32 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670498482 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.2670498482
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/21.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.4168897007
Short name T450
Test name
Test status
Simulation time 67875670 ps
CPU time 0.99 seconds
Started Aug 25 06:46:48 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168897007 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.4168897007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.483479386
Short name T457
Test name
Test status
Simulation time 95635196 ps
CPU time 0.61 seconds
Started Aug 25 06:46:52 AM UTC 24
Finished Aug 25 06:46:55 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483479386 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.483479386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.1687402270
Short name T459
Test name
Test status
Simulation time 37784761 ps
CPU time 0.64 seconds
Started Aug 25 06:46:51 AM UTC 24
Finished Aug 25 06:47:00 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687402270 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.1687402270
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.3337665813
Short name T461
Test name
Test status
Simulation time 111868960 ps
CPU time 0.84 seconds
Started Aug 25 06:46:51 AM UTC 24
Finished Aug 25 06:47:00 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337665813 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.3337665813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.938945931
Short name T469
Test name
Test status
Simulation time 31724592 ps
CPU time 0.8 seconds
Started Aug 25 06:46:52 AM UTC 24
Finished Aug 25 06:47:05 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938945931 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.938945931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.642869828
Short name T458
Test name
Test status
Simulation time 80392084 ps
CPU time 0.56 seconds
Started Aug 25 06:46:51 AM UTC 24
Finished Aug 25 06:47:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=642869828 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.642869828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.2679339232
Short name T467
Test name
Test status
Simulation time 52427399 ps
CPU time 0.7 seconds
Started Aug 25 06:46:52 AM UTC 24
Finished Aug 25 06:47:05 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2679339232 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invalid.2679339232
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.3815952604
Short name T474
Test name
Test status
Simulation time 44213130 ps
CPU time 0.62 seconds
Started Aug 25 06:46:47 AM UTC 24
Finished Aug 25 06:47:06 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3815952604 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.3815952604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.350267033
Short name T472
Test name
Test status
Simulation time 101570636 ps
CPU time 0.97 seconds
Started Aug 25 06:46:52 AM UTC 24
Finished Aug 25 06:47:06 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=350267033 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.350267033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.4168828947
Short name T460
Test name
Test status
Simulation time 86657602 ps
CPU time 0.84 seconds
Started Aug 25 06:46:51 AM UTC 24
Finished Aug 25 06:47:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168828947 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.4168828947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.955957272
Short name T455
Test name
Test status
Simulation time 889782590 ps
CPU time 3.39 seconds
Started Aug 25 06:46:48 AM UTC 24
Finished Aug 25 06:46:53 AM UTC 24
Peak memory 210748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=955957272 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.955957272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.1117494531
Short name T382
Test name
Test status
Simulation time 56324243 ps
CPU time 0.66 seconds
Started Aug 25 06:46:45 AM UTC 24
Finished Aug 25 06:46:50 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117494531 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1117494531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.192704859
Short name T479
Test name
Test status
Simulation time 838170775 ps
CPU time 3.45 seconds
Started Aug 25 06:46:53 AM UTC 24
Finished Aug 25 06:47:08 AM UTC 24
Peak memory 211356 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192704859 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.192704859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.4165229842
Short name T462
Test name
Test status
Simulation time 1236389818 ps
CPU time 5.72 seconds
Started Aug 25 06:46:53 AM UTC 24
Finished Aug 25 06:47:00 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4165229842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmg
r_stress_all_with_rand_reset.4165229842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.4076628919
Short name T484
Test name
Test status
Simulation time 32710268 ps
CPU time 0.63 seconds
Started Aug 25 06:46:47 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076628919 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.4076628919
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.973821901
Short name T518
Test name
Test status
Simulation time 47241847 ps
CPU time 0.54 seconds
Started Aug 25 06:47:00 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973821901 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.973821901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.1691296380
Short name T491
Test name
Test status
Simulation time 200335673 ps
CPU time 0.86 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1691296380 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.1691296380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.3748522043
Short name T490
Test name
Test status
Simulation time 37382085 ps
CPU time 0.67 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748522043 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.3748522043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.3212908583
Short name T500
Test name
Test status
Simulation time 146217444 ps
CPU time 0.67 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:20 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212908583 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invalid.3212908583
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2216810156
Short name T476
Test name
Test status
Simulation time 229362030 ps
CPU time 0.87 seconds
Started Aug 25 06:46:53 AM UTC 24
Finished Aug 25 06:47:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2216810156 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.2216810156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.2426209625
Short name T473
Test name
Test status
Simulation time 60474878 ps
CPU time 0.81 seconds
Started Aug 25 06:46:53 AM UTC 24
Finished Aug 25 06:47:06 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426209625 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.2426209625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.43627681
Short name T502
Test name
Test status
Simulation time 97741141 ps
CPU time 0.93 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=43627681 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.43627681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.1624289999
Short name T489
Test name
Test status
Simulation time 89841122 ps
CPU time 0.86 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1624289999 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.1624289999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1344600565
Short name T464
Test name
Test status
Simulation time 794630608 ps
CPU time 2.8 seconds
Started Aug 25 06:46:56 AM UTC 24
Finished Aug 25 06:47:03 AM UTC 24
Peak memory 211388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344600565 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1344600565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3657556744
Short name T517
Test name
Test status
Simulation time 785515055 ps
CPU time 3.03 seconds
Started Aug 25 06:46:56 AM UTC 24
Finished Aug 25 06:47:23 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3657556744 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3657556744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1028485427
Short name T521
Test name
Test status
Simulation time 464266556 ps
CPU time 0.81 seconds
Started Aug 25 06:47:00 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1028485427 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.1028485427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.3303980371
Short name T466
Test name
Test status
Simulation time 35177582 ps
CPU time 0.65 seconds
Started Aug 25 06:46:53 AM UTC 24
Finished Aug 25 06:47:05 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3303980371 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3303980371
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.3125849599
Short name T504
Test name
Test status
Simulation time 2118014444 ps
CPU time 2.39 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:22 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3125849599 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.3125849599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.1257980630
Short name T63
Test name
Test status
Simulation time 3675383101 ps
CPU time 12.49 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:32 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1257980630 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmg
r_stress_all_with_rand_reset.1257980630
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.841202149
Short name T488
Test name
Test status
Simulation time 180443507 ps
CPU time 0.99 seconds
Started Aug 25 06:46:53 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841202149 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.841202149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.1708187108
Short name T475
Test name
Test status
Simulation time 78274849 ps
CPU time 0.75 seconds
Started Aug 25 06:47:04 AM UTC 24
Finished Aug 25 06:47:06 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708187108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.1708187108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.2822258616
Short name T480
Test name
Test status
Simulation time 70803892 ps
CPU time 0.63 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:15 AM UTC 24
Peak memory 210740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822258616 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.2822258616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3664390391
Short name T676
Test name
Test status
Simulation time 36818227 ps
CPU time 0.54 seconds
Started Aug 25 06:47:05 AM UTC 24
Finished Aug 25 06:47:54 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664390391 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.3664390391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.412686547
Short name T524
Test name
Test status
Simulation time 115794432 ps
CPU time 0.89 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=412686547 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.412686547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.4231910820
Short name T522
Test name
Test status
Simulation time 49678063 ps
CPU time 0.8 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 206060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231910820 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.4231910820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.1933957265
Short name T498
Test name
Test status
Simulation time 75628858 ps
CPU time 0.55 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933957265 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.1933957265
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.3108568055
Short name T529
Test name
Test status
Simulation time 43495878 ps
CPU time 0.74 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108568055 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid.3108568055
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.962649349
Short name T471
Test name
Test status
Simulation time 136550820 ps
CPU time 0.79 seconds
Started Aug 25 06:47:03 AM UTC 24
Finished Aug 25 06:47:06 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962649349 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.962649349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.1928845760
Short name T508
Test name
Test status
Simulation time 46555757 ps
CPU time 0.58 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928845760 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.1928845760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.3637086297
Short name T482
Test name
Test status
Simulation time 100310533 ps
CPU time 0.97 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:15 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3637086297 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.3637086297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.3776336070
Short name T483
Test name
Test status
Simulation time 380615871 ps
CPU time 1.1 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:15 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776336070 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.3776336070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.248627354
Short name T478
Test name
Test status
Simulation time 795910204 ps
CPU time 2.86 seconds
Started Aug 25 06:47:04 AM UTC 24
Finished Aug 25 06:47:08 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248627354 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.248627354
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.145315233
Short name T704
Test name
Test status
Simulation time 768133641 ps
CPU time 3.34 seconds
Started Aug 25 06:47:05 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 211060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=145315233 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.145315233
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.4251157076
Short name T677
Test name
Test status
Simulation time 108181684 ps
CPU time 0.89 seconds
Started Aug 25 06:47:05 AM UTC 24
Finished Aug 25 06:47:54 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251157076 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.4251157076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.2511197094
Short name T505
Test name
Test status
Simulation time 35700506 ps
CPU time 0.62 seconds
Started Aug 25 06:47:01 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511197094 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2511197094
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.2566552062
Short name T542
Test name
Test status
Simulation time 1084076348 ps
CPU time 4.6 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:29 AM UTC 24
Peak memory 211552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2566552062 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2566552062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.209699196
Short name T103
Test name
Test status
Simulation time 6338823396 ps
CPU time 8.59 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:33 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=209699196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr
_stress_all_with_rand_reset.209699196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.3346857327
Short name T470
Test name
Test status
Simulation time 178196132 ps
CPU time 0.79 seconds
Started Aug 25 06:47:03 AM UTC 24
Finished Aug 25 06:47:06 AM UTC 24
Peak memory 208224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346857327 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.3346857327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.1772492268
Short name T477
Test name
Test status
Simulation time 214140877 ps
CPU time 1.05 seconds
Started Aug 25 06:47:03 AM UTC 24
Finished Aug 25 06:47:06 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772492268 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.1772492268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/24.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.3795185783
Short name T536
Test name
Test status
Simulation time 136948724 ps
CPU time 0.97 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:26 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795185783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.3795185783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.379815208
Short name T528
Test name
Test status
Simulation time 50792905 ps
CPU time 0.95 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379815208 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.379815208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.74535524
Short name T511
Test name
Test status
Simulation time 28362686 ps
CPU time 0.64 seconds
Started Aug 25 06:47:09 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 206116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74535524 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.74535524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.771017815
Short name T507
Test name
Test status
Simulation time 108552795 ps
CPU time 0.85 seconds
Started Aug 25 06:47:16 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771017815 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.771017815
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.4036711341
Short name T510
Test name
Test status
Simulation time 40095666 ps
CPU time 0.67 seconds
Started Aug 25 06:47:16 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 206120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036711341 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.4036711341
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.3288580687
Short name T503
Test name
Test status
Simulation time 207135752 ps
CPU time 0.72 seconds
Started Aug 25 06:47:16 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288580687 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.3288580687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.1307672274
Short name T492
Test name
Test status
Simulation time 45684085 ps
CPU time 0.64 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:20 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1307672274 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.1307672274
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.3379560534
Short name T535
Test name
Test status
Simulation time 310987445 ps
CPU time 0.98 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:26 AM UTC 24
Peak memory 208100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379560534 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.3379560534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.1565517576
Short name T532
Test name
Test status
Simulation time 37413015 ps
CPU time 0.8 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:26 AM UTC 24
Peak memory 210904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1565517576 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.1565517576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.3561709576
Short name T530
Test name
Test status
Simulation time 119216123 ps
CPU time 1.11 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:26 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561709576 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.3561709576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.3918838876
Short name T509
Test name
Test status
Simulation time 54702874 ps
CPU time 0.84 seconds
Started Aug 25 06:47:16 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3918838876 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.3918838876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4263109365
Short name T516
Test name
Test status
Simulation time 819830591 ps
CPU time 2.88 seconds
Started Aug 25 06:47:08 AM UTC 24
Finished Aug 25 06:47:23 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263109365 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4263109365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3559140469
Short name T515
Test name
Test status
Simulation time 1219468749 ps
CPU time 2.28 seconds
Started Aug 25 06:47:08 AM UTC 24
Finished Aug 25 06:47:22 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559140469 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3559140469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2475862100
Short name T513
Test name
Test status
Simulation time 151811030 ps
CPU time 0.84 seconds
Started Aug 25 06:47:09 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475862100 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2475862100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.945527180
Short name T481
Test name
Test status
Simulation time 65533812 ps
CPU time 0.62 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:15 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945527180 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.945527180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.1281187880
Short name T624
Test name
Test status
Simulation time 566129192 ps
CPU time 2.5 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:48 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281187880 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.1281187880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.1830697714
Short name T141
Test name
Test status
Simulation time 3721721003 ps
CPU time 4.93 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:24 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1830697714 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmg
r_stress_all_with_rand_reset.1830697714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.443930340
Short name T486
Test name
Test status
Simulation time 265297685 ps
CPU time 1.17 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=443930340 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.443930340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.264707586
Short name T533
Test name
Test status
Simulation time 171489516 ps
CPU time 0.84 seconds
Started Aug 25 06:47:06 AM UTC 24
Finished Aug 25 06:47:26 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264707586 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.264707586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.569299773
Short name T496
Test name
Test status
Simulation time 50489663 ps
CPU time 0.67 seconds
Started Aug 25 06:47:19 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569299773 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.569299773
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2715628581
Short name T526
Test name
Test status
Simulation time 36997715 ps
CPU time 0.58 seconds
Started Aug 25 06:47:21 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2715628581 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.2715628581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.865689000
Short name T548
Test name
Test status
Simulation time 378164711 ps
CPU time 0.8 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865689000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.865689000
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.2397436778
Short name T549
Test name
Test status
Simulation time 47133020 ps
CPU time 0.69 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397436778 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2397436778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.1947090058
Short name T544
Test name
Test status
Simulation time 53144685 ps
CPU time 0.61 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1947090058 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.1947090058
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.2787904124
Short name T552
Test name
Test status
Simulation time 71329709 ps
CPU time 0.76 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787904124 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.2787904124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.2457495911
Short name T499
Test name
Test status
Simulation time 321776228 ps
CPU time 0.9 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:20 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2457495911 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.2457495911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.1220848611
Short name T543
Test name
Test status
Simulation time 68757707 ps
CPU time 0.75 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:30 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220848611 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.1220848611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.1367194424
Short name T554
Test name
Test status
Simulation time 100818086 ps
CPU time 0.91 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367194424 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.1367194424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.2773341510
Short name T546
Test name
Test status
Simulation time 95288042 ps
CPU time 0.65 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773341510 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.2773341510
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3113329158
Short name T579
Test name
Test status
Simulation time 1149784172 ps
CPU time 2.38 seconds
Started Aug 25 06:47:20 AM UTC 24
Finished Aug 25 06:47:37 AM UTC 24
Peak memory 211080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3113329158 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3113329158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3681768427
Short name T540
Test name
Test status
Simulation time 855969251 ps
CPU time 2.69 seconds
Started Aug 25 06:47:20 AM UTC 24
Finished Aug 25 06:47:28 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681768427 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3681768427
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2316483193
Short name T534
Test name
Test status
Simulation time 72077491 ps
CPU time 0.95 seconds
Started Aug 25 06:47:21 AM UTC 24
Finished Aug 25 06:47:26 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316483193 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.2316483193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.1955093345
Short name T493
Test name
Test status
Simulation time 36011134 ps
CPU time 0.6 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:20 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955093345 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1955093345
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.1127116272
Short name T574
Test name
Test status
Simulation time 1550816052 ps
CPU time 5.41 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127116272 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.1127116272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.2938230470
Short name T733
Test name
Test status
Simulation time 11549818323 ps
CPU time 9.79 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 211648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2938230470 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmg
r_stress_all_with_rand_reset.2938230470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.2671297330
Short name T494
Test name
Test status
Simulation time 77154888 ps
CPU time 0.67 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:20 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671297330 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2671297330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.428238652
Short name T501
Test name
Test status
Simulation time 313880232 ps
CPU time 1.24 seconds
Started Aug 25 06:47:17 AM UTC 24
Finished Aug 25 06:47:21 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428238652 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.428238652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/26.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.1314961956
Short name T519
Test name
Test status
Simulation time 54171480 ps
CPU time 0.66 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314961956 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.1314961956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2825497492
Short name T658
Test name
Test status
Simulation time 62697191 ps
CPU time 0.95 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825497492 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.2825497492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.280064704
Short name T531
Test name
Test status
Simulation time 29567140 ps
CPU time 0.86 seconds
Started Aug 25 06:47:23 AM UTC 24
Finished Aug 25 06:47:26 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=280064704 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.280064704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.3486763901
Short name T583
Test name
Test status
Simulation time 796610248 ps
CPU time 0.76 seconds
Started Aug 25 06:47:25 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486763901 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.3486763901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.449841759
Short name T584
Test name
Test status
Simulation time 37537764 ps
CPU time 0.68 seconds
Started Aug 25 06:47:25 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=449841759 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.449841759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.2061142107
Short name T527
Test name
Test status
Simulation time 66152711 ps
CPU time 0.61 seconds
Started Aug 25 06:47:23 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061142107 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.2061142107
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.452534532
Short name T591
Test name
Test status
Simulation time 67511719 ps
CPU time 0.86 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 210480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452534532 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invalid.452534532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.22413605
Short name T663
Test name
Test status
Simulation time 91706962 ps
CPU time 0.95 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22413605 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.22413605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.381017619
Short name T662
Test name
Test status
Simulation time 325015343 ps
CPU time 0.99 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 210472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=381017619 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.381017619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.1486827551
Short name T553
Test name
Test status
Simulation time 212591403 ps
CPU time 0.88 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1486827551 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1486827551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.243911101
Short name T537
Test name
Test status
Simulation time 282970708 ps
CPU time 1.5 seconds
Started Aug 25 06:47:23 AM UTC 24
Finished Aug 25 06:47:26 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243911101 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.243911101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.346222543
Short name T539
Test name
Test status
Simulation time 814179989 ps
CPU time 2.93 seconds
Started Aug 25 06:47:23 AM UTC 24
Finished Aug 25 06:47:27 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346222543 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.346222543
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2781657601
Short name T538
Test name
Test status
Simulation time 942129376 ps
CPU time 2.54 seconds
Started Aug 25 06:47:23 AM UTC 24
Finished Aug 25 06:47:27 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781657601 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2781657601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.4167421948
Short name T525
Test name
Test status
Simulation time 82889314 ps
CPU time 0.81 seconds
Started Aug 25 06:47:23 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167421948 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.4167421948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.2810893088
Short name T589
Test name
Test status
Simulation time 58594768 ps
CPU time 0.82 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810893088 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2810893088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.3940953627
Short name T706
Test name
Test status
Simulation time 1675130845 ps
CPU time 5.34 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:57 AM UTC 24
Peak memory 211704 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940953627 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.3940953627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.3477112157
Short name T752
Test name
Test status
Simulation time 8316793836 ps
CPU time 13.91 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:48:06 AM UTC 24
Peak memory 211320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3477112157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmg
r_stress_all_with_rand_reset.3477112157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.2569523951
Short name T660
Test name
Test status
Simulation time 314514636 ps
CPU time 0.89 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2569523951 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.2569523951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.2963707957
Short name T520
Test name
Test status
Simulation time 48513767 ps
CPU time 0.73 seconds
Started Aug 25 06:47:22 AM UTC 24
Finished Aug 25 06:47:25 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963707957 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.2963707957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.606237690
Short name T562
Test name
Test status
Simulation time 48223828 ps
CPU time 0.77 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:35 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606237690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.606237690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.439856607
Short name T176
Test name
Test status
Simulation time 54152175 ps
CPU time 0.71 seconds
Started Aug 25 06:47:27 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 210876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=439856607 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.439856607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.84182322
Short name T560
Test name
Test status
Simulation time 27748134 ps
CPU time 0.66 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:34 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84182322 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.84182322
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.1549108453
Short name T563
Test name
Test status
Simulation time 1564405733 ps
CPU time 0.78 seconds
Started Aug 25 06:47:27 AM UTC 24
Finished Aug 25 06:47:35 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549108453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.1549108453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.3163735153
Short name T570
Test name
Test status
Simulation time 43317115 ps
CPU time 0.82 seconds
Started Aug 25 06:47:27 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3163735153 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.3163735153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.3367602401
Short name T569
Test name
Test status
Simulation time 37625548 ps
CPU time 0.72 seconds
Started Aug 25 06:47:27 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367602401 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3367602401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.2260190749
Short name T545
Test name
Test status
Simulation time 86768063 ps
CPU time 0.64 seconds
Started Aug 25 06:47:28 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2260190749 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invalid.2260190749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.1922183430
Short name T600
Test name
Test status
Simulation time 174985441 ps
CPU time 0.76 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:44 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922183430 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.1922183430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.488110050
Short name T558
Test name
Test status
Simulation time 76827622 ps
CPU time 1.04 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:32 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=488110050 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.488110050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.4087114882
Short name T575
Test name
Test status
Simulation time 123738491 ps
CPU time 0.95 seconds
Started Aug 25 06:47:27 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 219852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087114882 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.4087114882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.3296786791
Short name T564
Test name
Test status
Simulation time 559614247 ps
CPU time 0.88 seconds
Started Aug 25 06:47:27 AM UTC 24
Finished Aug 25 06:47:35 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3296786791 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.3296786791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.255942191
Short name T568
Test name
Test status
Simulation time 1156886549 ps
CPU time 1.81 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255942191 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.255942191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1077534269
Short name T607
Test name
Test status
Simulation time 915500404 ps
CPU time 2.28 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077534269 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1077534269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1574548834
Short name T557
Test name
Test status
Simulation time 62252863 ps
CPU time 0.84 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:32 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1574548834 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.1574548834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.3385939475
Short name T656
Test name
Test status
Simulation time 28477702 ps
CPU time 0.7 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385939475 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.3385939475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.17791176
Short name T559
Test name
Test status
Simulation time 686120763 ps
CPU time 3.05 seconds
Started Aug 25 06:47:28 AM UTC 24
Finished Aug 25 06:47:33 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17791176 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.17791176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.3506848709
Short name T104
Test name
Test status
Simulation time 2326291405 ps
CPU time 9.42 seconds
Started Aug 25 06:47:28 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3506848709 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmg
r_stress_all_with_rand_reset.3506848709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.573897170
Short name T561
Test name
Test status
Simulation time 262994112 ps
CPU time 0.95 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:35 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573897170 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.573897170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.205572565
Short name T601
Test name
Test status
Simulation time 193743329 ps
CPU time 1.09 seconds
Started Aug 25 06:47:26 AM UTC 24
Finished Aug 25 06:47:45 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205572565 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.205572565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.1464388827
Short name T555
Test name
Test status
Simulation time 35024919 ps
CPU time 0.96 seconds
Started Aug 25 06:47:29 AM UTC 24
Finished Aug 25 06:47:32 AM UTC 24
Peak memory 210948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1464388827 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.1464388827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.2307084597
Short name T573
Test name
Test status
Simulation time 49693234 ps
CPU time 0.8 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2307084597 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.2307084597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.3103594565
Short name T595
Test name
Test status
Simulation time 29577181 ps
CPU time 0.75 seconds
Started Aug 25 06:47:31 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103594565 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.3103594565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.1892764387
Short name T640
Test name
Test status
Simulation time 381454512 ps
CPU time 0.78 seconds
Started Aug 25 06:47:32 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1892764387 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.1892764387
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.2897960403
Short name T635
Test name
Test status
Simulation time 43173033 ps
CPU time 0.63 seconds
Started Aug 25 06:47:32 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 206140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897960403 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2897960403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.2809421905
Short name T593
Test name
Test status
Simulation time 31675087 ps
CPU time 0.56 seconds
Started Aug 25 06:47:32 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809421905 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.2809421905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.565503573
Short name T571
Test name
Test status
Simulation time 40847551 ps
CPU time 0.69 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565503573 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.565503573
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.136678134
Short name T556
Test name
Test status
Simulation time 247672415 ps
CPU time 1.15 seconds
Started Aug 25 06:47:28 AM UTC 24
Finished Aug 25 06:47:32 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136678134 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.136678134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.1329169126
Short name T551
Test name
Test status
Simulation time 82050577 ps
CPU time 0.89 seconds
Started Aug 25 06:47:28 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329169126 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.1329169126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.1145271177
Short name T576
Test name
Test status
Simulation time 176590795 ps
CPU time 0.93 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1145271177 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.1145271177
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.2693635428
Short name T582
Test name
Test status
Simulation time 75470112 ps
CPU time 0.8 seconds
Started Aug 25 06:47:32 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2693635428 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.2693635428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2364712477
Short name T578
Test name
Test status
Simulation time 1109641895 ps
CPU time 1.97 seconds
Started Aug 25 06:47:30 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364712477 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2364712477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2165069158
Short name T597
Test name
Test status
Simulation time 1157773659 ps
CPU time 1.96 seconds
Started Aug 25 06:47:31 AM UTC 24
Finished Aug 25 06:47:41 AM UTC 24
Peak memory 210380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2165069158 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2165069158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1983869945
Short name T581
Test name
Test status
Simulation time 135040386 ps
CPU time 0.87 seconds
Started Aug 25 06:47:31 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1983869945 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1983869945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.2090911351
Short name T547
Test name
Test status
Simulation time 44289551 ps
CPU time 0.6 seconds
Started Aug 25 06:47:28 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090911351 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2090911351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.3441300940
Short name T572
Test name
Test status
Simulation time 51154942 ps
CPU time 0.73 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441300940 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.3441300940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.248504875
Short name T587
Test name
Test status
Simulation time 2513885481 ps
CPU time 4.75 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 211564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=248504875 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr
_stress_all_with_rand_reset.248504875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.3350139314
Short name T655
Test name
Test status
Simulation time 63592090 ps
CPU time 0.73 seconds
Started Aug 25 06:47:29 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350139314 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.3350139314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.4277791947
Short name T550
Test name
Test status
Simulation time 128776522 ps
CPU time 0.68 seconds
Started Aug 25 06:47:29 AM UTC 24
Finished Aug 25 06:47:31 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4277791947 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.4277791947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.3069481587
Short name T49
Test name
Test status
Simulation time 46478498 ps
CPU time 1.35 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:36 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069481587 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3069481587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.1156640083
Short name T153
Test name
Test status
Simulation time 73783473 ps
CPU time 1.03 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:38 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1156640083 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.1156640083
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.2814075922
Short name T146
Test name
Test status
Simulation time 36457886 ps
CPU time 0.86 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:37 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814075922 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.2814075922
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.2183106163
Short name T147
Test name
Test status
Simulation time 518962540 ps
CPU time 1.31 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:38 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183106163 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.2183106163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2628849383
Short name T18
Test name
Test status
Simulation time 35735230 ps
CPU time 0.87 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:37 AM UTC 24
Peak memory 206208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628849383 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.2628849383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.738875591
Short name T188
Test name
Test status
Simulation time 41920681 ps
CPU time 0.86 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:37 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738875591 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.738875591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.3181438963
Short name T192
Test name
Test status
Simulation time 57881321 ps
CPU time 1.01 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:38 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181438963 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.3181438963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.582633164
Short name T89
Test name
Test status
Simulation time 345157187 ps
CPU time 1.71 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:36 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582633164 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.582633164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.285464949
Short name T186
Test name
Test status
Simulation time 92389865 ps
CPU time 1.51 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:36 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285464949 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.285464949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.1038316987
Short name T191
Test name
Test status
Simulation time 161280357 ps
CPU time 1.17 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:38 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038316987 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.1038316987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.4036588319
Short name T28
Test name
Test status
Simulation time 873060780 ps
CPU time 2.26 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:39 AM UTC 24
Peak memory 238812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036588319 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.4036588319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.2998142390
Short name T190
Test name
Test status
Simulation time 121685988 ps
CPU time 1.45 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:38 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998142390 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.2998142390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.861202372
Short name T160
Test name
Test status
Simulation time 2762578269 ps
CPU time 2.7 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:39 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861202372 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.861202372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3660004524
Short name T195
Test name
Test status
Simulation time 821955930 ps
CPU time 3.51 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:40 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660004524 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3660004524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2746182473
Short name T189
Test name
Test status
Simulation time 82405435 ps
CPU time 1.29 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:38 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746182473 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2746182473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.2585150499
Short name T185
Test name
Test status
Simulation time 30030489 ps
CPU time 0.99 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:36 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585150499 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.2585150499
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.2614230868
Short name T135
Test name
Test status
Simulation time 1638644094 ps
CPU time 10.24 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:45:47 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614230868 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.2614230868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.404681597
Short name T92
Test name
Test status
Simulation time 6937224239 ps
CPU time 24.44 seconds
Started Aug 25 06:45:35 AM UTC 24
Finished Aug 25 06:46:02 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=404681597 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_
stress_all_with_rand_reset.404681597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.1176609740
Short name T88
Test name
Test status
Simulation time 104902218 ps
CPU time 1.16 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:36 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176609740 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.1176609740
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.817416272
Short name T187
Test name
Test status
Simulation time 185780652 ps
CPU time 1.78 seconds
Started Aug 25 06:45:33 AM UTC 24
Finished Aug 25 06:45:36 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=817416272 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.817416272
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.768409882
Short name T611
Test name
Test status
Simulation time 25603032 ps
CPU time 0.73 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 207876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=768409882 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.768409882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.4054929325
Short name T644
Test name
Test status
Simulation time 55402946 ps
CPU time 0.75 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4054929325 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.4054929325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.185152353
Short name T630
Test name
Test status
Simulation time 39961133 ps
CPU time 0.64 seconds
Started Aug 25 06:47:35 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=185152353 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.185152353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.714233942
Short name T639
Test name
Test status
Simulation time 392908906 ps
CPU time 0.86 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 206208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=714233942 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.714233942
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.827094707
Short name T636
Test name
Test status
Simulation time 47643995 ps
CPU time 0.73 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 208944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=827094707 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.827094707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.1979854612
Short name T631
Test name
Test status
Simulation time 53651107 ps
CPU time 0.63 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 206180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979854612 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.1979854612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.2174907491
Short name T638
Test name
Test status
Simulation time 81603571 ps
CPU time 0.7 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2174907491 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invalid.2174907491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.3212024932
Short name T577
Test name
Test status
Simulation time 381351746 ps
CPU time 1.02 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:36 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3212024932 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.3212024932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.78271699
Short name T565
Test name
Test status
Simulation time 53906992 ps
CPU time 0.81 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:35 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78271699 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.78271699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.1722065319
Short name T643
Test name
Test status
Simulation time 120984465 ps
CPU time 0.89 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722065319 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1722065319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.320341986
Short name T637
Test name
Test status
Simulation time 210961468 ps
CPU time 1.24 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320341986 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.320341986
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3782779949
Short name T622
Test name
Test status
Simulation time 1358692520 ps
CPU time 2.06 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:48 AM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782779949 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3782779949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.425191303
Short name T687
Test name
Test status
Simulation time 1156929468 ps
CPU time 2.44 seconds
Started Aug 25 06:47:34 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=425191303 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.425191303
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1742927777
Short name T675
Test name
Test status
Simulation time 73801961 ps
CPU time 0.93 seconds
Started Aug 25 06:47:34 AM UTC 24
Finished Aug 25 06:47:54 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742927777 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.1742927777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.1116244586
Short name T609
Test name
Test status
Simulation time 54340526 ps
CPU time 0.76 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116244586 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.1116244586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.1541354613
Short name T680
Test name
Test status
Simulation time 1026382306 ps
CPU time 3.76 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1541354613 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.1541354613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.2781339211
Short name T142
Test name
Test status
Simulation time 512699894 ps
CPU time 2.48 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2781339211 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmg
r_stress_all_with_rand_reset.2781339211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.2276385601
Short name T566
Test name
Test status
Simulation time 173163558 ps
CPU time 0.8 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:35 AM UTC 24
Peak memory 208160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276385601 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.2276385601
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.924235547
Short name T567
Test name
Test status
Simulation time 162001074 ps
CPU time 0.95 seconds
Started Aug 25 06:47:33 AM UTC 24
Finished Aug 25 06:47:35 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=924235547 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.924235547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.3935904382
Short name T617
Test name
Test status
Simulation time 121030663 ps
CPU time 0.88 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935904382 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3935904382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.1816161687
Short name T596
Test name
Test status
Simulation time 60682492 ps
CPU time 0.74 seconds
Started Aug 25 06:47:38 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816161687 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.1816161687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.1423018399
Short name T586
Test name
Test status
Simulation time 38535652 ps
CPU time 0.52 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423018399 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.1423018399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.947670243
Short name T594
Test name
Test status
Simulation time 401009553 ps
CPU time 0.8 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=947670243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.947670243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.2256750926
Short name T592
Test name
Test status
Simulation time 63213079 ps
CPU time 0.56 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256750926 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.2256750926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.2328854968
Short name T590
Test name
Test status
Simulation time 82863998 ps
CPU time 0.57 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328854968 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.2328854968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.2467479338
Short name T605
Test name
Test status
Simulation time 53596452 ps
CPU time 0.68 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467479338 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid.2467479338
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.2057748329
Short name T615
Test name
Test status
Simulation time 245197765 ps
CPU time 1.03 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057748329 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.2057748329
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.1667268907
Short name T649
Test name
Test status
Simulation time 61526214 ps
CPU time 0.86 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667268907 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.1667268907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.1747631572
Short name T670
Test name
Test status
Simulation time 104821464 ps
CPU time 1.18 seconds
Started Aug 25 06:47:40 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1747631572 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1747631572
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.362651461
Short name T598
Test name
Test status
Simulation time 263392734 ps
CPU time 1.23 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:41 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362651461 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.362651461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2311180861
Short name T619
Test name
Test status
Simulation time 1058417053 ps
CPU time 2.04 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:47 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2311180861 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2311180861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.572080135
Short name T599
Test name
Test status
Simulation time 1219324071 ps
CPU time 1.88 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:41 AM UTC 24
Peak memory 210380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572080135 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.572080135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.2417170106
Short name T588
Test name
Test status
Simulation time 77745827 ps
CPU time 0.72 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:40 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2417170106 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.2417170106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.2746461905
Short name T642
Test name
Test status
Simulation time 65533055 ps
CPU time 0.58 seconds
Started Aug 25 06:47:36 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746461905 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.2746461905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.2237072605
Short name T623
Test name
Test status
Simulation time 811060174 ps
CPU time 2.82 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:48 AM UTC 24
Peak memory 211576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237072605 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.2237072605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.2283627679
Short name T625
Test name
Test status
Simulation time 2384826163 ps
CPU time 3.77 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:49 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2283627679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmg
r_stress_all_with_rand_reset.2283627679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.2234432905
Short name T618
Test name
Test status
Simulation time 190151025 ps
CPU time 1.04 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2234432905 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.2234432905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.2348507008
Short name T608
Test name
Test status
Simulation time 147484838 ps
CPU time 0.65 seconds
Started Aug 25 06:47:37 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348507008 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.2348507008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.3765808562
Short name T610
Test name
Test status
Simulation time 52893775 ps
CPU time 0.6 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765808562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3765808562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.97344320
Short name T648
Test name
Test status
Simulation time 51954380 ps
CPU time 0.83 seconds
Started Aug 25 06:47:46 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97344320 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.97344320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.3540961846
Short name T672
Test name
Test status
Simulation time 44981644 ps
CPU time 0.61 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 206044 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540961846 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.3540961846
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.3291096460
Short name T604
Test name
Test status
Simulation time 188067458 ps
CPU time 0.77 seconds
Started Aug 25 06:47:42 AM UTC 24
Finished Aug 25 06:47:45 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291096460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.3291096460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.93489849
Short name T602
Test name
Test status
Simulation time 41589775 ps
CPU time 0.58 seconds
Started Aug 25 06:47:42 AM UTC 24
Finished Aug 25 06:47:45 AM UTC 24
Peak memory 206208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93489849 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.93489849
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.2382037658
Short name T603
Test name
Test status
Simulation time 64089682 ps
CPU time 0.58 seconds
Started Aug 25 06:47:42 AM UTC 24
Finished Aug 25 06:47:45 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382037658 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2382037658
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.3093935171
Short name T647
Test name
Test status
Simulation time 44989503 ps
CPU time 0.73 seconds
Started Aug 25 06:47:46 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3093935171 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.3093935171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.2661332229
Short name T616
Test name
Test status
Simulation time 257400611 ps
CPU time 1.15 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661332229 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.2661332229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.1956105881
Short name T612
Test name
Test status
Simulation time 129344451 ps
CPU time 0.84 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 210428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956105881 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.1956105881
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.3346980212
Short name T650
Test name
Test status
Simulation time 163089888 ps
CPU time 0.83 seconds
Started Aug 25 06:47:46 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 220140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346980212 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.3346980212
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.718215317
Short name T673
Test name
Test status
Simulation time 94027900 ps
CPU time 0.81 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=718215317 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.718215317
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1493869744
Short name T620
Test name
Test status
Simulation time 929582422 ps
CPU time 2.2 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:48 AM UTC 24
Peak memory 210700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493869744 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1493869744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1863092007
Short name T621
Test name
Test status
Simulation time 1330652821 ps
CPU time 2.2 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:48 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1863092007 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1863092007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3355892776
Short name T674
Test name
Test status
Simulation time 177313138 ps
CPU time 0.87 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355892776 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3355892776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.74635079
Short name T606
Test name
Test status
Simulation time 29535911 ps
CPU time 0.64 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74635079 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.74635079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.1830246167
Short name T652
Test name
Test status
Simulation time 57534860 ps
CPU time 0.7 seconds
Started Aug 25 06:47:46 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830246167 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.1830246167
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.1821673707
Short name T743
Test name
Test status
Simulation time 4980163852 ps
CPU time 13.04 seconds
Started Aug 25 06:47:46 AM UTC 24
Finished Aug 25 06:48:04 AM UTC 24
Peak memory 211752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1821673707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmg
r_stress_all_with_rand_reset.1821673707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.1088954380
Short name T614
Test name
Test status
Simulation time 237789781 ps
CPU time 0.89 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1088954380 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.1088954380
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.4245987884
Short name T613
Test name
Test status
Simulation time 170720016 ps
CPU time 0.85 seconds
Started Aug 25 06:47:41 AM UTC 24
Finished Aug 25 06:47:46 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4245987884 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.4245987884
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.93646445
Short name T667
Test name
Test status
Simulation time 67145840 ps
CPU time 0.62 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93646445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.93646445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.3092238640
Short name T633
Test name
Test status
Simulation time 83118501 ps
CPU time 0.7 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092238640 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.3092238640
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3319192817
Short name T627
Test name
Test status
Simulation time 77172563 ps
CPU time 0.6 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:50 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319192817 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.3319192817
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.1458388584
Short name T629
Test name
Test status
Simulation time 378151662 ps
CPU time 0.84 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458388584 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.1458388584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.4270066722
Short name T628
Test name
Test status
Simulation time 81346940 ps
CPU time 0.58 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270066722 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.4270066722
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.3623264724
Short name T626
Test name
Test status
Simulation time 280881896 ps
CPU time 0.59 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:50 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623264724 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.3623264724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.2049700164
Short name T641
Test name
Test status
Simulation time 43751444 ps
CPU time 0.72 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2049700164 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid.2049700164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.3387149206
Short name T585
Test name
Test status
Simulation time 113850230 ps
CPU time 0.83 seconds
Started Aug 25 06:47:46 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387149206 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.3387149206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.373350238
Short name T661
Test name
Test status
Simulation time 100178809 ps
CPU time 1.09 seconds
Started Aug 25 06:47:46 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=373350238 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.373350238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.3298779268
Short name T634
Test name
Test status
Simulation time 161724428 ps
CPU time 0.72 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298779268 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.3298779268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.96564772
Short name T632
Test name
Test status
Simulation time 84818219 ps
CPU time 0.85 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96564772 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.96564772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.24205910
Short name T665
Test name
Test status
Simulation time 793048844 ps
CPU time 3.04 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24205910 -ass
ert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.24205910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4136663469
Short name T691
Test name
Test status
Simulation time 837656966 ps
CPU time 3.06 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136663469 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4136663469
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2618551432
Short name T671
Test name
Test status
Simulation time 70030228 ps
CPU time 0.89 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618551432 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2618551432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.923023394
Short name T653
Test name
Test status
Simulation time 27414816 ps
CPU time 0.78 seconds
Started Aug 25 06:47:46 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923023394 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.923023394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.722774266
Short name T664
Test name
Test status
Simulation time 1309242884 ps
CPU time 1.38 seconds
Started Aug 25 06:47:49 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=722774266 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.722774266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.386570969
Short name T707
Test name
Test status
Simulation time 3233776502 ps
CPU time 5.43 seconds
Started Aug 25 06:47:49 AM UTC 24
Finished Aug 25 06:47:57 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=386570969 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr
_stress_all_with_rand_reset.386570969
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.1481176381
Short name T669
Test name
Test status
Simulation time 373026234 ps
CPU time 0.97 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1481176381 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.1481176381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.3226810741
Short name T668
Test name
Test status
Simulation time 37505702 ps
CPU time 0.78 seconds
Started Aug 25 06:47:47 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3226810741 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.3226810741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.1620180274
Short name T666
Test name
Test status
Simulation time 61534753 ps
CPU time 0.75 seconds
Started Aug 25 06:47:50 AM UTC 24
Finished Aug 25 06:47:53 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620180274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1620180274
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.281619304
Short name T682
Test name
Test status
Simulation time 61121304 ps
CPU time 0.91 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=281619304 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.281619304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.1538181761
Short name T692
Test name
Test status
Simulation time 28071712 ps
CPU time 0.76 seconds
Started Aug 25 06:47:52 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 206188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1538181761 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.1538181761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.201056084
Short name T696
Test name
Test status
Simulation time 179750396 ps
CPU time 0.99 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=201056084 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.201056084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.1216451242
Short name T694
Test name
Test status
Simulation time 43238264 ps
CPU time 0.7 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216451242 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.1216451242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.3856435435
Short name T695
Test name
Test status
Simulation time 23346316 ps
CPU time 0.92 seconds
Started Aug 25 06:47:52 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3856435435 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.3856435435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.703129199
Short name T681
Test name
Test status
Simulation time 57481240 ps
CPU time 0.75 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703129199 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invalid.703129199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.1731084278
Short name T651
Test name
Test status
Simulation time 256225284 ps
CPU time 0.78 seconds
Started Aug 25 06:47:49 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1731084278 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.1731084278
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.3262987307
Short name T646
Test name
Test status
Simulation time 86535056 ps
CPU time 0.6 seconds
Started Aug 25 06:47:49 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262987307 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.3262987307
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.242134638
Short name T685
Test name
Test status
Simulation time 160013310 ps
CPU time 0.92 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242134638 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.242134638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.2607238007
Short name T693
Test name
Test status
Simulation time 180225268 ps
CPU time 0.78 seconds
Started Aug 25 06:47:52 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 208200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607238007 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.2607238007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3887133204
Short name T679
Test name
Test status
Simulation time 994919413 ps
CPU time 1.98 seconds
Started Aug 25 06:47:51 AM UTC 24
Finished Aug 25 06:47:54 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887133204 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3887133204
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3933682563
Short name T678
Test name
Test status
Simulation time 2693463293 ps
CPU time 1.89 seconds
Started Aug 25 06:47:51 AM UTC 24
Finished Aug 25 06:47:54 AM UTC 24
Peak memory 210372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3933682563 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3933682563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1637103149
Short name T697
Test name
Test status
Simulation time 70342951 ps
CPU time 1.06 seconds
Started Aug 25 06:47:52 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1637103149 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1637103149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.3709105555
Short name T645
Test name
Test status
Simulation time 40883871 ps
CPU time 0.59 seconds
Started Aug 25 06:47:49 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709105555 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3709105555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.1321081391
Short name T714
Test name
Test status
Simulation time 1401126547 ps
CPU time 3.67 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:58 AM UTC 24
Peak memory 211576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1321081391 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.1321081391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.3805256580
Short name T742
Test name
Test status
Simulation time 4610206595 ps
CPU time 9.59 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:48:03 AM UTC 24
Peak memory 211368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3805256580 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmg
r_stress_all_with_rand_reset.3805256580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.3249974266
Short name T654
Test name
Test status
Simulation time 142206047 ps
CPU time 0.86 seconds
Started Aug 25 06:47:49 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3249974266 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.3249974266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.3181250281
Short name T659
Test name
Test status
Simulation time 287414070 ps
CPU time 1.3 seconds
Started Aug 25 06:47:49 AM UTC 24
Finished Aug 25 06:47:52 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181250281 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.3181250281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.577554848
Short name T700
Test name
Test status
Simulation time 77132012 ps
CPU time 1.01 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 210808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577554848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.577554848
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.159094355
Short name T710
Test name
Test status
Simulation time 81677735 ps
CPU time 0.8 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:47:57 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=159094355 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.159094355
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.965345521
Short name T699
Test name
Test status
Simulation time 28835222 ps
CPU time 0.75 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965345521 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.965345521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.3272783113
Short name T690
Test name
Test status
Simulation time 435329432 ps
CPU time 0.86 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272783113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3272783113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.2763735988
Short name T686
Test name
Test status
Simulation time 141331165 ps
CPU time 0.6 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763735988 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2763735988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.2831521464
Short name T698
Test name
Test status
Simulation time 41813218 ps
CPU time 0.77 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831521464 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.2831521464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.1560038824
Short name T708
Test name
Test status
Simulation time 207324417 ps
CPU time 0.74 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:47:57 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560038824 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid.1560038824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.1181459521
Short name T689
Test name
Test status
Simulation time 188634636 ps
CPU time 1.17 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181459521 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.1181459521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.567240381
Short name T684
Test name
Test status
Simulation time 58786588 ps
CPU time 0.74 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567240381 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.567240381
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.755199825
Short name T713
Test name
Test status
Simulation time 93211325 ps
CPU time 1.08 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:47:57 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755199825 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.755199825
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.2403183367
Short name T702
Test name
Test status
Simulation time 267264969 ps
CPU time 1 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403183367 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.2403183367
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4285526320
Short name T715
Test name
Test status
Simulation time 873564591 ps
CPU time 2.54 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:58 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4285526320 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4285526320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.405661605
Short name T716
Test name
Test status
Simulation time 855510476 ps
CPU time 3.16 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:58 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405661605 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.405661605
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2686411292
Short name T703
Test name
Test status
Simulation time 75055277 ps
CPU time 1.2 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686411292 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2686411292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.1761621210
Short name T683
Test name
Test status
Simulation time 49085821 ps
CPU time 0.73 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:55 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761621210 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.1761621210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.182110820
Short name T718
Test name
Test status
Simulation time 1625345693 ps
CPU time 3.42 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:48:00 AM UTC 24
Peak memory 211520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=182110820 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.182110820
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.2627409463
Short name T64
Test name
Test status
Simulation time 3962010653 ps
CPU time 15.49 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2627409463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmg
r_stress_all_with_rand_reset.2627409463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.3059764443
Short name T705
Test name
Test status
Simulation time 200828874 ps
CPU time 1.42 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:57 AM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059764443 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.3059764443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.4079063905
Short name T701
Test name
Test status
Simulation time 422235149 ps
CPU time 1.24 seconds
Started Aug 25 06:47:53 AM UTC 24
Finished Aug 25 06:47:56 AM UTC 24
Peak memory 210976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4079063905 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.4079063905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.945107454
Short name T725
Test name
Test status
Simulation time 46106388 ps
CPU time 0.67 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:48:00 AM UTC 24
Peak memory 208136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945107454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.945107454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.298346932
Short name T748
Test name
Test status
Simulation time 60008113 ps
CPU time 0.82 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:05 AM UTC 24
Peak memory 210404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298346932 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.298346932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.3201362547
Short name T657
Test name
Test status
Simulation time 32259449 ps
CPU time 0.76 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201362547 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.3201362547
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.556048638
Short name T732
Test name
Test status
Simulation time 114156355 ps
CPU time 0.97 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=556048638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.556048638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.1013563093
Short name T709
Test name
Test status
Simulation time 82277645 ps
CPU time 0.67 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1013563093 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.1013563093
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.3448218506
Short name T721
Test name
Test status
Simulation time 50879672 ps
CPU time 0.69 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448218506 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3448218506
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.1829153047
Short name T775
Test name
Test status
Simulation time 41967525 ps
CPU time 0.84 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1829153047 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invalid.1829153047
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.1351759430
Short name T734
Test name
Test status
Simulation time 303885902 ps
CPU time 1.37 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351759430 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.1351759430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.137626985
Short name T712
Test name
Test status
Simulation time 125268408 ps
CPU time 0.87 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:47:57 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137626985 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.137626985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.430199739
Short name T747
Test name
Test status
Simulation time 116967089 ps
CPU time 0.85 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:05 AM UTC 24
Peak memory 220140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430199739 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.430199739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.3882471143
Short name T731
Test name
Test status
Simulation time 290313644 ps
CPU time 0.92 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 208160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3882471143 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.3882471143
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1064456709
Short name T741
Test name
Test status
Simulation time 835296345 ps
CPU time 3.05 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:48:03 AM UTC 24
Peak memory 211316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064456709 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1064456709
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.42650022
Short name T740
Test name
Test status
Simulation time 1313215311 ps
CPU time 1.95 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:48:02 AM UTC 24
Peak memory 210536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42650022 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.42650022
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3365802365
Short name T735
Test name
Test status
Simulation time 65457904 ps
CPU time 1.23 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365802365 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.3365802365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.139387967
Short name T711
Test name
Test status
Simulation time 31683256 ps
CPU time 0.76 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:47:57 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139387967 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.139387967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.2567747931
Short name T813
Test name
Test status
Simulation time 1731785450 ps
CPU time 5.47 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567747931 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.2567747931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.2524662679
Short name T861
Test name
Test status
Simulation time 3961728177 ps
CPU time 10.2 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2524662679 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmg
r_stress_all_with_rand_reset.2524662679
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.4012670136
Short name T717
Test name
Test status
Simulation time 246729302 ps
CPU time 1.21 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012670136 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.4012670136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.1458167260
Short name T719
Test name
Test status
Simulation time 78137594 ps
CPU time 0.87 seconds
Started Aug 25 06:47:55 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458167260 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.1458167260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.1039098137
Short name T744
Test name
Test status
Simulation time 105133273 ps
CPU time 0.85 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:05 AM UTC 24
Peak memory 210824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039098137 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.1039098137
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.2811304403
Short name T767
Test name
Test status
Simulation time 78708461 ps
CPU time 0.67 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:11 AM UTC 24
Peak memory 208984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2811304403 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.2811304403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2874357551
Short name T749
Test name
Test status
Simulation time 30298179 ps
CPU time 0.6 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:05 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874357551 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.2874357551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.2220716644
Short name T764
Test name
Test status
Simulation time 107664369 ps
CPU time 0.83 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:11 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220716644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.2220716644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.3276691906
Short name T766
Test name
Test status
Simulation time 61406924 ps
CPU time 0.65 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:11 AM UTC 24
Peak memory 206184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276691906 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.3276691906
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.49286084
Short name T523
Test name
Test status
Simulation time 34094691 ps
CPU time 0.63 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=49286084 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.49286084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.3486325700
Short name T768
Test name
Test status
Simulation time 81341571 ps
CPU time 0.63 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:11 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486325700 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.3486325700
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.3066570574
Short name T776
Test name
Test status
Simulation time 281393026 ps
CPU time 0.95 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066570574 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.3066570574
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.1493243758
Short name T745
Test name
Test status
Simulation time 156679089 ps
CPU time 1.06 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:05 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1493243758 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.1493243758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.3236932377
Short name T769
Test name
Test status
Simulation time 92978747 ps
CPU time 0.93 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:11 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236932377 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.3236932377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.2377553335
Short name T737
Test name
Test status
Simulation time 317994432 ps
CPU time 1.19 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377553335 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.2377553335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3179285619
Short name T757
Test name
Test status
Simulation time 1858623304 ps
CPU time 2.14 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:06 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179285619 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3179285619
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.55770534
Short name T758
Test name
Test status
Simulation time 888999119 ps
CPU time 3.17 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:08 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55770534 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.55770534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2479295586
Short name T753
Test name
Test status
Simulation time 64360885 ps
CPU time 0.9 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479295586 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.2479295586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.3123154594
Short name T770
Test name
Test status
Simulation time 54710483 ps
CPU time 0.66 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123154594 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.3123154594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.3598489324
Short name T774
Test name
Test status
Simulation time 2414294706 ps
CPU time 3.3 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:14 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3598489324 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.3598489324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.3791726454
Short name T869
Test name
Test status
Simulation time 13262804423 ps
CPU time 17.34 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:28 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3791726454 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmg
r_stress_all_with_rand_reset.3791726454
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.2134854091
Short name T784
Test name
Test status
Simulation time 246142883 ps
CPU time 1.18 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134854091 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.2134854091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.2545846564
Short name T777
Test name
Test status
Simulation time 70016559 ps
CPU time 0.91 seconds
Started Aug 25 06:47:56 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545846564 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.2545846564
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.965014226
Short name T746
Test name
Test status
Simulation time 31864530 ps
CPU time 1.03 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:05 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=965014226 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.965014226
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.4269725731
Short name T728
Test name
Test status
Simulation time 73901128 ps
CPU time 0.74 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:00 AM UTC 24
Peak memory 211048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4269725731 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.4269725731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.1728537824
Short name T729
Test name
Test status
Simulation time 32427569 ps
CPU time 0.85 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 205344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728537824 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.1728537824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.2649967077
Short name T724
Test name
Test status
Simulation time 108648965 ps
CPU time 0.89 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:00 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649967077 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.2649967077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.2263780070
Short name T726
Test name
Test status
Simulation time 45979176 ps
CPU time 0.74 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 206080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263780070 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.2263780070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.2519370528
Short name T720
Test name
Test status
Simulation time 60865468 ps
CPU time 0.57 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:00 AM UTC 24
Peak memory 206172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2519370528 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2519370528
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.1905491861
Short name T727
Test name
Test status
Simulation time 76604713 ps
CPU time 0.64 seconds
Started Aug 25 06:47:59 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905491861 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid.1905491861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.3749655369
Short name T778
Test name
Test status
Simulation time 356567647 ps
CPU time 1.09 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 210924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749655369 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.3749655369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.3189507914
Short name T771
Test name
Test status
Simulation time 103428415 ps
CPU time 0.81 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189507914 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.3189507914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.3867279513
Short name T688
Test name
Test status
Simulation time 268398070 ps
CPU time 0.81 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3867279513 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3867279513
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2738000096
Short name T730
Test name
Test status
Simulation time 144303131 ps
CPU time 1.05 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 208236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2738000096 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.2738000096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.865076523
Short name T739
Test name
Test status
Simulation time 1315550545 ps
CPU time 2.52 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:02 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865076523 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.865076523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.654372286
Short name T736
Test name
Test status
Simulation time 1083898115 ps
CPU time 1.95 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:01 AM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654372286 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.654372286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3849461809
Short name T722
Test name
Test status
Simulation time 52770419 ps
CPU time 0.87 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849461809 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3849461809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.1384132193
Short name T773
Test name
Test status
Simulation time 29519896 ps
CPU time 0.82 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384132193 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.1384132193
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.3225658087
Short name T738
Test name
Test status
Simulation time 866900362 ps
CPU time 1.76 seconds
Started Aug 25 06:47:59 AM UTC 24
Finished Aug 25 06:48:02 AM UTC 24
Peak memory 209692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225658087 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.3225658087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.3700505180
Short name T800
Test name
Test status
Simulation time 15129018658 ps
CPU time 13.77 seconds
Started Aug 25 06:47:59 AM UTC 24
Finished Aug 25 06:48:14 AM UTC 24
Peak memory 210968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3700505180 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmg
r_stress_all_with_rand_reset.3700505180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.2905630302
Short name T780
Test name
Test status
Simulation time 272657652 ps
CPU time 0.91 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2905630302 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.2905630302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.197549373
Short name T723
Test name
Test status
Simulation time 288093299 ps
CPU time 1.16 seconds
Started Aug 25 06:47:58 AM UTC 24
Finished Aug 25 06:48:00 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197549373 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.197549373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.3455245398
Short name T820
Test name
Test status
Simulation time 124854856 ps
CPU time 0.8 seconds
Started Aug 25 06:48:01 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455245398 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.3455245398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.2202170471
Short name T755
Test name
Test status
Simulation time 67256219 ps
CPU time 0.84 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:06 AM UTC 24
Peak memory 210284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2202170471 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.2202170471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.758017526
Short name T825
Test name
Test status
Simulation time 31831457 ps
CPU time 0.64 seconds
Started Aug 25 06:48:01 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 206144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=758017526 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.758017526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.26071877
Short name T754
Test name
Test status
Simulation time 209310117 ps
CPU time 0.81 seconds
Started Aug 25 06:48:02 AM UTC 24
Finished Aug 25 06:48:06 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26071877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.26071877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.1287006892
Short name T750
Test name
Test status
Simulation time 32317180 ps
CPU time 0.6 seconds
Started Aug 25 06:48:02 AM UTC 24
Finished Aug 25 06:48:05 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287006892 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1287006892
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.3360488352
Short name T759
Test name
Test status
Simulation time 41284668 ps
CPU time 0.6 seconds
Started Aug 25 06:48:01 AM UTC 24
Finished Aug 25 06:48:10 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3360488352 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.3360488352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.657644118
Short name T751
Test name
Test status
Simulation time 180251565 ps
CPU time 0.62 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:05 AM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657644118 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invalid.657644118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.3265573606
Short name T786
Test name
Test status
Simulation time 370573809 ps
CPU time 1.09 seconds
Started Aug 25 06:48:00 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265573606 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.3265573606
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.2633124100
Short name T782
Test name
Test status
Simulation time 74185437 ps
CPU time 0.95 seconds
Started Aug 25 06:48:00 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2633124100 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.2633124100
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.4271417351
Short name T756
Test name
Test status
Simulation time 155595059 ps
CPU time 0.87 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:06 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4271417351 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.4271417351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2582618822
Short name T836
Test name
Test status
Simulation time 1356938469 ps
CPU time 2.38 seconds
Started Aug 25 06:48:01 AM UTC 24
Finished Aug 25 06:48:19 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2582618822 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2582618822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2798583748
Short name T837
Test name
Test status
Simulation time 884458646 ps
CPU time 2.54 seconds
Started Aug 25 06:48:01 AM UTC 24
Finished Aug 25 06:48:19 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798583748 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2798583748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2690902363
Short name T823
Test name
Test status
Simulation time 84043516 ps
CPU time 0.8 seconds
Started Aug 25 06:48:01 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690902363 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.2690902363
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.2922069707
Short name T779
Test name
Test status
Simulation time 32359578 ps
CPU time 0.72 seconds
Started Aug 25 06:48:00 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2922069707 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.2922069707
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.3809018110
Short name T828
Test name
Test status
Simulation time 2866436520 ps
CPU time 4.88 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809018110 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.3809018110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.716445993
Short name T856
Test name
Test status
Simulation time 6755311599 ps
CPU time 8.67 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 211664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=716445993 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr
_stress_all_with_rand_reset.716445993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1280251638
Short name T821
Test name
Test status
Simulation time 188909276 ps
CPU time 1.02 seconds
Started Aug 25 06:48:01 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280251638 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1280251638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.3901595704
Short name T830
Test name
Test status
Simulation time 378176614 ps
CPU time 1.24 seconds
Started Aug 25 06:48:01 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901595704 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.3901595704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1495937316
Short name T15
Test name
Test status
Simulation time 40481857 ps
CPU time 1.27 seconds
Started Aug 25 06:45:37 AM UTC 24
Finished Aug 25 06:45:40 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495937316 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1495937316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3337595298
Short name T154
Test name
Test status
Simulation time 80221249 ps
CPU time 1.06 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337595298 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.3337595298
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.1284546600
Short name T152
Test name
Test status
Simulation time 30473714 ps
CPU time 0.95 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:41 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284546600 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.1284546600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3907642705
Short name T148
Test name
Test status
Simulation time 1151639720 ps
CPU time 1.3 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907642705 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3907642705
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.1534961644
Short name T19
Test name
Test status
Simulation time 50259443 ps
CPU time 1.03 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534961644 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.1534961644
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.3140711447
Short name T198
Test name
Test status
Simulation time 60437058 ps
CPU time 0.87 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:41 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3140711447 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.3140711447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.2277509845
Short name T200
Test name
Test status
Simulation time 46415041 ps
CPU time 0.98 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277509845 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.2277509845
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.1064189105
Short name T196
Test name
Test status
Simulation time 177543504 ps
CPU time 1.58 seconds
Started Aug 25 06:45:37 AM UTC 24
Finished Aug 25 06:45:40 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064189105 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.1064189105
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.4135075221
Short name T8
Test name
Test status
Simulation time 70561060 ps
CPU time 1.45 seconds
Started Aug 25 06:45:37 AM UTC 24
Finished Aug 25 06:45:40 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135075221 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.4135075221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.583103479
Short name T199
Test name
Test status
Simulation time 163133215 ps
CPU time 0.95 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583103479 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.583103479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.3769311652
Short name T203
Test name
Test status
Simulation time 393754464 ps
CPU time 1.44 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769311652 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.3769311652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.130516077
Short name T155
Test name
Test status
Simulation time 877478873 ps
CPU time 3.59 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130516077 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.130516077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3074786586
Short name T218
Test name
Test status
Simulation time 865687517 ps
CPU time 5.56 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:46 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074786586 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3074786586
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2137532324
Short name T201
Test name
Test status
Simulation time 66600065 ps
CPU time 1.37 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2137532324 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.2137532324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.3944807366
Short name T193
Test name
Test status
Simulation time 32237417 ps
CPU time 0.98 seconds
Started Aug 25 06:45:36 AM UTC 24
Finished Aug 25 06:45:38 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944807366 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.3944807366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.3350064741
Short name T204
Test name
Test status
Simulation time 204048509 ps
CPU time 1.53 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350064741 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.3350064741
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.270634283
Short name T25
Test name
Test status
Simulation time 3803937082 ps
CPU time 9.03 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:50 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=270634283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_
stress_all_with_rand_reset.270634283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.3919577921
Short name T172
Test name
Test status
Simulation time 198074146 ps
CPU time 1.7 seconds
Started Aug 25 06:45:37 AM UTC 24
Finished Aug 25 06:45:40 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919577921 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.3919577921
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.3654081235
Short name T197
Test name
Test status
Simulation time 483045615 ps
CPU time 1.96 seconds
Started Aug 25 06:45:37 AM UTC 24
Finished Aug 25 06:45:40 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3654081235 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.3654081235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/4.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.1396017446
Short name T795
Test name
Test status
Simulation time 19724114 ps
CPU time 0.63 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:13 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396017446 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1396017446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.2106788031
Short name T762
Test name
Test status
Simulation time 88106236 ps
CPU time 0.71 seconds
Started Aug 25 06:48:05 AM UTC 24
Finished Aug 25 06:48:11 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106788031 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.2106788031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.2735219837
Short name T794
Test name
Test status
Simulation time 32513053 ps
CPU time 0.58 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:13 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2735219837 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.2735219837
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.3686086504
Short name T822
Test name
Test status
Simulation time 24569535 ps
CPU time 0.69 seconds
Started Aug 25 06:48:04 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686086504 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.3686086504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.3371543302
Short name T819
Test name
Test status
Simulation time 37028643 ps
CPU time 0.82 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 206128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371543302 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.3371543302
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.24044151
Short name T761
Test name
Test status
Simulation time 87314998 ps
CPU time 0.65 seconds
Started Aug 25 06:48:05 AM UTC 24
Finished Aug 25 06:48:10 AM UTC 24
Peak memory 210780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24044151 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid.24044151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.3553659889
Short name T796
Test name
Test status
Simulation time 242417557 ps
CPU time 0.79 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:13 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3553659889 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.3553659889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.3715062876
Short name T792
Test name
Test status
Simulation time 25002411 ps
CPU time 0.66 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:13 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3715062876 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3715062876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.3675112336
Short name T763
Test name
Test status
Simulation time 155152984 ps
CPU time 0.86 seconds
Started Aug 25 06:48:05 AM UTC 24
Finished Aug 25 06:48:11 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3675112336 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.3675112336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.3195713032
Short name T829
Test name
Test status
Simulation time 232358041 ps
CPU time 1.19 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 210816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3195713032 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.3195713032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.812882476
Short name T804
Test name
Test status
Simulation time 891221352 ps
CPU time 3.11 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:15 AM UTC 24
Peak memory 211312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812882476 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.812882476
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.992755542
Short name T833
Test name
Test status
Simulation time 1257291369 ps
CPU time 2.2 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:18 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992755542 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.992755542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4247117005
Short name T816
Test name
Test status
Simulation time 52437735 ps
CPU time 0.87 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 208228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247117005 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4247117005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.2734485764
Short name T793
Test name
Test status
Simulation time 52449045 ps
CPU time 0.62 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:13 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2734485764 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.2734485764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.4216869931
Short name T765
Test name
Test status
Simulation time 596969156 ps
CPU time 1.21 seconds
Started Aug 25 06:48:05 AM UTC 24
Finished Aug 25 06:48:11 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216869931 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.4216869931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.70858437
Short name T143
Test name
Test status
Simulation time 11121879409 ps
CPU time 16.67 seconds
Started Aug 25 06:48:05 AM UTC 24
Finished Aug 25 06:48:27 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=70858437 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_
stress_all_with_rand_reset.70858437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.2385480056
Short name T797
Test name
Test status
Simulation time 364250931 ps
CPU time 0.91 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:13 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2385480056 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.2385480056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.742389699
Short name T798
Test name
Test status
Simulation time 267126910 ps
CPU time 1.06 seconds
Started Aug 25 06:48:03 AM UTC 24
Finished Aug 25 06:48:13 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742389699 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.742389699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.945035063
Short name T783
Test name
Test status
Simulation time 50617146 ps
CPU time 0.95 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 210928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945035063 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.945035063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.1159163616
Short name T844
Test name
Test status
Simulation time 64494259 ps
CPU time 0.73 seconds
Started Aug 25 06:48:11 AM UTC 24
Finished Aug 25 06:48:20 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1159163616 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.1159163616
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3690358109
Short name T785
Test name
Test status
Simulation time 50539653 ps
CPU time 0.63 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690358109 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.3690358109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.454316613
Short name T849
Test name
Test status
Simulation time 105828689 ps
CPU time 0.92 seconds
Started Aug 25 06:48:11 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454316613 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.454316613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.1393527998
Short name T846
Test name
Test status
Simulation time 54408150 ps
CPU time 0.74 seconds
Started Aug 25 06:48:11 AM UTC 24
Finished Aug 25 06:48:20 AM UTC 24
Peak memory 208932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393527998 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.1393527998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.3184052865
Short name T787
Test name
Test status
Simulation time 37400194 ps
CPU time 0.59 seconds
Started Aug 25 06:48:10 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184052865 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.3184052865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.495607312
Short name T853
Test name
Test status
Simulation time 77115402 ps
CPU time 0.77 seconds
Started Aug 25 06:48:11 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495607312 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invalid.495607312
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.1408908754
Short name T789
Test name
Test status
Simulation time 160987066 ps
CPU time 1.01 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1408908754 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.1408908754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.726435026
Short name T781
Test name
Test status
Simulation time 62835720 ps
CPU time 0.78 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726435026 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.726435026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.920508292
Short name T858
Test name
Test status
Simulation time 145801401 ps
CPU time 0.88 seconds
Started Aug 25 06:48:11 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920508292 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.920508292
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.1997943109
Short name T772
Test name
Test status
Simulation time 249885126 ps
CPU time 1.07 seconds
Started Aug 25 06:48:08 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 209452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997943109 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.1997943109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1684471646
Short name T799
Test name
Test status
Simulation time 966595069 ps
CPU time 2.11 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:13 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684471646 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1684471646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.525879014
Short name T801
Test name
Test status
Simulation time 831816214 ps
CPU time 3.23 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:15 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=525879014 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.525879014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3129050079
Short name T788
Test name
Test status
Simulation time 144789095 ps
CPU time 0.79 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129050079 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3129050079
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.3329812035
Short name T760
Test name
Test status
Simulation time 36953163 ps
CPU time 0.58 seconds
Started Aug 25 06:48:06 AM UTC 24
Finished Aug 25 06:48:10 AM UTC 24
Peak memory 208200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3329812035 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.3329812035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.189412682
Short name T790
Test name
Test status
Simulation time 289111549 ps
CPU time 1.23 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189412682 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.189412682
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.3911987178
Short name T791
Test name
Test status
Simulation time 247527426 ps
CPU time 1.07 seconds
Started Aug 25 06:48:07 AM UTC 24
Finished Aug 25 06:48:12 AM UTC 24
Peak memory 210536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911987178 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.3911987178
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.1108603213
Short name T805
Test name
Test status
Simulation time 22775921 ps
CPU time 0.79 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1108603213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.1108603213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.4191921673
Short name T814
Test name
Test status
Simulation time 59825846 ps
CPU time 0.85 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191921673 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.4191921673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1734392396
Short name T808
Test name
Test status
Simulation time 45629946 ps
CPU time 0.66 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1734392396 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.1734392396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.264442343
Short name T815
Test name
Test status
Simulation time 111682699 ps
CPU time 1.02 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 208216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=264442343 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.264442343
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.2454731626
Short name T812
Test name
Test status
Simulation time 37085823 ps
CPU time 0.71 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 206080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2454731626 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.2454731626
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.1445856600
Short name T809
Test name
Test status
Simulation time 97646595 ps
CPU time 0.68 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1445856600 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1445856600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.1178007566
Short name T817
Test name
Test status
Simulation time 49388167 ps
CPU time 0.72 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1178007566 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid.1178007566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.402777382
Short name T839
Test name
Test status
Simulation time 163483077 ps
CPU time 0.8 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:20 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402777382 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.402777382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.1221324026
Short name T811
Test name
Test status
Simulation time 180602831 ps
CPU time 0.77 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221324026 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.1221324026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.3106486569
Short name T807
Test name
Test status
Simulation time 100110812 ps
CPU time 0.91 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106486569 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.3106486569
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3782427675
Short name T835
Test name
Test status
Simulation time 769844991 ps
CPU time 3.13 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:18 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782427675 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3782427675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4094618331
Short name T834
Test name
Test status
Simulation time 872341554 ps
CPU time 2.83 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:18 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094618331 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4094618331
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2224513532
Short name T810
Test name
Test status
Simulation time 136727272 ps
CPU time 0.86 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2224513532 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.2224513532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.3849454927
Short name T841
Test name
Test status
Simulation time 1354142849 ps
CPU time 4.22 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:20 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849454927 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.3849454927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.3832590147
Short name T109
Test name
Test status
Simulation time 2281324587 ps
CPU time 7.67 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:23 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3832590147 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmg
r_stress_all_with_rand_reset.3832590147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.1343968362
Short name T806
Test name
Test status
Simulation time 74552823 ps
CPU time 0.89 seconds
Started Aug 25 06:48:13 AM UTC 24
Finished Aug 25 06:48:16 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343968362 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.1343968362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.559036761
Short name T831
Test name
Test status
Simulation time 85859393 ps
CPU time 0.95 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 210760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559036761 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.559036761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.2365607965
Short name T854
Test name
Test status
Simulation time 120747466 ps
CPU time 0.72 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 210700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365607965 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.2365607965
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.2328890169
Short name T843
Test name
Test status
Simulation time 30216628 ps
CPU time 0.61 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:20 AM UTC 24
Peak memory 205468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328890169 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.2328890169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.1897991441
Short name T848
Test name
Test status
Simulation time 381819046 ps
CPU time 0.82 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897991441 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.1897991441
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.872624800
Short name T847
Test name
Test status
Simulation time 64022447 ps
CPU time 0.7 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 206008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872624800 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.872624800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.3453028314
Short name T852
Test name
Test status
Simulation time 32226904 ps
CPU time 0.75 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453028314 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3453028314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.2240535452
Short name T855
Test name
Test status
Simulation time 43125789 ps
CPU time 0.68 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240535452 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid.2240535452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.611257016
Short name T832
Test name
Test status
Simulation time 335979725 ps
CPU time 1.57 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:18 AM UTC 24
Peak memory 208120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611257016 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.611257016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.2204266071
Short name T824
Test name
Test status
Simulation time 124826998 ps
CPU time 0.97 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204266071 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.2204266071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.2518990350
Short name T859
Test name
Test status
Simulation time 131395021 ps
CPU time 0.85 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2518990350 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.2518990350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.3476922419
Short name T851
Test name
Test status
Simulation time 133084170 ps
CPU time 0.95 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476922419 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.3476922419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4152310277
Short name T838
Test name
Test status
Simulation time 969763284 ps
CPU time 3.03 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:19 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152310277 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4152310277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3388971224
Short name T845
Test name
Test status
Simulation time 90167320 ps
CPU time 0.75 seconds
Started Aug 25 06:48:15 AM UTC 24
Finished Aug 25 06:48:20 AM UTC 24
Peak memory 207560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388971224 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3388971224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.3776074026
Short name T818
Test name
Test status
Simulation time 36917570 ps
CPU time 0.71 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776074026 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3776074026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.322420584
Short name T904
Test name
Test status
Simulation time 1355576093 ps
CPU time 4.47 seconds
Started Aug 25 06:48:16 AM UTC 24
Finished Aug 25 06:49:01 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322420584 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.322420584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.2404746203
Short name T917
Test name
Test status
Simulation time 3800612837 ps
CPU time 12.36 seconds
Started Aug 25 06:48:16 AM UTC 24
Finished Aug 25 06:49:09 AM UTC 24
Peak memory 221152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2404746203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmg
r_stress_all_with_rand_reset.2404746203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.1548163024
Short name T826
Test name
Test status
Simulation time 225668859 ps
CPU time 0.85 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1548163024 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.1548163024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.2883653063
Short name T827
Test name
Test status
Simulation time 186866583 ps
CPU time 0.85 seconds
Started Aug 25 06:48:14 AM UTC 24
Finished Aug 25 06:48:17 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883653063 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.2883653063
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3066788905
Short name T881
Test name
Test status
Simulation time 20003903 ps
CPU time 0.69 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066788905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.3066788905
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.2227404282
Short name T893
Test name
Test status
Simulation time 90217249 ps
CPU time 0.72 seconds
Started Aug 25 06:48:19 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227404282 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.2227404282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.2720832759
Short name T840
Test name
Test status
Simulation time 39886393 ps
CPU time 0.59 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:20 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720832759 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.2720832759
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.764311668
Short name T860
Test name
Test status
Simulation time 108949140 ps
CPU time 0.87 seconds
Started Aug 25 06:48:19 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764311668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.764311668
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.4084710070
Short name T857
Test name
Test status
Simulation time 37506884 ps
CPU time 0.74 seconds
Started Aug 25 06:48:19 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4084710070 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.4084710070
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.2169002245
Short name T891
Test name
Test status
Simulation time 42404245 ps
CPU time 0.61 seconds
Started Aug 25 06:48:19 AM UTC 24
Finished Aug 25 06:48:57 AM UTC 24
Peak memory 206132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169002245 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.2169002245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.436925744
Short name T884
Test name
Test status
Simulation time 171145043 ps
CPU time 1.14 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 208232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436925744 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.436925744
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.1719020530
Short name T879
Test name
Test status
Simulation time 76315334 ps
CPU time 0.99 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1719020530 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.1719020530
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.2356914681
Short name T850
Test name
Test status
Simulation time 303531914 ps
CPU time 1.2 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:21 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2356914681 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.2356914681
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2375402424
Short name T890
Test name
Test status
Simulation time 1413144645 ps
CPU time 2.11 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:57 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375402424 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2375402424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1876255335
Short name T899
Test name
Test status
Simulation time 867191623 ps
CPU time 2.91 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876255335 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1876255335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.917905214
Short name T883
Test name
Test status
Simulation time 74078166 ps
CPU time 0.96 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=917905214 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.917905214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.2223722747
Short name T878
Test name
Test status
Simulation time 56468210 ps
CPU time 0.7 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223722747 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.2223722747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.328897805
Short name T880
Test name
Test status
Simulation time 206792796 ps
CPU time 0.81 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328897805 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.328897805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.1890037350
Short name T888
Test name
Test status
Simulation time 197806677 ps
CPU time 1.18 seconds
Started Aug 25 06:48:17 AM UTC 24
Finished Aug 25 06:48:57 AM UTC 24
Peak memory 210284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890037350 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.1890037350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.3153777473
Short name T875
Test name
Test status
Simulation time 68876910 ps
CPU time 0.8 seconds
Started Aug 25 06:48:20 AM UTC 24
Finished Aug 25 06:48:45 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3153777473 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.3153777473
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.4207656132
Short name T912
Test name
Test status
Simulation time 1826588385 ps
CPU time 0.74 seconds
Started Aug 25 06:48:19 AM UTC 24
Finished Aug 25 06:49:05 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207656132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.4207656132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.1026029154
Short name T871
Test name
Test status
Simulation time 74122070 ps
CPU time 0.62 seconds
Started Aug 25 06:48:20 AM UTC 24
Finished Aug 25 06:48:35 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026029154 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.1026029154
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.822110736
Short name T872
Test name
Test status
Simulation time 74527935 ps
CPU time 0.59 seconds
Started Aug 25 06:48:20 AM UTC 24
Finished Aug 25 06:48:36 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822110736 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invalid.822110736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.1171075203
Short name T876
Test name
Test status
Simulation time 175128994 ps
CPU time 0.81 seconds
Started Aug 25 06:48:20 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1171075203 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.1171075203
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.3954023394
Short name T862
Test name
Test status
Simulation time 154497345 ps
CPU time 0.94 seconds
Started Aug 25 06:48:19 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954023394 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.3954023394
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.4256567149
Short name T936
Test name
Test status
Simulation time 812505971 ps
CPU time 3.29 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:49:24 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4256567149 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.4256567149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.3569744418
Short name T900
Test name
Test status
Simulation time 3684561083 ps
CPU time 3.44 seconds
Started Aug 25 06:48:21 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 211440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3569744418 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmg
r_stress_all_with_rand_reset.3569744418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.166018430
Short name T889
Test name
Test status
Simulation time 57041083 ps
CPU time 0.6 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:57 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166018430 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.166018430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.1806079895
Short name T867
Test name
Test status
Simulation time 73818014 ps
CPU time 0.62 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1806079895 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.1806079895
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.3960316695
Short name T865
Test name
Test status
Simulation time 30209179 ps
CPU time 0.63 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3960316695 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.3960316695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.1819024699
Short name T803
Test name
Test status
Simulation time 112354645 ps
CPU time 0.79 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819024699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.1819024699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.1715032342
Short name T802
Test name
Test status
Simulation time 48093385 ps
CPU time 0.62 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715032342 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.1715032342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.2242304995
Short name T866
Test name
Test status
Simulation time 35407718 ps
CPU time 0.56 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242304995 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2242304995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.3599012400
Short name T842
Test name
Test status
Simulation time 50682334 ps
CPU time 0.67 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3599012400 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid.3599012400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.4023893731
Short name T928
Test name
Test status
Simulation time 132246356 ps
CPU time 0.7 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4023893731 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.4023893731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.1628488998
Short name T864
Test name
Test status
Simulation time 94082126 ps
CPU time 0.85 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628488998 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.1628488998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.2891082164
Short name T868
Test name
Test status
Simulation time 272120647 ps
CPU time 0.87 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891082164 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.2891082164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.591254836
Short name T898
Test name
Test status
Simulation time 1064849347 ps
CPU time 1.8 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591254836 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.591254836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3327452697
Short name T902
Test name
Test status
Simulation time 831411301 ps
CPU time 2.71 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:59 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3327452697 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3327452697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3285353693
Short name T863
Test name
Test status
Simulation time 91926017 ps
CPU time 0.77 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:25 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3285353693 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3285353693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2770725223
Short name T926
Test name
Test status
Simulation time 31520490 ps
CPU time 0.61 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2770725223 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2770725223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.166131502
Short name T870
Test name
Test status
Simulation time 1803093414 ps
CPU time 3.87 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:29 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166131502 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.166131502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.4164918183
Short name T53
Test name
Test status
Simulation time 2332806718 ps
CPU time 8.52 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:48:33 AM UTC 24
Peak memory 211592 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4164918183 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmg
r_stress_all_with_rand_reset.4164918183
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.1534688208
Short name T938
Test name
Test status
Simulation time 461842805 ps
CPU time 0.79 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534688208 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.1534688208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.76523098
Short name T939
Test name
Test status
Simulation time 477824830 ps
CPU time 1.05 seconds
Started Aug 25 06:48:22 AM UTC 24
Finished Aug 25 06:49:29 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76523098 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.76523098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/46.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.1459827217
Short name T873
Test name
Test status
Simulation time 51639266 ps
CPU time 0.69 seconds
Started Aug 25 06:48:33 AM UTC 24
Finished Aug 25 06:48:36 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1459827217 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.1459827217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.3524084393
Short name T901
Test name
Test status
Simulation time 392674580 ps
CPU time 0.77 seconds
Started Aug 25 06:48:29 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524084393 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.3524084393
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.1221916764
Short name T897
Test name
Test status
Simulation time 35665524 ps
CPU time 0.57 seconds
Started Aug 25 06:48:29 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221916764 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.1221916764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.109960015
Short name T937
Test name
Test status
Simulation time 73047634 ps
CPU time 0.55 seconds
Started Aug 25 06:48:28 AM UTC 24
Finished Aug 25 06:49:28 AM UTC 24
Peak memory 205880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=109960015 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.109960015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.872506934
Short name T874
Test name
Test status
Simulation time 41911242 ps
CPU time 0.65 seconds
Started Aug 25 06:48:37 AM UTC 24
Finished Aug 25 06:48:45 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872506934 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invalid.872506934
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.682225883
Short name T894
Test name
Test status
Simulation time 31349243 ps
CPU time 0.68 seconds
Started Aug 25 06:48:26 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682225883 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.682225883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.387591938
Short name T886
Test name
Test status
Simulation time 151195338 ps
CPU time 0.76 seconds
Started Aug 25 06:48:34 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=387591938 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.387591938
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.1779460903
Short name T885
Test name
Test status
Simulation time 53834400 ps
CPU time 0.72 seconds
Started Aug 25 06:48:27 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779460903 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.1779460903
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3215884894
Short name T930
Test name
Test status
Simulation time 164128081 ps
CPU time 0.85 seconds
Started Aug 25 06:48:26 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215884894 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.3215884894
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.1824118260
Short name T882
Test name
Test status
Simulation time 28793266 ps
CPU time 0.69 seconds
Started Aug 25 06:48:24 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 208088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824118260 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.1824118260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.3248242717
Short name T905
Test name
Test status
Simulation time 2186186649 ps
CPU time 7.33 seconds
Started Aug 25 06:48:37 AM UTC 24
Finished Aug 25 06:49:02 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3248242717 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.3248242717
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.3473926893
Short name T54
Test name
Test status
Simulation time 2050102080 ps
CPU time 8.04 seconds
Started Aug 25 06:48:37 AM UTC 24
Finished Aug 25 06:48:53 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3473926893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmg
r_stress_all_with_rand_reset.3473926893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.4278140522
Short name T895
Test name
Test status
Simulation time 198687656 ps
CPU time 1.08 seconds
Started Aug 25 06:48:26 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278140522 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.4278140522
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.1490634208
Short name T877
Test name
Test status
Simulation time 45948899 ps
CPU time 0.58 seconds
Started Aug 25 06:48:54 AM UTC 24
Finished Aug 25 06:48:56 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1490634208 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.1490634208
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.2353136625
Short name T909
Test name
Test status
Simulation time 76325530 ps
CPU time 0.7 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:05 AM UTC 24
Peak memory 211052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353136625 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.2353136625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.2042761811
Short name T907
Test name
Test status
Simulation time 39424066 ps
CPU time 0.54 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:05 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042761811 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.2042761811
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.1537084206
Short name T913
Test name
Test status
Simulation time 196947433 ps
CPU time 0.77 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:06 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537084206 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.1537084206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3475496505
Short name T910
Test name
Test status
Simulation time 53488174 ps
CPU time 0.64 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:05 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475496505 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3475496505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.717130719
Short name T908
Test name
Test status
Simulation time 48308844 ps
CPU time 0.59 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:05 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717130719 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.717130719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.536143597
Short name T903
Test name
Test status
Simulation time 43289045 ps
CPU time 0.86 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:01 AM UTC 24
Peak memory 210912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536143597 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invalid.536143597
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.1010053382
Short name T932
Test name
Test status
Simulation time 224471417 ps
CPU time 1.04 seconds
Started Aug 25 06:48:46 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1010053382 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.1010053382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.1280325807
Short name T925
Test name
Test status
Simulation time 96760035 ps
CPU time 0.75 seconds
Started Aug 25 06:48:46 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 210900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280325807 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1280325807
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.891240745
Short name T915
Test name
Test status
Simulation time 104309489 ps
CPU time 0.96 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:06 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891240745 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.891240745
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.315773632
Short name T914
Test name
Test status
Simulation time 173917991 ps
CPU time 0.98 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315773632 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.315773632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3938948229
Short name T896
Test name
Test status
Simulation time 754223646 ps
CPU time 2.89 seconds
Started Aug 25 06:48:54 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938948229 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3938948229
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.489640508
Short name T916
Test name
Test status
Simulation time 1237477437 ps
CPU time 1.99 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:07 AM UTC 24
Peak memory 210352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489640508 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.489640508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1497041791
Short name T911
Test name
Test status
Simulation time 91093383 ps
CPU time 0.76 seconds
Started Aug 25 06:48:56 AM UTC 24
Finished Aug 25 06:49:05 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497041791 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1497041791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.3973130439
Short name T892
Test name
Test status
Simulation time 29821647 ps
CPU time 0.63 seconds
Started Aug 25 06:48:42 AM UTC 24
Finished Aug 25 06:48:58 AM UTC 24
Peak memory 208208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3973130439 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.3973130439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.1120992365
Short name T906
Test name
Test status
Simulation time 3461535278 ps
CPU time 4.32 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:04 AM UTC 24
Peak memory 211548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1120992365 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.1120992365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.1900551453
Short name T918
Test name
Test status
Simulation time 7662347231 ps
CPU time 10.46 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:10 AM UTC 24
Peak memory 211620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1900551453 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmg
r_stress_all_with_rand_reset.1900551453
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.2437350968
Short name T922
Test name
Test status
Simulation time 63215382 ps
CPU time 0.59 seconds
Started Aug 25 06:48:46 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2437350968 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.2437350968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.3748864352
Short name T933
Test name
Test status
Simulation time 362583754 ps
CPU time 1.07 seconds
Started Aug 25 06:48:46 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748864352 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.3748864352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/48.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.1150274799
Short name T927
Test name
Test status
Simulation time 22997022 ps
CPU time 0.73 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150274799 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.1150274799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.1154809495
Short name T887
Test name
Test status
Simulation time 185963204 ps
CPU time 0.86 seconds
Started Aug 25 06:48:59 AM UTC 24
Finished Aug 25 06:49:52 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154809495 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.1154809495
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.3048540169
Short name T929
Test name
Test status
Simulation time 72171417 ps
CPU time 0.58 seconds
Started Aug 25 06:48:59 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3048540169 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.3048540169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.908845708
Short name T921
Test name
Test status
Simulation time 240168969 ps
CPU time 0.87 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908845708 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.908845708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.1367002645
Short name T920
Test name
Test status
Simulation time 106671565 ps
CPU time 0.65 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:11 AM UTC 24
Peak memory 207952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367002645 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.1367002645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2937377
Short name T934
Test name
Test status
Simulation time 1112312524 ps
CPU time 2.01 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:22 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937377 -asse
rt nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /
workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2937377
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2753437559
Short name T935
Test name
Test status
Simulation time 1033533426 ps
CPU time 2.41 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:23 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753437559 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2753437559
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1284752612
Short name T931
Test name
Test status
Simulation time 53581520 ps
CPU time 0.79 seconds
Started Aug 25 06:48:59 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284752612 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.1284752612
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.4107371580
Short name T919
Test name
Test status
Simulation time 37654042 ps
CPU time 0.62 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:11 AM UTC 24
Peak memory 208032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107371580 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.4107371580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.3538957384
Short name T940
Test name
Test status
Simulation time 194793815 ps
CPU time 0.88 seconds
Started Aug 25 06:48:59 AM UTC 24
Finished Aug 25 06:49:59 AM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538957384 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.3538957384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.3791918914
Short name T941
Test name
Test status
Simulation time 3495092544 ps
CPU time 7.78 seconds
Started Aug 25 06:48:59 AM UTC 24
Finished Aug 25 06:50:06 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3791918914 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmg
r_stress_all_with_rand_reset.3791918914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.3838385195
Short name T924
Test name
Test status
Simulation time 199519793 ps
CPU time 0.7 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838385195 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.3838385195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.436673804
Short name T923
Test name
Test status
Simulation time 279592179 ps
CPU time 0.67 seconds
Started Aug 25 06:48:58 AM UTC 24
Finished Aug 25 06:49:21 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=436673804 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.436673804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.3110156855
Short name T47
Test name
Test status
Simulation time 31905811 ps
CPU time 1.09 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110156855 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.3110156855
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.1846725880
Short name T156
Test name
Test status
Simulation time 78637036 ps
CPU time 1 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:45 AM UTC 24
Peak memory 211072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1846725880 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.1846725880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.2813627037
Short name T149
Test name
Test status
Simulation time 32828573 ps
CPU time 0.85 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2813627037 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.2813627037
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.4108619847
Short name T150
Test name
Test status
Simulation time 113457874 ps
CPU time 1.46 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:45 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4108619847 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.4108619847
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.3448358144
Short name T211
Test name
Test status
Simulation time 49434140 ps
CPU time 0.98 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:45 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3448358144 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3448358144
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.3231348239
Short name T206
Test name
Test status
Simulation time 52919739 ps
CPU time 0.86 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231348239 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.3231348239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.4265638767
Short name T213
Test name
Test status
Simulation time 78475748 ps
CPU time 0.98 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:45 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265638767 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid.4265638767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.872768464
Short name T205
Test name
Test status
Simulation time 128433178 ps
CPU time 1.1 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872768464 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.872768464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.311991992
Short name T207
Test name
Test status
Simulation time 408609556 ps
CPU time 1.19 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=311991992 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.311991992
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.2000851955
Short name T217
Test name
Test status
Simulation time 100477928 ps
CPU time 1.38 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:46 AM UTC 24
Peak memory 220100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2000851955 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2000851955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.3527609743
Short name T208
Test name
Test status
Simulation time 117305950 ps
CPU time 1.12 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527609743 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.3527609743
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.932069904
Short name T224
Test name
Test status
Simulation time 927188428 ps
CPU time 5.17 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:48 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932069904 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.932069904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2992344373
Short name T157
Test name
Test status
Simulation time 1339236218 ps
CPU time 3.22 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:46 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992344373 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2992344373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.4057158170
Short name T209
Test name
Test status
Simulation time 50762988 ps
CPU time 1.4 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057158170 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.4057158170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3320212710
Short name T202
Test name
Test status
Simulation time 33270015 ps
CPU time 0.97 seconds
Started Aug 25 06:45:39 AM UTC 24
Finished Aug 25 06:45:42 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3320212710 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.3320212710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2894229951
Short name T229
Test name
Test status
Simulation time 1469387500 ps
CPU time 3.93 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:48 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894229951 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.2894229951
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2298102841
Short name T91
Test name
Test status
Simulation time 5804693614 ps
CPU time 14.7 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2298102841 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr
_stress_all_with_rand_reset.2298102841
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.941864378
Short name T210
Test name
Test status
Simulation time 252075020 ps
CPU time 2.09 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:44 AM UTC 24
Peak memory 210748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941864378 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.941864378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3952942862
Short name T212
Test name
Test status
Simulation time 270634026 ps
CPU time 2.48 seconds
Started Aug 25 06:45:41 AM UTC 24
Finished Aug 25 06:45:45 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952942862 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.3952942862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2259722479
Short name T134
Test name
Test status
Simulation time 36735776 ps
CPU time 1.43 seconds
Started Aug 25 06:45:44 AM UTC 24
Finished Aug 25 06:45:47 AM UTC 24
Peak memory 210908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2259722479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.2259722479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2820478408
Short name T158
Test name
Test status
Simulation time 67238783 ps
CPU time 1.08 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:48 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820478408 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.2820478408
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.359156973
Short name T151
Test name
Test status
Simulation time 40320319 ps
CPU time 0.86 seconds
Started Aug 25 06:45:45 AM UTC 24
Finished Aug 25 06:45:47 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=359156973 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.359156973
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.4018526021
Short name T231
Test name
Test status
Simulation time 113253631 ps
CPU time 1.43 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:49 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018526021 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.4018526021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.728035521
Short name T225
Test name
Test status
Simulation time 51750011 ps
CPU time 0.95 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:48 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728035521 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.728035521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.2572864596
Short name T221
Test name
Test status
Simulation time 88571583 ps
CPU time 0.9 seconds
Started Aug 25 06:45:45 AM UTC 24
Finished Aug 25 06:45:47 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572864596 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2572864596
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.2192728114
Short name T226
Test name
Test status
Simulation time 42488802 ps
CPU time 1.03 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:48 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192728114 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid.2192728114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.738143692
Short name T220
Test name
Test status
Simulation time 283542001 ps
CPU time 2.26 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:47 AM UTC 24
Peak memory 210820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738143692 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.738143692
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1271710168
Short name T215
Test name
Test status
Simulation time 84286962 ps
CPU time 1.15 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:46 AM UTC 24
Peak memory 210372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271710168 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1271710168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.1140640800
Short name T228
Test name
Test status
Simulation time 152945545 ps
CPU time 1.17 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:48 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1140640800 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.1140640800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.1960090096
Short name T223
Test name
Test status
Simulation time 289621606 ps
CPU time 1.49 seconds
Started Aug 25 06:45:45 AM UTC 24
Finished Aug 25 06:45:47 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960090096 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.1960090096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.166949781
Short name T105
Test name
Test status
Simulation time 754376814 ps
CPU time 5.29 seconds
Started Aug 25 06:45:44 AM UTC 24
Finished Aug 25 06:45:51 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166949781 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.166949781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3789393719
Short name T97
Test name
Test status
Simulation time 872111666 ps
CPU time 3.74 seconds
Started Aug 25 06:45:45 AM UTC 24
Finished Aug 25 06:45:49 AM UTC 24
Peak memory 211272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3789393719 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3789393719
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2653149390
Short name T222
Test name
Test status
Simulation time 171570621 ps
CPU time 1.29 seconds
Started Aug 25 06:45:45 AM UTC 24
Finished Aug 25 06:45:47 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653149390 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2653149390
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.580120563
Short name T214
Test name
Test status
Simulation time 164167052 ps
CPU time 0.91 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:45 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580120563 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.580120563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.3005117191
Short name T262
Test name
Test status
Simulation time 3257520827 ps
CPU time 8.72 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:56 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3005117191 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.3005117191
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.257650851
Short name T93
Test name
Test status
Simulation time 9550645797 ps
CPU time 16.99 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=257650851 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_
stress_all_with_rand_reset.257650851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1602308042
Short name T219
Test name
Test status
Simulation time 216922348 ps
CPU time 1.71 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:46 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602308042 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.1602308042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4263876999
Short name T216
Test name
Test status
Simulation time 235794883 ps
CPU time 1.11 seconds
Started Aug 25 06:45:43 AM UTC 24
Finished Aug 25 06:45:46 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4263876999 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.4263876999
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3648640337
Short name T232
Test name
Test status
Simulation time 45342108 ps
CPU time 0.88 seconds
Started Aug 25 06:45:47 AM UTC 24
Finished Aug 25 06:45:49 AM UTC 24
Peak memory 208168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3648640337 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.3648640337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3575291936
Short name T98
Test name
Test status
Simulation time 76690949 ps
CPU time 0.83 seconds
Started Aug 25 06:45:48 AM UTC 24
Finished Aug 25 06:45:50 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575291936 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.3575291936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.3517905113
Short name T234
Test name
Test status
Simulation time 113209068 ps
CPU time 1.46 seconds
Started Aug 25 06:45:49 AM UTC 24
Finished Aug 25 06:45:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517905113 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.3517905113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.1568434018
Short name T101
Test name
Test status
Simulation time 39629131 ps
CPU time 0.89 seconds
Started Aug 25 06:45:49 AM UTC 24
Finished Aug 25 06:45:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1568434018 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.1568434018
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.3616184328
Short name T99
Test name
Test status
Simulation time 49456416 ps
CPU time 0.85 seconds
Started Aug 25 06:45:49 AM UTC 24
Finished Aug 25 06:45:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3616184328 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.3616184328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.4134414505
Short name T106
Test name
Test status
Simulation time 42207168 ps
CPU time 1.06 seconds
Started Aug 25 06:45:49 AM UTC 24
Finished Aug 25 06:45:51 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4134414505 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.4134414505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.4055988015
Short name T95
Test name
Test status
Simulation time 216928776 ps
CPU time 1.1 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:49 AM UTC 24
Peak memory 208140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055988015 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.4055988015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3224216655
Short name T233
Test name
Test status
Simulation time 161878095 ps
CPU time 1.13 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:49 AM UTC 24
Peak memory 211032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224216655 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3224216655
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1582999764
Short name T235
Test name
Test status
Simulation time 109510720 ps
CPU time 1.71 seconds
Started Aug 25 06:45:49 AM UTC 24
Finished Aug 25 06:45:52 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582999764 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1582999764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.4008168349
Short name T108
Test name
Test status
Simulation time 361596152 ps
CPU time 1.46 seconds
Started Aug 25 06:45:49 AM UTC 24
Finished Aug 25 06:45:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4008168349 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.4008168349
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1052912213
Short name T242
Test name
Test status
Simulation time 819226447 ps
CPU time 3.35 seconds
Started Aug 25 06:45:48 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1052912213 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1052912213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3859658760
Short name T238
Test name
Test status
Simulation time 900222390 ps
CPU time 3.08 seconds
Started Aug 25 06:45:48 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859658760 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3859658760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3180834828
Short name T100
Test name
Test status
Simulation time 116545776 ps
CPU time 1.1 seconds
Started Aug 25 06:45:48 AM UTC 24
Finished Aug 25 06:45:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3180834828 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.3180834828
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.921525695
Short name T227
Test name
Test status
Simulation time 56108082 ps
CPU time 0.94 seconds
Started Aug 25 06:45:46 AM UTC 24
Finished Aug 25 06:45:48 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921525695 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.921525695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.1510698620
Short name T111
Test name
Test status
Simulation time 907790824 ps
CPU time 3.29 seconds
Started Aug 25 06:45:50 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1510698620 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.1510698620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.1594591802
Short name T230
Test name
Test status
Simulation time 42334372 ps
CPU time 0.95 seconds
Started Aug 25 06:45:47 AM UTC 24
Finished Aug 25 06:45:49 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594591802 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.1594591802
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2852481426
Short name T96
Test name
Test status
Simulation time 94207857 ps
CPU time 1.46 seconds
Started Aug 25 06:45:47 AM UTC 24
Finished Aug 25 06:45:49 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2852481426 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.2852481426
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.1273048311
Short name T240
Test name
Test status
Simulation time 60733876 ps
CPU time 0.93 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273048311 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.1273048311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2578662228
Short name T179
Test name
Test status
Simulation time 73118220 ps
CPU time 1.18 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578662228 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.2578662228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1411669336
Short name T241
Test name
Test status
Simulation time 30042691 ps
CPU time 0.84 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 205856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1411669336 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.1411669336
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.3782342672
Short name T247
Test name
Test status
Simulation time 387663790 ps
CPU time 1.23 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782342672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.3782342672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3100108521
Short name T250
Test name
Test status
Simulation time 51363604 ps
CPU time 0.88 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100108521 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3100108521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.3943699955
Short name T243
Test name
Test status
Simulation time 56561101 ps
CPU time 0.9 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3943699955 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.3943699955
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.4247345400
Short name T252
Test name
Test status
Simulation time 57653053 ps
CPU time 1.01 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247345400 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid.4247345400
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.4131876116
Short name T244
Test name
Test status
Simulation time 151628002 ps
CPU time 1.57 seconds
Started Aug 25 06:45:50 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131876116 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.4131876116
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.1736391242
Short name T236
Test name
Test status
Simulation time 144966423 ps
CPU time 0.95 seconds
Started Aug 25 06:45:50 AM UTC 24
Finished Aug 25 06:45:52 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1736391242 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.1736391242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3031941940
Short name T253
Test name
Test status
Simulation time 495347574 ps
CPU time 1.15 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3031941940 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.3031941940
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.215434974
Short name T248
Test name
Test status
Simulation time 185954075 ps
CPU time 1.33 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 207432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=215434974 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.215434974
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2463807049
Short name T263
Test name
Test status
Simulation time 781500464 ps
CPU time 4.85 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463807049 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2463807049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2064245141
Short name T260
Test name
Test status
Simulation time 877489428 ps
CPU time 3.84 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:56 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2064245141 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2064245141
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174392276
Short name T245
Test name
Test status
Simulation time 75399455 ps
CPU time 1.2 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174392276 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.4174392276
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2630797358
Short name T237
Test name
Test status
Simulation time 28930584 ps
CPU time 1.06 seconds
Started Aug 25 06:45:50 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630797358 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2630797358
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1019569171
Short name T278
Test name
Test status
Simulation time 2511406097 ps
CPU time 4.52 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 211420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1019569171 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1019569171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.1422984422
Short name T110
Test name
Test status
Simulation time 15132630382 ps
CPU time 24.49 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:46:19 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1422984422 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr
_stress_all_with_rand_reset.1422984422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.3777363268
Short name T246
Test name
Test status
Simulation time 202267245 ps
CPU time 1.59 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 208012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777363268 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.3777363268
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.466223568
Short name T239
Test name
Test status
Simulation time 51895737 ps
CPU time 1.04 seconds
Started Aug 25 06:45:51 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466223568 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.466223568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.3719046638
Short name T255
Test name
Test status
Simulation time 120435590 ps
CPU time 1.01 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719046638 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.3719046638
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.2933273435
Short name T178
Test name
Test status
Simulation time 56890011 ps
CPU time 1.06 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933273435 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.2933273435
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.846432641
Short name T265
Test name
Test status
Simulation time 29453879 ps
CPU time 0.95 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 205844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846432641 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.846432641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.84935114
Short name T272
Test name
Test status
Simulation time 200240868 ps
CPU time 1.31 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=84935114 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.84935114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.590946447
Short name T266
Test name
Test status
Simulation time 248170310 ps
CPU time 0.88 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 209048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590946447 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.590946447
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.573390761
Short name T264
Test name
Test status
Simulation time 86548469 ps
CPU time 0.87 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573390761 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.573390761
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.3848539306
Short name T271
Test name
Test status
Simulation time 107348158 ps
CPU time 1.01 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 210632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3848539306 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.3848539306
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.3338126370
Short name T257
Test name
Test status
Simulation time 115758292 ps
CPU time 1.15 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338126370 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.3338126370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.1018376535
Short name T256
Test name
Test status
Simulation time 106247852 ps
CPU time 1.2 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 210372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1018376535 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.1018376535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.2272141883
Short name T273
Test name
Test status
Simulation time 153308211 ps
CPU time 1.19 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272141883 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.2272141883
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.1251790448
Short name T267
Test name
Test status
Simulation time 234354237 ps
CPU time 1.15 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1251790448 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.1251790448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2204695255
Short name T277
Test name
Test status
Simulation time 900394141 ps
CPU time 3.86 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:58 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204695255 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.2204695255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2342475171
Short name T283
Test name
Test status
Simulation time 900611505 ps
CPU time 5.2 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342475171 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2342475171
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.433818508
Short name T261
Test name
Test status
Simulation time 62349123 ps
CPU time 1.25 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433818508 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.433818508
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.1181434929
Short name T254
Test name
Test status
Simulation time 26155241 ps
CPU time 0.96 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1181434929 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.1181434929
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.889914112
Short name T280
Test name
Test status
Simulation time 307786983 ps
CPU time 2.71 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 211668 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889914112 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.889914112
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.2154848782
Short name T102
Test name
Test status
Simulation time 7191282996 ps
CPU time 12.81 seconds
Started Aug 25 06:45:55 AM UTC 24
Finished Aug 25 06:46:09 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2154848782 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr
_stress_all_with_rand_reset.2154848782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.2995665765
Short name T259
Test name
Test status
Simulation time 581130965 ps
CPU time 1.35 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2995665765 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.2995665765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.3683786132
Short name T258
Test name
Test status
Simulation time 87155777 ps
CPU time 1.15 seconds
Started Aug 25 06:45:53 AM UTC 24
Finished Aug 25 06:45:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3683786132 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_24/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.3683786132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest
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