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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.95 98.23 96.58 99.62 96.00 96.37 100.00 98.85


Total test records in report: 1076
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html
T1004 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.4065875164 Aug 29 10:56:52 AM UTC 24 Aug 29 10:56:57 AM UTC 24 25681073 ps
T1005 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.3869316128 Aug 29 10:56:47 AM UTC 24 Aug 29 10:56:57 AM UTC 24 139397508 ps
T1006 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.3500534386 Aug 29 10:56:26 AM UTC 24 Aug 29 10:56:58 AM UTC 24 21646537 ps
T1007 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.570547991 Aug 29 10:56:16 AM UTC 24 Aug 29 10:56:58 AM UTC 24 22815773 ps
T1008 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3398866527 Aug 29 10:56:52 AM UTC 24 Aug 29 10:56:58 AM UTC 24 324268388 ps
T1009 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2493892004 Aug 29 10:56:26 AM UTC 24 Aug 29 10:56:58 AM UTC 24 27284570 ps
T1010 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.3795076631 Aug 29 10:56:26 AM UTC 24 Aug 29 10:56:58 AM UTC 24 19117447 ps
T1011 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2834517078 Aug 29 10:56:52 AM UTC 24 Aug 29 10:56:58 AM UTC 24 237350515 ps
T1012 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1981510214 Aug 29 10:56:53 AM UTC 24 Aug 29 10:56:58 AM UTC 24 184492315 ps
T1013 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3451725709 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:00 AM UTC 24 67773358 ps
T1014 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4267653555 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:01 AM UTC 24 67895103 ps
T1015 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2487716728 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:01 AM UTC 24 19725140 ps
T1016 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1598464067 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:01 AM UTC 24 17801701 ps
T1017 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.2291721506 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:01 AM UTC 24 57010335 ps
T1018 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.4226870412 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:01 AM UTC 24 37861700 ps
T1019 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.2489489800 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:01 AM UTC 24 18401267 ps
T1020 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2781132696 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:01 AM UTC 24 31752344 ps
T1021 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.2262297750 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:01 AM UTC 24 16993562 ps
T1022 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.3935195774 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:29 AM UTC 24 24688754 ps
T1023 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2121925117 Aug 29 10:56:57 AM UTC 24 Aug 29 10:57:06 AM UTC 24 72667892 ps
T1024 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3568927368 Aug 29 10:56:57 AM UTC 24 Aug 29 10:57:06 AM UTC 24 21866339 ps
T1025 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.402733081 Aug 29 10:56:57 AM UTC 24 Aug 29 10:57:06 AM UTC 24 37996362 ps
T106 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1823839464 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:06 AM UTC 24 20496538 ps
T1026 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.935044349 Aug 29 10:56:57 AM UTC 24 Aug 29 10:57:07 AM UTC 24 55493417 ps
T1027 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3860027267 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:07 AM UTC 24 102433832 ps
T1028 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.890638280 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:07 AM UTC 24 238227436 ps
T1029 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.2052284987 Aug 29 10:56:57 AM UTC 24 Aug 29 10:57:07 AM UTC 24 70142293 ps
T1030 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.559405508 Aug 29 10:56:57 AM UTC 24 Aug 29 10:57:07 AM UTC 24 265293896 ps
T1031 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.1107751151 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:11 AM UTC 24 44421060 ps
T1032 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.546455654 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:11 AM UTC 24 52235532 ps
T1033 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.577719969 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:11 AM UTC 24 25085361 ps
T1034 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.3324876260 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:11 AM UTC 24 19053509 ps
T1035 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.270526973 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:11 AM UTC 24 82176033 ps
T1036 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.379327764 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:11 AM UTC 24 27028267 ps
T1037 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1898727456 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:16 AM UTC 24 19017917 ps
T1038 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2025112813 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:16 AM UTC 24 81949497 ps
T107 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1273644567 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:16 AM UTC 24 23406975 ps
T1039 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.1771562149 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:17 AM UTC 24 74052917 ps
T1040 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1910492989 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:17 AM UTC 24 92266445 ps
T1041 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2133066539 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:17 AM UTC 24 22989216 ps
T1042 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1757249657 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:17 AM UTC 24 38947898 ps
T1043 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.804271134 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:17 AM UTC 24 111113612 ps
T1044 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1696979239 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:17 AM UTC 24 127246623 ps
T1045 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.205836778 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:17 AM UTC 24 102285490 ps
T1046 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3107923726 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:17 AM UTC 24 371426672 ps
T1047 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.2076694781 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:21 AM UTC 24 28240869 ps
T1048 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.3122621294 Aug 29 10:57:02 AM UTC 24 Aug 29 10:57:21 AM UTC 24 41054878 ps
T1049 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.2933626499 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:21 AM UTC 24 15213794 ps
T1050 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.3314206690 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:21 AM UTC 24 24878355 ps
T1051 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.1717737008 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:21 AM UTC 24 43840740 ps
T1052 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.3404203098 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:21 AM UTC 24 18149773 ps
T1053 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.1085041255 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:21 AM UTC 24 42395702 ps
T1054 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1011746860 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:22 AM UTC 24 47683927 ps
T1055 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.2254573210 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:22 AM UTC 24 30983814 ps
T1056 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.2912161585 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:22 AM UTC 24 19942046 ps
T1057 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.1051854212 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:22 AM UTC 24 22234723 ps
T1058 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.4198566015 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:22 AM UTC 24 22643158 ps
T1059 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.1180369256 Aug 29 10:56:47 AM UTC 24 Aug 29 10:57:22 AM UTC 24 67636085 ps
T1060 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1514426586 Aug 29 10:56:29 AM UTC 24 Aug 29 10:57:22 AM UTC 24 40398628 ps
T1061 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3007024614 Aug 29 10:56:23 AM UTC 24 Aug 29 10:57:22 AM UTC 24 111421290 ps
T1062 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.3041987397 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:29 AM UTC 24 17620857 ps
T1063 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1216335027 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:27 AM UTC 24 53660962 ps
T1064 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.3384569386 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:27 AM UTC 24 21437194 ps
T1065 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1647741186 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:27 AM UTC 24 64215980 ps
T1066 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3597393672 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:27 AM UTC 24 47257361 ps
T1067 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3644811008 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:27 AM UTC 24 52057529 ps
T1068 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2232943333 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:27 AM UTC 24 229985886 ps
T1069 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3272845879 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:27 AM UTC 24 106092945 ps
T1070 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.4095312562 Aug 29 10:56:58 AM UTC 24 Aug 29 10:57:28 AM UTC 24 87943072 ps
T108 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.2916193913 Aug 29 10:56:23 AM UTC 24 Aug 29 10:57:29 AM UTC 24 24644359 ps
T1071 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.3399766257 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:29 AM UTC 24 74681072 ps
T1072 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.2526197657 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:29 AM UTC 24 39498400 ps
T1073 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.2279487253 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:29 AM UTC 24 36507875 ps
T1074 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.4131170659 Aug 29 10:57:00 AM UTC 24 Aug 29 10:57:29 AM UTC 24 49444057 ps
T1075 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.363471587 Aug 29 10:56:47 AM UTC 24 Aug 29 10:57:30 AM UTC 24 31993618 ps
T1076 /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.1519328500 Aug 29 10:56:30 AM UTC 24 Aug 29 10:57:30 AM UTC 24 107896757 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.100834472
Short name T9
Test name
Test status
Simulation time 1594398886 ps
CPU time 3.29 seconds
Started Aug 29 10:52:28 AM UTC 24
Finished Aug 29 10:52:34 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100834472 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.100834472
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.1994371287
Short name T29
Test name
Test status
Simulation time 152169434 ps
CPU time 1.27 seconds
Started Aug 29 10:52:35 AM UTC 24
Finished Aug 29 10:52:37 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994371287 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.1994371287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.1260613896
Short name T24
Test name
Test status
Simulation time 4972582852 ps
CPU time 19.91 seconds
Started Aug 29 10:52:36 AM UTC 24
Finished Aug 29 10:52:58 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1260613896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr
_stress_all_with_rand_reset.1260613896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2246236984
Short name T22
Test name
Test status
Simulation time 922083324 ps
CPU time 2.43 seconds
Started Aug 29 10:52:52 AM UTC 24
Finished Aug 29 10:52:56 AM UTC 24
Peak memory 238880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2246236984 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.2246236984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.3011908153
Short name T34
Test name
Test status
Simulation time 406773251 ps
CPU time 1.57 seconds
Started Aug 29 10:52:39 AM UTC 24
Finished Aug 29 10:52:41 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011908153 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.3011908153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3901380885
Short name T57
Test name
Test status
Simulation time 194129784 ps
CPU time 1.39 seconds
Started Aug 29 10:56:15 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3901380885 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.3901380885
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.4089775400
Short name T43
Test name
Test status
Simulation time 45525063 ps
CPU time 1.1 seconds
Started Aug 29 10:52:36 AM UTC 24
Finished Aug 29 10:52:39 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4089775400 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid.4089775400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1406439000
Short name T28
Test name
Test status
Simulation time 962128087 ps
CPU time 4.01 seconds
Started Aug 29 10:52:41 AM UTC 24
Finished Aug 29 10:52:46 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406439000 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1406439000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2971393944
Short name T51
Test name
Test status
Simulation time 155742983 ps
CPU time 1.78 seconds
Started Aug 29 10:56:14 AM UTC 24
Finished Aug 29 10:56:18 AM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2971393944 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2971393944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2989830158
Short name T39
Test name
Test status
Simulation time 946574648 ps
CPU time 3.95 seconds
Started Aug 29 10:52:41 AM UTC 24
Finished Aug 29 10:52:46 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989830158 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2989830158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.2553809562
Short name T168
Test name
Test status
Simulation time 57984476 ps
CPU time 0.58 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:46 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553809562 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.2553809562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.3145335006
Short name T10
Test name
Test status
Simulation time 29599770 ps
CPU time 0.96 seconds
Started Aug 29 10:52:32 AM UTC 24
Finished Aug 29 10:52:34 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145335006 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.3145335006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.338843598
Short name T71
Test name
Test status
Simulation time 11477308447 ps
CPU time 18.52 seconds
Started Aug 29 10:53:26 AM UTC 24
Finished Aug 29 10:53:46 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=338843598 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_
stress_all_with_rand_reset.338843598
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.3451664362
Short name T100
Test name
Test status
Simulation time 50477595 ps
CPU time 0.91 seconds
Started Aug 29 10:56:14 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 210724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451664362 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.3451664362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.1596629953
Short name T52
Test name
Test status
Simulation time 286056681 ps
CPU time 1.35 seconds
Started Aug 29 10:52:33 AM UTC 24
Finished Aug 29 10:52:36 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1596629953 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.1596629953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.608927015
Short name T45
Test name
Test status
Simulation time 1518061996 ps
CPU time 3.37 seconds
Started Aug 29 10:52:46 AM UTC 24
Finished Aug 29 10:52:50 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=608927015 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.608927015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.2300291341
Short name T14
Test name
Test status
Simulation time 57743507 ps
CPU time 1.26 seconds
Started Aug 29 10:52:35 AM UTC 24
Finished Aug 29 10:52:37 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2300291341 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.2300291341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2704568047
Short name T63
Test name
Test status
Simulation time 61332585 ps
CPU time 0.96 seconds
Started Aug 29 10:56:14 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 209824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2704568047 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_w
ith_rand_reset.2704568047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.3398866527
Short name T1008
Test name
Test status
Simulation time 324268388 ps
CPU time 1.25 seconds
Started Aug 29 10:56:52 AM UTC 24
Finished Aug 29 10:56:58 AM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3398866527 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.3398866527
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.2203618206
Short name T159
Test name
Test status
Simulation time 57821436 ps
CPU time 0.97 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203618206 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.2203618206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.410853894
Short name T53
Test name
Test status
Simulation time 16317395 ps
CPU time 0.57 seconds
Started Aug 29 10:56:13 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410853894 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.410853894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.16122188
Short name T62
Test name
Test status
Simulation time 326444538 ps
CPU time 0.72 seconds
Started Aug 29 10:56:14 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16122188 -assert nopostproc +UV
M_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_same_csr_outstanding.16122188
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1034730245
Short name T7
Test name
Test status
Simulation time 2997363393 ps
CPU time 2.96 seconds
Started Aug 29 10:52:27 AM UTC 24
Finished Aug 29 10:52:32 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1034730245 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1034730245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.136503998
Short name T157
Test name
Test status
Simulation time 68356387 ps
CPU time 1.02 seconds
Started Aug 29 10:53:59 AM UTC 24
Finished Aug 29 10:54:01 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=136503998 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.136503998
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.695718713
Short name T17
Test name
Test status
Simulation time 48853800 ps
CPU time 0.9 seconds
Started Aug 29 10:52:44 AM UTC 24
Finished Aug 29 10:52:46 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=695718713 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.695718713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.4022777018
Short name T170
Test name
Test status
Simulation time 1100198875 ps
CPU time 2.97 seconds
Started Aug 29 10:56:14 AM UTC 24
Finished Aug 29 10:56:19 AM UTC 24
Peak memory 211320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022777018 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.4022777018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.3041337159
Short name T54
Test name
Test status
Simulation time 34493325 ps
CPU time 0.64 seconds
Started Aug 29 10:56:14 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 208384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041337159 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.3041337159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1232099369
Short name T55
Test name
Test status
Simulation time 53647674 ps
CPU time 0.59 seconds
Started Aug 29 10:56:14 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232099369 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1232099369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3074987794
Short name T65
Test name
Test status
Simulation time 157885618 ps
CPU time 2.15 seconds
Started Aug 29 10:56:13 AM UTC 24
Finished Aug 29 10:56:18 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074987794 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3074987794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.4085019280
Short name T50
Test name
Test status
Simulation time 184650025 ps
CPU time 0.98 seconds
Started Aug 29 10:56:13 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4085019280 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.4085019280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.1501721065
Short name T957
Test name
Test status
Simulation time 23740692 ps
CPU time 0.72 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 209332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501721065 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.1501721065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.414119404
Short name T968
Test name
Test status
Simulation time 785910697 ps
CPU time 2.82 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:24 AM UTC 24
Peak memory 211060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414119404 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.414119404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2478349686
Short name T956
Test name
Test status
Simulation time 32416926 ps
CPU time 0.56 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478349686 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2478349686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.1178783653
Short name T70
Test name
Test status
Simulation time 81043483 ps
CPU time 0.79 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 209824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1178783653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_w
ith_rand_reset.1178783653
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1284745849
Short name T110
Test name
Test status
Simulation time 26079027 ps
CPU time 0.58 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284745849 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1284745849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.570547991
Short name T1007
Test name
Test status
Simulation time 22815773 ps
CPU time 0.6 seconds
Started Aug 29 10:56:16 AM UTC 24
Finished Aug 29 10:56:58 AM UTC 24
Peak memory 207028 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570547991 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.570547991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.3015707166
Short name T111
Test name
Test status
Simulation time 46379433 ps
CPU time 0.65 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 210000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015707166 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.3015707166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.1123841746
Short name T986
Test name
Test status
Simulation time 53663504 ps
CPU time 0.9 seconds
Started Aug 29 10:56:47 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1123841746 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_
with_rand_reset.1123841746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.1180369256
Short name T1059
Test name
Test status
Simulation time 67636085 ps
CPU time 0.54 seconds
Started Aug 29 10:56:47 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180369256 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.1180369256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.2228707340
Short name T165
Test name
Test status
Simulation time 52992744 ps
CPU time 0.58 seconds
Started Aug 29 10:56:47 AM UTC 24
Finished Aug 29 10:56:55 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228707340 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.2228707340
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.363471587
Short name T1075
Test name
Test status
Simulation time 31993618 ps
CPU time 0.8 seconds
Started Aug 29 10:56:47 AM UTC 24
Finished Aug 29 10:57:30 AM UTC 24
Peak memory 209624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363471587 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.363471587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.1519328500
Short name T1076
Test name
Test status
Simulation time 107896757 ps
CPU time 1.84 seconds
Started Aug 29 10:56:30 AM UTC 24
Finished Aug 29 10:57:30 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1519328500 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.1519328500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.3627592455
Short name T72
Test name
Test status
Simulation time 195581175 ps
CPU time 1.47 seconds
Started Aug 29 10:56:37 AM UTC 24
Finished Aug 29 10:56:47 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3627592455 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.3627592455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.1154398283
Short name T999
Test name
Test status
Simulation time 62958735 ps
CPU time 0.63 seconds
Started Aug 29 10:56:48 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1154398283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_
with_rand_reset.1154398283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.1532052684
Short name T988
Test name
Test status
Simulation time 19781818 ps
CPU time 0.59 seconds
Started Aug 29 10:56:48 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 209848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1532052684 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.1532052684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.3945562216
Short name T985
Test name
Test status
Simulation time 25192802 ps
CPU time 0.53 seconds
Started Aug 29 10:56:48 AM UTC 24
Finished Aug 29 10:56:55 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3945562216 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.3945562216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.2851990943
Short name T998
Test name
Test status
Simulation time 21915815 ps
CPU time 0.62 seconds
Started Aug 29 10:56:48 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 209628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2851990943 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.2851990943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.3869316128
Short name T1005
Test name
Test status
Simulation time 139397508 ps
CPU time 2.26 seconds
Started Aug 29 10:56:47 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 210420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3869316128 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.3869316128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.1833644167
Short name T995
Test name
Test status
Simulation time 359817581 ps
CPU time 1.28 seconds
Started Aug 29 10:56:48 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 209732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833644167 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.1833644167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.2388180642
Short name T1001
Test name
Test status
Simulation time 40856203 ps
CPU time 0.75 seconds
Started Aug 29 10:56:52 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=2388180642 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_
with_rand_reset.2388180642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.4186660264
Short name T994
Test name
Test status
Simulation time 53727784 ps
CPU time 0.64 seconds
Started Aug 29 10:56:52 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 209308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186660264 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.4186660264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.2717566920
Short name T976
Test name
Test status
Simulation time 19503044 ps
CPU time 0.55 seconds
Started Aug 29 10:56:49 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2717566920 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.2717566920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.4065875164
Short name T1004
Test name
Test status
Simulation time 25681073 ps
CPU time 0.61 seconds
Started Aug 29 10:56:52 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 209852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4065875164 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.4065875164
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3491320213
Short name T982
Test name
Test status
Simulation time 115177690 ps
CPU time 1 seconds
Started Aug 29 10:56:49 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491320213 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3491320213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.192757493
Short name T981
Test name
Test status
Simulation time 272381878 ps
CPU time 0.98 seconds
Started Aug 29 10:56:49 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192757493 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.192757493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.1647707203
Short name T996
Test name
Test status
Simulation time 40830920 ps
CPU time 0.73 seconds
Started Aug 29 10:56:53 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1647707203 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_
with_rand_reset.1647707203
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.1243211764
Short name T987
Test name
Test status
Simulation time 107998860 ps
CPU time 0.52 seconds
Started Aug 29 10:56:53 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243211764 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.1243211764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.3941985730
Short name T990
Test name
Test status
Simulation time 62506013 ps
CPU time 0.53 seconds
Started Aug 29 10:56:53 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941985730 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.3941985730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.3520645943
Short name T989
Test name
Test status
Simulation time 26758760 ps
CPU time 0.62 seconds
Started Aug 29 10:56:53 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 209364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520645943 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.3520645943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.2834517078
Short name T1011
Test name
Test status
Simulation time 237350515 ps
CPU time 1.37 seconds
Started Aug 29 10:56:52 AM UTC 24
Finished Aug 29 10:56:58 AM UTC 24
Peak memory 209388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834517078 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.2834517078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.402733081
Short name T1025
Test name
Test status
Simulation time 37996362 ps
CPU time 0.68 seconds
Started Aug 29 10:56:57 AM UTC 24
Finished Aug 29 10:57:06 AM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=402733081 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_w
ith_rand_reset.402733081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.3165609393
Short name T991
Test name
Test status
Simulation time 42713003 ps
CPU time 0.58 seconds
Started Aug 29 10:56:53 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165609393 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.3165609393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.70206154
Short name T992
Test name
Test status
Simulation time 136642866 ps
CPU time 0.54 seconds
Started Aug 29 10:56:53 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 206952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=70206154 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas
e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pw
rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.70206154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2913066326
Short name T993
Test name
Test status
Simulation time 241192957 ps
CPU time 0.7 seconds
Started Aug 29 10:56:54 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2913066326 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.2913066326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1981510214
Short name T1012
Test name
Test status
Simulation time 184492315 ps
CPU time 2.32 seconds
Started Aug 29 10:56:53 AM UTC 24
Finished Aug 29 10:56:58 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1981510214 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1981510214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.330942861
Short name T1002
Test name
Test status
Simulation time 1696665317 ps
CPU time 1.36 seconds
Started Aug 29 10:56:53 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330942861 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.330942861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3860027267
Short name T1027
Test name
Test status
Simulation time 102433832 ps
CPU time 0.71 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:07 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3860027267 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_
with_rand_reset.3860027267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3568927368
Short name T1024
Test name
Test status
Simulation time 21866339 ps
CPU time 0.58 seconds
Started Aug 29 10:56:57 AM UTC 24
Finished Aug 29 10:57:06 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568927368 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3568927368
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.2121925117
Short name T1023
Test name
Test status
Simulation time 72667892 ps
CPU time 0.52 seconds
Started Aug 29 10:56:57 AM UTC 24
Finished Aug 29 10:57:06 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121925117 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.2121925117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.935044349
Short name T1026
Test name
Test status
Simulation time 55493417 ps
CPU time 0.74 seconds
Started Aug 29 10:56:57 AM UTC 24
Finished Aug 29 10:57:07 AM UTC 24
Peak memory 210128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935044349 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.935044349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.2052284987
Short name T1029
Test name
Test status
Simulation time 70142293 ps
CPU time 1.25 seconds
Started Aug 29 10:56:57 AM UTC 24
Finished Aug 29 10:57:07 AM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052284987 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.2052284987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.559405508
Short name T1030
Test name
Test status
Simulation time 265293896 ps
CPU time 1.4 seconds
Started Aug 29 10:56:57 AM UTC 24
Finished Aug 29 10:57:07 AM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559405508 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.559405508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.4267653555
Short name T1014
Test name
Test status
Simulation time 67895103 ps
CPU time 0.72 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:01 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=4267653555 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_
with_rand_reset.4267653555
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.1823839464
Short name T106
Test name
Test status
Simulation time 20496538 ps
CPU time 0.58 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:06 AM UTC 24
Peak memory 208540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823839464 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.1823839464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1898727456
Short name T1037
Test name
Test status
Simulation time 19017917 ps
CPU time 0.56 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:16 AM UTC 24
Peak memory 206752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1898727456 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.1898727456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.3451725709
Short name T1013
Test name
Test status
Simulation time 67773358 ps
CPU time 0.64 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:00 AM UTC 24
Peak memory 208776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3451725709 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.3451725709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1696979239
Short name T1044
Test name
Test status
Simulation time 127246623 ps
CPU time 1.6 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696979239 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1696979239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.890638280
Short name T1028
Test name
Test status
Simulation time 238227436 ps
CPU time 0.93 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:07 AM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890638280 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.890638280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1910492989
Short name T1040
Test name
Test status
Simulation time 92266445 ps
CPU time 0.69 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1910492989 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_
with_rand_reset.1910492989
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1273644567
Short name T107
Test name
Test status
Simulation time 23406975 ps
CPU time 0.57 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:16 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273644567 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1273644567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2025112813
Short name T1038
Test name
Test status
Simulation time 81949497 ps
CPU time 0.52 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:16 AM UTC 24
Peak memory 206676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025112813 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2025112813
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.2133066539
Short name T1041
Test name
Test status
Simulation time 22989216 ps
CPU time 0.76 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133066539 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.2133066539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.2291721506
Short name T1017
Test name
Test status
Simulation time 57010335 ps
CPU time 1.12 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:01 AM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2291721506 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.2291721506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.804271134
Short name T1043
Test name
Test status
Simulation time 111113612 ps
CPU time 1.03 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=804271134 -assert nopostproc +UVM_TESTNA
ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.804271134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.3272845879
Short name T1069
Test name
Test status
Simulation time 106092945 ps
CPU time 0.99 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3272845879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_
with_rand_reset.3272845879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.1771562149
Short name T1039
Test name
Test status
Simulation time 74052917 ps
CPU time 0.52 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 208964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771562149 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.1771562149
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.3384569386
Short name T1064
Test name
Test status
Simulation time 21437194 ps
CPU time 0.71 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3384569386 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.3384569386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1647741186
Short name T1065
Test name
Test status
Simulation time 64215980 ps
CPU time 0.77 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 209780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647741186 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.1647741186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.205836778
Short name T1045
Test name
Test status
Simulation time 102285490 ps
CPU time 1.27 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205836778 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.205836778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3107923726
Short name T1046
Test name
Test status
Simulation time 371426672 ps
CPU time 1.33 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107923726 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.3107923726
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.3597393672
Short name T1066
Test name
Test status
Simulation time 47257361 ps
CPU time 0.79 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 209744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3597393672 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_
with_rand_reset.3597393672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.1757249657
Short name T1042
Test name
Test status
Simulation time 38947898 ps
CPU time 0.52 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:17 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1757249657 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.1757249657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.3644811008
Short name T1067
Test name
Test status
Simulation time 52057529 ps
CPU time 0.7 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644811008 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.3644811008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.1216335027
Short name T1063
Test name
Test status
Simulation time 53660962 ps
CPU time 0.6 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 209100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1216335027 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.1216335027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.4095312562
Short name T1070
Test name
Test status
Simulation time 87943072 ps
CPU time 1.18 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:28 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095312562 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.4095312562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.2232943333
Short name T1068
Test name
Test status
Simulation time 229985886 ps
CPU time 0.99 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:27 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2232943333 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.2232943333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.3116794820
Short name T960
Test name
Test status
Simulation time 61325260 ps
CPU time 0.7 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 210124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116794820 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.3116794820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.2336814641
Short name T965
Test name
Test status
Simulation time 567671841 ps
CPU time 1.94 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:24 AM UTC 24
Peak memory 211120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336814641 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.2336814641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.2611828241
Short name T103
Test name
Test status
Simulation time 38627032 ps
CPU time 0.66 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611828241 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.2611828241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.3536783747
Short name T962
Test name
Test status
Simulation time 40991144 ps
CPU time 0.71 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3536783747 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_w
ith_rand_reset.3536783747
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.996061954
Short name T958
Test name
Test status
Simulation time 31640552 ps
CPU time 0.62 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 208500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=996061954 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.996061954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.3207343847
Short name T166
Test name
Test status
Simulation time 45914545 ps
CPU time 0.53 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207343847 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.3207343847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.3216006440
Short name T112
Test name
Test status
Simulation time 114929694 ps
CPU time 0.76 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216006440 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.3216006440
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.4098106219
Short name T966
Test name
Test status
Simulation time 150013862 ps
CPU time 2.36 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:24 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098106219 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.4098106219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.1373088623
Short name T67
Test name
Test status
Simulation time 395706711 ps
CPU time 2.03 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:23 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373088623 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.1373088623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.1598464067
Short name T1016
Test name
Test status
Simulation time 17801701 ps
CPU time 0.51 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:01 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598464067 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.1598464067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2487716728
Short name T1015
Test name
Test status
Simulation time 19725140 ps
CPU time 0.54 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:01 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487716728 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2487716728
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.2489489800
Short name T1019
Test name
Test status
Simulation time 18401267 ps
CPU time 0.52 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:01 AM UTC 24
Peak memory 205428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2489489800 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.2489489800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.2781132696
Short name T1020
Test name
Test status
Simulation time 31752344 ps
CPU time 0.55 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:01 AM UTC 24
Peak memory 205564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781132696 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.2781132696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.4226870412
Short name T1018
Test name
Test status
Simulation time 37861700 ps
CPU time 0.51 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:01 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4226870412 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.4226870412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.2262297750
Short name T1021
Test name
Test status
Simulation time 16993562 ps
CPU time 0.53 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:01 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262297750 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.2262297750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.3314206690
Short name T1050
Test name
Test status
Simulation time 24878355 ps
CPU time 0.51 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3314206690 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.3314206690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.1717737008
Short name T1051
Test name
Test status
Simulation time 43840740 ps
CPU time 0.52 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717737008 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.1717737008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.2933626499
Short name T1049
Test name
Test status
Simulation time 15213794 ps
CPU time 0.51 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2933626499 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.2933626499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.3404203098
Short name T1052
Test name
Test status
Simulation time 18149773 ps
CPU time 0.55 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404203098 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.3404203098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.29549025
Short name T963
Test name
Test status
Simulation time 32630822 ps
CPU time 0.72 seconds
Started Aug 29 10:56:18 AM UTC 24
Finished Aug 29 10:56:23 AM UTC 24
Peak memory 210056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29549025 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.29549025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.3505106427
Short name T967
Test name
Test status
Simulation time 312923167 ps
CPU time 1.87 seconds
Started Aug 29 10:56:18 AM UTC 24
Finished Aug 29 10:56:24 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505106427 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.3505106427
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.952052644
Short name T959
Test name
Test status
Simulation time 35610784 ps
CPU time 0.57 seconds
Started Aug 29 10:56:18 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952052644 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.952052644
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1597270355
Short name T73
Test name
Test status
Simulation time 367739868 ps
CPU time 0.7 seconds
Started Aug 29 10:56:19 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1597270355 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_w
ith_rand_reset.1597270355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.110724128
Short name T961
Test name
Test status
Simulation time 20397974 ps
CPU time 0.59 seconds
Started Aug 29 10:56:18 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 206952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110724128 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.110724128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.712661206
Short name T167
Test name
Test status
Simulation time 26602038 ps
CPU time 0.54 seconds
Started Aug 29 10:56:18 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712661206 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.712661206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.999699305
Short name T109
Test name
Test status
Simulation time 39008239 ps
CPU time 0.79 seconds
Started Aug 29 10:56:19 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 210124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999699305 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.999699305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.3578282425
Short name T964
Test name
Test status
Simulation time 247121883 ps
CPU time 1.44 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:23 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578282425 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.3578282425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.1817688088
Short name T156
Test name
Test status
Simulation time 137791158 ps
CPU time 1.01 seconds
Started Aug 29 10:56:17 AM UTC 24
Finished Aug 29 10:56:23 AM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1817688088 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.1817688088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.1085041255
Short name T1053
Test name
Test status
Simulation time 42395702 ps
CPU time 0.52 seconds
Started Aug 29 10:56:58 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1085041255 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.1085041255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1011746860
Short name T1054
Test name
Test status
Simulation time 47683927 ps
CPU time 0.54 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1011746860 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1011746860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.2279487253
Short name T1073
Test name
Test status
Simulation time 36507875 ps
CPU time 0.69 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279487253 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.2279487253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.2526197657
Short name T1072
Test name
Test status
Simulation time 39498400 ps
CPU time 0.73 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2526197657 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.2526197657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.3935195774
Short name T1022
Test name
Test status
Simulation time 24688754 ps
CPU time 0.62 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935195774 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.3935195774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.3399766257
Short name T1071
Test name
Test status
Simulation time 74681072 ps
CPU time 0.57 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399766257 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3399766257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.1051854212
Short name T1057
Test name
Test status
Simulation time 22234723 ps
CPU time 0.54 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1051854212 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.1051854212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.2254573210
Short name T1055
Test name
Test status
Simulation time 30983814 ps
CPU time 0.51 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254573210 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.2254573210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.2912161585
Short name T1056
Test name
Test status
Simulation time 19942046 ps
CPU time 0.54 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2912161585 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2912161585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.3041987397
Short name T1062
Test name
Test status
Simulation time 17620857 ps
CPU time 0.52 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3041987397 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.3041987397
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.2107378624
Short name T105
Test name
Test status
Simulation time 25154876 ps
CPU time 0.94 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 210924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107378624 -assert nopostproc +UVM_TESTNAME
=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.2107378624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.906004150
Short name T969
Test name
Test status
Simulation time 4361336523 ps
CPU time 3.05 seconds
Started Aug 29 10:56:20 AM UTC 24
Finished Aug 29 10:56:24 AM UTC 24
Peak memory 211240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906004150 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.906004150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.426343994
Short name T101
Test name
Test status
Simulation time 59925818 ps
CPU time 0.54 seconds
Started Aug 29 10:56:19 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=426343994 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.426343994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.1130535190
Short name T977
Test name
Test status
Simulation time 42657351 ps
CPU time 0.72 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1130535190 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_w
ith_rand_reset.1130535190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.1270630834
Short name T102
Test name
Test status
Simulation time 52879343 ps
CPU time 0.59 seconds
Started Aug 29 10:56:19 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 208780 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1270630834 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.1270630834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.848542800
Short name T66
Test name
Test status
Simulation time 20577596 ps
CPU time 0.54 seconds
Started Aug 29 10:56:19 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=848542800 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.848542800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.573133312
Short name T978
Test name
Test status
Simulation time 37623852 ps
CPU time 0.74 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 209824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=573133312 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.573133312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.2581035883
Short name T64
Test name
Test status
Simulation time 47302573 ps
CPU time 1.76 seconds
Started Aug 29 10:56:19 AM UTC 24
Finished Aug 29 10:56:23 AM UTC 24
Peak memory 211180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581035883 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.2581035883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.4167675858
Short name T58
Test name
Test status
Simulation time 115793305 ps
CPU time 1.13 seconds
Started Aug 29 10:56:19 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4167675858 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.4167675858
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.4131170659
Short name T1074
Test name
Test status
Simulation time 49444057 ps
CPU time 0.7 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 206712 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4131170659 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.4131170659
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.4198566015
Short name T1058
Test name
Test status
Simulation time 22643158 ps
CPU time 0.54 seconds
Started Aug 29 10:57:00 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 206960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198566015 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.4198566015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.3324876260
Short name T1034
Test name
Test status
Simulation time 19053509 ps
CPU time 0.53 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:11 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324876260 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.3324876260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.270526973
Short name T1035
Test name
Test status
Simulation time 82176033 ps
CPU time 0.54 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:11 AM UTC 24
Peak memory 206584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=270526973 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.270526973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.1107751151
Short name T1031
Test name
Test status
Simulation time 44421060 ps
CPU time 0.51 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:11 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107751151 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.1107751151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.577719969
Short name T1033
Test name
Test status
Simulation time 25085361 ps
CPU time 0.51 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:11 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577719969 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.577719969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.546455654
Short name T1032
Test name
Test status
Simulation time 52235532 ps
CPU time 0.54 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:11 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=546455654 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.546455654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.3122621294
Short name T1048
Test name
Test status
Simulation time 41054878 ps
CPU time 0.55 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3122621294 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.3122621294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.379327764
Short name T1036
Test name
Test status
Simulation time 27028267 ps
CPU time 0.54 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:11 AM UTC 24
Peak memory 206680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379327764 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.379327764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.2076694781
Short name T1047
Test name
Test status
Simulation time 28240869 ps
CPU time 0.52 seconds
Started Aug 29 10:57:02 AM UTC 24
Finished Aug 29 10:57:21 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076694781 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2076694781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.1440600352
Short name T980
Test name
Test status
Simulation time 38411334 ps
CPU time 0.7 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 210124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1440600352 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_w
ith_rand_reset.1440600352
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.2724776103
Short name T115
Test name
Test status
Simulation time 19957241 ps
CPU time 0.58 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 208304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724776103 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.2724776103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.3552391286
Short name T169
Test name
Test status
Simulation time 48278759 ps
CPU time 0.52 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:51 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552391286 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.3552391286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.2065314891
Short name T116
Test name
Test status
Simulation time 21793458 ps
CPU time 0.62 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 209096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2065314891 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.2065314891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.567787362
Short name T983
Test name
Test status
Simulation time 75416374 ps
CPU time 1.76 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:53 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567787362 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.567787362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.3846479185
Short name T68
Test name
Test status
Simulation time 1865920139 ps
CPU time 1.53 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3846479185 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.3846479185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.3741154049
Short name T970
Test name
Test status
Simulation time 52564364 ps
CPU time 0.68 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:46 AM UTC 24
Peak memory 209824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3741154049 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_w
ith_rand_reset.3741154049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.2916193913
Short name T108
Test name
Test status
Simulation time 24644359 ps
CPU time 0.57 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:57:29 AM UTC 24
Peak memory 208600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916193913 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.2916193913
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.254601680
Short name T979
Test name
Test status
Simulation time 51031498 ps
CPU time 0.56 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:52 AM UTC 24
Peak memory 207080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254601680 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.254601680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.2556282208
Short name T113
Test name
Test status
Simulation time 41533835 ps
CPU time 0.82 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:46 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2556282208 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.2556282208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.3019631732
Short name T984
Test name
Test status
Simulation time 101003736 ps
CPU time 2.28 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:56:53 AM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019631732 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.3019631732
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.3007024614
Short name T1061
Test name
Test status
Simulation time 111421290 ps
CPU time 1.08 seconds
Started Aug 29 10:56:23 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007024614 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.3007024614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.996656213
Short name T973
Test name
Test status
Simulation time 37977838 ps
CPU time 0.77 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:47 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=996656213 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm
_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_wi
th_rand_reset.996656213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.1385831420
Short name T971
Test name
Test status
Simulation time 20798361 ps
CPU time 0.55 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:46 AM UTC 24
Peak memory 208444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1385831420 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1385831420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.457680700
Short name T114
Test name
Test status
Simulation time 26771005 ps
CPU time 0.67 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:47 AM UTC 24
Peak memory 209560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457680700 -assert nopostproc +U
VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.457680700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.2388653684
Short name T974
Test name
Test status
Simulation time 66773898 ps
CPU time 1.45 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:47 AM UTC 24
Peak memory 209928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2388653684 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.2388653684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1896244810
Short name T154
Test name
Test status
Simulation time 108125881 ps
CPU time 1.17 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:47 AM UTC 24
Peak memory 211168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1896244810 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.1896244810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3011981562
Short name T1000
Test name
Test status
Simulation time 57582186 ps
CPU time 0.93 seconds
Started Aug 29 10:56:25 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 209824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=3011981562 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_w
ith_rand_reset.3011981562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.933623071
Short name T104
Test name
Test status
Simulation time 63689359 ps
CPU time 0.57 seconds
Started Aug 29 10:56:25 AM UTC 24
Finished Aug 29 10:56:47 AM UTC 24
Peak memory 206952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=933623071 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.933623071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.3799257380
Short name T972
Test name
Test status
Simulation time 20117100 ps
CPU time 0.53 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:46 AM UTC 24
Peak memory 207016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799257380 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.3799257380
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1694283444
Short name T997
Test name
Test status
Simulation time 18808906 ps
CPU time 0.66 seconds
Started Aug 29 10:56:25 AM UTC 24
Finished Aug 29 10:56:56 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694283444 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.1694283444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.4122129710
Short name T975
Test name
Test status
Simulation time 143135845 ps
CPU time 2.1 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:48 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122129710 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.4122129710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.3155681190
Short name T155
Test name
Test status
Simulation time 155094872 ps
CPU time 1.02 seconds
Started Aug 29 10:56:24 AM UTC 24
Finished Aug 29 10:56:47 AM UTC 24
Peak memory 211164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155681190 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.3155681190
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.1514426586
Short name T1060
Test name
Test status
Simulation time 40398628 ps
CPU time 0.96 seconds
Started Aug 29 10:56:29 AM UTC 24
Finished Aug 29 10:57:22 AM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s
cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s
eed=1514426586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c
m_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_w
ith_rand_reset.1514426586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.3795076631
Short name T1010
Test name
Test status
Simulation time 19117447 ps
CPU time 0.64 seconds
Started Aug 29 10:56:26 AM UTC 24
Finished Aug 29 10:56:58 AM UTC 24
Peak memory 206956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3795076631 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.3795076631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.3500534386
Short name T1006
Test name
Test status
Simulation time 21646537 ps
CPU time 0.55 seconds
Started Aug 29 10:56:26 AM UTC 24
Finished Aug 29 10:56:58 AM UTC 24
Peak memory 207020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3500534386 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.3500534386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.2493892004
Short name T1009
Test name
Test status
Simulation time 27284570 ps
CPU time 0.67 seconds
Started Aug 29 10:56:26 AM UTC 24
Finished Aug 29 10:56:58 AM UTC 24
Peak memory 209628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1
+UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493892004 -assert nopostproc +
UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.2493892004
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.583820954
Short name T1003
Test name
Test status
Simulation time 30361022 ps
CPU time 1.23 seconds
Started Aug 29 10:56:25 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 210908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV
M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=583820954 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba
se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/p
wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.583820954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2758327798
Short name T69
Test name
Test status
Simulation time 227871663 ps
CPU time 0.89 seconds
Started Aug 29 10:56:25 AM UTC 24
Finished Aug 29 10:56:57 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_
RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758327798 -assert nopostproc +UVM_TESTN
AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.2758327798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.1340060052
Short name T6
Test name
Test status
Simulation time 35334176 ps
CPU time 1.18 seconds
Started Aug 29 10:52:27 AM UTC 24
Finished Aug 29 10:52:30 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340060052 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.1340060052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3061292539
Short name T11
Test name
Test status
Simulation time 113565550 ps
CPU time 1.57 seconds
Started Aug 29 10:52:34 AM UTC 24
Finished Aug 29 10:52:37 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061292539 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3061292539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.3016901810
Short name T23
Test name
Test status
Simulation time 40906099 ps
CPU time 0.94 seconds
Started Aug 29 10:52:35 AM UTC 24
Finished Aug 29 10:52:37 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3016901810 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.3016901810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.3072142731
Short name T13
Test name
Test status
Simulation time 50168854 ps
CPU time 0.94 seconds
Started Aug 29 10:52:33 AM UTC 24
Finished Aug 29 10:52:36 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3072142731 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.3072142731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1116436178
Short name T4
Test name
Test status
Simulation time 370989190 ps
CPU time 1.38 seconds
Started Aug 29 10:52:24 AM UTC 24
Finished Aug 29 10:52:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116436178 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.1116436178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.4030471794
Short name T2
Test name
Test status
Simulation time 63200556 ps
CPU time 1.35 seconds
Started Aug 29 10:52:20 AM UTC 24
Finished Aug 29 10:52:23 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4030471794 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.4030471794
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.2698775987
Short name T20
Test name
Test status
Simulation time 999658769 ps
CPU time 2.15 seconds
Started Aug 29 10:52:36 AM UTC 24
Finished Aug 29 10:52:40 AM UTC 24
Peak memory 238880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698775987 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.2698775987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2580317364
Short name T8
Test name
Test status
Simulation time 177046024 ps
CPU time 1.31 seconds
Started Aug 29 10:52:31 AM UTC 24
Finished Aug 29 10:52:33 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2580317364 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2580317364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.2242401996
Short name T1
Test name
Test status
Simulation time 62315437 ps
CPU time 1 seconds
Started Aug 29 10:52:20 AM UTC 24
Finished Aug 29 10:52:23 AM UTC 24
Peak memory 210420 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242401996 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.2242401996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.3107265808
Short name T16
Test name
Test status
Simulation time 2831107087 ps
CPU time 6.77 seconds
Started Aug 29 10:52:38 AM UTC 24
Finished Aug 29 10:52:47 AM UTC 24
Peak memory 211480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107265808 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.3107265808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.2583524416
Short name T3
Test name
Test status
Simulation time 97692734 ps
CPU time 1.16 seconds
Started Aug 29 10:52:24 AM UTC 24
Finished Aug 29 10:52:26 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583524416 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.2583524416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.3647725568
Short name T5
Test name
Test status
Simulation time 218695141 ps
CPU time 1.62 seconds
Started Aug 29 10:52:25 AM UTC 24
Finished Aug 29 10:52:28 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647725568 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.3647725568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.4283893
Short name T15
Test name
Test status
Simulation time 96148280 ps
CPU time 1.04 seconds
Started Aug 29 10:52:40 AM UTC 24
Finished Aug 29 10:52:42 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283893 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=p
wrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vc
s/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.4283893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.3536967094
Short name T27
Test name
Test status
Simulation time 110482828 ps
CPU time 1.01 seconds
Started Aug 29 10:52:44 AM UTC 24
Finished Aug 29 10:52:46 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536967094 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.3536967094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1022720392
Short name T12
Test name
Test status
Simulation time 30471749 ps
CPU time 0.95 seconds
Started Aug 29 10:52:42 AM UTC 24
Finished Aug 29 10:52:44 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1022720392 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.1022720392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.883079172
Short name T40
Test name
Test status
Simulation time 1151011143 ps
CPU time 1.39 seconds
Started Aug 29 10:52:42 AM UTC 24
Finished Aug 29 10:52:45 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=883079172 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.883079172
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.2069981951
Short name T38
Test name
Test status
Simulation time 34734365 ps
CPU time 0.98 seconds
Started Aug 29 10:52:42 AM UTC 24
Finished Aug 29 10:52:44 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069981951 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.2069981951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.4268215712
Short name T47
Test name
Test status
Simulation time 42602015 ps
CPU time 1.1 seconds
Started Aug 29 10:52:45 AM UTC 24
Finished Aug 29 10:52:47 AM UTC 24
Peak memory 210732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268215712 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid.4268215712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.1838579033
Short name T33
Test name
Test status
Simulation time 75480585 ps
CPU time 1.5 seconds
Started Aug 29 10:52:39 AM UTC 24
Finished Aug 29 10:52:41 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1838579033 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1838579033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.1824453463
Short name T41
Test name
Test status
Simulation time 158830680 ps
CPU time 1.19 seconds
Started Aug 29 10:52:45 AM UTC 24
Finished Aug 29 10:52:47 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824453463 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.1824453463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.3633375130
Short name T21
Test name
Test status
Simulation time 629973299 ps
CPU time 3.97 seconds
Started Aug 29 10:52:45 AM UTC 24
Finished Aug 29 10:52:50 AM UTC 24
Peak memory 239048 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3633375130 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.3633375130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3291176637
Short name T60
Test name
Test status
Simulation time 162293793 ps
CPU time 1.16 seconds
Started Aug 29 10:52:42 AM UTC 24
Finished Aug 29 10:52:45 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291176637 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.3291176637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1102103256
Short name T37
Test name
Test status
Simulation time 90564695 ps
CPU time 1.31 seconds
Started Aug 29 10:52:41 AM UTC 24
Finished Aug 29 10:52:44 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102103256 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.1102103256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.3454063077
Short name T32
Test name
Test status
Simulation time 62040466 ps
CPU time 0.94 seconds
Started Aug 29 10:52:39 AM UTC 24
Finished Aug 29 10:52:40 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3454063077 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3454063077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.3616099050
Short name T25
Test name
Test status
Simulation time 3422856075 ps
CPU time 19.06 seconds
Started Aug 29 10:52:45 AM UTC 24
Finished Aug 29 10:53:05 AM UTC 24
Peak memory 211664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3616099050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr
_stress_all_with_rand_reset.3616099050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1398020851
Short name T36
Test name
Test status
Simulation time 291402436 ps
CPU time 1.62 seconds
Started Aug 29 10:52:40 AM UTC 24
Finished Aug 29 10:52:42 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1398020851 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1398020851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.2168295097
Short name T35
Test name
Test status
Simulation time 338052148 ps
CPU time 1.59 seconds
Started Aug 29 10:52:40 AM UTC 24
Finished Aug 29 10:52:42 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2168295097 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.2168295097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.3330974106
Short name T280
Test name
Test status
Simulation time 57983137 ps
CPU time 0.92 seconds
Started Aug 29 10:53:33 AM UTC 24
Finished Aug 29 10:53:34 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3330974106 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.3330974106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.1317120678
Short name T140
Test name
Test status
Simulation time 58808615 ps
CPU time 1.23 seconds
Started Aug 29 10:53:34 AM UTC 24
Finished Aug 29 10:53:37 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317120678 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.1317120678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.918173506
Short name T132
Test name
Test status
Simulation time 39407156 ps
CPU time 0.85 seconds
Started Aug 29 10:53:33 AM UTC 24
Finished Aug 29 10:53:35 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918173506 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.918173506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.3822147879
Short name T282
Test name
Test status
Simulation time 114914442 ps
CPU time 1.49 seconds
Started Aug 29 10:53:34 AM UTC 24
Finished Aug 29 10:53:37 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3822147879 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.3822147879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.2213601925
Short name T138
Test name
Test status
Simulation time 39386813 ps
CPU time 1 seconds
Started Aug 29 10:53:34 AM UTC 24
Finished Aug 29 10:53:36 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2213601925 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.2213601925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.4090136518
Short name T137
Test name
Test status
Simulation time 59193077 ps
CPU time 0.99 seconds
Started Aug 29 10:53:34 AM UTC 24
Finished Aug 29 10:53:36 AM UTC 24
Peak memory 206184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090136518 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.4090136518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.1726761735
Short name T284
Test name
Test status
Simulation time 82202156 ps
CPU time 1.04 seconds
Started Aug 29 10:53:36 AM UTC 24
Finished Aug 29 10:53:38 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726761735 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invalid.1726761735
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.3642870611
Short name T133
Test name
Test status
Simulation time 203278937 ps
CPU time 1.28 seconds
Started Aug 29 10:53:33 AM UTC 24
Finished Aug 29 10:53:35 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3642870611 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.3642870611
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.949527100
Short name T276
Test name
Test status
Simulation time 21728022 ps
CPU time 0.99 seconds
Started Aug 29 10:53:31 AM UTC 24
Finished Aug 29 10:53:33 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949527100 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.949527100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3728247825
Short name T281
Test name
Test status
Simulation time 145531833 ps
CPU time 1.26 seconds
Started Aug 29 10:53:34 AM UTC 24
Finished Aug 29 10:53:37 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728247825 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.3728247825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.3213796600
Short name T139
Test name
Test status
Simulation time 61021897 ps
CPU time 1.21 seconds
Started Aug 29 10:53:34 AM UTC 24
Finished Aug 29 10:53:36 AM UTC 24
Peak memory 208236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213796600 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.3213796600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1890623729
Short name T288
Test name
Test status
Simulation time 765123210 ps
CPU time 4.58 seconds
Started Aug 29 10:53:33 AM UTC 24
Finished Aug 29 10:53:38 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1890623729 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1890623729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2516848020
Short name T285
Test name
Test status
Simulation time 933278937 ps
CPU time 4.12 seconds
Started Aug 29 10:53:33 AM UTC 24
Finished Aug 29 10:53:38 AM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2516848020 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2516848020
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3540523152
Short name T134
Test name
Test status
Simulation time 94763809 ps
CPU time 1.3 seconds
Started Aug 29 10:53:33 AM UTC 24
Finished Aug 29 10:53:35 AM UTC 24
Peak memory 208172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540523152 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.3540523152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.2008526708
Short name T277
Test name
Test status
Simulation time 31478058 ps
CPU time 1.05 seconds
Started Aug 29 10:53:31 AM UTC 24
Finished Aug 29 10:53:33 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008526708 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2008526708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.1764006640
Short name T301
Test name
Test status
Simulation time 1430436115 ps
CPU time 4.58 seconds
Started Aug 29 10:53:36 AM UTC 24
Finished Aug 29 10:53:41 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1764006640 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.1764006640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.839070167
Short name T122
Test name
Test status
Simulation time 2898796660 ps
CPU time 11.47 seconds
Started Aug 29 10:53:36 AM UTC 24
Finished Aug 29 10:53:48 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=839070167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr
_stress_all_with_rand_reset.839070167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.46665593
Short name T136
Test name
Test status
Simulation time 284708564 ps
CPU time 2.23 seconds
Started Aug 29 10:53:33 AM UTC 24
Finished Aug 29 10:53:36 AM UTC 24
Peak memory 210808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=46665593 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.46665593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3297351900
Short name T135
Test name
Test status
Simulation time 183516630 ps
CPU time 1.94 seconds
Started Aug 29 10:53:33 AM UTC 24
Finished Aug 29 10:53:35 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3297351900 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3297351900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.508478262
Short name T95
Test name
Test status
Simulation time 27895125 ps
CPU time 1.25 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:39 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=508478262 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.508478262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.1387658705
Short name T297
Test name
Test status
Simulation time 65823417 ps
CPU time 1.17 seconds
Started Aug 29 10:53:39 AM UTC 24
Finished Aug 29 10:53:41 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387658705 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.1387658705
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.339474649
Short name T290
Test name
Test status
Simulation time 37670886 ps
CPU time 0.88 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:39 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339474649 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.339474649
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.2323744690
Short name T295
Test name
Test status
Simulation time 205755732 ps
CPU time 1.46 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:40 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2323744690 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.2323744690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.1114267781
Short name T296
Test name
Test status
Simulation time 60818835 ps
CPU time 0.92 seconds
Started Aug 29 10:53:39 AM UTC 24
Finished Aug 29 10:53:41 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1114267781 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.1114267781
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.420377186
Short name T292
Test name
Test status
Simulation time 32225821 ps
CPU time 0.97 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:39 AM UTC 24
Peak memory 206120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420377186 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.420377186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.299155337
Short name T299
Test name
Test status
Simulation time 43004216 ps
CPU time 1.15 seconds
Started Aug 29 10:53:39 AM UTC 24
Finished Aug 29 10:53:41 AM UTC 24
Peak memory 210916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=299155337 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invalid.299155337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.2254755401
Short name T289
Test name
Test status
Simulation time 245736480 ps
CPU time 2.18 seconds
Started Aug 29 10:53:36 AM UTC 24
Finished Aug 29 10:53:39 AM UTC 24
Peak memory 210944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2254755401 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.2254755401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1658748604
Short name T286
Test name
Test status
Simulation time 55917412 ps
CPU time 1.16 seconds
Started Aug 29 10:53:36 AM UTC 24
Finished Aug 29 10:53:38 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1658748604 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1658748604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.1370327001
Short name T300
Test name
Test status
Simulation time 160639124 ps
CPU time 1.28 seconds
Started Aug 29 10:53:39 AM UTC 24
Finished Aug 29 10:53:41 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1370327001 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.1370327001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.2206759696
Short name T294
Test name
Test status
Simulation time 325844339 ps
CPU time 1.59 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:40 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2206759696 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.2206759696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.958180510
Short name T307
Test name
Test status
Simulation time 819814464 ps
CPU time 5.46 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:44 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958180510 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.958180510
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1163597432
Short name T302
Test name
Test status
Simulation time 1545221918 ps
CPU time 3.23 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:42 AM UTC 24
Peak memory 210988 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1163597432 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1163597432
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.147368428
Short name T293
Test name
Test status
Simulation time 87861912 ps
CPU time 1.16 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:39 AM UTC 24
Peak memory 207932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147368428 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.147368428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.967026710
Short name T283
Test name
Test status
Simulation time 75611573 ps
CPU time 0.88 seconds
Started Aug 29 10:53:36 AM UTC 24
Finished Aug 29 10:53:38 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967026710 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.967026710
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.1840740977
Short name T298
Test name
Test status
Simulation time 28975560 ps
CPU time 1.05 seconds
Started Aug 29 10:53:39 AM UTC 24
Finished Aug 29 10:53:41 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1840740977 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.1840740977
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.3429335214
Short name T76
Test name
Test status
Simulation time 7111482765 ps
CPU time 18.98 seconds
Started Aug 29 10:53:39 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 211784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3429335214 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmg
r_stress_all_with_rand_reset.3429335214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.3956027996
Short name T287
Test name
Test status
Simulation time 168723487 ps
CPU time 1.13 seconds
Started Aug 29 10:53:36 AM UTC 24
Finished Aug 29 10:53:38 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956027996 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.3956027996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.2733001770
Short name T291
Test name
Test status
Simulation time 51134765 ps
CPU time 1.09 seconds
Started Aug 29 10:53:37 AM UTC 24
Finished Aug 29 10:53:39 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2733001770 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.2733001770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.2590081524
Short name T96
Test name
Test status
Simulation time 84433843 ps
CPU time 1.37 seconds
Started Aug 29 10:53:40 AM UTC 24
Finished Aug 29 10:53:43 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590081524 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.2590081524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.3251593336
Short name T163
Test name
Test status
Simulation time 58582799 ps
CPU time 1.08 seconds
Started Aug 29 10:53:42 AM UTC 24
Finished Aug 29 10:53:44 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3251593336 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.3251593336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.3069100170
Short name T308
Test name
Test status
Simulation time 30847288 ps
CPU time 1.01 seconds
Started Aug 29 10:53:42 AM UTC 24
Finished Aug 29 10:53:44 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3069100170 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.3069100170
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.510856641
Short name T312
Test name
Test status
Simulation time 246271822 ps
CPU time 1.46 seconds
Started Aug 29 10:53:42 AM UTC 24
Finished Aug 29 10:53:44 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510856641 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.510856641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.1996661972
Short name T310
Test name
Test status
Simulation time 51137651 ps
CPU time 0.96 seconds
Started Aug 29 10:53:42 AM UTC 24
Finished Aug 29 10:53:44 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996661972 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.1996661972
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.1487632740
Short name T309
Test name
Test status
Simulation time 53111219 ps
CPU time 0.92 seconds
Started Aug 29 10:53:42 AM UTC 24
Finished Aug 29 10:53:44 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487632740 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.1487632740
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.2798761395
Short name T316
Test name
Test status
Simulation time 86228879 ps
CPU time 1.03 seconds
Started Aug 29 10:53:43 AM UTC 24
Finished Aug 29 10:53:45 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798761395 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.2798761395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.1526100305
Short name T303
Test name
Test status
Simulation time 71507563 ps
CPU time 0.96 seconds
Started Aug 29 10:53:40 AM UTC 24
Finished Aug 29 10:53:42 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526100305 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.1526100305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2061865075
Short name T304
Test name
Test status
Simulation time 384969469 ps
CPU time 1.22 seconds
Started Aug 29 10:53:40 AM UTC 24
Finished Aug 29 10:53:42 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061865075 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2061865075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.1379416879
Short name T318
Test name
Test status
Simulation time 177472596 ps
CPU time 1.26 seconds
Started Aug 29 10:53:43 AM UTC 24
Finished Aug 29 10:53:46 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379416879 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.1379416879
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1606415229
Short name T314
Test name
Test status
Simulation time 255454560 ps
CPU time 1.72 seconds
Started Aug 29 10:53:42 AM UTC 24
Finished Aug 29 10:53:45 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606415229 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.1606415229
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.619071321
Short name T315
Test name
Test status
Simulation time 1206504559 ps
CPU time 3.36 seconds
Started Aug 29 10:53:40 AM UTC 24
Finished Aug 29 10:53:45 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619071321 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.619071321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2313432920
Short name T323
Test name
Test status
Simulation time 992953860 ps
CPU time 3.9 seconds
Started Aug 29 10:53:42 AM UTC 24
Finished Aug 29 10:53:47 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313432920 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2313432920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1189656180
Short name T311
Test name
Test status
Simulation time 66530384 ps
CPU time 1.31 seconds
Started Aug 29 10:53:42 AM UTC 24
Finished Aug 29 10:53:44 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189656180 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.1189656180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.3731345711
Short name T257
Test name
Test status
Simulation time 30435596 ps
CPU time 1.1 seconds
Started Aug 29 10:53:40 AM UTC 24
Finished Aug 29 10:53:42 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731345711 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.3731345711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.283463870
Short name T332
Test name
Test status
Simulation time 2212667945 ps
CPU time 4.22 seconds
Started Aug 29 10:53:44 AM UTC 24
Finished Aug 29 10:53:49 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283463870 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.283463870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.1020694383
Short name T123
Test name
Test status
Simulation time 6335953172 ps
CPU time 9.86 seconds
Started Aug 29 10:53:44 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 211528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1020694383 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmg
r_stress_all_with_rand_reset.1020694383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.2870038480
Short name T306
Test name
Test status
Simulation time 189101269 ps
CPU time 1.72 seconds
Started Aug 29 10:53:40 AM UTC 24
Finished Aug 29 10:53:43 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2870038480 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.2870038480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.4216718349
Short name T305
Test name
Test status
Simulation time 260825125 ps
CPU time 1.43 seconds
Started Aug 29 10:53:40 AM UTC 24
Finished Aug 29 10:53:43 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216718349 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.4216718349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.545779764
Short name T325
Test name
Test status
Simulation time 84658425 ps
CPU time 1.14 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:47 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545779764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.545779764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.117214926
Short name T329
Test name
Test status
Simulation time 76555083 ps
CPU time 1.04 seconds
Started Aug 29 10:53:46 AM UTC 24
Finished Aug 29 10:53:48 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=117214926 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.117214926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.4170776765
Short name T324
Test name
Test status
Simulation time 29081383 ps
CPU time 0.97 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:47 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170776765 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.4170776765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.3581963167
Short name T330
Test name
Test status
Simulation time 134721013 ps
CPU time 1.51 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:48 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3581963167 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.3581963167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.679806832
Short name T328
Test name
Test status
Simulation time 55626683 ps
CPU time 0.89 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:47 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679806832 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.679806832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.1755798138
Short name T326
Test name
Test status
Simulation time 39024628 ps
CPU time 0.93 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:47 AM UTC 24
Peak memory 206056 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1755798138 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.1755798138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.2032177806
Short name T334
Test name
Test status
Simulation time 44844951 ps
CPU time 1.11 seconds
Started Aug 29 10:53:47 AM UTC 24
Finished Aug 29 10:53:49 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2032177806 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invalid.2032177806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.3956066771
Short name T320
Test name
Test status
Simulation time 190962695 ps
CPU time 1.13 seconds
Started Aug 29 10:53:44 AM UTC 24
Finished Aug 29 10:53:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956066771 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.3956066771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.3844288778
Short name T319
Test name
Test status
Simulation time 58592092 ps
CPU time 1.14 seconds
Started Aug 29 10:53:44 AM UTC 24
Finished Aug 29 10:53:46 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844288778 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.3844288778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.4044428886
Short name T335
Test name
Test status
Simulation time 147354247 ps
CPU time 1.21 seconds
Started Aug 29 10:53:47 AM UTC 24
Finished Aug 29 10:53:49 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044428886 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.4044428886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.4096530334
Short name T331
Test name
Test status
Simulation time 179297547 ps
CPU time 1.8 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:48 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096530334 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.4096530334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2798041409
Short name T339
Test name
Test status
Simulation time 943598808 ps
CPU time 3.42 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:50 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2798041409 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2798041409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3442785644
Short name T340
Test name
Test status
Simulation time 1300467865 ps
CPU time 3.76 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:50 AM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442785644 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3442785644
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.4071021027
Short name T327
Test name
Test status
Simulation time 180301146 ps
CPU time 1.16 seconds
Started Aug 29 10:53:45 AM UTC 24
Finished Aug 29 10:53:47 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071021027 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.4071021027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.2084136661
Short name T317
Test name
Test status
Simulation time 36693226 ps
CPU time 1 seconds
Started Aug 29 10:53:44 AM UTC 24
Finished Aug 29 10:53:46 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084136661 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.2084136661
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.2220309612
Short name T97
Test name
Test status
Simulation time 2656704932 ps
CPU time 6.61 seconds
Started Aug 29 10:53:47 AM UTC 24
Finished Aug 29 10:53:55 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2220309612 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.2220309612
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.717085413
Short name T91
Test name
Test status
Simulation time 9473228429 ps
CPU time 15.68 seconds
Started Aug 29 10:53:47 AM UTC 24
Finished Aug 29 10:54:04 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=717085413 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr
_stress_all_with_rand_reset.717085413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.3871689571
Short name T322
Test name
Test status
Simulation time 165240476 ps
CPU time 1.3 seconds
Started Aug 29 10:53:44 AM UTC 24
Finished Aug 29 10:53:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3871689571 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.3871689571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.2709402678
Short name T321
Test name
Test status
Simulation time 41303712 ps
CPU time 1.13 seconds
Started Aug 29 10:53:44 AM UTC 24
Finished Aug 29 10:53:46 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709402678 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.2709402678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.1335072460
Short name T342
Test name
Test status
Simulation time 39915343 ps
CPU time 1.11 seconds
Started Aug 29 10:53:48 AM UTC 24
Finished Aug 29 10:53:51 AM UTC 24
Peak memory 207532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335072460 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.1335072460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.58053343
Short name T164
Test name
Test status
Simulation time 50371153 ps
CPU time 1.19 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:52 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58053343 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.58053343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.1392908237
Short name T341
Test name
Test status
Simulation time 32745640 ps
CPU time 0.88 seconds
Started Aug 29 10:53:49 AM UTC 24
Finished Aug 29 10:53:51 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392908237 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.1392908237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.4168660899
Short name T348
Test name
Test status
Simulation time 113176674 ps
CPU time 1.56 seconds
Started Aug 29 10:53:49 AM UTC 24
Finished Aug 29 10:53:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168660899 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.4168660899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.3941861204
Short name T345
Test name
Test status
Simulation time 35026692 ps
CPU time 0.99 seconds
Started Aug 29 10:53:49 AM UTC 24
Finished Aug 29 10:53:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941861204 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.3941861204
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.607123365
Short name T346
Test name
Test status
Simulation time 32468210 ps
CPU time 0.98 seconds
Started Aug 29 10:53:49 AM UTC 24
Finished Aug 29 10:53:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607123365 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.607123365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.2428539747
Short name T349
Test name
Test status
Simulation time 43264337 ps
CPU time 1.11 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:52 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428539747 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid.2428539747
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.1661293001
Short name T337
Test name
Test status
Simulation time 243245966 ps
CPU time 1.33 seconds
Started Aug 29 10:53:47 AM UTC 24
Finished Aug 29 10:53:49 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1661293001 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.1661293001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.1395940750
Short name T336
Test name
Test status
Simulation time 87976840 ps
CPU time 1.22 seconds
Started Aug 29 10:53:47 AM UTC 24
Finished Aug 29 10:53:49 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395940750 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.1395940750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.3229301091
Short name T353
Test name
Test status
Simulation time 101540986 ps
CPU time 1.54 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:53 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3229301091 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.3229301091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.1570950662
Short name T343
Test name
Test status
Simulation time 141800166 ps
CPU time 0.97 seconds
Started Aug 29 10:53:49 AM UTC 24
Finished Aug 29 10:53:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1570950662 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.1570950662
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1641287719
Short name T351
Test name
Test status
Simulation time 1196934194 ps
CPU time 2.89 seconds
Started Aug 29 10:53:49 AM UTC 24
Finished Aug 29 10:53:52 AM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641287719 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1641287719
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2226943549
Short name T358
Test name
Test status
Simulation time 871513720 ps
CPU time 4.27 seconds
Started Aug 29 10:53:49 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226943549 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2226943549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2080736565
Short name T347
Test name
Test status
Simulation time 72787749 ps
CPU time 1.32 seconds
Started Aug 29 10:53:49 AM UTC 24
Finished Aug 29 10:53:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2080736565 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.2080736565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.1182507849
Short name T333
Test name
Test status
Simulation time 49443770 ps
CPU time 0.93 seconds
Started Aug 29 10:53:47 AM UTC 24
Finished Aug 29 10:53:49 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182507849 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.1182507849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.2597093560
Short name T99
Test name
Test status
Simulation time 1997464540 ps
CPU time 7.38 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597093560 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.2597093560
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.152905277
Short name T90
Test name
Test status
Simulation time 7316102281 ps
CPU time 7.94 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 211724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=152905277 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr
_stress_all_with_rand_reset.152905277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2903953918
Short name T338
Test name
Test status
Simulation time 306205965 ps
CPU time 1.38 seconds
Started Aug 29 10:53:47 AM UTC 24
Finished Aug 29 10:53:50 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2903953918 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.2903953918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.105352642
Short name T344
Test name
Test status
Simulation time 269531424 ps
CPU time 1.33 seconds
Started Aug 29 10:53:48 AM UTC 24
Finished Aug 29 10:53:51 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=105352642 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.105352642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.397052423
Short name T357
Test name
Test status
Simulation time 47858366 ps
CPU time 1.32 seconds
Started Aug 29 10:53:51 AM UTC 24
Finished Aug 29 10:53:53 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397052423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.397052423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.3502891925
Short name T364
Test name
Test status
Simulation time 42957975 ps
CPU time 1.16 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502891925 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.3502891925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3144485412
Short name T359
Test name
Test status
Simulation time 28938873 ps
CPU time 0.97 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 208276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144485412 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.3144485412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.2071207783
Short name T365
Test name
Test status
Simulation time 111059034 ps
CPU time 1.53 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071207783 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.2071207783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.1327295131
Short name T362
Test name
Test status
Simulation time 24692065 ps
CPU time 0.94 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327295131 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.1327295131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.2855382002
Short name T361
Test name
Test status
Simulation time 41036981 ps
CPU time 1.01 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2855382002 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.2855382002
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.3829425667
Short name T369
Test name
Test status
Simulation time 70588332 ps
CPU time 1 seconds
Started Aug 29 10:53:53 AM UTC 24
Finished Aug 29 10:53:55 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829425667 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invalid.3829425667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.4291866725
Short name T356
Test name
Test status
Simulation time 99343734 ps
CPU time 1.39 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:53 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291866725 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.4291866725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.471318861
Short name T355
Test name
Test status
Simulation time 54869914 ps
CPU time 1.4 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:53 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=471318861 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.471318861
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.2670621206
Short name T367
Test name
Test status
Simulation time 123903606 ps
CPU time 0.91 seconds
Started Aug 29 10:53:53 AM UTC 24
Finished Aug 29 10:53:55 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670621206 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.2670621206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.2619600733
Short name T360
Test name
Test status
Simulation time 105434573 ps
CPU time 1 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619600733 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.2619600733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3171844357
Short name T374
Test name
Test status
Simulation time 939516698 ps
CPU time 4.14 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:57 AM UTC 24
Peak memory 211344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3171844357 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3171844357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.632681821
Short name T368
Test name
Test status
Simulation time 1430929459 ps
CPU time 2.46 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:55 AM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632681821 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.632681821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.3586640109
Short name T363
Test name
Test status
Simulation time 110716101 ps
CPU time 1.44 seconds
Started Aug 29 10:53:52 AM UTC 24
Finished Aug 29 10:53:54 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586640109 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.3586640109
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.2989520327
Short name T350
Test name
Test status
Simulation time 40313172 ps
CPU time 1.03 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:52 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2989520327 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.2989520327
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.793908390
Short name T373
Test name
Test status
Simulation time 798190347 ps
CPU time 2.44 seconds
Started Aug 29 10:53:53 AM UTC 24
Finished Aug 29 10:53:57 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=793908390 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.793908390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.497745269
Short name T388
Test name
Test status
Simulation time 2349106032 ps
CPU time 4.61 seconds
Started Aug 29 10:53:53 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 211660 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=497745269 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr
_stress_all_with_rand_reset.497745269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.2343411750
Short name T354
Test name
Test status
Simulation time 55161956 ps
CPU time 1.15 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2343411750 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.2343411750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.440276995
Short name T352
Test name
Test status
Simulation time 136606426 ps
CPU time 1.04 seconds
Started Aug 29 10:53:50 AM UTC 24
Finished Aug 29 10:53:53 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440276995 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.440276995
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.3569673143
Short name T98
Test name
Test status
Simulation time 21215142 ps
CPU time 1.02 seconds
Started Aug 29 10:53:54 AM UTC 24
Finished Aug 29 10:53:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3569673143 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.3569673143
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.652875059
Short name T379
Test name
Test status
Simulation time 55390678 ps
CPU time 1.28 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:53:58 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=652875059 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.652875059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.3665103901
Short name T375
Test name
Test status
Simulation time 28304739 ps
CPU time 0.98 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:53:57 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665103901 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.3665103901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.1053355006
Short name T380
Test name
Test status
Simulation time 114348762 ps
CPU time 1.52 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:53:58 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053355006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.1053355006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.3504498106
Short name T377
Test name
Test status
Simulation time 44321742 ps
CPU time 0.93 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:53:57 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504498106 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3504498106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.916433068
Short name T376
Test name
Test status
Simulation time 34815030 ps
CPU time 0.98 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:53:57 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916433068 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.916433068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.242402820
Short name T384
Test name
Test status
Simulation time 44321278 ps
CPU time 1.04 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 210964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=242402820 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invalid.242402820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.2414191733
Short name T372
Test name
Test status
Simulation time 210941752 ps
CPU time 1.49 seconds
Started Aug 29 10:53:54 AM UTC 24
Finished Aug 29 10:53:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2414191733 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.2414191733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.582768764
Short name T313
Test name
Test status
Simulation time 122489212 ps
CPU time 1.46 seconds
Started Aug 29 10:53:53 AM UTC 24
Finished Aug 29 10:53:56 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582768764 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.582768764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.2627114798
Short name T392
Test name
Test status
Simulation time 112074663 ps
CPU time 1.64 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627114798 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.2627114798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1644539877
Short name T381
Test name
Test status
Simulation time 253212632 ps
CPU time 1.64 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:53:58 AM UTC 24
Peak memory 210980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644539877 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.1644539877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1544828065
Short name T393
Test name
Test status
Simulation time 1267214272 ps
CPU time 3.44 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:54:00 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544828065 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1544828065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4220488727
Short name T382
Test name
Test status
Simulation time 1048411373 ps
CPU time 2.62 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220488727 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.4220488727
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.3290111459
Short name T378
Test name
Test status
Simulation time 69434944 ps
CPU time 1.46 seconds
Started Aug 29 10:53:55 AM UTC 24
Finished Aug 29 10:53:58 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290111459 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.3290111459
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3452806394
Short name T370
Test name
Test status
Simulation time 30979161 ps
CPU time 1.05 seconds
Started Aug 29 10:53:53 AM UTC 24
Finished Aug 29 10:53:55 AM UTC 24
Peak memory 208252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452806394 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3452806394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.1360274078
Short name T389
Test name
Test status
Simulation time 60930683 ps
CPU time 1.28 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1360274078 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.1360274078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.609429874
Short name T77
Test name
Test status
Simulation time 4244909454 ps
CPU time 11.64 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:54:10 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=609429874 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr
_stress_all_with_rand_reset.609429874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.871529305
Short name T366
Test name
Test status
Simulation time 165426201 ps
CPU time 1.37 seconds
Started Aug 29 10:53:54 AM UTC 24
Finished Aug 29 10:53:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=871529305 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.871529305
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.831549219
Short name T371
Test name
Test status
Simulation time 272799654 ps
CPU time 1.34 seconds
Started Aug 29 10:53:54 AM UTC 24
Finished Aug 29 10:53:56 AM UTC 24
Peak memory 210916 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831549219 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.831549219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.3760457160
Short name T383
Test name
Test status
Simulation time 38676647 ps
CPU time 0.84 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760457160 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.3760457160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.4087347511
Short name T394
Test name
Test status
Simulation time 39003861 ps
CPU time 0.86 seconds
Started Aug 29 10:53:58 AM UTC 24
Finished Aug 29 10:54:00 AM UTC 24
Peak memory 206064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087347511 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.4087347511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.74743078
Short name T399
Test name
Test status
Simulation time 958423370 ps
CPU time 1.46 seconds
Started Aug 29 10:53:59 AM UTC 24
Finished Aug 29 10:54:01 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=74743078 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.74743078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.1697692739
Short name T397
Test name
Test status
Simulation time 37526610 ps
CPU time 0.98 seconds
Started Aug 29 10:53:59 AM UTC 24
Finished Aug 29 10:54:01 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697692739 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.1697692739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.1511626109
Short name T395
Test name
Test status
Simulation time 48706636 ps
CPU time 0.95 seconds
Started Aug 29 10:53:59 AM UTC 24
Finished Aug 29 10:54:00 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511626109 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.1511626109
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.771082845
Short name T402
Test name
Test status
Simulation time 39859625 ps
CPU time 0.95 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771082845 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.771082845
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.1207406413
Short name T390
Test name
Test status
Simulation time 218979734 ps
CPU time 1.24 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207406413 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.1207406413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.1819982052
Short name T386
Test name
Test status
Simulation time 77289114 ps
CPU time 1.08 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1819982052 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.1819982052
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2822604161
Short name T398
Test name
Test status
Simulation time 149919463 ps
CPU time 1.04 seconds
Started Aug 29 10:53:59 AM UTC 24
Finished Aug 29 10:54:01 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822604161 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.2822604161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.20760445
Short name T400
Test name
Test status
Simulation time 157784818 ps
CPU time 1.78 seconds
Started Aug 29 10:53:58 AM UTC 24
Finished Aug 29 10:54:01 AM UTC 24
Peak memory 210980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20760445 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.20760445
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1557605504
Short name T401
Test name
Test status
Simulation time 1036243685 ps
CPU time 2.42 seconds
Started Aug 29 10:53:58 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557605504 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1557605504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3812717523
Short name T405
Test name
Test status
Simulation time 1189847747 ps
CPU time 2.96 seconds
Started Aug 29 10:53:58 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 210884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812717523 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3812717523
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2929798437
Short name T396
Test name
Test status
Simulation time 66000975 ps
CPU time 1.15 seconds
Started Aug 29 10:53:58 AM UTC 24
Finished Aug 29 10:54:00 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2929798437 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.2929798437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.99680415
Short name T385
Test name
Test status
Simulation time 36172947 ps
CPU time 0.98 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99680415 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.99680415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.2840103250
Short name T412
Test name
Test status
Simulation time 370520173 ps
CPU time 1.6 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:03 AM UTC 24
Peak memory 210516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840103250 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.2840103250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.2077200360
Short name T446
Test name
Test status
Simulation time 2041935896 ps
CPU time 6.84 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2077200360 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmg
r_stress_all_with_rand_reset.2077200360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.2327790325
Short name T391
Test name
Test status
Simulation time 520634187 ps
CPU time 1.25 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327790325 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.2327790325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.1617291412
Short name T387
Test name
Test status
Simulation time 33191960 ps
CPU time 0.95 seconds
Started Aug 29 10:53:57 AM UTC 24
Finished Aug 29 10:53:59 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617291412 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.1617291412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.2044171895
Short name T407
Test name
Test status
Simulation time 43289203 ps
CPU time 0.92 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044171895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.2044171895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.1990367038
Short name T416
Test name
Test status
Simulation time 71794646 ps
CPU time 0.99 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:04 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990367038 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.1990367038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.1380829152
Short name T410
Test name
Test status
Simulation time 29709636 ps
CPU time 0.94 seconds
Started Aug 29 10:54:01 AM UTC 24
Finished Aug 29 10:54:03 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380829152 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.1380829152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.4250183342
Short name T419
Test name
Test status
Simulation time 113701437 ps
CPU time 1.28 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:04 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250183342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.4250183342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.38002224
Short name T415
Test name
Test status
Simulation time 108329187 ps
CPU time 0.72 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:04 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38002224 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.38002224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.2755506551
Short name T409
Test name
Test status
Simulation time 21239362 ps
CPU time 0.75 seconds
Started Aug 29 10:54:01 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2755506551 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.2755506551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_invalid.3260997386
Short name T418
Test name
Test status
Simulation time 78677232 ps
CPU time 1.02 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:04 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3260997386 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invalid.3260997386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.570092119
Short name T408
Test name
Test status
Simulation time 78352009 ps
CPU time 1.04 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=570092119 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.570092119
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.1966094275
Short name T406
Test name
Test status
Simulation time 96554143 ps
CPU time 1.04 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1966094275 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.1966094275
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.3796706381
Short name T421
Test name
Test status
Simulation time 107279306 ps
CPU time 1.44 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:04 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3796706381 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3796706381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.3628193587
Short name T414
Test name
Test status
Simulation time 141244906 ps
CPU time 1.65 seconds
Started Aug 29 10:54:01 AM UTC 24
Finished Aug 29 10:54:03 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628193587 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.3628193587
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3981520048
Short name T424
Test name
Test status
Simulation time 808090487 ps
CPU time 3.31 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:05 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981520048 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3981520048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1173182919
Short name T423
Test name
Test status
Simulation time 727287897 ps
CPU time 3.33 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:05 AM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1173182919 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1173182919
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.590442096
Short name T413
Test name
Test status
Simulation time 64520035 ps
CPU time 1.43 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:03 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590442096 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.590442096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.3601801137
Short name T404
Test name
Test status
Simulation time 37568100 ps
CPU time 0.98 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601801137 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3601801137
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.3188169666
Short name T422
Test name
Test status
Simulation time 422036638 ps
CPU time 1.71 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:05 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188169666 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.3188169666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.3480488805
Short name T78
Test name
Test status
Simulation time 6016476832 ps
CPU time 8.91 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:12 AM UTC 24
Peak memory 211720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3480488805 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmg
r_stress_all_with_rand_reset.3480488805
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.3995237231
Short name T403
Test name
Test status
Simulation time 203754439 ps
CPU time 0.86 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:02 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3995237231 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.3995237231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.629444634
Short name T411
Test name
Test status
Simulation time 244324276 ps
CPU time 1.24 seconds
Started Aug 29 10:54:00 AM UTC 24
Finished Aug 29 10:54:03 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629444634 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.629444634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.3304784476
Short name T425
Test name
Test status
Simulation time 101057152 ps
CPU time 0.89 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:05 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304784476 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.3304784476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.2471955729
Short name T434
Test name
Test status
Simulation time 61360712 ps
CPU time 1.2 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 211072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2471955729 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.2471955729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1323279389
Short name T426
Test name
Test status
Simulation time 40253285 ps
CPU time 0.81 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323279389 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.1323279389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.3705569825
Short name T435
Test name
Test status
Simulation time 108314988 ps
CPU time 1.34 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705569825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.3705569825
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.2411507106
Short name T429
Test name
Test status
Simulation time 93022383 ps
CPU time 0.91 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411507106 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.2411507106
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.3184209656
Short name T430
Test name
Test status
Simulation time 40788839 ps
CPU time 1.03 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184209656 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.3184209656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.3582133596
Short name T433
Test name
Test status
Simulation time 46193235 ps
CPU time 0.99 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3582133596 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invalid.3582133596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.502403559
Short name T432
Test name
Test status
Simulation time 272761220 ps
CPU time 1.5 seconds
Started Aug 29 10:54:03 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=502403559 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.502403559
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.3814877800
Short name T417
Test name
Test status
Simulation time 62014278 ps
CPU time 0.78 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:04 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814877800 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.3814877800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.1066567792
Short name T437
Test name
Test status
Simulation time 91170008 ps
CPU time 1.3 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 220164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1066567792 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.1066567792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.3009349393
Short name T428
Test name
Test status
Simulation time 69511352 ps
CPU time 1 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009349393 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.3009349393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4036443394
Short name T439
Test name
Test status
Simulation time 880548325 ps
CPU time 2.27 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:07 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036443394 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4036443394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.551523871
Short name T438
Test name
Test status
Simulation time 1861859693 ps
CPU time 1.86 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:07 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551523871 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.551523871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3981617197
Short name T431
Test name
Test status
Simulation time 71707474 ps
CPU time 1.22 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3981617197 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3981617197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.1539011228
Short name T420
Test name
Test status
Simulation time 32518327 ps
CPU time 1 seconds
Started Aug 29 10:54:02 AM UTC 24
Finished Aug 29 10:54:04 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1539011228 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.1539011228
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.895605534
Short name T448
Test name
Test status
Simulation time 1001395361 ps
CPU time 1.78 seconds
Started Aug 29 10:54:05 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 210720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=895605534 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.895605534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.2604819944
Short name T474
Test name
Test status
Simulation time 1614682593 ps
CPU time 5.04 seconds
Started Aug 29 10:54:05 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2604819944 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmg
r_stress_all_with_rand_reset.2604819944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.2513289333
Short name T427
Test name
Test status
Simulation time 145497131 ps
CPU time 1.19 seconds
Started Aug 29 10:54:03 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513289333 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.2513289333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.320411606
Short name T436
Test name
Test status
Simulation time 425697158 ps
CPU time 1.71 seconds
Started Aug 29 10:54:04 AM UTC 24
Finished Aug 29 10:54:06 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320411606 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.320411606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.559666605
Short name T44
Test name
Test status
Simulation time 32538401 ps
CPU time 1.11 seconds
Started Aug 29 10:52:47 AM UTC 24
Finished Aug 29 10:52:50 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=559666605 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.559666605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.86613868
Short name T147
Test name
Test status
Simulation time 91727152 ps
CPU time 1.06 seconds
Started Aug 29 10:52:51 AM UTC 24
Finished Aug 29 10:52:53 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86613868 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.86613868
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.1382062606
Short name T141
Test name
Test status
Simulation time 30377424 ps
CPU time 0.99 seconds
Started Aug 29 10:52:49 AM UTC 24
Finished Aug 29 10:52:51 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382062606 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.1382062606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.2316504593
Short name T142
Test name
Test status
Simulation time 203170558 ps
CPU time 1.43 seconds
Started Aug 29 10:52:51 AM UTC 24
Finished Aug 29 10:52:53 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316504593 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.2316504593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.2747814999
Short name T18
Test name
Test status
Simulation time 65803054 ps
CPU time 0.73 seconds
Started Aug 29 10:52:51 AM UTC 24
Finished Aug 29 10:52:53 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747814999 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.2747814999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.531907915
Short name T174
Test name
Test status
Simulation time 67272337 ps
CPU time 0.9 seconds
Started Aug 29 10:52:51 AM UTC 24
Finished Aug 29 10:52:53 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531907915 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.531907915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.775289274
Short name T48
Test name
Test status
Simulation time 40859228 ps
CPU time 1.07 seconds
Started Aug 29 10:52:52 AM UTC 24
Finished Aug 29 10:52:54 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775289274 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.775289274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.1645201793
Short name T74
Test name
Test status
Simulation time 415048293 ps
CPU time 1.73 seconds
Started Aug 29 10:52:46 AM UTC 24
Finished Aug 29 10:52:49 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645201793 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.1645201793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.3203547634
Short name T42
Test name
Test status
Simulation time 113501965 ps
CPU time 1.17 seconds
Started Aug 29 10:52:46 AM UTC 24
Finished Aug 29 10:52:48 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203547634 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.3203547634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.180640680
Short name T46
Test name
Test status
Simulation time 353717802 ps
CPU time 1.19 seconds
Started Aug 29 10:52:52 AM UTC 24
Finished Aug 29 10:52:54 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=180640680 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.180640680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.2883895584
Short name T61
Test name
Test status
Simulation time 128343139 ps
CPU time 1.6 seconds
Started Aug 29 10:52:50 AM UTC 24
Finished Aug 29 10:52:52 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2883895584 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.2883895584
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1069435449
Short name T152
Test name
Test status
Simulation time 804593320 ps
CPU time 5.35 seconds
Started Aug 29 10:52:47 AM UTC 24
Finished Aug 29 10:52:54 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069435449 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1069435449
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.549886468
Short name T146
Test name
Test status
Simulation time 953502353 ps
CPU time 3.29 seconds
Started Aug 29 10:52:47 AM UTC 24
Finished Aug 29 10:52:52 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549886468 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.549886468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2966442851
Short name T173
Test name
Test status
Simulation time 73555111 ps
CPU time 1.46 seconds
Started Aug 29 10:52:49 AM UTC 24
Finished Aug 29 10:52:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966442851 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.2966442851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.92910283
Short name T124
Test name
Test status
Simulation time 75600828 ps
CPU time 0.96 seconds
Started Aug 29 10:52:46 AM UTC 24
Finished Aug 29 10:52:48 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92910283 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.92910283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.1122472996
Short name T118
Test name
Test status
Simulation time 1371868357 ps
CPU time 8.93 seconds
Started Aug 29 10:52:53 AM UTC 24
Finished Aug 29 10:53:03 AM UTC 24
Peak memory 210820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122472996 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.1122472996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.4189164900
Short name T171
Test name
Test status
Simulation time 205388830 ps
CPU time 1.22 seconds
Started Aug 29 10:52:47 AM UTC 24
Finished Aug 29 10:52:50 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189164900 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.4189164900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.2948217383
Short name T172
Test name
Test status
Simulation time 319873396 ps
CPU time 2.51 seconds
Started Aug 29 10:52:47 AM UTC 24
Finished Aug 29 10:52:51 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948217383 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.2948217383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.3386427756
Short name T447
Test name
Test status
Simulation time 43918180 ps
CPU time 1.36 seconds
Started Aug 29 10:54:06 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386427756 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.3386427756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.3891659236
Short name T442
Test name
Test status
Simulation time 37745314 ps
CPU time 0.8 seconds
Started Aug 29 10:54:06 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891659236 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.3891659236
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.2416160351
Short name T455
Test name
Test status
Simulation time 375485122 ps
CPU time 0.99 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 208128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2416160351 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.2416160351
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.3207726884
Short name T451
Test name
Test status
Simulation time 50755482 ps
CPU time 0.84 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 205912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207726884 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.3207726884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.3278805017
Short name T450
Test name
Test status
Simulation time 64866783 ps
CPU time 0.87 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3278805017 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.3278805017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.3452800059
Short name T453
Test name
Test status
Simulation time 57509660 ps
CPU time 0.85 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452800059 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invalid.3452800059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.1365716534
Short name T444
Test name
Test status
Simulation time 292661221 ps
CPU time 1.06 seconds
Started Aug 29 10:54:06 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365716534 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wakeup_race.1365716534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.3913383642
Short name T441
Test name
Test status
Simulation time 122282848 ps
CPU time 1.11 seconds
Started Aug 29 10:54:05 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913383642 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.3913383642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.1946893756
Short name T462
Test name
Test status
Simulation time 103772915 ps
CPU time 1.3 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:10 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946893756 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.1946893756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.1909905115
Short name T458
Test name
Test status
Simulation time 165728759 ps
CPU time 1.39 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 208152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909905115 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.1909905115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.998893986
Short name T454
Test name
Test status
Simulation time 1255480139 ps
CPU time 2.35 seconds
Started Aug 29 10:54:06 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=998893986 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.998893986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1082995156
Short name T461
Test name
Test status
Simulation time 941703540 ps
CPU time 2.81 seconds
Started Aug 29 10:54:06 AM UTC 24
Finished Aug 29 10:54:10 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082995156 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1082995156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1033137817
Short name T445
Test name
Test status
Simulation time 51924507 ps
CPU time 1.01 seconds
Started Aug 29 10:54:06 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033137817 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.1033137817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.3218198686
Short name T440
Test name
Test status
Simulation time 31534537 ps
CPU time 0.81 seconds
Started Aug 29 10:54:05 AM UTC 24
Finished Aug 29 10:54:07 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218198686 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.3218198686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.1505295284
Short name T485
Test name
Test status
Simulation time 3952649235 ps
CPU time 4.52 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505295284 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.1505295284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.1810362960
Short name T79
Test name
Test status
Simulation time 8780955578 ps
CPU time 11.17 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:20 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1810362960 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmg
r_stress_all_with_rand_reset.1810362960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.3522948544
Short name T443
Test name
Test status
Simulation time 104326900 ps
CPU time 1.08 seconds
Started Aug 29 10:54:06 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3522948544 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.3522948544
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.1580526499
Short name T449
Test name
Test status
Simulation time 257539109 ps
CPU time 1.61 seconds
Started Aug 29 10:54:06 AM UTC 24
Finished Aug 29 10:54:08 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1580526499 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.1580526499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/20.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.2981527854
Short name T464
Test name
Test status
Simulation time 34319712 ps
CPU time 0.95 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981527854 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.2981527854
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.2892274938
Short name T469
Test name
Test status
Simulation time 145914396 ps
CPU time 0.96 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2892274938 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.2892274938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.3453445010
Short name T465
Test name
Test status
Simulation time 37494143 ps
CPU time 0.82 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453445010 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.3453445010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.1826835512
Short name T471
Test name
Test status
Simulation time 205421828 ps
CPU time 1.14 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 206184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1826835512 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.1826835512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.1603220700
Short name T468
Test name
Test status
Simulation time 49985235 ps
CPU time 0.89 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603220700 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1603220700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.218330568
Short name T466
Test name
Test status
Simulation time 95788198 ps
CPU time 0.75 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218330568 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.218330568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.2613910187
Short name T472
Test name
Test status
Simulation time 80154224 ps
CPU time 0.87 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2613910187 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid.2613910187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.2581952419
Short name T463
Test name
Test status
Simulation time 220645081 ps
CPU time 1.61 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:10 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581952419 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.2581952419
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.3445813816
Short name T459
Test name
Test status
Simulation time 143901646 ps
CPU time 1.1 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445813816 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.3445813816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.1545204079
Short name T473
Test name
Test status
Simulation time 163522614 ps
CPU time 1.01 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545204079 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1545204079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.822629850
Short name T467
Test name
Test status
Simulation time 345172379 ps
CPU time 1.19 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 210984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822629850 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.822629850
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1950460173
Short name T475
Test name
Test status
Simulation time 1339822964 ps
CPU time 2.31 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:12 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1950460173 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1950460173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1391316157
Short name T486
Test name
Test status
Simulation time 835611710 ps
CPU time 3.18 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1391316157 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1391316157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3222096290
Short name T470
Test name
Test status
Simulation time 170776988 ps
CPU time 1.16 seconds
Started Aug 29 10:54:09 AM UTC 24
Finished Aug 29 10:54:11 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3222096290 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.3222096290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.1174434497
Short name T456
Test name
Test status
Simulation time 29647408 ps
CPU time 0.98 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 211088 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174434497 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.1174434497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1625762723
Short name T522
Test name
Test status
Simulation time 2108022770 ps
CPU time 7.45 seconds
Started Aug 29 10:54:10 AM UTC 24
Finished Aug 29 10:54:19 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625762723 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.1625762723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.4200765196
Short name T531
Test name
Test status
Simulation time 5622750566 ps
CPU time 17.14 seconds
Started Aug 29 10:54:10 AM UTC 24
Finished Aug 29 10:54:29 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4200765196 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmg
r_stress_all_with_rand_reset.4200765196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.1400602278
Short name T457
Test name
Test status
Simulation time 68410208 ps
CPU time 0.97 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1400602278 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.1400602278
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.2076897579
Short name T460
Test name
Test status
Simulation time 216272375 ps
CPU time 0.95 seconds
Started Aug 29 10:54:07 AM UTC 24
Finished Aug 29 10:54:09 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076897579 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.2076897579
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/21.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.1039212743
Short name T484
Test name
Test status
Simulation time 118674291 ps
CPU time 1.09 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039212743 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1039212743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3319242376
Short name T490
Test name
Test status
Simulation time 60575547 ps
CPU time 0.91 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:14 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319242376 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.3319242376
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3952052281
Short name T478
Test name
Test status
Simulation time 31668027 ps
CPU time 0.78 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3952052281 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.3952052281
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.2572185127
Short name T489
Test name
Test status
Simulation time 110479783 ps
CPU time 1.3 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572185127 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.2572185127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.3573570939
Short name T477
Test name
Test status
Simulation time 40501712 ps
CPU time 0.63 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573570939 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.3573570939
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.2908980310
Short name T480
Test name
Test status
Simulation time 59295048 ps
CPU time 0.75 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2908980310 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.2908980310
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.625047054
Short name T494
Test name
Test status
Simulation time 43250322 ps
CPU time 1.09 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:14 AM UTC 24
Peak memory 210384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=625047054 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invalid.625047054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.922546875
Short name T483
Test name
Test status
Simulation time 226222998 ps
CPU time 1.24 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922546875 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.922546875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.1463584377
Short name T479
Test name
Test status
Simulation time 90662645 ps
CPU time 1.1 seconds
Started Aug 29 10:54:10 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463584377 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1463584377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.2683955115
Short name T496
Test name
Test status
Simulation time 143810478 ps
CPU time 1.17 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:14 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683955115 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.2683955115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1079020092
Short name T488
Test name
Test status
Simulation time 159354131 ps
CPU time 1.07 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 210980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079020092 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.1079020092
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.316492024
Short name T491
Test name
Test status
Simulation time 912408435 ps
CPU time 2.29 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:14 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=316492024 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.316492024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1205231255
Short name T500
Test name
Test status
Simulation time 816003935 ps
CPU time 2.6 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:15 AM UTC 24
Peak memory 211312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205231255 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1205231255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1045837522
Short name T481
Test name
Test status
Simulation time 91028186 ps
CPU time 0.92 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045837522 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.1045837522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.1676199549
Short name T476
Test name
Test status
Simulation time 41492071 ps
CPU time 0.94 seconds
Started Aug 29 10:54:10 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 207692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676199549 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.1676199549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.3289999155
Short name T452
Test name
Test status
Simulation time 1172074958 ps
CPU time 3.83 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:17 AM UTC 24
Peak memory 211164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289999155 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.3289999155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.525279154
Short name T80
Test name
Test status
Simulation time 7682777485 ps
CPU time 11.69 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:25 AM UTC 24
Peak memory 211604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=525279154 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr
_stress_all_with_rand_reset.525279154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.83599284
Short name T482
Test name
Test status
Simulation time 138963713 ps
CPU time 1.04 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83599284 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.83599284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.3999642342
Short name T487
Test name
Test status
Simulation time 376371502 ps
CPU time 1.31 seconds
Started Aug 29 10:54:11 AM UTC 24
Finished Aug 29 10:54:13 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999642342 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.3999642342
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/22.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.569104006
Short name T495
Test name
Test status
Simulation time 25884883 ps
CPU time 0.9 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:14 AM UTC 24
Peak memory 208072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569104006 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.569104006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.432923553
Short name T160
Test name
Test status
Simulation time 46878657 ps
CPU time 1.09 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=432923553 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.432923553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3560534748
Short name T502
Test name
Test status
Simulation time 39070734 ps
CPU time 0.79 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560534748 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.3560534748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.3562024693
Short name T511
Test name
Test status
Simulation time 170494758 ps
CPU time 1.41 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3562024693 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3562024693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.1273181944
Short name T504
Test name
Test status
Simulation time 23416050 ps
CPU time 0.86 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1273181944 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.1273181944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.940859491
Short name T501
Test name
Test status
Simulation time 24828714 ps
CPU time 0.71 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940859491 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.940859491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.3524082758
Short name T506
Test name
Test status
Simulation time 44958807 ps
CPU time 0.86 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3524082758 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invalid.3524082758
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.1291329542
Short name T499
Test name
Test status
Simulation time 344729898 ps
CPU time 1.24 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:15 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1291329542 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.1291329542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.3583327534
Short name T493
Test name
Test status
Simulation time 79915408 ps
CPU time 0.98 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:14 AM UTC 24
Peak memory 210956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583327534 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.3583327534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.2134238251
Short name T507
Test name
Test status
Simulation time 420442197 ps
CPU time 0.96 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134238251 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.2134238251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2575149049
Short name T508
Test name
Test status
Simulation time 183155835 ps
CPU time 1.22 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575149049 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.2575149049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3540171499
Short name T515
Test name
Test status
Simulation time 804633141 ps
CPU time 3.6 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:17 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540171499 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3540171499
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2475768543
Short name T514
Test name
Test status
Simulation time 1111372873 ps
CPU time 2.97 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475768543 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2475768543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.2472552221
Short name T503
Test name
Test status
Simulation time 95279149 ps
CPU time 0.86 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2472552221 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.2472552221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.3516879636
Short name T492
Test name
Test status
Simulation time 33544492 ps
CPU time 0.9 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:14 AM UTC 24
Peak memory 208108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3516879636 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.3516879636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.1689685110
Short name T513
Test name
Test status
Simulation time 274581435 ps
CPU time 1.17 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689685110 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.1689685110
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.2573337900
Short name T530
Test name
Test status
Simulation time 4880939738 ps
CPU time 10.95 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:26 AM UTC 24
Peak memory 211560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2573337900 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmg
r_stress_all_with_rand_reset.2573337900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.4115237375
Short name T497
Test name
Test status
Simulation time 174451353 ps
CPU time 1.04 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:14 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115237375 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.4115237375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.2746638736
Short name T498
Test name
Test status
Simulation time 52501158 ps
CPU time 1.05 seconds
Started Aug 29 10:54:12 AM UTC 24
Finished Aug 29 10:54:15 AM UTC 24
Peak memory 210628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2746638736 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.2746638736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/23.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.2243238622
Short name T517
Test name
Test status
Simulation time 31838617 ps
CPU time 1.19 seconds
Started Aug 29 10:54:15 AM UTC 24
Finished Aug 29 10:54:18 AM UTC 24
Peak memory 211000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243238622 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.2243238622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.4233908382
Short name T526
Test name
Test status
Simulation time 68424809 ps
CPU time 0.82 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:21 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233908382 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.4233908382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3425164268
Short name T516
Test name
Test status
Simulation time 30563871 ps
CPU time 0.76 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:17 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425164268 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.3425164268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.2456546694
Short name T528
Test name
Test status
Simulation time 111739088 ps
CPU time 1.06 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456546694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.2456546694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.254417511
Short name T525
Test name
Test status
Simulation time 58821873 ps
CPU time 0.73 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:21 AM UTC 24
Peak memory 206180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254417511 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.254417511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.146964220
Short name T524
Test name
Test status
Simulation time 54210918 ps
CPU time 0.73 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:20 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=146964220 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.146964220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.415781684
Short name T529
Test name
Test status
Simulation time 121044825 ps
CPU time 0.77 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:21 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415781684 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid.415781684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.1250861804
Short name T505
Test name
Test status
Simulation time 61275692 ps
CPU time 0.76 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1250861804 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.1250861804
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.859618242
Short name T510
Test name
Test status
Simulation time 185789880 ps
CPU time 1.01 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=859618242 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.859618242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.1337167074
Short name T527
Test name
Test status
Simulation time 101973082 ps
CPU time 0.87 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:21 AM UTC 24
Peak memory 220148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337167074 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.1337167074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.2149543288
Short name T520
Test name
Test status
Simulation time 169614010 ps
CPU time 1.37 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:18 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149543288 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.2149543288
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2255472767
Short name T521
Test name
Test status
Simulation time 1175811547 ps
CPU time 2.2 seconds
Started Aug 29 10:54:15 AM UTC 24
Finished Aug 29 10:54:19 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2255472767 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2255472767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3800027648
Short name T523
Test name
Test status
Simulation time 1050486679 ps
CPU time 2.78 seconds
Started Aug 29 10:54:15 AM UTC 24
Finished Aug 29 10:54:19 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3800027648 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3800027648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3907443294
Short name T518
Test name
Test status
Simulation time 171554325 ps
CPU time 1.3 seconds
Started Aug 29 10:54:16 AM UTC 24
Finished Aug 29 10:54:18 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3907443294 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.3907443294
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.452403357
Short name T509
Test name
Test status
Simulation time 55178954 ps
CPU time 0.87 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=452403357 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.452403357
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.2799673187
Short name T532
Test name
Test status
Simulation time 1194359982 ps
CPU time 2.14 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:37 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799673187 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2799673187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.359850860
Short name T125
Test name
Test status
Simulation time 2204629011 ps
CPU time 4.95 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:50 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=359850860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr
_stress_all_with_rand_reset.359850860
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.1313981061
Short name T512
Test name
Test status
Simulation time 349186042 ps
CPU time 1.03 seconds
Started Aug 29 10:54:14 AM UTC 24
Finished Aug 29 10:54:16 AM UTC 24
Peak memory 208228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1313981061 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.1313981061
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.2880939631
Short name T519
Test name
Test status
Simulation time 430523953 ps
CPU time 1.41 seconds
Started Aug 29 10:54:15 AM UTC 24
Finished Aug 29 10:54:18 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2880939631 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.2880939631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/24.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.2701403886
Short name T547
Test name
Test status
Simulation time 36688032 ps
CPU time 0.66 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701403886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2701403886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.3489959704
Short name T535
Test name
Test status
Simulation time 109329857 ps
CPU time 0.78 seconds
Started Aug 29 10:54:19 AM UTC 24
Finished Aug 29 10:54:42 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3489959704 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.3489959704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.1617814345
Short name T553
Test name
Test status
Simulation time 29306162 ps
CPU time 0.57 seconds
Started Aug 29 10:54:18 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617814345 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.1617814345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.1663002068
Short name T589
Test name
Test status
Simulation time 591753541 ps
CPU time 0.73 seconds
Started Aug 29 10:54:18 AM UTC 24
Finished Aug 29 10:54:57 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1663002068 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.1663002068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.2626507828
Short name T534
Test name
Test status
Simulation time 109327035 ps
CPU time 0.59 seconds
Started Aug 29 10:54:19 AM UTC 24
Finished Aug 29 10:54:42 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2626507828 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2626507828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.2537823840
Short name T543
Test name
Test status
Simulation time 81241255 ps
CPU time 0.63 seconds
Started Aug 29 10:54:18 AM UTC 24
Finished Aug 29 10:54:45 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2537823840 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2537823840
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.1206168370
Short name T537
Test name
Test status
Simulation time 41604454 ps
CPU time 0.63 seconds
Started Aug 29 10:54:19 AM UTC 24
Finished Aug 29 10:54:42 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206168370 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.1206168370
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.3404974530
Short name T549
Test name
Test status
Simulation time 402483618 ps
CPU time 1 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 208272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404974530 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.3404974530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.2676125232
Short name T546
Test name
Test status
Simulation time 456272261 ps
CPU time 0.89 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676125232 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.2676125232
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.1224212487
Short name T540
Test name
Test status
Simulation time 105236588 ps
CPU time 0.91 seconds
Started Aug 29 10:54:19 AM UTC 24
Finished Aug 29 10:54:42 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224212487 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.1224212487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.1684739767
Short name T605
Test name
Test status
Simulation time 92472207 ps
CPU time 0.88 seconds
Started Aug 29 10:54:18 AM UTC 24
Finished Aug 29 10:55:07 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684739767 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.1684739767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1406400208
Short name T560
Test name
Test status
Simulation time 892989754 ps
CPU time 2.53 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:48 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1406400208 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1406400208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.465643289
Short name T559
Test name
Test status
Simulation time 1029549129 ps
CPU time 2.01 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:48 AM UTC 24
Peak memory 211568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465643289 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.465643289
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1567894706
Short name T556
Test name
Test status
Simulation time 749385048 ps
CPU time 0.91 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1567894706 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1567894706
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.1595459001
Short name T545
Test name
Test status
Simulation time 33625175 ps
CPU time 0.69 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595459001 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.1595459001
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.2130901798
Short name T542
Test name
Test status
Simulation time 1783932393 ps
CPU time 3.75 seconds
Started Aug 29 10:54:19 AM UTC 24
Finished Aug 29 10:54:45 AM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130901798 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.2130901798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.943425633
Short name T541
Test name
Test status
Simulation time 585956845 ps
CPU time 1.47 seconds
Started Aug 29 10:54:19 AM UTC 24
Finished Aug 29 10:54:43 AM UTC 24
Peak memory 210416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=943425633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr
_stress_all_with_rand_reset.943425633
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.2819113264
Short name T552
Test name
Test status
Simulation time 566787680 ps
CPU time 0.92 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2819113264 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.2819113264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.3475234921
Short name T554
Test name
Test status
Simulation time 295114770 ps
CPU time 1 seconds
Started Aug 29 10:54:17 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3475234921 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.3475234921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.472933194
Short name T649
Test name
Test status
Simulation time 84762933 ps
CPU time 0.59 seconds
Started Aug 29 10:54:26 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472933194 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.472933194
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.2376477404
Short name T550
Test name
Test status
Simulation time 92755834 ps
CPU time 0.54 seconds
Started Aug 29 10:54:21 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376477404 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.2376477404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.1070110991
Short name T588
Test name
Test status
Simulation time 378024459 ps
CPU time 0.73 seconds
Started Aug 29 10:54:22 AM UTC 24
Finished Aug 29 10:54:57 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1070110991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1070110991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.3937857132
Short name T555
Test name
Test status
Simulation time 55914600 ps
CPU time 0.59 seconds
Started Aug 29 10:54:22 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937857132 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.3937857132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.69381817
Short name T604
Test name
Test status
Simulation time 48869879 ps
CPU time 0.68 seconds
Started Aug 29 10:54:22 AM UTC 24
Finished Aug 29 10:55:06 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69381817 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.69381817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.2497559085
Short name T587
Test name
Test status
Simulation time 51852544 ps
CPU time 0.57 seconds
Started Aug 29 10:54:28 AM UTC 24
Finished Aug 29 10:54:57 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2497559085 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.2497559085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.2874103595
Short name T574
Test name
Test status
Simulation time 237637417 ps
CPU time 0.89 seconds
Started Aug 29 10:54:20 AM UTC 24
Finished Aug 29 10:54:52 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874103595 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.2874103595
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.2357826968
Short name T538
Test name
Test status
Simulation time 46772575 ps
CPU time 0.58 seconds
Started Aug 29 10:54:19 AM UTC 24
Finished Aug 29 10:54:42 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357826968 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.2357826968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.2077521600
Short name T536
Test name
Test status
Simulation time 114367732 ps
CPU time 0.82 seconds
Started Aug 29 10:54:27 AM UTC 24
Finished Aug 29 10:54:42 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077521600 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.2077521600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.3347554239
Short name T558
Test name
Test status
Simulation time 220630322 ps
CPU time 1.01 seconds
Started Aug 29 10:54:21 AM UTC 24
Finished Aug 29 10:54:47 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3347554239 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.3347554239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.4198150785
Short name T557
Test name
Test status
Simulation time 134286522 ps
CPU time 0.78 seconds
Started Aug 29 10:54:21 AM UTC 24
Finished Aug 29 10:54:47 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198150785 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.4198150785
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.1244751238
Short name T539
Test name
Test status
Simulation time 33666186 ps
CPU time 0.61 seconds
Started Aug 29 10:54:19 AM UTC 24
Finished Aug 29 10:54:42 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1244751238 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.1244751238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.3689237617
Short name T614
Test name
Test status
Simulation time 1021875617 ps
CPU time 3.31 seconds
Started Aug 29 10:54:34 AM UTC 24
Finished Aug 29 10:55:09 AM UTC 24
Peak memory 211556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689237617 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.3689237617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.2074486053
Short name T544
Test name
Test status
Simulation time 4828313325 ps
CPU time 4.65 seconds
Started Aug 29 10:54:30 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 211596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2074486053 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmg
r_stress_all_with_rand_reset.2074486053
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.2577152325
Short name T576
Test name
Test status
Simulation time 264957836 ps
CPU time 1.17 seconds
Started Aug 29 10:54:20 AM UTC 24
Finished Aug 29 10:54:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2577152325 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.2577152325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.2536192426
Short name T570
Test name
Test status
Simulation time 50375041 ps
CPU time 0.86 seconds
Started Aug 29 10:54:42 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536192426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.2536192426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.2718033312
Short name T658
Test name
Test status
Simulation time 46697322 ps
CPU time 0.7 seconds
Started Aug 29 10:54:46 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718033312 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.2718033312
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.4144879615
Short name T563
Test name
Test status
Simulation time 30616677 ps
CPU time 0.62 seconds
Started Aug 29 10:54:42 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 205956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144879615 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.4144879615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.4250061366
Short name T571
Test name
Test status
Simulation time 206994355 ps
CPU time 0.75 seconds
Started Aug 29 10:54:43 AM UTC 24
Finished Aug 29 10:54:52 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250061366 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.4250061366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.3919686568
Short name T548
Test name
Test status
Simulation time 36169152 ps
CPU time 0.53 seconds
Started Aug 29 10:54:44 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3919686568 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.3919686568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.3560031834
Short name T566
Test name
Test status
Simulation time 65433352 ps
CPU time 0.59 seconds
Started Aug 29 10:54:43 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3560031834 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.3560031834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.1204931512
Short name T955
Test name
Test status
Simulation time 70799984 ps
CPU time 0.58 seconds
Started Aug 29 10:54:46 AM UTC 24
Finished Aug 29 10:56:58 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1204931512 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invalid.1204931512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.881611071
Short name T533
Test name
Test status
Simulation time 189089969 ps
CPU time 0.69 seconds
Started Aug 29 10:54:39 AM UTC 24
Finished Aug 29 10:54:41 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=881611071 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.881611071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.2620126091
Short name T645
Test name
Test status
Simulation time 126376324 ps
CPU time 0.85 seconds
Started Aug 29 10:54:38 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620126091 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.2620126091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.1077601537
Short name T836
Test name
Test status
Simulation time 107275937 ps
CPU time 0.96 seconds
Started Aug 29 10:54:46 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 220196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1077601537 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.1077601537
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.949618878
Short name T567
Test name
Test status
Simulation time 148791959 ps
CPU time 0.65 seconds
Started Aug 29 10:54:42 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949618878 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.949618878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1280594945
Short name T579
Test name
Test status
Simulation time 807033839 ps
CPU time 2.63 seconds
Started Aug 29 10:54:42 AM UTC 24
Finished Aug 29 10:54:53 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280594945 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1280594945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3587921956
Short name T575
Test name
Test status
Simulation time 1109697860 ps
CPU time 1.77 seconds
Started Aug 29 10:54:42 AM UTC 24
Finished Aug 29 10:54:52 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587921956 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3587921956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3190870631
Short name T569
Test name
Test status
Simulation time 123680806 ps
CPU time 0.84 seconds
Started Aug 29 10:54:42 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3190870631 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.3190870631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.1641721073
Short name T590
Test name
Test status
Simulation time 30201608 ps
CPU time 0.58 seconds
Started Aug 29 10:54:36 AM UTC 24
Finished Aug 29 10:55:01 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1641721073 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.1641721073
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.1785270666
Short name T578
Test name
Test status
Simulation time 508328717 ps
CPU time 1.56 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:54:53 AM UTC 24
Peak memory 210484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785270666 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.1785270666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.3744160582
Short name T693
Test name
Test status
Simulation time 4261082362 ps
CPU time 5.15 seconds
Started Aug 29 10:54:46 AM UTC 24
Finished Aug 29 10:55:25 AM UTC 24
Peak memory 210976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3744160582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmg
r_stress_all_with_rand_reset.3744160582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.123128304
Short name T551
Test name
Test status
Simulation time 277495637 ps
CPU time 1.03 seconds
Started Aug 29 10:54:41 AM UTC 24
Finished Aug 29 10:54:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123128304 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.123128304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.3108138475
Short name T568
Test name
Test status
Simulation time 307247268 ps
CPU time 0.95 seconds
Started Aug 29 10:54:42 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108138475 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.3108138475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.742683892
Short name T686
Test name
Test status
Simulation time 26783731 ps
CPU time 0.78 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=742683892 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.742683892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.2670583476
Short name T561
Test name
Test status
Simulation time 79125627 ps
CPU time 0.6 seconds
Started Aug 29 10:54:48 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2670583476 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.2670583476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.599925740
Short name T562
Test name
Test status
Simulation time 51963325 ps
CPU time 0.6 seconds
Started Aug 29 10:54:48 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599925740 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.599925740
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.3665322231
Short name T680
Test name
Test status
Simulation time 73315279 ps
CPU time 0.54 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665322231 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.3665322231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.3331145593
Short name T564
Test name
Test status
Simulation time 43586710 ps
CPU time 0.59 seconds
Started Aug 29 10:54:50 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 210768 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331145593 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invalid.3331145593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.518948816
Short name T577
Test name
Test status
Simulation time 291030525 ps
CPU time 1.31 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:54:53 AM UTC 24
Peak memory 210116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=518948816 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.518948816
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.2753621266
Short name T573
Test name
Test status
Simulation time 62231462 ps
CPU time 0.84 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:54:52 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753621266 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.2753621266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.2992586529
Short name T565
Test name
Test status
Simulation time 112722343 ps
CPU time 0.69 seconds
Started Aug 29 10:54:48 AM UTC 24
Finished Aug 29 10:54:51 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2992586529 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.2992586529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2694868631
Short name T690
Test name
Test status
Simulation time 922209834 ps
CPU time 2.33 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:55:24 AM UTC 24
Peak memory 211264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2694868631 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2694868631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.1795698731
Short name T572
Test name
Test status
Simulation time 56663466 ps
CPU time 0.61 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:54:52 AM UTC 24
Peak memory 209996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795698731 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.1795698731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.1922538518
Short name T701
Test name
Test status
Simulation time 3308077627 ps
CPU time 4.16 seconds
Started Aug 29 10:54:51 AM UTC 24
Finished Aug 29 10:55:30 AM UTC 24
Peak memory 211428 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922538518 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.1922538518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.2630556075
Short name T685
Test name
Test status
Simulation time 191453884 ps
CPU time 0.72 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2630556075 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.2630556075
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.567147207
Short name T687
Test name
Test status
Simulation time 407573531 ps
CPU time 1.08 seconds
Started Aug 29 10:54:47 AM UTC 24
Finished Aug 29 10:55:23 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=567147207 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.567147207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.907447191
Short name T609
Test name
Test status
Simulation time 30957803 ps
CPU time 0.72 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:07 AM UTC 24
Peak memory 208132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907447191 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.907447191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.1958709090
Short name T597
Test name
Test status
Simulation time 68252295 ps
CPU time 0.68 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:01 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958709090 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.1958709090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.2652391337
Short name T591
Test name
Test status
Simulation time 28833447 ps
CPU time 0.6 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:01 AM UTC 24
Peak memory 206188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652391337 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.2652391337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.4138462330
Short name T596
Test name
Test status
Simulation time 207258360 ps
CPU time 0.71 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:01 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138462330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.4138462330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.999917508
Short name T595
Test name
Test status
Simulation time 79753243 ps
CPU time 0.52 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:01 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999917508 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.999917508
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.4190034672
Short name T592
Test name
Test status
Simulation time 82501841 ps
CPU time 0.53 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:01 AM UTC 24
Peak memory 206200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190034672 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.4190034672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.3543776130
Short name T580
Test name
Test status
Simulation time 67097730 ps
CPU time 0.56 seconds
Started Aug 29 10:54:53 AM UTC 24
Finished Aug 29 10:54:56 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543776130 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.3543776130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.1075792096
Short name T611
Test name
Test status
Simulation time 399534159 ps
CPU time 0.97 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:07 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1075792096 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.1075792096
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.683314935
Short name T697
Test name
Test status
Simulation time 73240051 ps
CPU time 0.82 seconds
Started Aug 29 10:54:51 AM UTC 24
Finished Aug 29 10:55:26 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683314935 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.683314935
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.698316212
Short name T582
Test name
Test status
Simulation time 126710718 ps
CPU time 0.71 seconds
Started Aug 29 10:54:53 AM UTC 24
Finished Aug 29 10:54:56 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698316212 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.698316212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.2801659290
Short name T594
Test name
Test status
Simulation time 32294296 ps
CPU time 0.63 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2801659290 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.2801659290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4247464234
Short name T613
Test name
Test status
Simulation time 2033342347 ps
CPU time 1.69 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:08 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247464234 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4247464234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1956252775
Short name T654
Test name
Test status
Simulation time 802864948 ps
CPU time 2.91 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:19 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956252775 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1956252775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1095321491
Short name T646
Test name
Test status
Simulation time 53250334 ps
CPU time 0.86 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095321491 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1095321491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.2614407283
Short name T694
Test name
Test status
Simulation time 37031446 ps
CPU time 0.58 seconds
Started Aug 29 10:54:51 AM UTC 24
Finished Aug 29 10:55:26 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614407283 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.2614407283
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.2940951150
Short name T593
Test name
Test status
Simulation time 1736665681 ps
CPU time 5.39 seconds
Started Aug 29 10:54:53 AM UTC 24
Finished Aug 29 10:55:01 AM UTC 24
Peak memory 211452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940951150 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.2940951150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.4285975359
Short name T92
Test name
Test status
Simulation time 7851666554 ps
CPU time 7.45 seconds
Started Aug 29 10:54:53 AM UTC 24
Finished Aug 29 10:55:03 AM UTC 24
Peak memory 211664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=4285975359 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmg
r_stress_all_with_rand_reset.4285975359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.2521057175
Short name T643
Test name
Test status
Simulation time 292167494 ps
CPU time 0.84 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521057175 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.2521057175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.1715895776
Short name T607
Test name
Test status
Simulation time 39510027 ps
CPU time 0.6 seconds
Started Aug 29 10:54:52 AM UTC 24
Finished Aug 29 10:55:07 AM UTC 24
Peak memory 210692 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1715895776 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.1715895776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.2439031155
Short name T93
Test name
Test status
Simulation time 164955509 ps
CPU time 1.14 seconds
Started Aug 29 10:52:55 AM UTC 24
Finished Aug 29 10:52:57 AM UTC 24
Peak memory 210924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439031155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.2439031155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.3337530596
Short name T85
Test name
Test status
Simulation time 50315101 ps
CPU time 1.24 seconds
Started Aug 29 10:52:57 AM UTC 24
Finished Aug 29 10:53:00 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337530596 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.3337530596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.3438833722
Short name T81
Test name
Test status
Simulation time 33094725 ps
CPU time 0.92 seconds
Started Aug 29 10:52:56 AM UTC 24
Finished Aug 29 10:52:58 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3438833722 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.3438833722
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.3332198543
Short name T86
Test name
Test status
Simulation time 626799184 ps
CPU time 1.41 seconds
Started Aug 29 10:52:57 AM UTC 24
Finished Aug 29 10:53:00 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332198543 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.3332198543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.2590943846
Short name T19
Test name
Test status
Simulation time 62806473 ps
CPU time 0.89 seconds
Started Aug 29 10:52:57 AM UTC 24
Finished Aug 29 10:53:00 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2590943846 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.2590943846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.4025535081
Short name T84
Test name
Test status
Simulation time 70601370 ps
CPU time 0.88 seconds
Started Aug 29 10:52:57 AM UTC 24
Finished Aug 29 10:53:00 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4025535081 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.4025535081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.838638655
Short name T88
Test name
Test status
Simulation time 49087397 ps
CPU time 1.09 seconds
Started Aug 29 10:52:59 AM UTC 24
Finished Aug 29 10:53:01 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838638655 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.838638655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.3264741304
Short name T176
Test name
Test status
Simulation time 91378205 ps
CPU time 1.12 seconds
Started Aug 29 10:52:53 AM UTC 24
Finished Aug 29 10:52:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3264741304 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.3264741304
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.2301026782
Short name T177
Test name
Test status
Simulation time 33612503 ps
CPU time 1.15 seconds
Started Aug 29 10:52:53 AM UTC 24
Finished Aug 29 10:52:56 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301026782 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.2301026782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3110992636
Short name T87
Test name
Test status
Simulation time 105027635 ps
CPU time 1.46 seconds
Started Aug 29 10:52:57 AM UTC 24
Finished Aug 29 10:53:00 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110992636 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3110992636
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.4020948796
Short name T30
Test name
Test status
Simulation time 685411616 ps
CPU time 2.76 seconds
Started Aug 29 10:52:59 AM UTC 24
Finished Aug 29 10:53:02 AM UTC 24
Peak memory 238820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020948796 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.4020948796
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.908936277
Short name T83
Test name
Test status
Simulation time 354272562 ps
CPU time 1.56 seconds
Started Aug 29 10:52:56 AM UTC 24
Finished Aug 29 10:52:59 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=908936277 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.908936277
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1344236028
Short name T82
Test name
Test status
Simulation time 1442444797 ps
CPU time 2.64 seconds
Started Aug 29 10:52:55 AM UTC 24
Finished Aug 29 10:52:58 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1344236028 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1344236028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2722673798
Short name T181
Test name
Test status
Simulation time 865027466 ps
CPU time 5.69 seconds
Started Aug 29 10:52:55 AM UTC 24
Finished Aug 29 10:53:02 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2722673798 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.2722673798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2059089453
Short name T179
Test name
Test status
Simulation time 332769365 ps
CPU time 1.18 seconds
Started Aug 29 10:52:55 AM UTC 24
Finished Aug 29 10:52:57 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2059089453 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2059089453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.3011843638
Short name T175
Test name
Test status
Simulation time 47415471 ps
CPU time 0.94 seconds
Started Aug 29 10:52:53 AM UTC 24
Finished Aug 29 10:52:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3011843638 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.3011843638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.212551526
Short name T117
Test name
Test status
Simulation time 252364433 ps
CPU time 1.99 seconds
Started Aug 29 10:52:59 AM UTC 24
Finished Aug 29 10:53:02 AM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212551526 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.212551526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3904951212
Short name T26
Test name
Test status
Simulation time 5150249602 ps
CPU time 16.54 seconds
Started Aug 29 10:52:59 AM UTC 24
Finished Aug 29 10:53:16 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3904951212 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr
_stress_all_with_rand_reset.3904951212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.3997351404
Short name T178
Test name
Test status
Simulation time 257502733 ps
CPU time 1.35 seconds
Started Aug 29 10:52:54 AM UTC 24
Finished Aug 29 10:52:56 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997351404 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.3997351404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.3512376634
Short name T180
Test name
Test status
Simulation time 686523205 ps
CPU time 1.41 seconds
Started Aug 29 10:52:55 AM UTC 24
Finished Aug 29 10:52:57 AM UTC 24
Peak memory 211032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512376634 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.3512376634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.1495704284
Short name T598
Test name
Test status
Simulation time 26311310 ps
CPU time 0.71 seconds
Started Aug 29 10:54:57 AM UTC 24
Finished Aug 29 10:55:02 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1495704284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.1495704284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1100756574
Short name T158
Test name
Test status
Simulation time 58149532 ps
CPU time 0.76 seconds
Started Aug 29 10:54:58 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1100756574 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.1100756574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.3651727406
Short name T624
Test name
Test status
Simulation time 29473878 ps
CPU time 0.55 seconds
Started Aug 29 10:54:57 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651727406 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.3651727406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.2344677538
Short name T610
Test name
Test status
Simulation time 111288073 ps
CPU time 0.74 seconds
Started Aug 29 10:54:58 AM UTC 24
Finished Aug 29 10:55:07 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2344677538 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.2344677538
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.3349242668
Short name T606
Test name
Test status
Simulation time 53497737 ps
CPU time 0.54 seconds
Started Aug 29 10:54:58 AM UTC 24
Finished Aug 29 10:55:07 AM UTC 24
Peak memory 206896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3349242668 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.3349242668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.3509578700
Short name T623
Test name
Test status
Simulation time 31687018 ps
CPU time 0.54 seconds
Started Aug 29 10:54:57 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509578700 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.3509578700
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.2296402624
Short name T629
Test name
Test status
Simulation time 71374586 ps
CPU time 0.56 seconds
Started Aug 29 10:54:59 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296402624 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invalid.2296402624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.3900698956
Short name T585
Test name
Test status
Simulation time 414242168 ps
CPU time 0.84 seconds
Started Aug 29 10:54:54 AM UTC 24
Finished Aug 29 10:54:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3900698956 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.3900698956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.2123895334
Short name T583
Test name
Test status
Simulation time 172618842 ps
CPU time 0.64 seconds
Started Aug 29 10:54:54 AM UTC 24
Finished Aug 29 10:54:56 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123895334 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.2123895334
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.1513794271
Short name T608
Test name
Test status
Simulation time 145292247 ps
CPU time 0.71 seconds
Started Aug 29 10:54:58 AM UTC 24
Finished Aug 29 10:55:07 AM UTC 24
Peak memory 218964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513794271 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1513794271
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.3619148463
Short name T622
Test name
Test status
Simulation time 81326059 ps
CPU time 0.54 seconds
Started Aug 29 10:54:57 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619148463 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.3619148463
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1607466193
Short name T631
Test name
Test status
Simulation time 1386043871 ps
CPU time 1.72 seconds
Started Aug 29 10:54:57 AM UTC 24
Finished Aug 29 10:55:13 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607466193 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1607466193
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2399479211
Short name T632
Test name
Test status
Simulation time 997313970 ps
CPU time 1.85 seconds
Started Aug 29 10:54:57 AM UTC 24
Finished Aug 29 10:55:13 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399479211 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2399479211
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3831405673
Short name T599
Test name
Test status
Simulation time 67458644 ps
CPU time 0.71 seconds
Started Aug 29 10:54:57 AM UTC 24
Finished Aug 29 10:55:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831405673 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.3831405673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.1857542230
Short name T581
Test name
Test status
Simulation time 36659454 ps
CPU time 0.57 seconds
Started Aug 29 10:54:53 AM UTC 24
Finished Aug 29 10:54:56 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857542230 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.1857542230
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.3709887666
Short name T612
Test name
Test status
Simulation time 5032435756 ps
CPU time 2.51 seconds
Started Aug 29 10:55:01 AM UTC 24
Finished Aug 29 10:55:08 AM UTC 24
Peak memory 211672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709887666 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.3709887666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.3599460785
Short name T126
Test name
Test status
Simulation time 6528845364 ps
CPU time 11.44 seconds
Started Aug 29 10:55:01 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3599460785 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmg
r_stress_all_with_rand_reset.3599460785
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.1976143424
Short name T584
Test name
Test status
Simulation time 273987276 ps
CPU time 0.68 seconds
Started Aug 29 10:54:55 AM UTC 24
Finished Aug 29 10:54:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1976143424 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.1976143424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.2337154721
Short name T586
Test name
Test status
Simulation time 262245848 ps
CPU time 0.84 seconds
Started Aug 29 10:54:55 AM UTC 24
Finished Aug 29 10:54:56 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337154721 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.2337154721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.683612337
Short name T626
Test name
Test status
Simulation time 96462452 ps
CPU time 0.59 seconds
Started Aug 29 10:55:07 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 211036 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683612337 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.683612337
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2474891369
Short name T602
Test name
Test status
Simulation time 31617885 ps
CPU time 0.5 seconds
Started Aug 29 10:55:05 AM UTC 24
Finished Aug 29 10:55:06 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2474891369 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.2474891369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.1711779157
Short name T628
Test name
Test status
Simulation time 1542667259 ps
CPU time 0.75 seconds
Started Aug 29 10:55:07 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711779157 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.1711779157
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.2081872048
Short name T625
Test name
Test status
Simulation time 81570066 ps
CPU time 0.52 seconds
Started Aug 29 10:55:07 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081872048 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.2081872048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.1649607256
Short name T621
Test name
Test status
Simulation time 43726320 ps
CPU time 0.53 seconds
Started Aug 29 10:55:07 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649607256 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1649607256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.571815492
Short name T640
Test name
Test status
Simulation time 106142241 ps
CPU time 0.58 seconds
Started Aug 29 10:55:08 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 210844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571815492 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid.571815492
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.4120727087
Short name T648
Test name
Test status
Simulation time 195418054 ps
CPU time 0.67 seconds
Started Aug 29 10:55:02 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 208132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120727087 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.4120727087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.1671015032
Short name T601
Test name
Test status
Simulation time 51270040 ps
CPU time 0.62 seconds
Started Aug 29 10:55:01 AM UTC 24
Finished Aug 29 10:55:06 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671015032 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.1671015032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.1208774128
Short name T627
Test name
Test status
Simulation time 179561602 ps
CPU time 0.71 seconds
Started Aug 29 10:55:07 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1208774128 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.1208774128
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.295931613
Short name T650
Test name
Test status
Simulation time 125693599 ps
CPU time 0.62 seconds
Started Aug 29 10:55:06 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295931613 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.295931613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3059383195
Short name T619
Test name
Test status
Simulation time 1460498239 ps
CPU time 1.58 seconds
Started Aug 29 10:55:02 AM UTC 24
Finished Aug 29 10:55:11 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059383195 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3059383195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.315378343
Short name T620
Test name
Test status
Simulation time 1100295422 ps
CPU time 2.02 seconds
Started Aug 29 10:55:03 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315378343 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.315378343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.667753103
Short name T603
Test name
Test status
Simulation time 53751473 ps
CPU time 0.77 seconds
Started Aug 29 10:55:05 AM UTC 24
Finished Aug 29 10:55:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667753103 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.667753103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.1595968493
Short name T600
Test name
Test status
Simulation time 57981737 ps
CPU time 0.55 seconds
Started Aug 29 10:55:01 AM UTC 24
Finished Aug 29 10:55:06 AM UTC 24
Peak memory 207928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595968493 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.1595968493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.3583752437
Short name T652
Test name
Test status
Simulation time 1065084010 ps
CPU time 1.67 seconds
Started Aug 29 10:55:08 AM UTC 24
Finished Aug 29 10:55:18 AM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583752437 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3583752437
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.996185967
Short name T127
Test name
Test status
Simulation time 1298004719 ps
CPU time 4.36 seconds
Started Aug 29 10:55:08 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=996185967 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr
_stress_all_with_rand_reset.996185967
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.711628223
Short name T615
Test name
Test status
Simulation time 157918371 ps
CPU time 0.9 seconds
Started Aug 29 10:55:02 AM UTC 24
Finished Aug 29 10:55:11 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=711628223 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.711628223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.4166468027
Short name T617
Test name
Test status
Simulation time 56785222 ps
CPU time 0.53 seconds
Started Aug 29 10:55:09 AM UTC 24
Finished Aug 29 10:55:11 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4166468027 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.4166468027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.2986448369
Short name T657
Test name
Test status
Simulation time 60464312 ps
CPU time 0.65 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2986448369 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.2986448369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.891128091
Short name T636
Test name
Test status
Simulation time 28839133 ps
CPU time 0.55 seconds
Started Aug 29 10:55:11 AM UTC 24
Finished Aug 29 10:55:16 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=891128091 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.891128091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.2593108895
Short name T660
Test name
Test status
Simulation time 348747338 ps
CPU time 0.75 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 208100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2593108895 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.2593108895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2697700809
Short name T656
Test name
Test status
Simulation time 58334176 ps
CPU time 0.54 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2697700809 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2697700809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.897392507
Short name T647
Test name
Test status
Simulation time 28959619 ps
CPU time 0.58 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:20 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897392507 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.897392507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.4278254512
Short name T667
Test name
Test status
Simulation time 43347808 ps
CPU time 0.6 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4278254512 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.4278254512
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.1176088629
Short name T644
Test name
Test status
Simulation time 338526099 ps
CPU time 0.8 seconds
Started Aug 29 10:55:08 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176088629 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.1176088629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.3772478712
Short name T642
Test name
Test status
Simulation time 46932605 ps
CPU time 0.66 seconds
Started Aug 29 10:55:08 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 209776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772478712 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.3772478712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.836441191
Short name T671
Test name
Test status
Simulation time 169620652 ps
CPU time 0.7 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=836441191 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.836441191
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.3600354542
Short name T659
Test name
Test status
Simulation time 126070670 ps
CPU time 0.76 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3600354542 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.3600354542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1345952112
Short name T630
Test name
Test status
Simulation time 974758867 ps
CPU time 1.75 seconds
Started Aug 29 10:55:09 AM UTC 24
Finished Aug 29 10:55:12 AM UTC 24
Peak memory 210804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1345952112 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1345952112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2138895250
Short name T633
Test name
Test status
Simulation time 881160983 ps
CPU time 2.9 seconds
Started Aug 29 10:55:10 AM UTC 24
Finished Aug 29 10:55:15 AM UTC 24
Peak memory 211320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2138895250 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2138895250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2196692248
Short name T637
Test name
Test status
Simulation time 53738651 ps
CPU time 0.77 seconds
Started Aug 29 10:55:11 AM UTC 24
Finished Aug 29 10:55:16 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196692248 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.2196692248
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.463864720
Short name T639
Test name
Test status
Simulation time 32214831 ps
CPU time 0.55 seconds
Started Aug 29 10:55:08 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=463864720 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.463864720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.169975268
Short name T692
Test name
Test status
Simulation time 1997076152 ps
CPU time 2.97 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:24 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169975268 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.169975268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.3178760842
Short name T702
Test name
Test status
Simulation time 11295566589 ps
CPU time 8.38 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:30 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3178760842 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmg
r_stress_all_with_rand_reset.3178760842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.2285326791
Short name T616
Test name
Test status
Simulation time 82904872 ps
CPU time 0.56 seconds
Started Aug 29 10:55:08 AM UTC 24
Finished Aug 29 10:55:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2285326791 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.2285326791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.3878271338
Short name T618
Test name
Test status
Simulation time 91820653 ps
CPU time 0.63 seconds
Started Aug 29 10:55:09 AM UTC 24
Finished Aug 29 10:55:11 AM UTC 24
Peak memory 211064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878271338 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.3878271338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.4290390489
Short name T638
Test name
Test status
Simulation time 42540487 ps
CPU time 0.74 seconds
Started Aug 29 10:55:14 AM UTC 24
Finished Aug 29 10:55:17 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290390489 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.4290390489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.2270902675
Short name T683
Test name
Test status
Simulation time 72806331 ps
CPU time 0.64 seconds
Started Aug 29 10:55:17 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 210284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270902675 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.2270902675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.3551333406
Short name T676
Test name
Test status
Simulation time 29617880 ps
CPU time 0.55 seconds
Started Aug 29 10:55:17 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551333406 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.3551333406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.4171119551
Short name T681
Test name
Test status
Simulation time 674941723 ps
CPU time 0.74 seconds
Started Aug 29 10:55:17 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4171119551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.4171119551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.2884514803
Short name T684
Test name
Test status
Simulation time 34220957 ps
CPU time 0.56 seconds
Started Aug 29 10:55:17 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2884514803 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.2884514803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.1141380591
Short name T679
Test name
Test status
Simulation time 102615307 ps
CPU time 0.6 seconds
Started Aug 29 10:55:17 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141380591 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1141380591
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.1266670932
Short name T662
Test name
Test status
Simulation time 68448502 ps
CPU time 0.61 seconds
Started Aug 29 10:55:18 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1266670932 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid.1266670932
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.3639490855
Short name T677
Test name
Test status
Simulation time 54491683 ps
CPU time 0.73 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3639490855 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.3639490855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.2776964218
Short name T674
Test name
Test status
Simulation time 269635105 ps
CPU time 0.71 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2776964218 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.2776964218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.2098489849
Short name T665
Test name
Test status
Simulation time 107919377 ps
CPU time 0.86 seconds
Started Aug 29 10:55:18 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098489849 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.2098489849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.1824907688
Short name T682
Test name
Test status
Simulation time 295340371 ps
CPU time 0.84 seconds
Started Aug 29 10:55:17 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824907688 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.1824907688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.667224963
Short name T653
Test name
Test status
Simulation time 778259946 ps
CPU time 2.65 seconds
Started Aug 29 10:55:14 AM UTC 24
Finished Aug 29 10:55:19 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=667224963 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.667224963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3812436145
Short name T651
Test name
Test status
Simulation time 1006683447 ps
CPU time 1.8 seconds
Started Aug 29 10:55:15 AM UTC 24
Finished Aug 29 10:55:18 AM UTC 24
Peak memory 210540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3812436145 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3812436145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.603120886
Short name T786
Test name
Test status
Simulation time 134774178 ps
CPU time 0.68 seconds
Started Aug 29 10:55:16 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603120886 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.603120886
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.510119065
Short name T666
Test name
Test status
Simulation time 123623037 ps
CPU time 0.56 seconds
Started Aug 29 10:55:13 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510119065 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.510119065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.1335996394
Short name T689
Test name
Test status
Simulation time 2588402372 ps
CPU time 2.79 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:23 AM UTC 24
Peak memory 211608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335996394 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.1335996394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.3178825237
Short name T49
Test name
Test status
Simulation time 2269260373 ps
CPU time 6.6 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:27 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3178825237 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmg
r_stress_all_with_rand_reset.3178825237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.738339875
Short name T634
Test name
Test status
Simulation time 46065591 ps
CPU time 0.61 seconds
Started Aug 29 10:55:14 AM UTC 24
Finished Aug 29 10:55:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738339875 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.738339875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.139500999
Short name T635
Test name
Test status
Simulation time 350953955 ps
CPU time 1.02 seconds
Started Aug 29 10:55:14 AM UTC 24
Finished Aug 29 10:55:16 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139500999 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.139500999
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.424087971
Short name T678
Test name
Test status
Simulation time 61961235 ps
CPU time 0.84 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424087971 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.424087971
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.2853345922
Short name T805
Test name
Test status
Simulation time 86519178 ps
CPU time 0.62 seconds
Started Aug 29 10:55:21 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853345922 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.2853345922
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.479543282
Short name T669
Test name
Test status
Simulation time 30219192 ps
CPU time 0.57 seconds
Started Aug 29 10:55:20 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=479543282 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.479543282
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.3750521958
Short name T759
Test name
Test status
Simulation time 362944683 ps
CPU time 0.72 seconds
Started Aug 29 10:55:21 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 207312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3750521958 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.3750521958
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.4128231848
Short name T801
Test name
Test status
Simulation time 45992503 ps
CPU time 0.51 seconds
Started Aug 29 10:55:21 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4128231848 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.4128231848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.284275389
Short name T802
Test name
Test status
Simulation time 65396828 ps
CPU time 0.55 seconds
Started Aug 29 10:55:21 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284275389 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.284275389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.1401169094
Short name T735
Test name
Test status
Simulation time 43796074 ps
CPU time 0.65 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:40 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1401169094 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invalid.1401169094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.3884024656
Short name T655
Test name
Test status
Simulation time 90822836 ps
CPU time 0.56 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:20 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884024656 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.3884024656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.1542094264
Short name T663
Test name
Test status
Simulation time 95933427 ps
CPU time 0.66 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1542094264 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1542094264
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.3568287552
Short name T739
Test name
Test status
Simulation time 115329274 ps
CPU time 0.81 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 219436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568287552 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.3568287552
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.462944964
Short name T760
Test name
Test status
Simulation time 256047935 ps
CPU time 0.75 seconds
Started Aug 29 10:55:21 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462944964 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.462944964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.171038398
Short name T688
Test name
Test status
Simulation time 859102616 ps
CPU time 2.16 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:23 AM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=171038398 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.171038398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2054627154
Short name T691
Test name
Test status
Simulation time 945347850 ps
CPU time 2.91 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:24 AM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054627154 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2054627154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1183490367
Short name T673
Test name
Test status
Simulation time 62200529 ps
CPU time 0.73 seconds
Started Aug 29 10:55:20 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183490367 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.1183490367
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.520536620
Short name T661
Test name
Test status
Simulation time 30691893 ps
CPU time 0.55 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=520536620 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.520536620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.3201917471
Short name T725
Test name
Test status
Simulation time 700909346 ps
CPU time 2.71 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:33 AM UTC 24
Peak memory 211360 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3201917471 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.3201917471
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.1179269884
Short name T128
Test name
Test status
Simulation time 9580658011 ps
CPU time 5.59 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:36 AM UTC 24
Peak memory 211472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1179269884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmg
r_stress_all_with_rand_reset.1179269884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.3455441949
Short name T668
Test name
Test status
Simulation time 349419822 ps
CPU time 0.83 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 207732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455441949 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.3455441949
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.1505862111
Short name T675
Test name
Test status
Simulation time 850618651 ps
CPU time 1.04 seconds
Started Aug 29 10:55:19 AM UTC 24
Finished Aug 29 10:55:22 AM UTC 24
Peak memory 210280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1505862111 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.1505862111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.1269133745
Short name T709
Test name
Test status
Simulation time 81013269 ps
CPU time 0.77 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:31 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269133745 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.1269133745
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.1410180664
Short name T722
Test name
Test status
Simulation time 63490434 ps
CPU time 0.62 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1410180664 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.1410180664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.2757711166
Short name T705
Test name
Test status
Simulation time 34708504 ps
CPU time 0.5 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:31 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757711166 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.2757711166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.3930404957
Short name T721
Test name
Test status
Simulation time 206508077 ps
CPU time 0.75 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 207620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930404957 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3930404957
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.2749099631
Short name T716
Test name
Test status
Simulation time 54819091 ps
CPU time 0.63 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 207316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2749099631 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.2749099631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.1702367388
Short name T717
Test name
Test status
Simulation time 29331181 ps
CPU time 0.55 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702367388 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.1702367388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.3390435087
Short name T751
Test name
Test status
Simulation time 71446920 ps
CPU time 0.58 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:42 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3390435087 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid.3390435087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.2353069640
Short name T710
Test name
Test status
Simulation time 153600840 ps
CPU time 0.87 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:31 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353069640 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.2353069640
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.3007154243
Short name T706
Test name
Test status
Simulation time 58364318 ps
CPU time 0.78 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:31 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007154243 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3007154243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.2996035843
Short name T755
Test name
Test status
Simulation time 179211186 ps
CPU time 0.79 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:42 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996035843 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.2996035843
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.1409609519
Short name T718
Test name
Test status
Simulation time 145796802 ps
CPU time 0.73 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1409609519 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.1409609519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.614952539
Short name T723
Test name
Test status
Simulation time 1482408065 ps
CPU time 1.97 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 210472 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614952539 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.614952539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3836653468
Short name T700
Test name
Test status
Simulation time 831111281 ps
CPU time 2.9 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:28 AM UTC 24
Peak memory 211312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3836653468 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3836653468
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2315533101
Short name T708
Test name
Test status
Simulation time 65484109 ps
CPU time 0.72 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:31 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315533101 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2315533101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.2381251847
Short name T707
Test name
Test status
Simulation time 28911005 ps
CPU time 0.65 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:31 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381251847 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.2381251847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.2565632244
Short name T845
Test name
Test status
Simulation time 2231394653 ps
CPU time 2.82 seconds
Started Aug 29 10:55:24 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 211364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565632244 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.2565632244
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.3302372405
Short name T129
Test name
Test status
Simulation time 11804015066 ps
CPU time 16.21 seconds
Started Aug 29 10:55:23 AM UTC 24
Finished Aug 29 10:55:58 AM UTC 24
Peak memory 211720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3302372405 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmg
r_stress_all_with_rand_reset.3302372405
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.1336385354
Short name T704
Test name
Test status
Simulation time 90123820 ps
CPU time 0.71 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:31 AM UTC 24
Peak memory 208052 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336385354 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.1336385354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.328374285
Short name T711
Test name
Test status
Simulation time 304006686 ps
CPU time 0.84 seconds
Started Aug 29 10:55:22 AM UTC 24
Finished Aug 29 10:55:31 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328374285 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.328374285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.2820181631
Short name T714
Test name
Test status
Simulation time 54386891 ps
CPU time 0.61 seconds
Started Aug 29 10:55:27 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820181631 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.2820181631
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.969690089
Short name T696
Test name
Test status
Simulation time 29490285 ps
CPU time 0.54 seconds
Started Aug 29 10:55:24 AM UTC 24
Finished Aug 29 10:55:26 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=969690089 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.969690089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.1684004690
Short name T713
Test name
Test status
Simulation time 64982133 ps
CPU time 0.56 seconds
Started Aug 29 10:55:26 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684004690 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.1684004690
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.744554757
Short name T715
Test name
Test status
Simulation time 53573679 ps
CPU time 0.58 seconds
Started Aug 29 10:55:27 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=744554757 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invalid.744554757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.3609298474
Short name T719
Test name
Test status
Simulation time 158019347 ps
CPU time 0.69 seconds
Started Aug 29 10:55:27 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609298474 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3609298474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.977130120
Short name T733
Test name
Test status
Simulation time 799062389 ps
CPU time 2.04 seconds
Started Aug 29 10:55:24 AM UTC 24
Finished Aug 29 10:55:38 AM UTC 24
Peak memory 211372 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=977130120 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.977130120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1441905390
Short name T699
Test name
Test status
Simulation time 1236803767 ps
CPU time 1.92 seconds
Started Aug 29 10:55:24 AM UTC 24
Finished Aug 29 10:55:27 AM UTC 24
Peak memory 210412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1441905390 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1441905390
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.378131033
Short name T695
Test name
Test status
Simulation time 315714052 ps
CPU time 0.69 seconds
Started Aug 29 10:55:24 AM UTC 24
Finished Aug 29 10:55:26 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=378131033 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.378131033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.3168746385
Short name T732
Test name
Test status
Simulation time 999959827 ps
CPU time 2.17 seconds
Started Aug 29 10:55:28 AM UTC 24
Finished Aug 29 10:55:38 AM UTC 24
Peak memory 211500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3168746385 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.3168746385
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.2389546802
Short name T731
Test name
Test status
Simulation time 1895969254 ps
CPU time 5.89 seconds
Started Aug 29 10:55:27 AM UTC 24
Finished Aug 29 10:55:37 AM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2389546802 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmg
r_stress_all_with_rand_reset.2389546802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.3902182829
Short name T698
Test name
Test status
Simulation time 209345655 ps
CPU time 0.74 seconds
Started Aug 29 10:55:24 AM UTC 24
Finished Aug 29 10:55:27 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3902182829 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.3902182829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.2127117991
Short name T758
Test name
Test status
Simulation time 125528105 ps
CPU time 0.73 seconds
Started Aug 29 10:55:31 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 210468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2127117991 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.2127117991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.916286847
Short name T741
Test name
Test status
Simulation time 55673460 ps
CPU time 0.78 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=916286847 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.916286847
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.993704614
Short name T893
Test name
Test status
Simulation time 29711735 ps
CPU time 0.58 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993704614 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.993704614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.2879878881
Short name T896
Test name
Test status
Simulation time 1828934672 ps
CPU time 0.73 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2879878881 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.2879878881
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.2634057442
Short name T892
Test name
Test status
Simulation time 64359049 ps
CPU time 0.55 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 206112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2634057442 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2634057442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.1579849411
Short name T782
Test name
Test status
Simulation time 169698338 ps
CPU time 0.6 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:55:50 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579849411 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.1579849411
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.809640650
Short name T734
Test name
Test status
Simulation time 62745148 ps
CPU time 0.58 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:55:40 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=809640650 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.809640650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.1901948234
Short name T724
Test name
Test status
Simulation time 255146544 ps
CPU time 1.04 seconds
Started Aug 29 10:55:29 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1901948234 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.1901948234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.4031484285
Short name T728
Test name
Test status
Simulation time 50950636 ps
CPU time 0.58 seconds
Started Aug 29 10:55:28 AM UTC 24
Finished Aug 29 10:55:36 AM UTC 24
Peak memory 210484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031484285 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.4031484285
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.2540001738
Short name T736
Test name
Test status
Simulation time 292536006 ps
CPU time 0.68 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:55:40 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2540001738 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.2540001738
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.3326436607
Short name T894
Test name
Test status
Simulation time 127171096 ps
CPU time 0.61 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326436607 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.3326436607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3017855605
Short name T901
Test name
Test status
Simulation time 818246187 ps
CPU time 2.53 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:56:09 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3017855605 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3017855605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3331107751
Short name T900
Test name
Test status
Simulation time 1054806924 ps
CPU time 1.92 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:56:08 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3331107751 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3331107751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.4097951413
Short name T897
Test name
Test status
Simulation time 74452629 ps
CPU time 0.86 seconds
Started Aug 29 10:55:32 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4097951413 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.4097951413
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.2585084138
Short name T727
Test name
Test status
Simulation time 58044972 ps
CPU time 0.55 seconds
Started Aug 29 10:55:28 AM UTC 24
Finished Aug 29 10:55:36 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585084138 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.2585084138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.1839069776
Short name T745
Test name
Test status
Simulation time 77771985 ps
CPU time 1.2 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839069776 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.1839069776
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.39562485
Short name T830
Test name
Test status
Simulation time 5647720036 ps
CPU time 15.9 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=39562485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl
+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_
stress_all_with_rand_reset.39562485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.886594703
Short name T720
Test name
Test status
Simulation time 78636040 ps
CPU time 0.57 seconds
Started Aug 29 10:55:30 AM UTC 24
Finished Aug 29 10:55:32 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886594703 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.886594703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.1176341599
Short name T761
Test name
Test status
Simulation time 202109350 ps
CPU time 0.75 seconds
Started Aug 29 10:55:31 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 208364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176341599 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.1176341599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.431755697
Short name T742
Test name
Test status
Simulation time 51195220 ps
CPU time 0.63 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=431755697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.431755697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.1497919490
Short name T750
Test name
Test status
Simulation time 93337697 ps
CPU time 0.59 seconds
Started Aug 29 10:55:37 AM UTC 24
Finished Aug 29 10:55:42 AM UTC 24
Peak memory 210792 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1497919490 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.1497919490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.692274586
Short name T670
Test name
Test status
Simulation time 30380096 ps
CPU time 0.54 seconds
Started Aug 29 10:55:34 AM UTC 24
Finished Aug 29 10:55:37 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=692274586 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.692274586
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.2967085201
Short name T730
Test name
Test status
Simulation time 106689119 ps
CPU time 0.76 seconds
Started Aug 29 10:55:35 AM UTC 24
Finished Aug 29 10:55:37 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2967085201 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.2967085201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.1182383601
Short name T785
Test name
Test status
Simulation time 23827227 ps
CPU time 0.51 seconds
Started Aug 29 10:55:36 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1182383601 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.1182383601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.2602297323
Short name T726
Test name
Test status
Simulation time 77698439 ps
CPU time 0.51 seconds
Started Aug 29 10:55:34 AM UTC 24
Finished Aug 29 10:55:36 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602297323 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2602297323
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.4283918959
Short name T754
Test name
Test status
Simulation time 42833663 ps
CPU time 0.72 seconds
Started Aug 29 10:55:37 AM UTC 24
Finished Aug 29 10:55:42 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283918959 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid.4283918959
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.2479131447
Short name T740
Test name
Test status
Simulation time 359959567 ps
CPU time 0.66 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2479131447 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.2479131447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.2420453355
Short name T743
Test name
Test status
Simulation time 52928899 ps
CPU time 0.84 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420453355 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.2420453355
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.3766290711
Short name T753
Test name
Test status
Simulation time 109907197 ps
CPU time 0.8 seconds
Started Aug 29 10:55:37 AM UTC 24
Finished Aug 29 10:55:42 AM UTC 24
Peak memory 219776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766290711 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.3766290711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.2649054032
Short name T729
Test name
Test status
Simulation time 200051556 ps
CPU time 0.73 seconds
Started Aug 29 10:55:34 AM UTC 24
Finished Aug 29 10:55:37 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649054032 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.2649054032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2279004751
Short name T757
Test name
Test status
Simulation time 1397162836 ps
CPU time 1.96 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:43 AM UTC 24
Peak memory 210444 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279004751 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.2279004751
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2263567057
Short name T756
Test name
Test status
Simulation time 1010708009 ps
CPU time 1.8 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:43 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263567057 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2263567057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3649405121
Short name T749
Test name
Test status
Simulation time 184413199 ps
CPU time 0.75 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:42 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649405121 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.3649405121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.2408924542
Short name T737
Test name
Test status
Simulation time 72372769 ps
CPU time 0.54 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:40 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408924542 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.2408924542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.890831657
Short name T778
Test name
Test status
Simulation time 1973881314 ps
CPU time 5.9 seconds
Started Aug 29 10:55:37 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890831657 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.890831657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.3565303388
Short name T56
Test name
Test status
Simulation time 4800200460 ps
CPU time 14.9 seconds
Started Aug 29 10:55:37 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3565303388 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmg
r_stress_all_with_rand_reset.3565303388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.1109519145
Short name T744
Test name
Test status
Simulation time 219275706 ps
CPU time 0.82 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1109519145 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.1109519145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.3336335975
Short name T738
Test name
Test status
Simulation time 51513781 ps
CPU time 0.65 seconds
Started Aug 29 10:55:33 AM UTC 24
Finished Aug 29 10:55:40 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336335975 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.3336335975
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.1525654242
Short name T768
Test name
Test status
Simulation time 90914068 ps
CPU time 0.68 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1525654242 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1525654242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.1278963257
Short name T772
Test name
Test status
Simulation time 121741898 ps
CPU time 0.6 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 210812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278963257 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.1278963257
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.2763554398
Short name T767
Test name
Test status
Simulation time 45404115 ps
CPU time 0.53 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763554398 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.2763554398
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.2462973560
Short name T774
Test name
Test status
Simulation time 719091466 ps
CPU time 0.73 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462973560 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2462973560
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.1150997352
Short name T771
Test name
Test status
Simulation time 80581137 ps
CPU time 0.59 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 206160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1150997352 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1150997352
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.2028837856
Short name T769
Test name
Test status
Simulation time 92250672 ps
CPU time 0.54 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 207828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028837856 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.2028837856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.3404949792
Short name T770
Test name
Test status
Simulation time 88293575 ps
CPU time 0.58 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3404949792 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invalid.3404949792
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.3942458748
Short name T747
Test name
Test status
Simulation time 124365264 ps
CPU time 0.68 seconds
Started Aug 29 10:55:38 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 208072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3942458748 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.3942458748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.2140269583
Short name T746
Test name
Test status
Simulation time 60552398 ps
CPU time 0.61 seconds
Started Aug 29 10:55:38 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 210896 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140269583 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.2140269583
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.2490212782
Short name T773
Test name
Test status
Simulation time 149178726 ps
CPU time 0.74 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2490212782 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.2490212782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.1131721856
Short name T776
Test name
Test status
Simulation time 242863034 ps
CPU time 0.86 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1131721856 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.1131721856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1730135709
Short name T781
Test name
Test status
Simulation time 860761370 ps
CPU time 2.95 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:49 AM UTC 24
Peak memory 210808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730135709 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1730135709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2804309829
Short name T780
Test name
Test status
Simulation time 863676358 ps
CPU time 2.93 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:49 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804309829 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2804309829
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1483283270
Short name T817
Test name
Test status
Simulation time 113385032 ps
CPU time 0.91 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:54 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1483283270 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1483283270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.4006964139
Short name T752
Test name
Test status
Simulation time 41633339 ps
CPU time 0.64 seconds
Started Aug 29 10:55:37 AM UTC 24
Finished Aug 29 10:55:42 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006964139 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.4006964139
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.470288605
Short name T848
Test name
Test status
Simulation time 981088890 ps
CPU time 3.38 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:57 AM UTC 24
Peak memory 211484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470288605 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.470288605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.3955135848
Short name T898
Test name
Test status
Simulation time 7221437940 ps
CPU time 14.49 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:56:08 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3955135848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmg
r_stress_all_with_rand_reset.3955135848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.2238995185
Short name T748
Test name
Test status
Simulation time 57844853 ps
CPU time 0.64 seconds
Started Aug 29 10:55:39 AM UTC 24
Finished Aug 29 10:55:41 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2238995185 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.2238995185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.164198484
Short name T775
Test name
Test status
Simulation time 204996292 ps
CPU time 1.12 seconds
Started Aug 29 10:55:42 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 210796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=164198484 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.164198484
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_aborted_low_power.1994782918
Short name T119
Test name
Test status
Simulation time 46382201 ps
CPU time 1.4 seconds
Started Aug 29 10:53:01 AM UTC 24
Finished Aug 29 10:53:04 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994782918 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_aborted_low_power.1994782918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3271879265
Short name T148
Test name
Test status
Simulation time 73511978 ps
CPU time 1.01 seconds
Started Aug 29 10:53:04 AM UTC 24
Finished Aug 29 10:53:06 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271879265 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.3271879265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_esc_clk_rst_malfunc.3877026186
Short name T145
Test name
Test status
Simulation time 30199981 ps
CPU time 0.97 seconds
Started Aug 29 10:53:02 AM UTC 24
Finished Aug 29 10:53:05 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3877026186 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_esc_clk_rst_malfunc.3877026186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3773384462
Short name T143
Test name
Test status
Simulation time 109034326 ps
CPU time 1.51 seconds
Started Aug 29 10:53:04 AM UTC 24
Finished Aug 29 10:53:07 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3773384462 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3773384462
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.548173
Short name T189
Test name
Test status
Simulation time 85500063 ps
CPU time 0.95 seconds
Started Aug 29 10:53:04 AM UTC 24
Finished Aug 29 10:53:06 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548173 -assert nopostproc +UVM_TESTNAME=pwrmgr_b
ase_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.548173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.754392746
Short name T188
Test name
Test status
Simulation time 58575304 ps
CPU time 0.95 seconds
Started Aug 29 10:53:04 AM UTC 24
Finished Aug 29 10:53:06 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754392746 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.754392746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.3170834873
Short name T192
Test name
Test status
Simulation time 54517809 ps
CPU time 1.02 seconds
Started Aug 29 10:53:05 AM UTC 24
Finished Aug 29 10:53:07 AM UTC 24
Peak memory 210732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3170834873 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.3170834873
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.3026464808
Short name T184
Test name
Test status
Simulation time 276792865 ps
CPU time 1.12 seconds
Started Aug 29 10:53:01 AM UTC 24
Finished Aug 29 10:53:03 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026464808 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.3026464808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.2809125207
Short name T183
Test name
Test status
Simulation time 71752279 ps
CPU time 0.94 seconds
Started Aug 29 10:53:00 AM UTC 24
Finished Aug 29 10:53:02 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2809125207 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.2809125207
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.2546804222
Short name T191
Test name
Test status
Simulation time 111334257 ps
CPU time 1.46 seconds
Started Aug 29 10:53:04 AM UTC 24
Finished Aug 29 10:53:07 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546804222 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.2546804222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.3694191047
Short name T31
Test name
Test status
Simulation time 328917932 ps
CPU time 2.65 seconds
Started Aug 29 10:53:05 AM UTC 24
Finished Aug 29 10:53:09 AM UTC 24
Peak memory 238820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694191047 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.3694191047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_ctrl_config_regwen.896059166
Short name T190
Test name
Test status
Simulation time 57247718 ps
CPU time 1.29 seconds
Started Aug 29 10:53:04 AM UTC 24
Finished Aug 29 10:53:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=896059166 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_ctrl_config_regwen.896059166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3935166685
Short name T153
Test name
Test status
Simulation time 941682191 ps
CPU time 4.26 seconds
Started Aug 29 10:53:02 AM UTC 24
Finished Aug 29 10:53:08 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3935166685 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3935166685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.330476685
Short name T194
Test name
Test status
Simulation time 785905376 ps
CPU time 3.94 seconds
Started Aug 29 10:53:02 AM UTC 24
Finished Aug 29 10:53:08 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330476685 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rom_ctrl_inters
ig_mubi.330476685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3192260379
Short name T187
Test name
Test status
Simulation time 63993411 ps
CPU time 1.43 seconds
Started Aug 29 10:53:02 AM UTC 24
Finished Aug 29 10:53:05 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3192260379 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm_rstmgr_intersig_mubi.3192260379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.218693806
Short name T182
Test name
Test status
Simulation time 114340472 ps
CPU time 0.94 seconds
Started Aug 29 10:53:00 AM UTC 24
Finished Aug 29 10:53:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218693806 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.218693806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.395753652
Short name T209
Test name
Test status
Simulation time 1937783605 ps
CPU time 7.54 seconds
Started Aug 29 10:53:05 AM UTC 24
Finished Aug 29 10:53:14 AM UTC 24
Peak memory 211380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=395753652 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.395753652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.2553893185
Short name T75
Test name
Test status
Simulation time 4934766565 ps
CPU time 17.64 seconds
Started Aug 29 10:53:05 AM UTC 24
Finished Aug 29 10:53:24 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2553893185 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr
_stress_all_with_rand_reset.2553893185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.2689046406
Short name T185
Test name
Test status
Simulation time 35637231 ps
CPU time 1.04 seconds
Started Aug 29 10:53:01 AM UTC 24
Finished Aug 29 10:53:03 AM UTC 24
Peak memory 207880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689046406 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.2689046406
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup_reset.2977704213
Short name T186
Test name
Test status
Simulation time 292675193 ps
CPU time 2.29 seconds
Started Aug 29 10:53:01 AM UTC 24
Finished Aug 29 10:53:04 AM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977704213 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup_reset.2977704213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/4.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.1397118675
Short name T763
Test name
Test status
Simulation time 61941814 ps
CPU time 0.58 seconds
Started Aug 29 10:55:43 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397118675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.1397118675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.3370596657
Short name T798
Test name
Test status
Simulation time 63632297 ps
CPU time 0.75 seconds
Started Aug 29 10:55:47 AM UTC 24
Finished Aug 29 10:55:52 AM UTC 24
Peak memory 211096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3370596657 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.3370596657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.1721938268
Short name T792
Test name
Test status
Simulation time 30388306 ps
CPU time 0.59 seconds
Started Aug 29 10:55:46 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 205892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1721938268 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.1721938268
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.2977737216
Short name T797
Test name
Test status
Simulation time 407473054 ps
CPU time 0.75 seconds
Started Aug 29 10:55:47 AM UTC 24
Finished Aug 29 10:55:52 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2977737216 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.2977737216
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.2148029800
Short name T793
Test name
Test status
Simulation time 30292381 ps
CPU time 0.54 seconds
Started Aug 29 10:55:47 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148029800 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.2148029800
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.63250962
Short name T791
Test name
Test status
Simulation time 62183332 ps
CPU time 0.55 seconds
Started Aug 29 10:55:47 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63250962 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.63250962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.3146576213
Short name T795
Test name
Test status
Simulation time 48473346 ps
CPU time 0.58 seconds
Started Aug 29 10:55:47 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146576213 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid.3146576213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.640680697
Short name T762
Test name
Test status
Simulation time 437684781 ps
CPU time 0.78 seconds
Started Aug 29 10:55:43 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=640680697 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.640680697
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.3903669629
Short name T800
Test name
Test status
Simulation time 102519053 ps
CPU time 0.9 seconds
Started Aug 29 10:55:43 AM UTC 24
Finished Aug 29 10:55:52 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3903669629 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.3903669629
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.1206409911
Short name T796
Test name
Test status
Simulation time 95116269 ps
CPU time 0.81 seconds
Started Aug 29 10:55:47 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206409911 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.1206409911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.2430311343
Short name T794
Test name
Test status
Simulation time 295673758 ps
CPU time 0.68 seconds
Started Aug 29 10:55:47 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 207924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2430311343 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.2430311343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1674594990
Short name T779
Test name
Test status
Simulation time 844616684 ps
CPU time 2.71 seconds
Started Aug 29 10:55:43 AM UTC 24
Finished Aug 29 10:55:48 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674594990 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1674594990
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3036738221
Short name T777
Test name
Test status
Simulation time 1012275706 ps
CPU time 1.81 seconds
Started Aug 29 10:55:43 AM UTC 24
Finished Aug 29 10:55:47 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3036738221 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3036738221
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1686246135
Short name T766
Test name
Test status
Simulation time 200820755 ps
CPU time 0.74 seconds
Started Aug 29 10:55:44 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686246135 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.1686246135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.3975554378
Short name T799
Test name
Test status
Simulation time 46044158 ps
CPU time 0.59 seconds
Started Aug 29 10:55:43 AM UTC 24
Finished Aug 29 10:55:52 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3975554378 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.3975554378
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.1509933618
Short name T712
Test name
Test status
Simulation time 456957414 ps
CPU time 0.81 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1509933618 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.1509933618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.637611880
Short name T130
Test name
Test status
Simulation time 3144671510 ps
CPU time 10.15 seconds
Started Aug 29 10:55:47 AM UTC 24
Finished Aug 29 10:56:01 AM UTC 24
Peak memory 211476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=637611880 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr
_stress_all_with_rand_reset.637611880
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.1656076233
Short name T764
Test name
Test status
Simulation time 303673256 ps
CPU time 0.83 seconds
Started Aug 29 10:55:43 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656076233 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.1656076233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.4062428155
Short name T765
Test name
Test status
Simulation time 95956480 ps
CPU time 0.73 seconds
Started Aug 29 10:55:43 AM UTC 24
Finished Aug 29 10:55:46 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4062428155 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.4062428155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.3203354994
Short name T806
Test name
Test status
Simulation time 33327953 ps
CPU time 0.7 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3203354994 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.3203354994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.4132227877
Short name T788
Test name
Test status
Simulation time 54567631 ps
CPU time 0.67 seconds
Started Aug 29 10:55:49 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4132227877 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.4132227877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.3944825908
Short name T807
Test name
Test status
Simulation time 32497300 ps
CPU time 0.53 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944825908 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.3944825908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.2953424760
Short name T789
Test name
Test status
Simulation time 109545227 ps
CPU time 0.73 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953424760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.2953424760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.2672089652
Short name T787
Test name
Test status
Simulation time 57337111 ps
CPU time 0.62 seconds
Started Aug 29 10:55:49 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 205888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672089652 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.2672089652
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.2309625374
Short name T784
Test name
Test status
Simulation time 39636694 ps
CPU time 0.51 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309625374 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.2309625374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.664113614
Short name T809
Test name
Test status
Simulation time 179371651 ps
CPU time 0.64 seconds
Started Aug 29 10:55:51 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664113614 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invalid.664113614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.3588153200
Short name T664
Test name
Test status
Simulation time 637044181 ps
CPU time 0.74 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588153200 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.3588153200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.1816263057
Short name T783
Test name
Test status
Simulation time 111651071 ps
CPU time 0.69 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1816263057 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.1816263057
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.581567593
Short name T790
Test name
Test status
Simulation time 116680117 ps
CPU time 0.79 seconds
Started Aug 29 10:55:49 AM UTC 24
Finished Aug 29 10:55:51 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=581567593 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.581567593
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.1380916130
Short name T815
Test name
Test status
Simulation time 250981907 ps
CPU time 1.13 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380916130 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.1380916130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3340919562
Short name T818
Test name
Test status
Simulation time 1175071569 ps
CPU time 1.76 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:54 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3340919562 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3340919562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2873907717
Short name T819
Test name
Test status
Simulation time 798740969 ps
CPU time 2.81 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:55 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873907717 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2873907717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3301421420
Short name T808
Test name
Test status
Simulation time 53396008 ps
CPU time 0.84 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301421420 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3301421420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.1776696050
Short name T803
Test name
Test status
Simulation time 59510714 ps
CPU time 0.56 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776696050 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.1776696050
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.3768750855
Short name T839
Test name
Test status
Simulation time 4337750304 ps
CPU time 3.52 seconds
Started Aug 29 10:55:51 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 211588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768750855 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.3768750855
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.1034068287
Short name T855
Test name
Test status
Simulation time 2762319252 ps
CPU time 6.34 seconds
Started Aug 29 10:55:51 AM UTC 24
Finished Aug 29 10:55:59 AM UTC 24
Peak memory 211576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=1034068287 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmg
r_stress_all_with_rand_reset.1034068287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.2475060032
Short name T804
Test name
Test status
Simulation time 50072765 ps
CPU time 0.59 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475060032 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.2475060032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.2334392655
Short name T812
Test name
Test status
Simulation time 301564381 ps
CPU time 1.13 seconds
Started Aug 29 10:55:48 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334392655 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.2334392655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.2147209246
Short name T820
Test name
Test status
Simulation time 102559473 ps
CPU time 0.73 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:55 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2147209246 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.2147209246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.2925309051
Short name T828
Test name
Test status
Simulation time 95717308 ps
CPU time 0.73 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925309051 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.2925309051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.1700766495
Short name T824
Test name
Test status
Simulation time 29419991 ps
CPU time 0.66 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1700766495 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.1700766495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.3230202834
Short name T826
Test name
Test status
Simulation time 114517189 ps
CPU time 0.8 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230202834 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.3230202834
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.911143131
Short name T821
Test name
Test status
Simulation time 123582921 ps
CPU time 0.59 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:55 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=911143131 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.911143131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.1884500430
Short name T823
Test name
Test status
Simulation time 93497508 ps
CPU time 0.57 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884500430 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1884500430
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.3439835453
Short name T888
Test name
Test status
Simulation time 150595517 ps
CPU time 0.58 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3439835453 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid.3439835453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.3956858014
Short name T816
Test name
Test status
Simulation time 192223661 ps
CPU time 0.99 seconds
Started Aug 29 10:55:52 AM UTC 24
Finished Aug 29 10:55:54 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956858014 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.3956858014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.1775185339
Short name T810
Test name
Test status
Simulation time 107480496 ps
CPU time 0.74 seconds
Started Aug 29 10:55:51 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775185339 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.1775185339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.539071841
Short name T849
Test name
Test status
Simulation time 93813209 ps
CPU time 0.82 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:57 AM UTC 24
Peak memory 220184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=539071841 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.539071841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.2005990790
Short name T838
Test name
Test status
Simulation time 202879161 ps
CPU time 1.25 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2005990790 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.2005990790
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1522875797
Short name T850
Test name
Test status
Simulation time 1385606451 ps
CPU time 2.16 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:57 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1522875797 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1522875797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3851163617
Short name T853
Test name
Test status
Simulation time 1081540734 ps
CPU time 2.56 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:57 AM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3851163617 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3851163617
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.776444546
Short name T827
Test name
Test status
Simulation time 76025006 ps
CPU time 0.86 seconds
Started Aug 29 10:55:53 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 207648 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=776444546 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.776444546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.3586244830
Short name T811
Test name
Test status
Simulation time 71488891 ps
CPU time 0.64 seconds
Started Aug 29 10:55:51 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586244830 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.3586244830
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.2120877888
Short name T854
Test name
Test status
Simulation time 930173646 ps
CPU time 2.63 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:59 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2120877888 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.2120877888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.3742546730
Short name T871
Test name
Test status
Simulation time 4409674034 ps
CPU time 8.13 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:56:03 AM UTC 24
Peak memory 211720 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3742546730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmg
r_stress_all_with_rand_reset.3742546730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2980325621
Short name T814
Test name
Test status
Simulation time 145819513 ps
CPU time 0.87 seconds
Started Aug 29 10:55:52 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2980325621 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.2980325621
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.1791220144
Short name T813
Test name
Test status
Simulation time 69794123 ps
CPU time 0.74 seconds
Started Aug 29 10:55:52 AM UTC 24
Finished Aug 29 10:55:53 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1791220144 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.1791220144
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.1473135456
Short name T833
Test name
Test status
Simulation time 33093704 ps
CPU time 0.71 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1473135456 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.1473135456
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.980997195
Short name T842
Test name
Test status
Simulation time 73662084 ps
CPU time 0.62 seconds
Started Aug 29 10:55:55 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=980997195 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.980997195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.4073399318
Short name T831
Test name
Test status
Simulation time 31039802 ps
CPU time 0.61 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4073399318 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.4073399318
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.2609207821
Short name T846
Test name
Test status
Simulation time 111918545 ps
CPU time 0.88 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2609207821 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.2609207821
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.2937283286
Short name T840
Test name
Test status
Simulation time 71371327 ps
CPU time 0.6 seconds
Started Aug 29 10:55:55 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937283286 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.2937283286
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.334090672
Short name T837
Test name
Test status
Simulation time 49982046 ps
CPU time 0.57 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334090672 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.334090672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.505885942
Short name T904
Test name
Test status
Simulation time 46067080 ps
CPU time 0.68 seconds
Started Aug 29 10:55:56 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 209744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505885942 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid.505885942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.141008711
Short name T832
Test name
Test status
Simulation time 209294883 ps
CPU time 0.77 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=141008711 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.141008711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.2379677778
Short name T835
Test name
Test status
Simulation time 148041653 ps
CPU time 0.77 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2379677778 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.2379677778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.3915717496
Short name T910
Test name
Test status
Simulation time 105406726 ps
CPU time 1.02 seconds
Started Aug 29 10:55:56 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 220192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3915717496 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3915717496
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.1769363386
Short name T844
Test name
Test status
Simulation time 190125628 ps
CPU time 0.73 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1769363386 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.1769363386
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4191109354
Short name T851
Test name
Test status
Simulation time 1018174295 ps
CPU time 1.84 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:57 AM UTC 24
Peak memory 210408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191109354 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4191109354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3609615729
Short name T852
Test name
Test status
Simulation time 1029571488 ps
CPU time 1.85 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:57 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3609615729 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3609615729
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3184196269
Short name T843
Test name
Test status
Simulation time 117469483 ps
CPU time 0.88 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184196269 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.3184196269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.3711175009
Short name T829
Test name
Test status
Simulation time 82935075 ps
CPU time 0.63 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711175009 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3711175009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.2919902556
Short name T927
Test name
Test status
Simulation time 1987988353 ps
CPU time 2.59 seconds
Started Aug 29 10:55:56 AM UTC 24
Finished Aug 29 10:56:13 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2919902556 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.2919902556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.3083008730
Short name T952
Test name
Test status
Simulation time 4633771713 ps
CPU time 11.61 seconds
Started Aug 29 10:55:56 AM UTC 24
Finished Aug 29 10:56:22 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3083008730 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmg
r_stress_all_with_rand_reset.3083008730
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.2076065012
Short name T841
Test name
Test status
Simulation time 343295698 ps
CPU time 1.01 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2076065012 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.2076065012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.745094210
Short name T847
Test name
Test status
Simulation time 325172207 ps
CPU time 1 seconds
Started Aug 29 10:55:54 AM UTC 24
Finished Aug 29 10:55:56 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745094210 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.745094210
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3723759174
Short name T868
Test name
Test status
Simulation time 47887956 ps
CPU time 0.84 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723759174 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.3723759174
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.2051911480
Short name T834
Test name
Test status
Simulation time 61011295 ps
CPU time 0.63 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:05 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2051911480 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.2051911480
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.295825375
Short name T866
Test name
Test status
Simulation time 40988110 ps
CPU time 0.54 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=295825375 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.295825375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.2097954606
Short name T928
Test name
Test status
Simulation time 402384447 ps
CPU time 0.75 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:13 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097954606 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2097954606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.2135871477
Short name T822
Test name
Test status
Simulation time 38326452 ps
CPU time 0.63 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:05 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2135871477 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2135871477
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.4111610960
Short name T924
Test name
Test status
Simulation time 281094788 ps
CPU time 0.52 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:12 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111610960 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.4111610960
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.3578935698
Short name T703
Test name
Test status
Simulation time 40295811 ps
CPU time 0.65 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:05 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578935698 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invalid.3578935698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.1009930797
Short name T867
Test name
Test status
Simulation time 277399855 ps
CPU time 0.78 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009930797 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.1009930797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.328128566
Short name T865
Test name
Test status
Simulation time 23966766 ps
CPU time 0.6 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328128566 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.328128566
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.123746698
Short name T863
Test name
Test status
Simulation time 166760811 ps
CPU time 0.68 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:05 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123746698 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.123746698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3324269964
Short name T931
Test name
Test status
Simulation time 153066479 ps
CPU time 1.02 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:13 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324269964 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.3324269964
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4005933302
Short name T874
Test name
Test status
Simulation time 858597268 ps
CPU time 3.07 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:05 AM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4005933302 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.4005933302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3563109911
Short name T872
Test name
Test status
Simulation time 3551146752 ps
CPU time 1.81 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:03 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563109911 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.3563109911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1857036807
Short name T926
Test name
Test status
Simulation time 194792659 ps
CPU time 0.72 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:13 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1857036807 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.1857036807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.413163074
Short name T862
Test name
Test status
Simulation time 46243743 ps
CPU time 0.53 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=413163074 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.413163074
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.3551669250
Short name T672
Test name
Test status
Simulation time 58424890 ps
CPU time 0.72 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551669250 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.3551669250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.2683420696
Short name T131
Test name
Test status
Simulation time 3198343946 ps
CPU time 6.36 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 211460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2683420696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmg
r_stress_all_with_rand_reset.2683420696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.2828797350
Short name T869
Test name
Test status
Simulation time 268958931 ps
CPU time 1 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2828797350 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.2828797350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.1767834282
Short name T870
Test name
Test status
Simulation time 436280281 ps
CPU time 1.04 seconds
Started Aug 29 10:55:57 AM UTC 24
Finished Aug 29 10:56:03 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767834282 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.1767834282
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.3561205481
Short name T878
Test name
Test status
Simulation time 90973364 ps
CPU time 0.64 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3561205481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.3561205481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.1951780901
Short name T864
Test name
Test status
Simulation time 71474750 ps
CPU time 0.59 seconds
Started Aug 29 10:56:00 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1951780901 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.1951780901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2511192638
Short name T858
Test name
Test status
Simulation time 28924616 ps
CPU time 0.54 seconds
Started Aug 29 10:55:59 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2511192638 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.2511192638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.3689946699
Short name T857
Test name
Test status
Simulation time 120781796 ps
CPU time 0.77 seconds
Started Aug 29 10:55:59 AM UTC 24
Finished Aug 29 10:56:01 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3689946699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.3689946699
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.459887870
Short name T856
Test name
Test status
Simulation time 29539509 ps
CPU time 0.53 seconds
Started Aug 29 10:55:59 AM UTC 24
Finished Aug 29 10:56:01 AM UTC 24
Peak memory 206208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=459887870 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.459887870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.447751871
Short name T859
Test name
Test status
Simulation time 171628008 ps
CPU time 0.55 seconds
Started Aug 29 10:55:59 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447751871 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.447751871
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.2268132185
Short name T880
Test name
Test status
Simulation time 286470235 ps
CPU time 0.55 seconds
Started Aug 29 10:56:01 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268132185 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invalid.2268132185
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.1008938856
Short name T641
Test name
Test status
Simulation time 141745204 ps
CPU time 0.64 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1008938856 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_wakeup_race.1008938856
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.2940859622
Short name T877
Test name
Test status
Simulation time 93879254 ps
CPU time 0.77 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940859622 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.2940859622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.2661774743
Short name T881
Test name
Test status
Simulation time 124302037 ps
CPU time 0.72 seconds
Started Aug 29 10:56:01 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 219868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661774743 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.2661774743
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.31169253
Short name T861
Test name
Test status
Simulation time 163152527 ps
CPU time 0.7 seconds
Started Aug 29 10:55:59 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 207820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31169253 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.31169253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1968027455
Short name T899
Test name
Test status
Simulation time 779300331 ps
CPU time 2.77 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:08 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968027455 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.1968027455
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2275016634
Short name T873
Test name
Test status
Simulation time 837076917 ps
CPU time 2.69 seconds
Started Aug 29 10:55:59 AM UTC 24
Finished Aug 29 10:56:04 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2275016634 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.2275016634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3095017838
Short name T860
Test name
Test status
Simulation time 53827563 ps
CPU time 0.76 seconds
Started Aug 29 10:55:59 AM UTC 24
Finished Aug 29 10:56:02 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3095017838 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.3095017838
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.3346406933
Short name T825
Test name
Test status
Simulation time 25507348 ps
CPU time 0.59 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346406933 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.3346406933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.3673217373
Short name T922
Test name
Test status
Simulation time 1032556163 ps
CPU time 1.64 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:12 AM UTC 24
Peak memory 209664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673217373 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.3673217373
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.2173381848
Short name T951
Test name
Test status
Simulation time 7842153801 ps
CPU time 11.07 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:21 AM UTC 24
Peak memory 211656 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2173381848 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmg
r_stress_all_with_rand_reset.2173381848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.1253537000
Short name T875
Test name
Test status
Simulation time 111528436 ps
CPU time 0.71 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253537000 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.1253537000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.3930910756
Short name T879
Test name
Test status
Simulation time 298274497 ps
CPU time 0.82 seconds
Started Aug 29 10:55:58 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 210972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930910756 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.3930910756
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/45.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.944526123
Short name T907
Test name
Test status
Simulation time 28443310 ps
CPU time 0.81 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 210924 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944526123 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.944526123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.1760030546
Short name T891
Test name
Test status
Simulation time 63266082 ps
CPU time 0.78 seconds
Started Aug 29 10:56:05 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1760030546 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.1760030546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.949358233
Short name T882
Test name
Test status
Simulation time 47097313 ps
CPU time 0.52 seconds
Started Aug 29 10:56:04 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949358233 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.949358233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.1063671691
Short name T887
Test name
Test status
Simulation time 396533174 ps
CPU time 0.71 seconds
Started Aug 29 10:56:04 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1063671691 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.1063671691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.2673461519
Short name T885
Test name
Test status
Simulation time 58878855 ps
CPU time 0.56 seconds
Started Aug 29 10:56:05 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673461519 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.2673461519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.2523940359
Short name T883
Test name
Test status
Simulation time 207074702 ps
CPU time 0.55 seconds
Started Aug 29 10:56:04 AM UTC 24
Finished Aug 29 10:56:06 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523940359 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.2523940359
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.1922630372
Short name T909
Test name
Test status
Simulation time 41136648 ps
CPU time 0.61 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 210920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922630372 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid.1922630372
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.2802189569
Short name T906
Test name
Test status
Simulation time 317229999 ps
CPU time 0.79 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2802189569 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.2802189569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.4154283489
Short name T905
Test name
Test status
Simulation time 62434602 ps
CPU time 0.68 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4154283489 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.4154283489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.975711615
Short name T912
Test name
Test status
Simulation time 290077935 ps
CPU time 0.67 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=975711615 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.975711615
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1796493497
Short name T886
Test name
Test status
Simulation time 368655828 ps
CPU time 0.82 seconds
Started Aug 29 10:56:04 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796493497 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.1796493497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3680939772
Short name T925
Test name
Test status
Simulation time 1006044065 ps
CPU time 2.2 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:12 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3680939772 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_inters
ig_mubi.3680939772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.384731208
Short name T933
Test name
Test status
Simulation time 812305743 ps
CPU time 2.88 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:13 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384731208 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.384731208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.197777760
Short name T884
Test name
Test status
Simulation time 146470155 ps
CPU time 0.73 seconds
Started Aug 29 10:56:04 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=197777760 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.197777760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.2195606754
Short name T903
Test name
Test status
Simulation time 63158151 ps
CPU time 0.58 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2195606754 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.2195606754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.139280453
Short name T917
Test name
Test status
Simulation time 407927894 ps
CPU time 0.77 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=139280453 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.139280453
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.3506509687
Short name T949
Test name
Test status
Simulation time 4589455141 ps
CPU time 6.52 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 211496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=3506509687 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmg
r_stress_all_with_rand_reset.3506509687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.1369197899
Short name T902
Test name
Test status
Simulation time 33790564 ps
CPU time 0.57 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369197899 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.1369197899
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.569085451
Short name T895
Test name
Test status
Simulation time 66090270 ps
CPU time 0.53 seconds
Started Aug 29 10:56:03 AM UTC 24
Finished Aug 29 10:56:07 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569085451 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.569085451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/46.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.3529945169
Short name T919
Test name
Test status
Simulation time 26747316 ps
CPU time 0.62 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529945169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.3529945169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.937666823
Short name T941
Test name
Test status
Simulation time 47048381 ps
CPU time 0.69 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 211100 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937666823 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.937666823
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.961475252
Short name T934
Test name
Test status
Simulation time 31408525 ps
CPU time 0.52 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:15 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=961475252 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.961475252
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.1845234568
Short name T938
Test name
Test status
Simulation time 203261851 ps
CPU time 0.78 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1845234568 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.1845234568
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.2944571217
Short name T942
Test name
Test status
Simulation time 23404956 ps
CPU time 0.61 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944571217 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.2944571217
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.1189764550
Short name T936
Test name
Test status
Simulation time 48158377 ps
CPU time 0.54 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189764550 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.1189764550
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.1805807077
Short name T945
Test name
Test status
Simulation time 43947179 ps
CPU time 0.65 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805807077 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invalid.1805807077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.2194109196
Short name T920
Test name
Test status
Simulation time 638666038 ps
CPU time 0.78 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2194109196 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wakeup_race.2194109196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.181354919
Short name T921
Test name
Test status
Simulation time 67803734 ps
CPU time 0.79 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181354919 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.181354919
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.700371481
Short name T946
Test name
Test status
Simulation time 94598527 ps
CPU time 0.98 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 219172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700371481 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.700371481
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.1592493224
Short name T937
Test name
Test status
Simulation time 107169470 ps
CPU time 0.64 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 209772 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592493224 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.1592493224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.700065624
Short name T929
Test name
Test status
Simulation time 1368274568 ps
CPU time 2.04 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:13 AM UTC 24
Peak memory 211508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700065624 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.700065624
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1095387464
Short name T932
Test name
Test status
Simulation time 912425801 ps
CPU time 2.31 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:13 AM UTC 24
Peak memory 211516 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095387464 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_inte
rsig_mubi.1095387464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.492350686
Short name T935
Test name
Test status
Simulation time 65076286 ps
CPU time 0.78 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492350686 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.492350686
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.95932325
Short name T914
Test name
Test status
Simulation time 33373503 ps
CPU time 0.66 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95932325 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.95932325
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.3178192746
Short name T948
Test name
Test status
Simulation time 156810463 ps
CPU time 0.71 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3178192746 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.3178192746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.2468739614
Short name T954
Test name
Test status
Simulation time 4120669334 ps
CPU time 13.19 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:29 AM UTC 24
Peak memory 211456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2468739614 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmg
r_stress_all_with_rand_reset.2468739614
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.749183646
Short name T915
Test name
Test status
Simulation time 87746074 ps
CPU time 0.63 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=749183646 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.749183646
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.2171510807
Short name T923
Test name
Test status
Simulation time 313289417 ps
CPU time 1.29 seconds
Started Aug 29 10:56:06 AM UTC 24
Finished Aug 29 10:56:12 AM UTC 24
Peak memory 210424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171510807 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.2171510807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.988626292
Short name T939
Test name
Test status
Simulation time 37813629 ps
CPU time 0.71 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988626292 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-
vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.988626292
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.2134083767
Short name T916
Test name
Test status
Simulation time 93529571 ps
CPU time 0.66 seconds
Started Aug 29 10:56:09 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134083767 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.2134083767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.3937462253
Short name T918
Test name
Test status
Simulation time 205722136 ps
CPU time 0.76 seconds
Started Aug 29 10:56:09 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937462253 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.3937462253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.3518155038
Short name T913
Test name
Test status
Simulation time 59994103 ps
CPU time 0.52 seconds
Started Aug 29 10:56:09 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518155038 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.3518155038
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.970805465
Short name T911
Test name
Test status
Simulation time 48523078 ps
CPU time 0.49 seconds
Started Aug 29 10:56:09 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=970805465 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.970805465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.257687698
Short name T876
Test name
Test status
Simulation time 181354303 ps
CPU time 1.01 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257687698 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.257687698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.2181223952
Short name T943
Test name
Test status
Simulation time 107991389 ps
CPU time 0.7 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181223952 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.2181223952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.3218069569
Short name T930
Test name
Test status
Simulation time 103021598 ps
CPU time 0.94 seconds
Started Aug 29 10:56:10 AM UTC 24
Finished Aug 29 10:56:13 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3218069569 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.3218069569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.733145490
Short name T908
Test name
Test status
Simulation time 135744455 ps
CPU time 0.61 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:11 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733145490 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.733145490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.259972375
Short name T944
Test name
Test status
Simulation time 56850950 ps
CPU time 0.58 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259972375 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.259972375
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.2140408069
Short name T889
Test name
Test status
Simulation time 278139056 ps
CPU time 0.84 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2140408069 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.2140408069
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.2942546234
Short name T947
Test name
Test status
Simulation time 75237984 ps
CPU time 0.74 seconds
Started Aug 29 10:56:08 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942546234 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.2942546234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/48.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.2226805557
Short name T890
Test name
Test status
Simulation time 52771697 ps
CPU time 0.63 seconds
Started Aug 29 10:56:13 AM UTC 24
Finished Aug 29 10:56:16 AM UTC 24
Peak memory 210800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2226805557 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invalid.2226805557
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/49.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.1790472103
Short name T940
Test name
Test status
Simulation time 110714893 ps
CPU time 0.96 seconds
Started Aug 29 10:56:13 AM UTC 24
Finished Aug 29 10:56:17 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1790472103 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1790472103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/49.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.3058267023
Short name T950
Test name
Test status
Simulation time 702846494 ps
CPU time 2.09 seconds
Started Aug 29 10:56:13 AM UTC 24
Finished Aug 29 10:56:18 AM UTC 24
Peak memory 211424 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3058267023 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.3058267023
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.2849419490
Short name T953
Test name
Test status
Simulation time 24454027473 ps
CPU time 12.25 seconds
Started Aug 29 10:56:13 AM UTC 24
Finished Aug 29 10:56:28 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2849419490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmg
r_stress_all_with_rand_reset.2849419490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2400083720
Short name T120
Test name
Test status
Simulation time 58306935 ps
CPU time 0.94 seconds
Started Aug 29 10:53:08 AM UTC 24
Finished Aug 29 10:53:10 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400083720 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2400083720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.2666572270
Short name T149
Test name
Test status
Simulation time 48690196 ps
CPU time 1.26 seconds
Started Aug 29 10:53:09 AM UTC 24
Finished Aug 29 10:53:12 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2666572270 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.2666572270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.3110224627
Short name T201
Test name
Test status
Simulation time 29946273 ps
CPU time 0.98 seconds
Started Aug 29 10:53:08 AM UTC 24
Finished Aug 29 10:53:11 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110224627 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.3110224627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3731482392
Short name T144
Test name
Test status
Simulation time 115361539 ps
CPU time 1.56 seconds
Started Aug 29 10:53:09 AM UTC 24
Finished Aug 29 10:53:12 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731482392 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.3731482392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.4111271676
Short name T203
Test name
Test status
Simulation time 70111027 ps
CPU time 0.9 seconds
Started Aug 29 10:53:09 AM UTC 24
Finished Aug 29 10:53:11 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4111271676 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.4111271676
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.96381519
Short name T204
Test name
Test status
Simulation time 84155736 ps
CPU time 0.94 seconds
Started Aug 29 10:53:09 AM UTC 24
Finished Aug 29 10:53:11 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=96381519 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20
24_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.96381519
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_invalid.3443121985
Short name T207
Test name
Test status
Simulation time 83470485 ps
CPU time 1.04 seconds
Started Aug 29 10:53:11 AM UTC 24
Finished Aug 29 10:53:14 AM UTC 24
Peak memory 210732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443121985 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_invalid.3443121985
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.3091367362
Short name T199
Test name
Test status
Simulation time 216746821 ps
CPU time 2.05 seconds
Started Aug 29 10:53:07 AM UTC 24
Finished Aug 29 10:53:10 AM UTC 24
Peak memory 210752 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3091367362 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.3091367362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.1340990108
Short name T195
Test name
Test status
Simulation time 85525270 ps
CPU time 0.98 seconds
Started Aug 29 10:53:07 AM UTC 24
Finished Aug 29 10:53:09 AM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1340990108 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.1340990108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.2881362332
Short name T210
Test name
Test status
Simulation time 110066189 ps
CPU time 1.69 seconds
Started Aug 29 10:53:11 AM UTC 24
Finished Aug 29 10:53:14 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2881362332 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.2881362332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1577467482
Short name T202
Test name
Test status
Simulation time 260091200 ps
CPU time 1.28 seconds
Started Aug 29 10:53:08 AM UTC 24
Finished Aug 29 10:53:11 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1577467482 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.1577467482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.232989818
Short name T213
Test name
Test status
Simulation time 911838372 ps
CPU time 5.61 seconds
Started Aug 29 10:53:08 AM UTC 24
Finished Aug 29 10:53:15 AM UTC 24
Peak memory 210672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=232989818 -as
sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir
/workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersig
_mubi.232989818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3563568921
Short name T205
Test name
Test status
Simulation time 807971806 ps
CPU time 4.17 seconds
Started Aug 29 10:53:08 AM UTC 24
Finished Aug 29 10:53:13 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563568921 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3563568921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3081117717
Short name T200
Test name
Test status
Simulation time 75372663 ps
CPU time 1.25 seconds
Started Aug 29 10:53:08 AM UTC 24
Finished Aug 29 10:53:10 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081117717 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3081117717
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.3367125808
Short name T193
Test name
Test status
Simulation time 117562438 ps
CPU time 0.96 seconds
Started Aug 29 10:53:05 AM UTC 24
Finished Aug 29 10:53:07 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3367125808 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.3367125808
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.3855175543
Short name T228
Test name
Test status
Simulation time 1624557546 ps
CPU time 7.63 seconds
Started Aug 29 10:53:11 AM UTC 24
Finished Aug 29 10:53:20 AM UTC 24
Peak memory 211468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3855175543 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.3855175543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all_with_rand_reset.2556769153
Short name T59
Test name
Test status
Simulation time 6794985564 ps
CPU time 27.11 seconds
Started Aug 29 10:53:11 AM UTC 24
Finished Aug 29 10:53:40 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2556769153 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr
_stress_all_with_rand_reset.2556769153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.606344970
Short name T196
Test name
Test status
Simulation time 67423949 ps
CPU time 0.96 seconds
Started Aug 29 10:53:07 AM UTC 24
Finished Aug 29 10:53:09 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606344970 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.606344970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.1529979701
Short name T197
Test name
Test status
Simulation time 377744894 ps
CPU time 1.38 seconds
Started Aug 29 10:53:07 AM UTC 24
Finished Aug 29 10:53:09 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1529979701 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.1529979701
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2134587170
Short name T94
Test name
Test status
Simulation time 31423454 ps
CPU time 1.04 seconds
Started Aug 29 10:53:12 AM UTC 24
Finished Aug 29 10:53:14 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2134587170 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.2134587170
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.4292109160
Short name T151
Test name
Test status
Simulation time 69090615 ps
CPU time 1.14 seconds
Started Aug 29 10:53:16 AM UTC 24
Finished Aug 29 10:53:18 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4292109160 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.4292109160
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.1234905392
Short name T215
Test name
Test status
Simulation time 49786328 ps
CPU time 0.88 seconds
Started Aug 29 10:53:14 AM UTC 24
Finished Aug 29 10:53:16 AM UTC 24
Peak memory 206096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234905392 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.1234905392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.3426129551
Short name T217
Test name
Test status
Simulation time 430115016 ps
CPU time 1.13 seconds
Started Aug 29 10:53:15 AM UTC 24
Finished Aug 29 10:53:17 AM UTC 24
Peak memory 206160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426129551 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.3426129551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3300607270
Short name T221
Test name
Test status
Simulation time 56770671 ps
CPU time 1.07 seconds
Started Aug 29 10:53:16 AM UTC 24
Finished Aug 29 10:53:18 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3300607270 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3300607270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.2639343097
Short name T216
Test name
Test status
Simulation time 63782742 ps
CPU time 1 seconds
Started Aug 29 10:53:15 AM UTC 24
Finished Aug 29 10:53:16 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639343097 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2639343097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_invalid.3388164358
Short name T222
Test name
Test status
Simulation time 85099615 ps
CPU time 1.02 seconds
Started Aug 29 10:53:16 AM UTC 24
Finished Aug 29 10:53:18 AM UTC 24
Peak memory 210732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3388164358 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_invalid.3388164358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.2703520182
Short name T211
Test name
Test status
Simulation time 425080813 ps
CPU time 1 seconds
Started Aug 29 10:53:12 AM UTC 24
Finished Aug 29 10:53:14 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2703520182 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.2703520182
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.514658561
Short name T206
Test name
Test status
Simulation time 50433062 ps
CPU time 0.86 seconds
Started Aug 29 10:53:11 AM UTC 24
Finished Aug 29 10:53:14 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514658561 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.514658561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.4125636802
Short name T223
Test name
Test status
Simulation time 154358846 ps
CPU time 1.24 seconds
Started Aug 29 10:53:16 AM UTC 24
Finished Aug 29 10:53:18 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4125636802 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.4125636802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.3378571954
Short name T219
Test name
Test status
Simulation time 303983760 ps
CPU time 1.52 seconds
Started Aug 29 10:53:15 AM UTC 24
Finished Aug 29 10:53:17 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378571954 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.3378571954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3460324088
Short name T150
Test name
Test status
Simulation time 1599746155 ps
CPU time 3.41 seconds
Started Aug 29 10:53:13 AM UTC 24
Finished Aug 29 10:53:18 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460324088 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3460324088
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3275353326
Short name T220
Test name
Test status
Simulation time 1216171060 ps
CPU time 3.46 seconds
Started Aug 29 10:53:13 AM UTC 24
Finished Aug 29 10:53:18 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275353326 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3275353326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2772259091
Short name T218
Test name
Test status
Simulation time 54680337 ps
CPU time 1.38 seconds
Started Aug 29 10:53:14 AM UTC 24
Finished Aug 29 10:53:17 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772259091 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.2772259091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_smoke.2444562475
Short name T208
Test name
Test status
Simulation time 32716014 ps
CPU time 1.02 seconds
Started Aug 29 10:53:11 AM UTC 24
Finished Aug 29 10:53:14 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2444562475 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_smoke.2444562475
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.1059090498
Short name T235
Test name
Test status
Simulation time 681740487 ps
CPU time 4.91 seconds
Started Aug 29 10:53:16 AM UTC 24
Finished Aug 29 10:53:22 AM UTC 24
Peak memory 211524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059090498 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.1059090498
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.741545079
Short name T89
Test name
Test status
Simulation time 14080229652 ps
CPU time 14.73 seconds
Started Aug 29 10:53:16 AM UTC 24
Finished Aug 29 10:53:32 AM UTC 24
Peak memory 211532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=741545079 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg
l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_
stress_all_with_rand_reset.741545079
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.3386400094
Short name T212
Test name
Test status
Simulation time 211731199 ps
CPU time 1.27 seconds
Started Aug 29 10:53:12 AM UTC 24
Finished Aug 29 10:53:14 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3386400094 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.3386400094
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.4232682374
Short name T214
Test name
Test status
Simulation time 216142899 ps
CPU time 1.93 seconds
Started Aug 29 10:53:12 AM UTC 24
Finished Aug 29 10:53:15 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232682374 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.4232682374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.2382520600
Short name T229
Test name
Test status
Simulation time 236885553 ps
CPU time 1.09 seconds
Started Aug 29 10:53:19 AM UTC 24
Finished Aug 29 10:53:21 AM UTC 24
Peak memory 208160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2382520600 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.2382520600
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.3304992683
Short name T161
Test name
Test status
Simulation time 74003736 ps
CPU time 1.03 seconds
Started Aug 29 10:53:20 AM UTC 24
Finished Aug 29 10:53:22 AM UTC 24
Peak memory 211040 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3304992683 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.3304992683
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.533044086
Short name T230
Test name
Test status
Simulation time 30985724 ps
CPU time 0.95 seconds
Started Aug 29 10:53:19 AM UTC 24
Finished Aug 29 10:53:21 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533044086 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.533044086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.470745930
Short name T237
Test name
Test status
Simulation time 114503505 ps
CPU time 1.53 seconds
Started Aug 29 10:53:20 AM UTC 24
Finished Aug 29 10:53:23 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470745930 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.470745930
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.3109399383
Short name T233
Test name
Test status
Simulation time 79650656 ps
CPU time 0.88 seconds
Started Aug 29 10:53:20 AM UTC 24
Finished Aug 29 10:53:22 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109399383 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3109399383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.826093006
Short name T232
Test name
Test status
Simulation time 27620822 ps
CPU time 0.91 seconds
Started Aug 29 10:53:20 AM UTC 24
Finished Aug 29 10:53:22 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=826093006 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.826093006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.575394844
Short name T239
Test name
Test status
Simulation time 43226925 ps
CPU time 1.15 seconds
Started Aug 29 10:53:21 AM UTC 24
Finished Aug 29 10:53:24 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575394844 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.575394844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.399344760
Short name T226
Test name
Test status
Simulation time 629383741 ps
CPU time 1.32 seconds
Started Aug 29 10:53:17 AM UTC 24
Finished Aug 29 10:53:20 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399344760 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.399344760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.3785372330
Short name T225
Test name
Test status
Simulation time 146816793 ps
CPU time 1.09 seconds
Started Aug 29 10:53:17 AM UTC 24
Finished Aug 29 10:53:20 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785372330 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.3785372330
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.3062237673
Short name T240
Test name
Test status
Simulation time 122208418 ps
CPU time 1.28 seconds
Started Aug 29 10:53:21 AM UTC 24
Finished Aug 29 10:53:24 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062237673 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.3062237673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.2421985785
Short name T236
Test name
Test status
Simulation time 274617606 ps
CPU time 2.23 seconds
Started Aug 29 10:53:19 AM UTC 24
Finished Aug 29 10:53:23 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421985785 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.2421985785
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1997107590
Short name T241
Test name
Test status
Simulation time 962295087 ps
CPU time 3.72 seconds
Started Aug 29 10:53:19 AM UTC 24
Finished Aug 29 10:53:24 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997107590 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.1997107590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3698911142
Short name T243
Test name
Test status
Simulation time 993144541 ps
CPU time 4.28 seconds
Started Aug 29 10:53:19 AM UTC 24
Finished Aug 29 10:53:24 AM UTC 24
Peak memory 211404 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3698911142 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.3698911142
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1154455542
Short name T231
Test name
Test status
Simulation time 75139590 ps
CPU time 1.21 seconds
Started Aug 29 10:53:19 AM UTC 24
Finished Aug 29 10:53:21 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1154455542 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.1154455542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.843968239
Short name T224
Test name
Test status
Simulation time 38975703 ps
CPU time 0.98 seconds
Started Aug 29 10:53:17 AM UTC 24
Finished Aug 29 10:53:19 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843968239 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.843968239
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.3885281924
Short name T275
Test name
Test status
Simulation time 1648891075 ps
CPU time 10.47 seconds
Started Aug 29 10:53:22 AM UTC 24
Finished Aug 29 10:53:33 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3885281924 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.3885281924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.2324015725
Short name T121
Test name
Test status
Simulation time 7781519537 ps
CPU time 12 seconds
Started Aug 29 10:53:22 AM UTC 24
Finished Aug 29 10:53:35 AM UTC 24
Peak memory 211388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq
=pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si
m.tcl +ntb_random_seed=2324015725 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t
gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr
_stress_all_with_rand_reset.2324015725
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.4091715461
Short name T227
Test name
Test status
Simulation time 142789586 ps
CPU time 1.24 seconds
Started Aug 29 10:53:17 AM UTC 24
Finished Aug 29 10:53:20 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091715461 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.4091715461
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.2391843951
Short name T234
Test name
Test status
Simulation time 245794280 ps
CPU time 2.2 seconds
Started Aug 29 10:53:19 AM UTC 24
Finished Aug 29 10:53:22 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2391843951 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.2391843951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3227036760
Short name T244
Test name
Test status
Simulation time 196448053 ps
CPU time 1.05 seconds
Started Aug 29 10:53:23 AM UTC 24
Finished Aug 29 10:53:25 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227036760 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3227036760
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2124826946
Short name T162
Test name
Test status
Simulation time 81507628 ps
CPU time 1.04 seconds
Started Aug 29 10:53:26 AM UTC 24
Finished Aug 29 10:53:28 AM UTC 24
Peak memory 209960 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124826946 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.2124826946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.1955695404
Short name T247
Test name
Test status
Simulation time 30959770 ps
CPU time 0.98 seconds
Started Aug 29 10:53:24 AM UTC 24
Finished Aug 29 10:53:26 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955695404 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.1955695404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1218156003
Short name T251
Test name
Test status
Simulation time 208026012 ps
CPU time 1.42 seconds
Started Aug 29 10:53:24 AM UTC 24
Finished Aug 29 10:53:27 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218156003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE
Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-si
m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.1218156003
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.3705817698
Short name T252
Test name
Test status
Simulation time 100503141 ps
CPU time 0.91 seconds
Started Aug 29 10:53:26 AM UTC 24
Finished Aug 29 10:53:28 AM UTC 24
Peak memory 206212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705817698 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.3705817698
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.1116264986
Short name T248
Test name
Test status
Simulation time 29517176 ps
CPU time 0.96 seconds
Started Aug 29 10:53:24 AM UTC 24
Finished Aug 29 10:53:26 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116264986 -assert nopostproc +UVM_TESTNAME=p
wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.1116264986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.3112346918
Short name T253
Test name
Test status
Simulation time 94451468 ps
CPU time 1.01 seconds
Started Aug 29 10:53:26 AM UTC 24
Finished Aug 29 10:53:28 AM UTC 24
Peak memory 210732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112346918 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid.3112346918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.2637509709
Short name T198
Test name
Test status
Simulation time 47415468 ps
CPU time 0.95 seconds
Started Aug 29 10:53:23 AM UTC 24
Finished Aug 29 10:53:25 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637509709 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.2637509709
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.772162739
Short name T245
Test name
Test status
Simulation time 117706912 ps
CPU time 1.12 seconds
Started Aug 29 10:53:23 AM UTC 24
Finished Aug 29 10:53:25 AM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772162739 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.772162739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.999700014
Short name T256
Test name
Test status
Simulation time 98981240 ps
CPU time 1.54 seconds
Started Aug 29 10:53:26 AM UTC 24
Finished Aug 29 10:53:28 AM UTC 24
Peak memory 219796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=999700014 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.999700014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.50702220
Short name T250
Test name
Test status
Simulation time 337029085 ps
CPU time 1.55 seconds
Started Aug 29 10:53:24 AM UTC 24
Finished Aug 29 10:53:27 AM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50702220 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_
regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.50702220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3849466733
Short name T254
Test name
Test status
Simulation time 795280191 ps
CPU time 3.97 seconds
Started Aug 29 10:53:23 AM UTC 24
Finished Aug 29 10:53:28 AM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849466733 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3849466733
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4022682219
Short name T258
Test name
Test status
Simulation time 1292639398 ps
CPU time 3.74 seconds
Started Aug 29 10:53:24 AM UTC 24
Finished Aug 29 10:53:29 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022682219 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.4022682219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1157939828
Short name T249
Test name
Test status
Simulation time 94114764 ps
CPU time 1.23 seconds
Started Aug 29 10:53:24 AM UTC 24
Finished Aug 29 10:53:26 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157939828 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.1157939828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.2868578907
Short name T238
Test name
Test status
Simulation time 61741388 ps
CPU time 0.93 seconds
Started Aug 29 10:53:22 AM UTC 24
Finished Aug 29 10:53:23 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2868578907 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.2868578907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.1601573465
Short name T267
Test name
Test status
Simulation time 1604018219 ps
CPU time 4.09 seconds
Started Aug 29 10:53:26 AM UTC 24
Finished Aug 29 10:53:31 AM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1601573465 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.1601573465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.302540660
Short name T242
Test name
Test status
Simulation time 41460694 ps
CPU time 1.07 seconds
Started Aug 29 10:53:23 AM UTC 24
Finished Aug 29 10:53:25 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=302540660 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.302540660
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.45503121
Short name T246
Test name
Test status
Simulation time 377727349 ps
CPU time 1.63 seconds
Started Aug 29 10:53:23 AM UTC 24
Finished Aug 29 10:53:26 AM UTC 24
Peak memory 210496 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=45503121 -assert nopostproc +UVM_TESTNAME=pwrmgr
_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202
4_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.45503121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.76572596
Short name T259
Test name
Test status
Simulation time 17303383 ps
CPU time 1 seconds
Started Aug 29 10:53:27 AM UTC 24
Finished Aug 29 10:53:29 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76572596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=
pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-v
cs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.76572596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.628965237
Short name T272
Test name
Test status
Simulation time 67601086 ps
CPU time 1.13 seconds
Started Aug 29 10:53:30 AM UTC 24
Finished Aug 29 10:53:32 AM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=628965237 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.628965237
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.1750813920
Short name T264
Test name
Test status
Simulation time 30741673 ps
CPU time 1.01 seconds
Started Aug 29 10:53:29 AM UTC 24
Finished Aug 29 10:53:31 AM UTC 24
Peak memory 206224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1750813920 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.1750813920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.129688129
Short name T273
Test name
Test status
Simulation time 417276567 ps
CPU time 1.08 seconds
Started Aug 29 10:53:30 AM UTC 24
Finished Aug 29 10:53:32 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -
licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129688129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ
=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim
-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.129688129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.195086486
Short name T271
Test name
Test status
Simulation time 39428438 ps
CPU time 1.04 seconds
Started Aug 29 10:53:30 AM UTC 24
Finished Aug 29 10:53:32 AM UTC 24
Peak memory 206216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195086486 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.195086486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.928130247
Short name T265
Test name
Test status
Simulation time 25502451 ps
CPU time 0.94 seconds
Started Aug 29 10:53:29 AM UTC 24
Finished Aug 29 10:53:31 AM UTC 24
Peak memory 206220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO
TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928130247 -assert nopostproc +UVM_TESTNAME=pw
rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.928130247
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.1092569775
Short name T270
Test name
Test status
Simulation time 108219615 ps
CPU time 1 seconds
Started Aug 29 10:53:30 AM UTC 24
Finished Aug 29 10:53:32 AM UTC 24
Peak memory 210732 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1092569775 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.1092569775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_lowpower_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.328146954
Short name T262
Test name
Test status
Simulation time 213268519 ps
CPU time 1.27 seconds
Started Aug 29 10:53:27 AM UTC 24
Finished Aug 29 10:53:29 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=328146954 -assert nopostproc +UVM_TESTNAME=pwrmg
r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.328146954
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.3070303262
Short name T260
Test name
Test status
Simulation time 242834301 ps
CPU time 1.08 seconds
Started Aug 29 10:53:27 AM UTC 24
Finished Aug 29 10:53:29 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070303262 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.3070303262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.1724474524
Short name T274
Test name
Test status
Simulation time 602591709 ps
CPU time 1.18 seconds
Started Aug 29 10:53:30 AM UTC 24
Finished Aug 29 10:53:32 AM UTC 24
Peak memory 220188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1724474524 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_
2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.1724474524
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3250747402
Short name T269
Test name
Test status
Simulation time 259353360 ps
CPU time 2.23 seconds
Started Aug 29 10:53:29 AM UTC 24
Finished Aug 29 10:53:32 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3250747402 -assert nopostproc +UVM_TESTNAME=pwr
mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.3250747402
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3375099078
Short name T268
Test name
Test status
Simulation time 1397601081 ps
CPU time 3.44 seconds
Started Aug 29 10:53:27 AM UTC 24
Finished Aug 29 10:53:32 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum
entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3375099078 -a
ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di
r /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersi
g_mubi.3375099078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1723801884
Short name T279
Test name
Test status
Simulation time 813444397 ps
CPU time 4.35 seconds
Started Aug 29 10:53:29 AM UTC 24
Finished Aug 29 10:53:34 AM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru
mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1723801884 -
assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d
ir /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_inter
sig_mubi.1723801884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2789352138
Short name T266
Test name
Test status
Simulation time 175542640 ps
CPU time 1.34 seconds
Started Aug 29 10:53:29 AM UTC 24
Finished Aug 29 10:53:31 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2789352138 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.2789352138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.3958487016
Short name T255
Test name
Test status
Simulation time 57927773 ps
CPU time 0.96 seconds
Started Aug 29 10:53:26 AM UTC 24
Finished Aug 29 10:53:28 AM UTC 24
Peak memory 208264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958487016 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.3958487016
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1545751035
Short name T278
Test name
Test status
Simulation time 534710861 ps
CPU time 1.25 seconds
Started Aug 29 10:53:31 AM UTC 24
Finished Aug 29 10:53:33 AM UTC 24
Peak memory 208268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545751035 -assert nopostproc +UVM_TESTNAME=
pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.1545751035
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.1233556363
Short name T261
Test name
Test status
Simulation time 113960700 ps
CPU time 1.22 seconds
Started Aug 29 10:53:27 AM UTC 24
Finished Aug 29 10:53:29 AM UTC 24
Peak memory 208260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233556363 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08
_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.1233556363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.1428892628
Short name T263
Test name
Test status
Simulation time 185652649 ps
CPU time 1.26 seconds
Started Aug 29 10:53:27 AM UTC 24
Finished Aug 29 10:53:30 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES
+UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428892628 -assert nopostproc +UVM_TESTNAME=pwrm
gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2
024_08_28/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.1428892628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest
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