| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 97.97 | 98.23 | 96.58 | 99.62 | 96.00 | 96.37 | 100.00 | 99.02 |
| T65 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1253514030 | Sep 04 01:58:43 AM UTC 24 | Sep 04 01:58:45 AM UTC 24 | 223416187 ps | ||
| T114 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3343206745 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:50 AM UTC 24 | 100456123 ps | ||
| T1009 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.2978364838 | Sep 04 01:58:42 AM UTC 24 | Sep 04 01:58:45 AM UTC 24 | 102524529 ps | ||
| T1010 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.2707012305 | Sep 04 01:58:43 AM UTC 24 | Sep 04 01:58:45 AM UTC 24 | 227270326 ps | ||
| T1011 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2236245511 | Sep 04 01:58:43 AM UTC 24 | Sep 04 01:58:45 AM UTC 24 | 102697987 ps | ||
| T117 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.1232903091 | Sep 04 01:58:44 AM UTC 24 | Sep 04 01:58:46 AM UTC 24 | 31221177 ps | ||
| T1012 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2161451242 | Sep 04 01:58:44 AM UTC 24 | Sep 04 01:58:46 AM UTC 24 | 66754797 ps | ||
| T162 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.4018969327 | Sep 04 01:58:44 AM UTC 24 | Sep 04 01:58:46 AM UTC 24 | 105942401 ps | ||
| T1013 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.3119086218 | Sep 04 01:58:44 AM UTC 24 | Sep 04 01:58:47 AM UTC 24 | 282128171 ps | ||
| T1014 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1945242212 | Sep 04 01:58:45 AM UTC 24 | Sep 04 01:58:47 AM UTC 24 | 47675508 ps | ||
| T1015 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.562752347 | Sep 04 01:58:45 AM UTC 24 | Sep 04 01:58:47 AM UTC 24 | 80365328 ps | ||
| T1016 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.573394797 | Sep 04 01:58:44 AM UTC 24 | Sep 04 01:58:47 AM UTC 24 | 124140098 ps | ||
| T1017 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.1569083298 | Sep 04 01:58:45 AM UTC 24 | Sep 04 01:58:47 AM UTC 24 | 22369403 ps | ||
| T1018 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.233930539 | Sep 04 01:58:45 AM UTC 24 | Sep 04 01:58:47 AM UTC 24 | 23012486 ps | ||
| T1019 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3374452825 | Sep 04 01:58:45 AM UTC 24 | Sep 04 01:58:47 AM UTC 24 | 42536992 ps | ||
| T1020 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2607672832 | Sep 04 01:58:45 AM UTC 24 | Sep 04 01:58:48 AM UTC 24 | 130982090 ps | ||
| T1021 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.4145705041 | Sep 04 01:58:46 AM UTC 24 | Sep 04 01:58:49 AM UTC 24 | 98016384 ps | ||
| T1022 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.3809759147 | Sep 04 01:58:46 AM UTC 24 | Sep 04 01:58:48 AM UTC 24 | 20273215 ps | ||
| T1023 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.2930685755 | Sep 04 01:58:46 AM UTC 24 | Sep 04 01:58:48 AM UTC 24 | 23995466 ps | ||
| T1024 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.571033548 | Sep 04 01:58:45 AM UTC 24 | Sep 04 01:58:48 AM UTC 24 | 256076836 ps | ||
| T1025 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.405972675 | Sep 04 01:58:47 AM UTC 24 | Sep 04 01:58:48 AM UTC 24 | 57003278 ps | ||
| T1026 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.1252970684 | Sep 04 01:58:47 AM UTC 24 | Sep 04 01:58:48 AM UTC 24 | 36623280 ps | ||
| T1027 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3186999702 | Sep 04 01:58:46 AM UTC 24 | Sep 04 01:58:49 AM UTC 24 | 122868553 ps | ||
| T1028 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.503715110 | Sep 04 01:58:47 AM UTC 24 | Sep 04 01:58:49 AM UTC 24 | 164156285 ps | ||
| T1029 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1064658653 | Sep 04 01:58:47 AM UTC 24 | Sep 04 01:58:49 AM UTC 24 | 27166477 ps | ||
| T1030 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2865283654 | Sep 04 01:58:46 AM UTC 24 | Sep 04 01:58:49 AM UTC 24 | 314362069 ps | ||
| T1031 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.746906342 | Sep 04 01:58:46 AM UTC 24 | Sep 04 01:58:49 AM UTC 24 | 84583116 ps | ||
| T1032 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.3535648883 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:50 AM UTC 24 | 92692183 ps | ||
| T1033 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.2795658487 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:50 AM UTC 24 | 48591933 ps | ||
| T1034 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.300844971 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:50 AM UTC 24 | 63944452 ps | ||
| T1035 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3255210116 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:50 AM UTC 24 | 72961327 ps | ||
| T1036 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3157664034 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:50 AM UTC 24 | 210156407 ps | ||
| T1037 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1106401791 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:50 AM UTC 24 | 81003496 ps | ||
| T1038 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4230185757 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:50 AM UTC 24 | 67284121 ps | ||
| T1039 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1579379494 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 160904065 ps | ||
| T66 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1359429241 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 126691589 ps | ||
| T1040 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4195625447 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 22709216 ps | ||
| T1041 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3724540171 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 46401233 ps | ||
| T118 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2937750920 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 21658886 ps | ||
| T1042 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.3504928584 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 110803576 ps | ||
| T1043 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1199848006 | Sep 04 01:58:48 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 42209119 ps | ||
| T1044 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.457352539 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 103600574 ps | ||
| T1045 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2097137290 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 27414243 ps | ||
| T1046 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1600586321 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 18004510 ps | ||
| T1047 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1961694829 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:51 AM UTC 24 | 356250418 ps | ||
| T1048 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1090682069 | Sep 04 01:58:49 AM UTC 24 | Sep 04 01:58:52 AM UTC 24 | 318639366 ps | ||
| T1049 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.1278573030 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:53 AM UTC 24 | 45541808 ps | ||
| T119 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3115353319 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:53 AM UTC 24 | 38138334 ps | ||
| T1050 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3368752000 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:53 AM UTC 24 | 39082092 ps | ||
| T1051 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.678757333 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:53 AM UTC 24 | 25383044 ps | ||
| T1052 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2417188764 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:53 AM UTC 24 | 42242349 ps | ||
| T1053 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2189841156 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:53 AM UTC 24 | 243176356 ps | ||
| T1054 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3177909276 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:53 AM UTC 24 | 51734911 ps | ||
| T71 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2522521584 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:53 AM UTC 24 | 445278592 ps | ||
| T1055 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1218920471 | Sep 04 01:58:51 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 288498657 ps | ||
| T1056 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.168789047 | Sep 04 01:58:57 AM UTC 24 | Sep 04 01:58:59 AM UTC 24 | 39779626 ps | ||
| T1057 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.967496233 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 68590616 ps | ||
| T1058 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1804017739 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 20760932 ps | ||
| T1059 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1314622922 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 20238463 ps | ||
| T1060 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.557883099 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 20228273 ps | ||
| T1061 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2581528741 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 64962956 ps | ||
| T1062 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1478686736 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 60540633 ps | ||
| T1063 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.1430820977 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 31768440 ps | ||
| T1064 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2643139522 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:54 AM UTC 24 | 31863319 ps | ||
| T1065 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3724471884 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:55 AM UTC 24 | 154017981 ps | ||
| T1066 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.73464981 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:55 AM UTC 24 | 54848008 ps | ||
| T1067 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.69175372 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:55 AM UTC 24 | 33174103 ps | ||
| T1068 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1655766987 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:55 AM UTC 24 | 52847625 ps | ||
| T1069 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.894178327 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:55 AM UTC 24 | 243227654 ps | ||
| T1070 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.3082408530 | Sep 04 01:58:52 AM UTC 24 | Sep 04 01:58:55 AM UTC 24 | 90242124 ps | ||
| T1071 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.4057604166 | Sep 04 01:58:54 AM UTC 24 | Sep 04 01:58:55 AM UTC 24 | 59198281 ps | ||
| T1072 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.1090263940 | Sep 04 01:58:54 AM UTC 24 | Sep 04 01:58:56 AM UTC 24 | 20075563 ps | ||
| T1073 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1897292410 | Sep 04 01:58:53 AM UTC 24 | Sep 04 01:58:56 AM UTC 24 | 59478626 ps | ||
| T1074 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.4038365582 | Sep 04 01:58:53 AM UTC 24 | Sep 04 01:58:56 AM UTC 24 | 50180667 ps | ||
| T1075 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4257058755 | Sep 04 01:58:54 AM UTC 24 | Sep 04 01:58:56 AM UTC 24 | 116965999 ps | ||
| T1076 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.1280779669 | Sep 04 01:58:53 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 80243395 ps | ||
| T1077 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.3574670477 | Sep 04 01:58:57 AM UTC 24 | Sep 04 01:58:59 AM UTC 24 | 58724045 ps | ||
| T1078 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.2456855015 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 57463284 ps | ||
| T1079 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2962949653 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 32885120 ps | ||
| T1080 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.670439225 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 70702810 ps | ||
| T1081 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.254551701 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 22245599 ps | ||
| T1082 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2061622714 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 38893558 ps | ||
| T1083 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.284059508 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 20138339 ps | ||
| T1084 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.4168811202 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 25508613 ps | ||
| T1085 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2847618682 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 25025917 ps | ||
| T1086 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.139483845 | Sep 04 01:58:55 AM UTC 24 | Sep 04 01:58:57 AM UTC 24 | 73130494 ps | ||
| T1087 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2366422846 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 54314348 ps | ||
| T1088 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.930072770 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 72519584 ps | ||
| T1089 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.1579031123 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 18572115 ps | ||
| T1090 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.336926099 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 17630125 ps | ||
| T1091 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.4163370794 | Sep 04 01:58:58 AM UTC 24 | Sep 04 01:58:59 AM UTC 24 | 168201110 ps | ||
| T1092 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.4083728373 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 28596062 ps | ||
| T1093 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.4230226003 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 43533789 ps | ||
| T1094 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1177349187 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 50932080 ps | ||
| T1095 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.822476469 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 22039831 ps | ||
| T1096 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.3938988932 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 35790151 ps | ||
| T1097 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.3463395120 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 41563652 ps | ||
| T1098 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.3426553935 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 18723096 ps | ||
| T1099 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.2602502690 | Sep 04 01:58:56 AM UTC 24 | Sep 04 01:58:58 AM UTC 24 | 42954666 ps | ||
| T1100 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3033303281 | Sep 04 01:58:57 AM UTC 24 | Sep 04 01:58:59 AM UTC 24 | 21335287 ps | ||
| T1101 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.2918209259 | Sep 04 01:58:58 AM UTC 24 | Sep 04 01:58:59 AM UTC 24 | 43355560 ps | ||
| T1102 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.812284479 | Sep 04 01:58:58 AM UTC 24 | Sep 04 01:58:59 AM UTC 24 | 17942470 ps | ||
| T1103 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.3831743675 | Sep 04 01:58:58 AM UTC 24 | Sep 04 01:58:59 AM UTC 24 | 30168493 ps | ||
| T1104 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.2302545570 | Sep 04 01:58:58 AM UTC 24 | Sep 04 01:59:00 AM UTC 24 | 24972936 ps | ||
| T1105 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.1811060954 | Sep 04 01:58:58 AM UTC 24 | Sep 04 01:59:00 AM UTC 24 | 18553361 ps | ||
| T1106 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.2013063054 | Sep 04 01:58:58 AM UTC 24 | Sep 04 01:59:00 AM UTC 24 | 17434403 ps | ||
| T1107 | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.3497968452 | Sep 04 01:58:58 AM UTC 24 | Sep 04 01:59:00 AM UTC 24 | 27904222 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all.3189469244 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 1141293529 ps |
| CPU time | 3.93 seconds |
| Started | Sep 04 02:26:38 AM UTC 24 |
| Finished | Sep 04 02:26:46 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3189469244 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_stress_all.3189469244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset_invalid.3350134146 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 176472309 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 02:26:28 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3350134146 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset_invalid.3350134146 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm.2979840701 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 341304312 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:34 AM UTC 24 |
| Peak memory | 236700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979840701 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm.2979840701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2821404805 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 797176877 ps |
| CPU time | 3.17 seconds |
| Started | Sep 04 02:26:27 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821404805 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.2821404805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all_with_rand_reset.3893273101 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 1464145828 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:27:01 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3893273101 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr _stress_all_with_rand_reset.3893273101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_intg_err.2559319229 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 337836582 ps |
| CPU time | 2.02 seconds |
| Started | Sep 04 01:58:31 AM UTC 24 |
| Finished | Sep 04 01:58:34 AM UTC 24 |
| Peak memory | 211056 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559319229 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_intg_err.2559319229 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_invalid.1666612745 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 51056187 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:26:28 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1666612745 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_invalid.1666612745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_tl_errors.3686061265 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 139843640 ps |
| CPU time | 3.52 seconds |
| Started | Sep 04 01:58:31 AM UTC 24 |
| Finished | Sep 04 01:58:35 AM UTC 24 |
| Peak memory | 210704 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686061265 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_tl_errors.3686061265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_intr_test.905480907 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 27174129 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 01:58:36 AM UTC 24 |
| Finished | Sep 04 01:58:38 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=905480907 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_intr_test.905480907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_escalation_timeout.3930191464 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 125061162 ps |
| CPU time | 1.25 seconds |
| Started | Sep 04 02:26:28 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3930191464 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_escalation_timeout.3930191464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_aliasing.1554337761 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 64776161 ps |
| CPU time | 1.18 seconds |
| Started | Sep 04 01:58:36 AM UTC 24 |
| Finished | Sep 04 01:58:39 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1554337761 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_aliasing.1554337761 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all_with_rand_reset.755150981 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2732085618 ps |
| CPU time | 7.66 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:40 AM UTC 24 |
| Peak memory | 211456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=755150981 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_ stress_all_with_rand_reset.755150981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3896178560 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 1069348863 ps |
| CPU time | 2.4 seconds |
| Started | Sep 04 02:26:27 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896178560 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.3896178560 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_ctrl_config_regwen.3983002005 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 291292309 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 02:26:28 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3983002005 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_ctrl_config_regwen.3983002005 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_disable_rom_integrity_check.1139294278 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 72846078 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:26:28 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1139294278 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_disable_rom_integrity_check.1139294278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_disable_rom_integrity_check.2642947947 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 119464167 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642947947 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_disable_rom_integrity_check.2642947947 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_rw.1800702424 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 147090639 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 01:58:31 AM UTC 24 |
| Finished | Sep 04 01:58:33 AM UTC 24 |
| Peak memory | 209192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1800702424 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_rw.1800702424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_aborted_low_power.212415254 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 139307046 ps |
| CPU time | 1.02 seconds |
| Started | Sep 04 02:26:30 AM UTC 24 |
| Finished | Sep 04 02:26:32 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212415254 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_aborted_low_power.212415254 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_intg_err.3369997888 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 146435097 ps |
| CPU time | 1.66 seconds |
| Started | Sep 04 01:58:33 AM UTC 24 |
| Finished | Sep 04 01:58:36 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369997888 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_intg_err.3369997888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_intr_test.1252970684 |
| Short name | T1026 |
| Test name | |
| Test status | |
| Simulation time | 36623280 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 01:58:47 AM UTC 24 |
| Finished | Sep 04 01:58:48 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1252970684 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_intr_test.1252970684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_disable_rom_integrity_check.167450855 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 94733133 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167450855 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_disable_rom_integrity_check.167450855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_intg_err.503715110 |
| Short name | T1028 |
| Test name | |
| Test status | |
| Simulation time | 164156285 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 01:58:47 AM UTC 24 |
| Finished | Sep 04 01:58:49 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503715110 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_intg_err.503715110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_intg_err.1359429241 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 126691589 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1359429241 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_intg_err.1359429241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_intg_err.2522521584 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 445278592 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:53 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2522521584 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_intg_err.2522521584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_glitch.1350040683 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 52444603 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 02:26:28 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 206208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350040683 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_glitch.1350040683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_aliasing.1556326076 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 50792986 ps |
| CPU time | 1.42 seconds |
| Started | Sep 04 01:58:32 AM UTC 24 |
| Finished | Sep 04 01:58:35 AM UTC 24 |
| Peak memory | 210064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1556326076 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_aliasing.1556326076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_bit_bash.416730602 |
| Short name | T992 |
| Test name | |
| Test status | |
| Simulation time | 118245387 ps |
| CPU time | 2.63 seconds |
| Started | Sep 04 01:58:32 AM UTC 24 |
| Finished | Sep 04 01:58:36 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=416730602 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_bit_bash.416730602 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_hw_reset.2646043691 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 33147482 ps |
| CPU time | 1.02 seconds |
| Started | Sep 04 01:58:31 AM UTC 24 |
| Finished | Sep 04 01:58:33 AM UTC 24 |
| Peak memory | 209128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646043691 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_hw_reset.2646043691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_csr_mem_rw_with_rand_reset.2682916885 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 103503489 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 01:58:33 AM UTC 24 |
| Finished | Sep 04 01:58:35 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2682916885 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_csr_mem_rw_w ith_rand_reset.2682916885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_intr_test.686700183 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 47023342 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 01:58:31 AM UTC 24 |
| Finished | Sep 04 01:58:33 AM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=686700183 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_intr_test.686700183 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/0.pwrmgr_same_csr_outstanding.799456341 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 22606495 ps |
| CPU time | 1.02 seconds |
| Started | Sep 04 01:58:33 AM UTC 24 |
| Finished | Sep 04 01:58:35 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=799456341 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.pwrmgr_same_csr_outstanding.799456341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_aliasing.2037230891 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 69502015 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 01:58:35 AM UTC 24 |
| Finished | Sep 04 01:58:37 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037230891 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_aliasing.2037230891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_bit_bash.1407718630 |
| Short name | T994 |
| Test name | |
| Test status | |
| Simulation time | 556777073 ps |
| CPU time | 4.81 seconds |
| Started | Sep 04 01:58:35 AM UTC 24 |
| Finished | Sep 04 01:58:40 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1407718630 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_bit_bash.1407718630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_hw_reset.2993398165 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 20679869 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 01:58:33 AM UTC 24 |
| Finished | Sep 04 01:58:35 AM UTC 24 |
| Peak memory | 208384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2993398165 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_hw_reset.2993398165 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_mem_rw_with_rand_reset.2949141860 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 40985522 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 01:58:35 AM UTC 24 |
| Finished | Sep 04 01:58:37 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2949141860 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_mem_rw_w ith_rand_reset.2949141860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_csr_rw.1272975987 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 59289121 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 01:58:33 AM UTC 24 |
| Finished | Sep 04 01:58:35 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272975987 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_csr_rw.1272975987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_intr_test.3410868508 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 57462530 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 01:58:33 AM UTC 24 |
| Finished | Sep 04 01:58:35 AM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410868508 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_intr_test.3410868508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_same_csr_outstanding.1887607506 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 57240299 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 01:58:35 AM UTC 24 |
| Finished | Sep 04 01:58:37 AM UTC 24 |
| Peak memory | 208848 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887607506 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_same_csr_outstanding.1887607506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/1.pwrmgr_tl_errors.2132845199 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 115162813 ps |
| CPU time | 2.87 seconds |
| Started | Sep 04 01:58:33 AM UTC 24 |
| Finished | Sep 04 01:58:37 AM UTC 24 |
| Peak memory | 211068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2132845199 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.pwrmgr_tl_errors.2132845199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_mem_rw_with_rand_reset.405972675 |
| Short name | T1025 |
| Test name | |
| Test status | |
| Simulation time | 57003278 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 01:58:47 AM UTC 24 |
| Finished | Sep 04 01:58:48 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=405972675 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_mem_rw_w ith_rand_reset.405972675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_csr_rw.2930685755 |
| Short name | T1023 |
| Test name | |
| Test status | |
| Simulation time | 23995466 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 01:58:46 AM UTC 24 |
| Finished | Sep 04 01:58:48 AM UTC 24 |
| Peak memory | 208484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2930685755 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_csr_rw.2930685755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_intr_test.3809759147 |
| Short name | T1022 |
| Test name | |
| Test status | |
| Simulation time | 20273215 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 01:58:46 AM UTC 24 |
| Finished | Sep 04 01:58:48 AM UTC 24 |
| Peak memory | 207072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3809759147 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_intr_test.3809759147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_same_csr_outstanding.3186999702 |
| Short name | T1027 |
| Test name | |
| Test status | |
| Simulation time | 122868553 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 01:58:46 AM UTC 24 |
| Finished | Sep 04 01:58:49 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186999702 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_same_csr_outstanding.3186999702 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_errors.746906342 |
| Short name | T1031 |
| Test name | |
| Test status | |
| Simulation time | 84583116 ps |
| CPU time | 2.09 seconds |
| Started | Sep 04 01:58:46 AM UTC 24 |
| Finished | Sep 04 01:58:49 AM UTC 24 |
| Peak memory | 211064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746906342 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_errors.746906342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/10.pwrmgr_tl_intg_err.4145705041 |
| Short name | T1021 |
| Test name | |
| Test status | |
| Simulation time | 98016384 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 01:58:46 AM UTC 24 |
| Finished | Sep 04 01:58:49 AM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4145705041 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.pwrmgr_tl_intg_err.4145705041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_mem_rw_with_rand_reset.4230185757 |
| Short name | T1038 |
| Test name | |
| Test status | |
| Simulation time | 67284121 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:50 AM UTC 24 |
| Peak memory | 211196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4230185757 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_mem_rw_ with_rand_reset.4230185757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_csr_rw.3343206745 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 100456123 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:50 AM UTC 24 |
| Peak memory | 209168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343206745 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_csr_rw.3343206745 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_same_csr_outstanding.300844971 |
| Short name | T1034 |
| Test name | |
| Test status | |
| Simulation time | 63944452 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:50 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300844971 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_same_csr_outstanding.300844971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/11.pwrmgr_tl_errors.1064658653 |
| Short name | T1029 |
| Test name | |
| Test status | |
| Simulation time | 27166477 ps |
| CPU time | 1.32 seconds |
| Started | Sep 04 01:58:47 AM UTC 24 |
| Finished | Sep 04 01:58:49 AM UTC 24 |
| Peak memory | 211176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064658653 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.pwrmgr_tl_errors.1064658653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_mem_rw_with_rand_reset.1106401791 |
| Short name | T1037 |
| Test name | |
| Test status | |
| Simulation time | 81003496 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:50 AM UTC 24 |
| Peak memory | 211228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1106401791 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_mem_rw_ with_rand_reset.1106401791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_csr_rw.2795658487 |
| Short name | T1033 |
| Test name | |
| Test status | |
| Simulation time | 48591933 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:50 AM UTC 24 |
| Peak memory | 208124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795658487 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_csr_rw.2795658487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_intr_test.3535648883 |
| Short name | T1032 |
| Test name | |
| Test status | |
| Simulation time | 92692183 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:50 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3535648883 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_intr_test.3535648883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_same_csr_outstanding.3255210116 |
| Short name | T1035 |
| Test name | |
| Test status | |
| Simulation time | 72961327 ps |
| CPU time | 0.94 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:50 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255210116 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_same_csr_outstanding.3255210116 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_errors.3157664034 |
| Short name | T1036 |
| Test name | |
| Test status | |
| Simulation time | 210156407 ps |
| CPU time | 1.42 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:50 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3157664034 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_errors.3157664034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/12.pwrmgr_tl_intg_err.1579379494 |
| Short name | T1039 |
| Test name | |
| Test status | |
| Simulation time | 160904065 ps |
| CPU time | 1.53 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579379494 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.pwrmgr_tl_intg_err.1579379494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_mem_rw_with_rand_reset.3724540171 |
| Short name | T1041 |
| Test name | |
| Test status | |
| Simulation time | 46401233 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3724540171 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_mem_rw_ with_rand_reset.3724540171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_csr_rw.2937750920 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 21658886 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 208484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937750920 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_csr_rw.2937750920 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_intr_test.4195625447 |
| Short name | T1040 |
| Test name | |
| Test status | |
| Simulation time | 22709216 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 206748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195625447 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_intr_test.4195625447 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_same_csr_outstanding.457352539 |
| Short name | T1044 |
| Test name | |
| Test status | |
| Simulation time | 103600574 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457352539 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_same_csr_outstanding.457352539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/13.pwrmgr_tl_errors.1199848006 |
| Short name | T1043 |
| Test name | |
| Test status | |
| Simulation time | 42209119 ps |
| CPU time | 1.91 seconds |
| Started | Sep 04 01:58:48 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1199848006 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.pwrmgr_tl_errors.1199848006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_mem_rw_with_rand_reset.2417188764 |
| Short name | T1052 |
| Test name | |
| Test status | |
| Simulation time | 42242349 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:53 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2417188764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_mem_rw_ with_rand_reset.2417188764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_csr_rw.1600586321 |
| Short name | T1046 |
| Test name | |
| Test status | |
| Simulation time | 18004510 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 208448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600586321 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_csr_rw.1600586321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_intr_test.3504928584 |
| Short name | T1042 |
| Test name | |
| Test status | |
| Simulation time | 110803576 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3504928584 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_intr_test.3504928584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_same_csr_outstanding.2097137290 |
| Short name | T1045 |
| Test name | |
| Test status | |
| Simulation time | 27414243 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097137290 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_same_csr_outstanding.2097137290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_errors.1090682069 |
| Short name | T1048 |
| Test name | |
| Test status | |
| Simulation time | 318639366 ps |
| CPU time | 2.09 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:52 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090682069 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_errors.1090682069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/14.pwrmgr_tl_intg_err.1961694829 |
| Short name | T1047 |
| Test name | |
| Test status | |
| Simulation time | 356250418 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 01:58:49 AM UTC 24 |
| Finished | Sep 04 01:58:51 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961694829 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.pwrmgr_tl_intg_err.1961694829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_mem_rw_with_rand_reset.3368752000 |
| Short name | T1050 |
| Test name | |
| Test status | |
| Simulation time | 39082092 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:53 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3368752000 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_mem_rw_ with_rand_reset.3368752000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_csr_rw.3115353319 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 38138334 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:53 AM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115353319 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_csr_rw.3115353319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_intr_test.1278573030 |
| Short name | T1049 |
| Test name | |
| Test status | |
| Simulation time | 45541808 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:53 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1278573030 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_intr_test.1278573030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_same_csr_outstanding.678757333 |
| Short name | T1051 |
| Test name | |
| Test status | |
| Simulation time | 25383044 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:53 AM UTC 24 |
| Peak memory | 210124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=678757333 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_same_csr_outstanding.678757333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_errors.3177909276 |
| Short name | T1054 |
| Test name | |
| Test status | |
| Simulation time | 51734911 ps |
| CPU time | 1.4 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:53 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3177909276 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_errors.3177909276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/15.pwrmgr_tl_intg_err.2189841156 |
| Short name | T1053 |
| Test name | |
| Test status | |
| Simulation time | 243176356 ps |
| CPU time | 1.29 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:53 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2189841156 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.pwrmgr_tl_intg_err.2189841156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_mem_rw_with_rand_reset.2581528741 |
| Short name | T1061 |
| Test name | |
| Test status | |
| Simulation time | 64962956 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2581528741 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_mem_rw_ with_rand_reset.2581528741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_csr_rw.967496233 |
| Short name | T1057 |
| Test name | |
| Test status | |
| Simulation time | 68590616 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967496233 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_csr_rw.967496233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_intr_test.1804017739 |
| Short name | T1058 |
| Test name | |
| Test status | |
| Simulation time | 20760932 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1804017739 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_intr_test.1804017739 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_same_csr_outstanding.1478686736 |
| Short name | T1062 |
| Test name | |
| Test status | |
| Simulation time | 60540633 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478686736 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_same_csr_outstanding.1478686736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/16.pwrmgr_tl_errors.1218920471 |
| Short name | T1055 |
| Test name | |
| Test status | |
| Simulation time | 288498657 ps |
| CPU time | 1.67 seconds |
| Started | Sep 04 01:58:51 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218920471 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.pwrmgr_tl_errors.1218920471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_mem_rw_with_rand_reset.1655766987 |
| Short name | T1068 |
| Test name | |
| Test status | |
| Simulation time | 52847625 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:55 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1655766987 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_mem_rw_ with_rand_reset.1655766987 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_csr_rw.1314622922 |
| Short name | T1059 |
| Test name | |
| Test status | |
| Simulation time | 20238463 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314622922 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_csr_rw.1314622922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_intr_test.2643139522 |
| Short name | T1064 |
| Test name | |
| Test status | |
| Simulation time | 31863319 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 206888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643139522 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_intr_test.2643139522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_same_csr_outstanding.557883099 |
| Short name | T1060 |
| Test name | |
| Test status | |
| Simulation time | 20228273 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 209624 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=557883099 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_same_csr_outstanding.557883099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_errors.3082408530 |
| Short name | T1070 |
| Test name | |
| Test status | |
| Simulation time | 90242124 ps |
| CPU time | 1.54 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:55 AM UTC 24 |
| Peak memory | 211128 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082408530 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_errors.3082408530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/17.pwrmgr_tl_intg_err.894178327 |
| Short name | T1069 |
| Test name | |
| Test status | |
| Simulation time | 243227654 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:55 AM UTC 24 |
| Peak memory | 211168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=894178327 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.pwrmgr_tl_intg_err.894178327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_mem_rw_with_rand_reset.4038365582 |
| Short name | T1074 |
| Test name | |
| Test status | |
| Simulation time | 50180667 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 01:58:53 AM UTC 24 |
| Finished | Sep 04 01:58:56 AM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=4038365582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_mem_rw_ with_rand_reset.4038365582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_csr_rw.73464981 |
| Short name | T1066 |
| Test name | |
| Test status | |
| Simulation time | 54848008 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:55 AM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=73464981 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_csr_rw.73464981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_intr_test.1430820977 |
| Short name | T1063 |
| Test name | |
| Test status | |
| Simulation time | 31768440 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:54 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430820977 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_intr_test.1430820977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_same_csr_outstanding.1897292410 |
| Short name | T1073 |
| Test name | |
| Test status | |
| Simulation time | 59478626 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 01:58:53 AM UTC 24 |
| Finished | Sep 04 01:58:56 AM UTC 24 |
| Peak memory | 210608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897292410 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_same_csr_outstanding.1897292410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_errors.69175372 |
| Short name | T1067 |
| Test name | |
| Test status | |
| Simulation time | 33174103 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:55 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69175372 -assert nopostproc +UVM_TESTNAME=pwrmgr_bas e_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pw rmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_errors.69175372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/18.pwrmgr_tl_intg_err.3724471884 |
| Short name | T1065 |
| Test name | |
| Test status | |
| Simulation time | 154017981 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 01:58:52 AM UTC 24 |
| Finished | Sep 04 01:58:55 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724471884 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.pwrmgr_tl_intg_err.3724471884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_mem_rw_with_rand_reset.139483845 |
| Short name | T1086 |
| Test name | |
| Test status | |
| Simulation time | 73130494 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 211112 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=139483845 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_mem_rw_w ith_rand_reset.139483845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_csr_rw.4057604166 |
| Short name | T1071 |
| Test name | |
| Test status | |
| Simulation time | 59198281 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 01:58:54 AM UTC 24 |
| Finished | Sep 04 01:58:55 AM UTC 24 |
| Peak memory | 206960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057604166 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_csr_rw.4057604166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_intr_test.1090263940 |
| Short name | T1072 |
| Test name | |
| Test status | |
| Simulation time | 20075563 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 01:58:54 AM UTC 24 |
| Finished | Sep 04 01:58:56 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090263940 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_intr_test.1090263940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_same_csr_outstanding.2061622714 |
| Short name | T1082 |
| Test name | |
| Test status | |
| Simulation time | 38893558 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2061622714 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_same_csr_outstanding.2061622714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_errors.1280779669 |
| Short name | T1076 |
| Test name | |
| Test status | |
| Simulation time | 80243395 ps |
| CPU time | 1.83 seconds |
| Started | Sep 04 01:58:53 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 211120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1280779669 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_errors.1280779669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/19.pwrmgr_tl_intg_err.4257058755 |
| Short name | T1075 |
| Test name | |
| Test status | |
| Simulation time | 116965999 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:58:54 AM UTC 24 |
| Finished | Sep 04 01:58:56 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4257058755 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.pwrmgr_tl_intg_err.4257058755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_bit_bash.67063316 |
| Short name | T996 |
| Test name | |
| Test status | |
| Simulation time | 1269222004 ps |
| CPU time | 3.55 seconds |
| Started | Sep 04 01:58:36 AM UTC 24 |
| Finished | Sep 04 01:58:41 AM UTC 24 |
| Peak memory | 211236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67063316 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_bit_bash.67063316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_hw_reset.1379815236 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 38617412 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 01:58:36 AM UTC 24 |
| Finished | Sep 04 01:58:38 AM UTC 24 |
| Peak memory | 208384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1379815236 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_hw_reset.1379815236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_mem_rw_with_rand_reset.886763463 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 56829633 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 01:58:36 AM UTC 24 |
| Finished | Sep 04 01:58:39 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=886763463 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_mem_rw_wi th_rand_reset.886763463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_csr_rw.2931154386 |
| Short name | T993 |
| Test name | |
| Test status | |
| Simulation time | 28284093 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 01:58:36 AM UTC 24 |
| Finished | Sep 04 01:58:38 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2931154386 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_csr_rw.2931154386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_same_csr_outstanding.1606628547 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 126411931 ps |
| CPU time | 1.28 seconds |
| Started | Sep 04 01:58:36 AM UTC 24 |
| Finished | Sep 04 01:58:39 AM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1606628547 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_same_csr_outstanding.1606628547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_errors.3013925772 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 44099557 ps |
| CPU time | 2.68 seconds |
| Started | Sep 04 01:58:35 AM UTC 24 |
| Finished | Sep 04 01:58:38 AM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013925772 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_errors.3013925772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/2.pwrmgr_tl_intg_err.162930645 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 106967065 ps |
| CPU time | 1.45 seconds |
| Started | Sep 04 01:58:35 AM UTC 24 |
| Finished | Sep 04 01:58:37 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162930645 -assert nopostproc +UVM_TESTNA ME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.pwrmgr_tl_intg_err.162930645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/20.pwrmgr_intr_test.2456855015 |
| Short name | T1078 |
| Test name | |
| Test status | |
| Simulation time | 57463284 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456855015 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.pwrmgr_intr_test.2456855015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/21.pwrmgr_intr_test.2962949653 |
| Short name | T1079 |
| Test name | |
| Test status | |
| Simulation time | 32885120 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2962949653 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.pwrmgr_intr_test.2962949653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/22.pwrmgr_intr_test.254551701 |
| Short name | T1081 |
| Test name | |
| Test status | |
| Simulation time | 22245599 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254551701 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.pwrmgr_intr_test.254551701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/23.pwrmgr_intr_test.670439225 |
| Short name | T1080 |
| Test name | |
| Test status | |
| Simulation time | 70702810 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670439225 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.pwrmgr_intr_test.670439225 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/24.pwrmgr_intr_test.2847618682 |
| Short name | T1085 |
| Test name | |
| Test status | |
| Simulation time | 25025917 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 207072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2847618682 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.pwrmgr_intr_test.2847618682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/25.pwrmgr_intr_test.284059508 |
| Short name | T1083 |
| Test name | |
| Test status | |
| Simulation time | 20138339 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=284059508 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.pwrmgr_intr_test.284059508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/26.pwrmgr_intr_test.4168811202 |
| Short name | T1084 |
| Test name | |
| Test status | |
| Simulation time | 25508613 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 01:58:55 AM UTC 24 |
| Finished | Sep 04 01:58:57 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168811202 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.pwrmgr_intr_test.4168811202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/27.pwrmgr_intr_test.2366422846 |
| Short name | T1087 |
| Test name | |
| Test status | |
| Simulation time | 54314348 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2366422846 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.pwrmgr_intr_test.2366422846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/28.pwrmgr_intr_test.336926099 |
| Short name | T1090 |
| Test name | |
| Test status | |
| Simulation time | 17630125 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336926099 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.pwrmgr_intr_test.336926099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/29.pwrmgr_intr_test.930072770 |
| Short name | T1088 |
| Test name | |
| Test status | |
| Simulation time | 72519584 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=930072770 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.pwrmgr_intr_test.930072770 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_aliasing.2310595807 |
| Short name | T995 |
| Test name | |
| Test status | |
| Simulation time | 106970885 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 01:58:38 AM UTC 24 |
| Finished | Sep 04 01:58:41 AM UTC 24 |
| Peak memory | 210076 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310595807 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_aliasing.2310595807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_bit_bash.1234401863 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 47594475 ps |
| CPU time | 1.98 seconds |
| Started | Sep 04 01:58:38 AM UTC 24 |
| Finished | Sep 04 01:58:41 AM UTC 24 |
| Peak memory | 211300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1234401863 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_bit_bash.1234401863 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_hw_reset.2785760928 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 51430361 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 01:58:38 AM UTC 24 |
| Finished | Sep 04 01:58:40 AM UTC 24 |
| Peak memory | 208360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2785760928 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_hw_reset.2785760928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_mem_rw_with_rand_reset.1962080187 |
| Short name | T998 |
| Test name | |
| Test status | |
| Simulation time | 107098544 ps |
| CPU time | 1.17 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:42 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=1962080187 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_mem_rw_w ith_rand_reset.1962080187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_csr_rw.2468514379 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 28709622 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 01:58:38 AM UTC 24 |
| Finished | Sep 04 01:58:40 AM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2468514379 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_csr_rw.2468514379 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_intr_test.821549982 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 34886749 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 01:58:38 AM UTC 24 |
| Finished | Sep 04 01:58:40 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=821549982 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_intr_test.821549982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_same_csr_outstanding.1696131924 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 39833510 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:42 AM UTC 24 |
| Peak memory | 209100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696131924 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_same_csr_outstanding.1696131924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_errors.2116423514 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 87481893 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 01:58:37 AM UTC 24 |
| Finished | Sep 04 01:58:40 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2116423514 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_errors.2116423514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/3.pwrmgr_tl_intg_err.2155372296 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 238803240 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:58:37 AM UTC 24 |
| Finished | Sep 04 01:58:40 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155372296 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.pwrmgr_tl_intg_err.2155372296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/30.pwrmgr_intr_test.1579031123 |
| Short name | T1089 |
| Test name | |
| Test status | |
| Simulation time | 18572115 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1579031123 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.pwrmgr_intr_test.1579031123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/31.pwrmgr_intr_test.1177349187 |
| Short name | T1094 |
| Test name | |
| Test status | |
| Simulation time | 50932080 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1177349187 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.pwrmgr_intr_test.1177349187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/32.pwrmgr_intr_test.3938988932 |
| Short name | T1096 |
| Test name | |
| Test status | |
| Simulation time | 35790151 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206756 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938988932 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.pwrmgr_intr_test.3938988932 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/33.pwrmgr_intr_test.4083728373 |
| Short name | T1092 |
| Test name | |
| Test status | |
| Simulation time | 28596062 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206900 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083728373 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.pwrmgr_intr_test.4083728373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/34.pwrmgr_intr_test.822476469 |
| Short name | T1095 |
| Test name | |
| Test status | |
| Simulation time | 22039831 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822476469 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.pwrmgr_intr_test.822476469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/35.pwrmgr_intr_test.3426553935 |
| Short name | T1098 |
| Test name | |
| Test status | |
| Simulation time | 18723096 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3426553935 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.pwrmgr_intr_test.3426553935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/36.pwrmgr_intr_test.3463395120 |
| Short name | T1097 |
| Test name | |
| Test status | |
| Simulation time | 41563652 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463395120 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.pwrmgr_intr_test.3463395120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/37.pwrmgr_intr_test.4230226003 |
| Short name | T1093 |
| Test name | |
| Test status | |
| Simulation time | 43533789 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4230226003 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.pwrmgr_intr_test.4230226003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/38.pwrmgr_intr_test.2602502690 |
| Short name | T1099 |
| Test name | |
| Test status | |
| Simulation time | 42954666 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 01:58:56 AM UTC 24 |
| Finished | Sep 04 01:58:58 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602502690 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.pwrmgr_intr_test.2602502690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/39.pwrmgr_intr_test.168789047 |
| Short name | T1056 |
| Test name | |
| Test status | |
| Simulation time | 39779626 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 01:58:57 AM UTC 24 |
| Finished | Sep 04 01:58:59 AM UTC 24 |
| Peak memory | 206372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168789047 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.pwrmgr_intr_test.168789047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_aliasing.1079482907 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 75559849 ps |
| CPU time | 1.42 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:43 AM UTC 24 |
| Peak memory | 209860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079482907 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_aliasing.1079482907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_csr_aliasing/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_bit_bash.2034604207 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 1513590482 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:45 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2034604207 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_bit_bash.2034604207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_csr_bit_bash/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_hw_reset.1074295963 |
| Short name | T997 |
| Test name | |
| Test status | |
| Simulation time | 26669654 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:42 AM UTC 24 |
| Peak memory | 208444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1074295963 -assert nopostproc +UVM_TESTNAME =pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_hw_reset.1074295963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_csr_hw_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_mem_rw_with_rand_reset.209158261 |
| Short name | T1000 |
| Test name | |
| Test status | |
| Simulation time | 133233148 ps |
| CPU time | 1.46 seconds |
| Started | Sep 04 01:58:41 AM UTC 24 |
| Finished | Sep 04 01:58:44 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=209158261 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_mem_rw_wi th_rand_reset.209158261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_csr_rw.470937000 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 49687691 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:42 AM UTC 24 |
| Peak memory | 206952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470937000 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_csr_rw.470937000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_intr_test.4048894651 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 26572689 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:42 AM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4048894651 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_intr_test.4048894651 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_same_csr_outstanding.3213772523 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 94348452 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 01:58:41 AM UTC 24 |
| Finished | Sep 04 01:58:43 AM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3213772523 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_same_csr_outstanding.3213772523 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_errors.978737773 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 181143791 ps |
| CPU time | 1.44 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:42 AM UTC 24 |
| Peak memory | 211188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=978737773 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_errors.978737773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/4.pwrmgr_tl_intg_err.3225107748 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 201187421 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 01:58:40 AM UTC 24 |
| Finished | Sep 04 01:58:42 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3225107748 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.pwrmgr_tl_intg_err.3225107748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/40.pwrmgr_intr_test.3033303281 |
| Short name | T1100 |
| Test name | |
| Test status | |
| Simulation time | 21335287 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 01:58:57 AM UTC 24 |
| Finished | Sep 04 01:58:59 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033303281 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.pwrmgr_intr_test.3033303281 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/41.pwrmgr_intr_test.3574670477 |
| Short name | T1077 |
| Test name | |
| Test status | |
| Simulation time | 58724045 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 01:58:57 AM UTC 24 |
| Finished | Sep 04 01:58:59 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574670477 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.pwrmgr_intr_test.3574670477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/42.pwrmgr_intr_test.812284479 |
| Short name | T1102 |
| Test name | |
| Test status | |
| Simulation time | 17942470 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 01:58:58 AM UTC 24 |
| Finished | Sep 04 01:58:59 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=812284479 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.pwrmgr_intr_test.812284479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/43.pwrmgr_intr_test.2302545570 |
| Short name | T1104 |
| Test name | |
| Test status | |
| Simulation time | 24972936 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 01:58:58 AM UTC 24 |
| Finished | Sep 04 01:59:00 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302545570 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.pwrmgr_intr_test.2302545570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/44.pwrmgr_intr_test.2918209259 |
| Short name | T1101 |
| Test name | |
| Test status | |
| Simulation time | 43355560 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 01:58:58 AM UTC 24 |
| Finished | Sep 04 01:58:59 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2918209259 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.pwrmgr_intr_test.2918209259 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/45.pwrmgr_intr_test.4163370794 |
| Short name | T1091 |
| Test name | |
| Test status | |
| Simulation time | 168201110 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 01:58:58 AM UTC 24 |
| Finished | Sep 04 01:58:59 AM UTC 24 |
| Peak memory | 207072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4163370794 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.pwrmgr_intr_test.4163370794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/46.pwrmgr_intr_test.1811060954 |
| Short name | T1105 |
| Test name | |
| Test status | |
| Simulation time | 18553361 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 01:58:58 AM UTC 24 |
| Finished | Sep 04 01:59:00 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811060954 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.pwrmgr_intr_test.1811060954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/47.pwrmgr_intr_test.3831743675 |
| Short name | T1103 |
| Test name | |
| Test status | |
| Simulation time | 30168493 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 01:58:58 AM UTC 24 |
| Finished | Sep 04 01:58:59 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831743675 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.pwrmgr_intr_test.3831743675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/48.pwrmgr_intr_test.3497968452 |
| Short name | T1107 |
| Test name | |
| Test status | |
| Simulation time | 27904222 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 01:58:58 AM UTC 24 |
| Finished | Sep 04 01:59:00 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3497968452 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.pwrmgr_intr_test.3497968452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/49.pwrmgr_intr_test.2013063054 |
| Short name | T1106 |
| Test name | |
| Test status | |
| Simulation time | 17434403 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 01:58:58 AM UTC 24 |
| Finished | Sep 04 01:59:00 AM UTC 24 |
| Peak memory | 206956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013063054 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.pwrmgr_intr_test.2013063054 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_mem_rw_with_rand_reset.3849004138 |
| Short name | T1004 |
| Test name | |
| Test status | |
| Simulation time | 47641138 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 01:58:42 AM UTC 24 |
| Finished | Sep 04 01:58:44 AM UTC 24 |
| Peak memory | 211172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3849004138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_mem_rw_w ith_rand_reset.3849004138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_csr_rw.3946825637 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 50691582 ps |
| CPU time | 0.94 seconds |
| Started | Sep 04 01:58:41 AM UTC 24 |
| Finished | Sep 04 01:58:44 AM UTC 24 |
| Peak memory | 208976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946825637 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_csr_rw.3946825637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_intr_test.1597330033 |
| Short name | T999 |
| Test name | |
| Test status | |
| Simulation time | 16524478 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 01:58:41 AM UTC 24 |
| Finished | Sep 04 01:58:43 AM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597330033 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_intr_test.1597330033 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_same_csr_outstanding.1614691960 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 56679221 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 01:58:41 AM UTC 24 |
| Finished | Sep 04 01:58:43 AM UTC 24 |
| Peak memory | 209340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1614691960 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_same_csr_outstanding.1614691960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_errors.3964140911 |
| Short name | T1005 |
| Test name | |
| Test status | |
| Simulation time | 65639126 ps |
| CPU time | 2.23 seconds |
| Started | Sep 04 01:58:41 AM UTC 24 |
| Finished | Sep 04 01:58:44 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3964140911 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_errors.3964140911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/5.pwrmgr_tl_intg_err.2696016874 |
| Short name | T1001 |
| Test name | |
| Test status | |
| Simulation time | 237438635 ps |
| CPU time | 1.43 seconds |
| Started | Sep 04 01:58:41 AM UTC 24 |
| Finished | Sep 04 01:58:44 AM UTC 24 |
| Peak memory | 211116 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2696016874 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.pwrmgr_tl_intg_err.2696016874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_mem_rw_with_rand_reset.2236245511 |
| Short name | T1011 |
| Test name | |
| Test status | |
| Simulation time | 102697987 ps |
| CPU time | 1.68 seconds |
| Started | Sep 04 01:58:43 AM UTC 24 |
| Finished | Sep 04 01:58:45 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2236245511 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_mem_rw_w ith_rand_reset.2236245511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_csr_rw.4182694 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 59625200 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 01:58:43 AM UTC 24 |
| Finished | Sep 04 01:58:44 AM UTC 24 |
| Peak memory | 207072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4182694 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_csr_rw.4182694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_intr_test.1609683188 |
| Short name | T1003 |
| Test name | |
| Test status | |
| Simulation time | 19810362 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 01:58:43 AM UTC 24 |
| Finished | Sep 04 01:58:44 AM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1609683188 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_intr_test.1609683188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_same_csr_outstanding.1515373941 |
| Short name | T1006 |
| Test name | |
| Test status | |
| Simulation time | 36338085 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 01:58:43 AM UTC 24 |
| Finished | Sep 04 01:58:45 AM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1515373941 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_same_csr_outstanding.1515373941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_errors.2978364838 |
| Short name | T1009 |
| Test name | |
| Test status | |
| Simulation time | 102524529 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 01:58:42 AM UTC 24 |
| Finished | Sep 04 01:58:45 AM UTC 24 |
| Peak memory | 211204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2978364838 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_errors.2978364838 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/6.pwrmgr_tl_intg_err.1187331960 |
| Short name | T1008 |
| Test name | |
| Test status | |
| Simulation time | 352360726 ps |
| CPU time | 1.66 seconds |
| Started | Sep 04 01:58:42 AM UTC 24 |
| Finished | Sep 04 01:58:45 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187331960 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.pwrmgr_tl_intg_err.1187331960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_mem_rw_with_rand_reset.573394797 |
| Short name | T1016 |
| Test name | |
| Test status | |
| Simulation time | 124140098 ps |
| CPU time | 2.1 seconds |
| Started | Sep 04 01:58:44 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 211536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=573394797 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm _dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_mem_rw_wi th_rand_reset.573394797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_csr_rw.1232903091 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 31221177 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 01:58:44 AM UTC 24 |
| Finished | Sep 04 01:58:46 AM UTC 24 |
| Peak memory | 207020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232903091 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_csr_rw.1232903091 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_intr_test.1141121260 |
| Short name | T1007 |
| Test name | |
| Test status | |
| Simulation time | 16454408 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 01:58:43 AM UTC 24 |
| Finished | Sep 04 01:58:45 AM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141121260 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_intr_test.1141121260 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_same_csr_outstanding.2161451242 |
| Short name | T1012 |
| Test name | |
| Test status | |
| Simulation time | 66754797 ps |
| CPU time | 1.13 seconds |
| Started | Sep 04 01:58:44 AM UTC 24 |
| Finished | Sep 04 01:58:46 AM UTC 24 |
| Peak memory | 209604 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161451242 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_same_csr_outstanding.2161451242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_errors.2707012305 |
| Short name | T1010 |
| Test name | |
| Test status | |
| Simulation time | 227270326 ps |
| CPU time | 1.59 seconds |
| Started | Sep 04 01:58:43 AM UTC 24 |
| Finished | Sep 04 01:58:45 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2707012305 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_errors.2707012305 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/7.pwrmgr_tl_intg_err.1253514030 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 223416187 ps |
| CPU time | 1.37 seconds |
| Started | Sep 04 01:58:43 AM UTC 24 |
| Finished | Sep 04 01:58:45 AM UTC 24 |
| Peak memory | 211164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253514030 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.pwrmgr_tl_intg_err.1253514030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_mem_rw_with_rand_reset.3374452825 |
| Short name | T1019 |
| Test name | |
| Test status | |
| Simulation time | 42536992 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 211148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=3374452825 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_mem_rw_w ith_rand_reset.3374452825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_csr_rw.562752347 |
| Short name | T1015 |
| Test name | |
| Test status | |
| Simulation time | 80365328 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 208536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562752347 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_csr_rw.562752347 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_intr_test.3240894328 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 20523800 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3240894328 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_intr_test.3240894328 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_same_csr_outstanding.1945242212 |
| Short name | T1014 |
| Test name | |
| Test status | |
| Simulation time | 47675508 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 208660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1945242212 -assert nopostproc + UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_same_csr_outstanding.1945242212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_errors.3119086218 |
| Short name | T1013 |
| Test name | |
| Test status | |
| Simulation time | 282128171 ps |
| CPU time | 1.91 seconds |
| Started | Sep 04 01:58:44 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3119086218 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_errors.3119086218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/8.pwrmgr_tl_intg_err.4018969327 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 105942401 ps |
| CPU time | 1.24 seconds |
| Started | Sep 04 01:58:44 AM UTC 24 |
| Finished | Sep 04 01:58:46 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4018969327 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.pwrmgr_tl_intg_err.4018969327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_mem_rw_with_rand_reset.2865283654 |
| Short name | T1030 |
| Test name | |
| Test status | |
| Simulation time | 314362069 ps |
| CPU time | 1.64 seconds |
| Started | Sep 04 01:58:46 AM UTC 24 |
| Finished | Sep 04 01:58:49 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_s cb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_s eed=2865283654 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -c m_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_mem_rw_w ith_rand_reset.2865283654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_csr_mem_rw_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_csr_rw.3378594320 |
| Short name | T1002 |
| Test name | |
| Test status | |
| Simulation time | 138143910 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 208328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3378594320 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_csr_rw.3378594320 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_csr_rw/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_intr_test.1569083298 |
| Short name | T1017 |
| Test name | |
| Test status | |
| Simulation time | 22369403 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 206964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1569083298 -assert nopostproc +UVM_TESTNAME=pwrmgr_b ase_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/ pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_intr_test.1569083298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_intr_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_same_csr_outstanding.233930539 |
| Short name | T1018 |
| Test name | |
| Test status | |
| Simulation time | 23012486 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:47 AM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=233930539 -assert nopostproc +U VM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_same_csr_outstanding.233930539 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_same_csr_outstanding/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_errors.571033548 |
| Short name | T1024 |
| Test name | |
| Test status | |
| Simulation time | 256076836 ps |
| CPU time | 2.15 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:48 AM UTC 24 |
| Peak memory | 211184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UV M_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=571033548 -assert nopostproc +UVM_TESTNAME=pwrmgr_ba se_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/p wrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_errors.571033548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_tl_errors/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top/9.pwrmgr_tl_intg_err.2607672832 |
| Short name | T1020 |
| Test name | |
| Test status | |
| Simulation time | 130982090 ps |
| CPU time | 1.36 seconds |
| Started | Sep 04 01:58:45 AM UTC 24 |
| Finished | Sep 04 01:58:48 AM UTC 24 |
| Peak memory | 211124 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_ RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2607672832 -assert nopostproc +UVM_TESTN AME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.pwrmgr_tl_intg_err.2607672832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_tl_intg_err/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_aborted_low_power.2052479132 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 64147076 ps |
| CPU time | 1.03 seconds |
| Started | Sep 04 02:26:27 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052479132 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_aborted_low_power.2052479132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_esc_clk_rst_malfunc.1393953193 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 55540659 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:26:27 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1393953193 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_esc_clk_rst_malfunc.1393953193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_global_esc.2756606829 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 113461740 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:26:28 AM UTC 24 |
| Finished | Sep 04 02:26:30 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2756606829 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_global_esc.2756606829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_lowpower_wakeup_race.1628867176 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 31476022 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 02:26:27 AM UTC 24 |
| Finished | Sep 04 02:26:28 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628867176 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_lowpower_wakeup_race.1628867176 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_reset.3841921288 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 83176796 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 02:26:26 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3841921288 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_reset.3841921288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm.1743583899 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 356306854 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 02:26:29 AM UTC 24 |
| Finished | Sep 04 02:26:32 AM UTC 24 |
| Peak memory | 236700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1743583899 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm.1743583899 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2084290065 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 52521561 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 02:26:27 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2084290065 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_sec_cm_rstmgr_intersig_mubi.2084290065 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_smoke.1623156535 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 29686829 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:26:25 AM UTC 24 |
| Finished | Sep 04 02:26:27 AM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623156535 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_smoke.1623156535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all.261585697 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 1578934666 ps |
| CPU time | 3.46 seconds |
| Started | Sep 04 02:26:29 AM UTC 24 |
| Finished | Sep 04 02:26:34 AM UTC 24 |
| Peak memory | 211288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261585697 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_stress_all.261585697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_stress_all_with_rand_reset.1582795582 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 7906961060 ps |
| CPU time | 10.41 seconds |
| Started | Sep 04 02:26:29 AM UTC 24 |
| Finished | Sep 04 02:26:41 AM UTC 24 |
| Peak memory | 211748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1582795582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr _stress_all_with_rand_reset.1582795582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup.2257112966 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 177323818 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 02:26:27 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257112966 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup.2257112966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/0.pwrmgr_wakeup_reset.3458225267 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 163557128 ps |
| CPU time | 1.2 seconds |
| Started | Sep 04 02:26:27 AM UTC 24 |
| Finished | Sep 04 02:26:29 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3458225267 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.pwrmgr_wakeup_reset.3458225267 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/0.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_disable_rom_integrity_check.584944399 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 63367382 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584944399 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_disable_rom_integrity_check.584944399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_esc_clk_rst_malfunc.1544811460 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 32247269 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1544811460 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_esc_clk_rst_malfunc.1544811460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_escalation_timeout.1327567663 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 384977780 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1327567663 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_escalation_timeout.1327567663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_glitch.3037632728 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 55933108 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3037632728 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_glitch.3037632728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_global_esc.3197586890 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 92578755 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3197586890 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_global_esc.3197586890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_invalid.3263862502 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 52562386 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263862502 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_invalid.3263862502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_lowpower_wakeup_race.4241591569 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 175234353 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:26:29 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241591569 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_lowpower_wakeup_race.4241591569 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset.1713384561 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 36799717 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:26:29 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1713384561 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset.1713384561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_reset_invalid.317853480 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 244081798 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317853480 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_reset_invalid.317853480 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_ctrl_config_regwen.3570197870 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 237655042 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 208224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3570197870 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_ctrl_config_regwen.3570197870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4222525722 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 884179003 ps |
| CPU time | 3.3 seconds |
| Started | Sep 04 02:26:30 AM UTC 24 |
| Finished | Sep 04 02:26:34 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4222525722 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.4222525722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2806225166 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 823101734 ps |
| CPU time | 2.65 seconds |
| Started | Sep 04 02:26:30 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806225166 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.2806225166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2426670786 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 120887765 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:26:30 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2426670786 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_sec_cm_rstmgr_intersig_mubi.2426670786 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_smoke.3273787939 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 48390856 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:26:29 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273787939 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_smoke.3273787939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_stress_all.585972755 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 240134290 ps |
| CPU time | 1.48 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:34 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585972755 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_stress_all.585972755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup.1294337670 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 260709120 ps |
| CPU time | 1.39 seconds |
| Started | Sep 04 02:26:30 AM UTC 24 |
| Finished | Sep 04 02:26:32 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294337670 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup.1294337670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/1.pwrmgr_wakeup_reset.2400840505 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 86294000 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:26:30 AM UTC 24 |
| Finished | Sep 04 02:26:31 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2400840505 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.pwrmgr_wakeup_reset.2400840505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/1.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_aborted_low_power.4160383798 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 22469569 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:27:18 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160383798 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_aborted_low_power.4160383798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_disable_rom_integrity_check.846989303 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 51660012 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 211064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=846989303 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_disable_rom_integrity_check.846989303 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_esc_clk_rst_malfunc.1880791859 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 36343551 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:22 AM UTC 24 |
| Peak memory | 205884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1880791859 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_esc_clk_rst_malfunc.1880791859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_escalation_timeout.2824358243 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 1873759083 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824358243 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_escalation_timeout.2824358243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_glitch.3298113992 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 50499440 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298113992 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_glitch.3298113992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_global_esc.2948773641 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 46777203 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:22 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2948773641 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_global_esc.2948773641 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_invalid.3792485999 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 59304639 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 210708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792485999 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_invalid.3792485999 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_lowpower_wakeup_race.1086825561 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 196223106 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:27:17 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1086825561 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_lowpower_wakeup_race.1086825561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset.3085362057 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 53441379 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:27:16 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3085362057 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset.3085362057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_reset_invalid.3176660458 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 156601228 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176660458 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_reset_invalid.3176660458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_ctrl_config_regwen.4206939277 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 58753369 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206939277 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_ctrl_config_regwen.4206939277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4122417507 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 1178672996 ps |
| CPU time | 2.09 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 210960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4122417507 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4122417507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3617933779 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 1190571619 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3617933779 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3617933779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_sec_cm_rstmgr_intersig_mubi.4082603514 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 53504272 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 207820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4082603514 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_sec_cm_rstmgr_intersig_mubi.4082603514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_smoke.2227889976 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 32924018 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:27:16 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2227889976 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_smoke.2227889976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all.4229245596 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 2209732720 ps |
| CPU time | 3.39 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:26 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229245596 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_stress_all.4229245596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_stress_all_with_rand_reset.2664887820 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3118372319 ps |
| CPU time | 5.08 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:27 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2664887820 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmg r_stress_all_with_rand_reset.2664887820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup.2288924887 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 289666575 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:27:18 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2288924887 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup.2288924887 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/10.pwrmgr_wakeup_reset.3181467578 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 140017406 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 02:27:18 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181467578 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.pwrmgr_wakeup_reset.3181467578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/10.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_aborted_low_power.4264020350 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 67253319 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:27:21 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4264020350 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_aborted_low_power.4264020350 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_esc_clk_rst_malfunc.1699202857 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 30619347 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 206144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1699202857 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_esc_clk_rst_malfunc.1699202857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_escalation_timeout.1302333130 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 119626606 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1302333130 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_escalation_timeout.1302333130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_glitch.2337301041 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 62515488 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2337301041 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_glitch.2337301041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_global_esc.1329458583 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 47443304 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329458583 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_global_esc.1329458583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_invalid.1729927301 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 44534617 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 209904 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729927301 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_invalid.1729927301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_lowpower_wakeup_race.190591912 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 171212178 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:21 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=190591912 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_lowpower_wakeup_race.190591912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset.1272061982 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 150543245 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1272061982 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset.1272061982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_reset_invalid.3982964775 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 97376086 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982964775 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_reset_invalid.3982964775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_ctrl_config_regwen.3819166924 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 250429483 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3819166924 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_ctrl_config_regwen.3819166924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1343386288 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 929507216 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 02:27:23 AM UTC 24 |
| Finished | Sep 04 02:27:29 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1343386288 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1343386288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.385578311 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 1251599943 ps |
| CPU time | 2.11 seconds |
| Started | Sep 04 02:27:23 AM UTC 24 |
| Finished | Sep 04 02:27:29 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385578311 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.385578311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1317333848 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 53174959 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 208220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317333848 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_sec_cm_rstmgr_intersig_mubi.1317333848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_smoke.3804980163 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 29432872 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:27:20 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804980163 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_smoke.3804980163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all.3186308371 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 302000614 ps |
| CPU time | 1.27 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 211180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186308371 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_stress_all.3186308371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_stress_all_with_rand_reset.1744571426 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 5256551014 ps |
| CPU time | 10.38 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 210840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1744571426 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmg r_stress_all_with_rand_reset.1744571426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup.1035883718 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 260631826 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:27:21 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035883718 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup.1035883718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/11.pwrmgr_wakeup_reset.1309380348 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 282823563 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:27:21 AM UTC 24 |
| Finished | Sep 04 02:27:23 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309380348 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.pwrmgr_wakeup_reset.1309380348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/11.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_aborted_low_power.3695400319 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 34791371 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695400319 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_aborted_low_power.3695400319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_disable_rom_integrity_check.498466462 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 61980866 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498466462 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_disable_rom_integrity_check.498466462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_esc_clk_rst_malfunc.1491862622 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 29310735 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491862622 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_esc_clk_rst_malfunc.1491862622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_escalation_timeout.2223507144 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 107883174 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223507144 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_escalation_timeout.2223507144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_glitch.16663371 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 39354385 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=16663371 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_glitch.16663371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_global_esc.3762894463 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 81712609 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762894463 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_global_esc.3762894463 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_invalid.2033446583 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 46040807 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 210788 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033446583 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_invalid.2033446583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_lowpower_wakeup_race.2499846615 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 174686994 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499846615 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_lowpower_wakeup_race.2499846615 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset.2654854862 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 182924975 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2654854862 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset.2654854862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_reset_invalid.2643708622 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 157831709 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643708622 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_reset_invalid.2643708622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_ctrl_config_regwen.1841716828 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 162754691 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841716828 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_ctrl_config_regwen.1841716828 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4142445245 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 960328921 ps |
| CPU time | 2.07 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:29 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4142445245 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4142445245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3779477381 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 1066230160 ps |
| CPU time | 2.17 seconds |
| Started | Sep 04 02:27:26 AM UTC 24 |
| Finished | Sep 04 02:27:30 AM UTC 24 |
| Peak memory | 211208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3779477381 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3779477381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3371914343 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 68551672 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:27:26 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 207856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3371914343 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_sec_cm_rstmgr_intersig_mubi.3371914343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_smoke.2642831042 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 29621915 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642831042 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_smoke.2642831042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all.495699443 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 774305380 ps |
| CPU time | 1.74 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:40 AM UTC 24 |
| Peak memory | 210820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=495699443 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_stress_all.495699443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.632111754 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 9295883586 ps |
| CPU time | 11.03 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:49 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=632111754 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr _stress_all_with_rand_reset.632111754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup.4220665113 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 69247380 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4220665113 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup.4220665113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_wakeup_reset.3365697836 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 313896792 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:27:25 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3365697836 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.pwrmgr_wakeup_reset.3365697836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/12.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_aborted_low_power.906828853 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 77028783 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906828853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_aborted_low_power.906828853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.2003090655 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 57232626 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:27:32 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2003090655 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_disable_rom_integrity_check.2003090655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_esc_clk_rst_malfunc.4012628283 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 39706891 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012628283 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_esc_clk_rst_malfunc.4012628283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.4183834870 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 110343632 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183834870 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_escalation_timeout.4183834870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.3828654287 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 46454787 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3828654287 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_glitch.3828654287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_global_esc.255521546 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 87474516 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255521546 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_global_esc.255521546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_invalid.3481102553 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 70760425 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:27:34 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481102553 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_invalid.3481102553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_lowpower_wakeup_race.4138307741 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 174513892 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:39 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138307741 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_lowpower_wakeup_race.4138307741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset.2825612776 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 91737487 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:39 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2825612776 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset.2825612776 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.1239369766 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 484436872 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:27:34 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 220164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1239369766 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_reset_invalid.1239369766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.3216749897 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 318795593 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216749897 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_ctrl_config_regwen.3216749897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.179083986 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 750218366 ps |
| CPU time | 2.69 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:35 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179083986 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.179083986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1824337372 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 950801308 ps |
| CPU time | 2.71 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:35 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824337372 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1824337372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rstmgr_intersig_mubi.599872316 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 167347131 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599872316 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_sec_cm_rstmgr_intersig_mubi.599872316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_smoke.1261731760 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 29177439 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:27:29 AM UTC 24 |
| Finished | Sep 04 02:27:39 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261731760 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_smoke.1261731760 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.2750789616 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 2004596636 ps |
| CPU time | 4.93 seconds |
| Started | Sep 04 02:27:34 AM UTC 24 |
| Finished | Sep 04 02:27:50 AM UTC 24 |
| Peak memory | 211452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2750789616 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_stress_all.2750789616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.2196665016 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 8849916827 ps |
| CPU time | 9.14 seconds |
| Started | Sep 04 02:27:34 AM UTC 24 |
| Finished | Sep 04 02:27:54 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2196665016 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmg r_stress_all_with_rand_reset.2196665016 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup.2859346764 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 328072785 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2859346764 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup.2859346764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_wakeup_reset.3603507274 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 35071560 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:27:31 AM UTC 24 |
| Finished | Sep 04 02:27:33 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3603507274 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.pwrmgr_wakeup_reset.3603507274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/13.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.746736612 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 55417710 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:27:36 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=746736612 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_aborted_low_power.746736612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.2077327275 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 87473071 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2077327275 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_disable_rom_integrity_check.2077327275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.3628952690 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 37659196 ps |
| CPU time | 0.5 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3628952690 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_esc_clk_rst_malfunc.3628952690 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.2998556877 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 1850245471 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:45 AM UTC 24 |
| Peak memory | 205884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998556877 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_escalation_timeout.2998556877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.2044778626 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 47057635 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2044778626 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_glitch.2044778626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.992832368 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 28979011 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:45 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=992832368 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_global_esc.992832368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_invalid.2823114428 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 80247516 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2823114428 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_invalid.2823114428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.396949553 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 101647954 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:27:34 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=396949553 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_lowpower_wakeup_race.396949553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.369023841 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 150897211 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:27:34 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 209540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=369023841 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset.369023841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.2098005409 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 162503607 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2098005409 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_reset_invalid.2098005409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.2431824717 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 239746165 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:45 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2431824717 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_ctrl_config_regwen.2431824717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3660347250 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 811303219 ps |
| CPU time | 2.8 seconds |
| Started | Sep 04 02:27:36 AM UTC 24 |
| Finished | Sep 04 02:27:40 AM UTC 24 |
| Peak memory | 211344 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3660347250 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3660347250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2110747984 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 861465393 ps |
| CPU time | 2.81 seconds |
| Started | Sep 04 02:27:37 AM UTC 24 |
| Finished | Sep 04 02:27:48 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2110747984 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2110747984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.465625324 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 64877526 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:45 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=465625324 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_sec_cm_rstmgr_intersig_mubi.465625324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.3757646919 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 186888073 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:27:34 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757646919 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_smoke.3757646919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.3052607197 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 1056635542 ps |
| CPU time | 3.76 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3052607197 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_stress_all.3052607197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.2935199374 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 5589506674 ps |
| CPU time | 6.68 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:49 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2935199374 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmg r_stress_all_with_rand_reset.2935199374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.1540123732 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 387489770 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:27:34 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 208252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540123732 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup.1540123732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.751335101 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 122439489 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:27:35 AM UTC 24 |
| Finished | Sep 04 02:27:38 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=751335101 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.pwrmgr_wakeup_reset.751335101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/14.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.3291018763 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 122133336 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291018763 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_aborted_low_power.3291018763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.1660716731 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 61037087 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1660716731 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_disable_rom_integrity_check.1660716731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.1361577428 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 39054595 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361577428 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_esc_clk_rst_malfunc.1361577428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.657414846 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 635537958 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:27:41 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=657414846 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_escalation_timeout.657414846 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.1872006512 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 59549506 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:27:41 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1872006512 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_glitch.1872006512 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.4071009832 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 58461204 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071009832 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_global_esc.4071009832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_invalid.3015030506 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 44035159 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3015030506 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_invalid.3015030506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.1973497068 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 282228333 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1973497068 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_lowpower_wakeup_race.1973497068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.1242664210 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 79470839 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242664210 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset.1242664210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.1200121942 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 132075489 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200121942 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_reset_invalid.1200121942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.753537234 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 274346221 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=753537234 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_ctrl_config_regwen.753537234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3892262812 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 1411306803 ps |
| CPU time | 1.74 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 210404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3892262812 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3892262812 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1504213517 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 1464731105 ps |
| CPU time | 1.65 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1504213517 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1504213517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2336764859 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 65736336 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2336764859 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_sec_cm_rstmgr_intersig_mubi.2336764859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.2729495595 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 37710739 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2729495595 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_smoke.2729495595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.38533672 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 698348412 ps |
| CPU time | 2.63 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:49 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=38533672 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_stress_all.38533672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.3421610150 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 9803562573 ps |
| CPU time | 6.94 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3421610150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmg r_stress_all_with_rand_reset.3421610150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.1308674743 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 230595778 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:44 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1308674743 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup.1308674743 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.3874446034 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 191145570 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:27:40 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3874446034 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.pwrmgr_wakeup_reset.3874446034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/15.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.3956679707 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 73311962 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 207948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3956679707 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_aborted_low_power.3956679707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.2774769140 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 74856068 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2774769140 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_disable_rom_integrity_check.2774769140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_esc_clk_rst_malfunc.562978374 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 107102120 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 206032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562978374 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_esc_clk_rst_malfunc.562978374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.1255257186 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 365270326 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255257186 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_escalation_timeout.1255257186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.3236196553 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 57588206 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236196553 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_glitch.3236196553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.4042027012 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 115980987 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4042027012 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_global_esc.4042027012 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_invalid.1170054747 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 94975464 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170054747 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_invalid.1170054747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.2937836336 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 315929187 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937836336 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_lowpower_wakeup_race.2937836336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.2345258979 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 125196035 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345258979 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset.2345258979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.3021434032 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 109112955 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3021434032 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_reset_invalid.3021434032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.1988898179 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 326205926 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1988898179 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_ctrl_config_regwen.1988898179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2674099536 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 1253900477 ps |
| CPU time | 1.92 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:48 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674099536 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2674099536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.157180253 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 1048640262 ps |
| CPU time | 1.87 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:48 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=157180253 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.157180253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.346626997 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 66883609 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=346626997 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_sec_cm_rstmgr_intersig_mubi.346626997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3870132527 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 36729752 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3870132527 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_smoke.3870132527 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.462332198 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 2356980875 ps |
| CPU time | 1.82 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:48 AM UTC 24 |
| Peak memory | 210448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462332198 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_stress_all.462332198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.1820013653 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 9922574232 ps |
| CPU time | 10.12 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:57 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1820013653 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmg r_stress_all_with_rand_reset.1820013653 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup.4266143475 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 144985197 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 208024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266143475 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup.4266143475 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.2822919437 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 173247344 ps |
| CPU time | 1.01 seconds |
| Started | Sep 04 02:27:45 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822919437 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.pwrmgr_wakeup_reset.2822919437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/16.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.192395135 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 24156802 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 209700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=192395135 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_aborted_low_power.192395135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.3670811479 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 76425114 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3670811479 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_disable_rom_integrity_check.3670811479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.3893610989 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 29357087 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3893610989 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_esc_clk_rst_malfunc.3893610989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.3228999964 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 115404713 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3228999964 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_escalation_timeout.3228999964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.960926937 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 60084635 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=960926937 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_glitch.960926937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.2057597327 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 138183785 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2057597327 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_global_esc.2057597327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_invalid.1023971891 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 42079253 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1023971891 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_invalid.1023971891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.3061305865 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 86275329 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3061305865 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_lowpower_wakeup_race.3061305865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.3265791277 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 68303347 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3265791277 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset.3265791277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.3601507533 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 169384353 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601507533 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_reset_invalid.3601507533 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3623138219 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 642219195 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3623138219 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_ctrl_config_regwen.3623138219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3861532 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 874643020 ps |
| CPU time | 2.77 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861532 -asse rt nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir / workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3861532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3290037045 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 1341376125 ps |
| CPU time | 1.69 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290037045 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3290037045 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.88966548 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 93453022 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88966548 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_sec_cm_rstmgr_intersig_mubi.88966548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.2308187948 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 32205568 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2308187948 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_smoke.2308187948 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.2839117857 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 817390006 ps |
| CPU time | 2 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2839117857 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_stress_all.2839117857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.4169490283 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 6429532892 ps |
| CPU time | 15.09 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:28:06 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4169490283 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmg r_stress_all_with_rand_reset.4169490283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.4170175706 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 103158504 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170175706 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup.4170175706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.3909704313 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 691818336 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:27:49 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909704313 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.pwrmgr_wakeup_reset.3909704313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/17.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.575068752 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 48972910 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575068752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_aborted_low_power.575068752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.3518595125 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 124273041 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 208580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3518595125 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_disable_rom_integrity_check.3518595125 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.2192677384 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 36005141 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 206172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192677384 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_esc_clk_rst_malfunc.2192677384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.2240174872 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 271625696 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2240174872 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_escalation_timeout.2240174872 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.629791040 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 37835971 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629791040 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_glitch.629791040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.4120588678 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 68825014 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 208636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120588678 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_global_esc.4120588678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_invalid.737707429 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 44893188 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737707429 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_invalid.737707429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.1984266409 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 130014188 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984266409 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_lowpower_wakeup_race.1984266409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.1285882149 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 81586526 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1285882149 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset.1285882149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.3941049491 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 101806493 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941049491 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_reset_invalid.3941049491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.1420882210 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 254937260 ps |
| CPU time | 1.21 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1420882210 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_ctrl_config_regwen.1420882210 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1091170018 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 750591478 ps |
| CPU time | 2.69 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:55 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1091170018 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1091170018 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.379301478 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 1455404240 ps |
| CPU time | 1.94 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:54 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379301478 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.379301478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3651898515 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 184833770 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651898515 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3651898515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.3896767632 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 53876499 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:51 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896767632 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_smoke.3896767632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.2724480410 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 339800554 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724480410 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_stress_all.2724480410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.2744593233 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2739954133 ps |
| CPU time | 7.29 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:28:00 AM UTC 24 |
| Peak memory | 211688 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2744593233 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmg r_stress_all_with_rand_reset.2744593233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.1471540922 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 57310330 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1471540922 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup.1471540922 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.3123604224 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 226274675 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3123604224 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.pwrmgr_wakeup_reset.3123604224 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/18.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.304629829 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 102645055 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=304629829 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_aborted_low_power.304629829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.3281317444 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 83134593 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3281317444 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_disable_rom_integrity_check.3281317444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1259204427 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 33461247 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:00 AM UTC 24 |
| Peak memory | 206000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259204427 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_esc_clk_rst_malfunc.1259204427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.1463398240 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 431122570 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:01 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463398240 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_escalation_timeout.1463398240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.1082012471 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 62008807 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:00 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1082012471 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_glitch.1082012471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.1907967516 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 22640633 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:01 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1907967516 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_global_esc.1907967516 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_invalid.2266564876 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 54218239 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266564876 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_invalid.2266564876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.2324245307 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 128190279 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2324245307 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_lowpower_wakeup_race.2324245307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.2318199693 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 75814758 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2318199693 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset.2318199693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.3275532115 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 106495298 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:08 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275532115 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_reset_invalid.3275532115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.1482731244 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 93356968 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:01 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482731244 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_ctrl_config_regwen.1482731244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1645471321 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 882229637 ps |
| CPU time | 2.71 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:55 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645471321 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1645471321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1425155171 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 924512554 ps |
| CPU time | 2.17 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:55 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425155171 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1425155171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3400367967 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 257963593 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:01 AM UTC 24 |
| Peak memory | 208060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400367967 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3400367967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.210981122 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 30508267 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:52 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210981122 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_smoke.210981122 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.2561222755 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 1797410828 ps |
| CPU time | 6.38 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:24 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561222755 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_stress_all.2561222755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.1718679031 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 7175690795 ps |
| CPU time | 9.43 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:27 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1718679031 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmg r_stress_all_with_rand_reset.1718679031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.990119429 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 185911479 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:53 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=990119429 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup.990119429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.783494149 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 299857928 ps |
| CPU time | 1.31 seconds |
| Started | Sep 04 02:27:50 AM UTC 24 |
| Finished | Sep 04 02:27:54 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783494149 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.pwrmgr_wakeup_reset.783494149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/19.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_aborted_low_power.2548848439 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 80631963 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:26:32 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 210744 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548848439 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_aborted_low_power.2548848439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_esc_clk_rst_malfunc.3319861505 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 32219499 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319861505 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_esc_clk_rst_malfunc.3319861505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_escalation_timeout.310589138 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 727994131 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310589138 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_escalation_timeout.310589138 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_glitch.3760948182 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 24829288 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760948182 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_glitch.3760948182 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_global_esc.3861872117 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 43285718 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861872117 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_global_esc.3861872117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_invalid.3589232383 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 143483165 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589232383 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_invalid.3589232383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_lowpower_wakeup_race.100926357 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 278981592 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 208220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100926357 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_lowpower_wakeup_race.100926357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset.1351921171 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 94358917 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:34 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1351921171 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset.1351921171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_reset_invalid.2863278830 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 147702471 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2863278830 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_reset_invalid.2863278830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm.2018197161 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 933634112 ps |
| CPU time | 1.4 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:36 AM UTC 24 |
| Peak memory | 236880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2018197161 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm.2018197161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_ctrl_config_regwen.98978795 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 573823543 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98978795 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_ctrl_config_regwen.98978795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3075052964 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 1813776616 ps |
| CPU time | 2.06 seconds |
| Started | Sep 04 02:26:32 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3075052964 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3075052964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2553372795 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 1355217287 ps |
| CPU time | 2.25 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:36 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553372795 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.2553372795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1636409219 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 53524478 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636409219 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_sec_cm_rstmgr_intersig_mubi.1636409219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_smoke.3593569570 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 29401617 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3593569570 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_smoke.3593569570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all.4135337738 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 5357228628 ps |
| CPU time | 3.34 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:38 AM UTC 24 |
| Peak memory | 211516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4135337738 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_stress_all.4135337738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_stress_all_with_rand_reset.1537194599 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4568716224 ps |
| CPU time | 14.4 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:49 AM UTC 24 |
| Peak memory | 211520 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1537194599 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr _stress_all_with_rand_reset.1537194599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup.1761952481 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 141468625 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:26:31 AM UTC 24 |
| Finished | Sep 04 02:26:33 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1761952481 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup.1761952481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/2.pwrmgr_wakeup_reset.3007579589 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 277225954 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 02:26:32 AM UTC 24 |
| Finished | Sep 04 02:26:34 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007579589 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.pwrmgr_wakeup_reset.3007579589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/2.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.1895629169 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 30447429 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1895629169 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_aborted_low_power.1895629169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.210973158 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 54138328 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210973158 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_disable_rom_integrity_check.210973158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.2191936271 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 30328376 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191936271 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_esc_clk_rst_malfunc.2191936271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.210820478 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 273890123 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210820478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_escalation_timeout.210820478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.3695601417 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 38572966 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3695601417 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_glitch.3695601417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.2378030436 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 39708205 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378030436 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_global_esc.2378030436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_invalid.151802742 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 46105590 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:25 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=151802742 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_invalid.151802742 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.2264435506 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 135704657 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2264435506 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_lowpower_wakeup_race.2264435506 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.1143299290 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 51710787 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143299290 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset.1143299290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.3644686499 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 152456325 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:19 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3644686499 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_reset_invalid.3644686499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.4162178933 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 133470232 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 210388 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4162178933 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_ctrl_config_regwen.4162178933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.457194195 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 814611447 ps |
| CPU time | 1.98 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:03 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457194195 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.457194195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3749270603 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 900874246 ps |
| CPU time | 3.13 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:05 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3749270603 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3749270603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2302032428 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 67807857 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 207992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2302032428 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2302032428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.772899394 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 47129439 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772899394 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_smoke.772899394 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.884219100 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 605762797 ps |
| CPU time | 2.12 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:27 AM UTC 24 |
| Peak memory | 211544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=884219100 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_stress_all.884219100 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.3827047166 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 6955123006 ps |
| CPU time | 8.95 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:34 AM UTC 24 |
| Peak memory | 211504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3827047166 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmg r_stress_all_with_rand_reset.3827047166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.945168205 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 412146569 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=945168205 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup.945168205 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.1702801455 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 228647302 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:27:59 AM UTC 24 |
| Finished | Sep 04 02:28:02 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1702801455 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.pwrmgr_wakeup_reset.1702801455 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/20.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.2639060265 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 29072095 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639060265 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_aborted_low_power.2639060265 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.726941171 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 58408491 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=726941171 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_disable_rom_integrity_check.726941171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2247192304 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 33947435 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247192304 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_esc_clk_rst_malfunc.2247192304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.4169044519 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 111198765 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169044519 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_escalation_timeout.4169044519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.1243729142 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 65481871 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243729142 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_glitch.1243729142 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.2550368735 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 33650040 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2550368735 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_global_esc.2550368735 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_invalid.2683590311 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 43893010 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2683590311 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_invalid.2683590311 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.3857874238 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 163372917 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3857874238 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_lowpower_wakeup_race.3857874238 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.473967188 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 56733724 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=473967188 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset.473967188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.1348139953 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 101397771 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1348139953 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_reset_invalid.1348139953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.2850785931 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 265491953 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2850785931 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_ctrl_config_regwen.2850785931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2721186854 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 1059489084 ps |
| CPU time | 1.89 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:14 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2721186854 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2721186854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1676350686 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 806055079 ps |
| CPU time | 2.77 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:15 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1676350686 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1676350686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.4216279299 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 66626710 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4216279299 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_sec_cm_rstmgr_intersig_mubi.4216279299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.683079472 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 37292457 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=683079472 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_smoke.683079472 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.100676587 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 411883191 ps |
| CPU time | 1.64 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:24 AM UTC 24 |
| Peak memory | 210700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=100676587 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_stress_all.100676587 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.24832149 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 4627240610 ps |
| CPU time | 3.66 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=24832149 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_ stress_all_with_rand_reset.24832149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.1684906700 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 362293637 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1684906700 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup.1684906700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.481529415 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 156998183 ps |
| CPU time | 0.94 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481529415 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.pwrmgr_wakeup_reset.481529415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/21.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.1675241915 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 186298511 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1675241915 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_aborted_low_power.1675241915 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3554174664 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 59494119 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 211092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3554174664 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_disable_rom_integrity_check.3554174664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.3147789607 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 32898735 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3147789607 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_esc_clk_rst_malfunc.3147789607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.337567373 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 199369424 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=337567373 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_escalation_timeout.337567373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.2812645346 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 60474723 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2812645346 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_glitch.2812645346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.1992241085 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 45419651 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 208092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1992241085 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_global_esc.1992241085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_invalid.394111706 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 54038826 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394111706 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_invalid.394111706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.4138974890 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 223288201 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138974890 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_lowpower_wakeup_race.4138974890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.1228693824 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 73588669 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1228693824 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset.1228693824 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.2393587353 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 183109766 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:19 AM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2393587353 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_reset_invalid.2393587353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.3922339366 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 136351205 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:19 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3922339366 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_ctrl_config_regwen.3922339366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3662639935 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2236794398 ps |
| CPU time | 1.81 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:19 AM UTC 24 |
| Peak memory | 210536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3662639935 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3662639935 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.278088354 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 1155825941 ps |
| CPU time | 2.19 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:20 AM UTC 24 |
| Peak memory | 211412 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278088354 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.278088354 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.25200900 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 146880529 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 207988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25200900 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_sec_cm_rstmgr_intersig_mubi.25200900 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.167641266 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 57178278 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:28:00 AM UTC 24 |
| Finished | Sep 04 02:28:13 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=167641266 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_smoke.167641266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.690475004 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 88795669 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:19 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690475004 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_stress_all.690475004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.1398434764 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 3649285557 ps |
| CPU time | 10.45 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:28 AM UTC 24 |
| Peak memory | 211500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1398434764 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmg r_stress_all_with_rand_reset.1398434764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.3763394906 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 212801101 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:08 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763394906 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup.3763394906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.3748795231 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 102301933 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:28:05 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 211104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3748795231 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.pwrmgr_wakeup_reset.3748795231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/22.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.1217635481 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 58174209 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:25 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217635481 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_aborted_low_power.1217635481 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.3247642588 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 53431829 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3247642588 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_disable_rom_integrity_check.3247642588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.3707807167 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 38149041 ps |
| CPU time | 0.49 seconds |
| Started | Sep 04 02:28:09 AM UTC 24 |
| Finished | Sep 04 02:28:17 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3707807167 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_esc_clk_rst_malfunc.3707807167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.3272140995 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 421395959 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272140995 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_escalation_timeout.3272140995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.2661463204 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 42203484 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661463204 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_glitch.2661463204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.1986742503 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 75512783 ps |
| CPU time | 0.5 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1986742503 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_global_esc.1986742503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_invalid.213252223 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 77393141 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=213252223 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_invalid.213252223 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.2279287709 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 184791002 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 208196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2279287709 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_lowpower_wakeup_race.2279287709 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.3271417799 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 158526916 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:25 AM UTC 24 |
| Peak memory | 210832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271417799 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset.3271417799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.1776126678 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 118280167 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776126678 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_reset_invalid.1776126678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.166495865 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 73637374 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=166495865 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_ctrl_config_regwen.166495865 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2946933995 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 1839995524 ps |
| CPU time | 1.76 seconds |
| Started | Sep 04 02:28:07 AM UTC 24 |
| Finished | Sep 04 02:28:27 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2946933995 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2946933995 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1485184087 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 3543087151 ps |
| CPU time | 1.79 seconds |
| Started | Sep 04 02:28:07 AM UTC 24 |
| Finished | Sep 04 02:28:27 AM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485184087 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1485184087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3243379193 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 140141827 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:28:09 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3243379193 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3243379193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.901920700 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 29757628 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901920700 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_smoke.901920700 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2682118097 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 3396640457 ps |
| CPU time | 4.75 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:22 AM UTC 24 |
| Peak memory | 211708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2682118097 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_stress_all.2682118097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.4166291955 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 3211273364 ps |
| CPU time | 6.15 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:24 AM UTC 24 |
| Peak memory | 211384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4166291955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmg r_stress_all_with_rand_reset.4166291955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.651017791 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 57989053 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 208252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=651017791 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup.651017791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.3732847211 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 240556627 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 02:28:06 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3732847211 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.pwrmgr_wakeup_reset.3732847211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/23.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.3403969119 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 42043837 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 208024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403969119 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_aborted_low_power.3403969119 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.3313491637 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 62281042 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313491637 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_disable_rom_integrity_check.3313491637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.3961083004 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 35521560 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3961083004 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_esc_clk_rst_malfunc.3961083004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.875955988 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 1325802128 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875955988 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_escalation_timeout.875955988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.454500321 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 61518997 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=454500321 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_glitch.454500321 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.2941498510 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 54577163 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2941498510 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_global_esc.2941498510 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_invalid.2081091959 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 48507980 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:30 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081091959 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_invalid.2081091959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.4096219226 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 77233219 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:28:17 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4096219226 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_lowpower_wakeup_race.4096219226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.3725995554 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 98763531 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725995554 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset.3725995554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.1703073676 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 146892226 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1703073676 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_reset_invalid.1703073676 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.3198104442 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 107048929 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3198104442 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_ctrl_config_regwen.3198104442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1714225488 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 852222718 ps |
| CPU time | 2.3 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:25 AM UTC 24 |
| Peak memory | 210872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1714225488 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1714225488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.447633909 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 887976447 ps |
| CPU time | 2.93 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:25 AM UTC 24 |
| Peak memory | 211308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=447633909 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.447633909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1975072499 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 76161488 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:28:20 AM UTC 24 |
| Finished | Sep 04 02:28:23 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1975072499 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_sec_cm_rstmgr_intersig_mubi.1975072499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.2301688579 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 57804243 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:28:15 AM UTC 24 |
| Finished | Sep 04 02:28:18 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301688579 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_smoke.2301688579 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.2082925062 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 231741465 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2082925062 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_stress_all.2082925062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.3674301325 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 988934251 ps |
| CPU time | 4.37 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:34 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3674301325 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmg r_stress_all_with_rand_reset.3674301325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.3045078498 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 281961828 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 02:28:17 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3045078498 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup.3045078498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.3740933502 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 72943829 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:28:17 AM UTC 24 |
| Finished | Sep 04 02:28:26 AM UTC 24 |
| Peak memory | 210896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740933502 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.pwrmgr_wakeup_reset.3740933502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/24.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.2708125628 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 24357490 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2708125628 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_aborted_low_power.2708125628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.705247763 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 102572986 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705247763 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_disable_rom_integrity_check.705247763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3758226083 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 29604247 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758226083 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_esc_clk_rst_malfunc.3758226083 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.64991330 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 108229560 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64991330 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ= pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_escalation_timeout.64991330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.2121150910 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 40691711 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2121150910 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_glitch.2121150910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.2046343901 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 57522731 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046343901 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_global_esc.2046343901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_invalid.2405238960 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 42806256 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405238960 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_invalid.2405238960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.775163567 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 118828929 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775163567 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_lowpower_wakeup_race.775163567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.28996304 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 148483523 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28996304 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset.28996304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.794837161 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 98512384 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794837161 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_reset_invalid.794837161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.218002753 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 135594095 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218002753 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_ctrl_config_regwen.218002753 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3987101576 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 749345961 ps |
| CPU time | 2.61 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987101576 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3987101576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1338238344 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 1401948554 ps |
| CPU time | 2.03 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:32 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1338238344 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1338238344 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2559082180 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 108108120 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2559082180 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_sec_cm_rstmgr_intersig_mubi.2559082180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.3267449037 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 39101167 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:30 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3267449037 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_smoke.3267449037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.4010177369 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 2156903536 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:35 AM UTC 24 |
| Peak memory | 211552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4010177369 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_stress_all.4010177369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all_with_rand_reset.1040078704 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 1978080692 ps |
| CPU time | 7.62 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:39 AM UTC 24 |
| Peak memory | 211532 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1040078704 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmg r_stress_all_with_rand_reset.1040078704 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.314943365 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 218999482 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=314943365 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup.314943365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.2377696015 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 503290258 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:31 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377696015 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.pwrmgr_wakeup_reset.2377696015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/25.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.2370558498 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 74891756 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2370558498 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_aborted_low_power.2370558498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.3850088488 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 81034579 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:28:43 AM UTC 24 |
| Finished | Sep 04 02:28:45 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850088488 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_disable_rom_integrity_check.3850088488 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.3879612426 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 37695046 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3879612426 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_esc_clk_rst_malfunc.3879612426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.1855487586 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 382395244 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855487586 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_escalation_timeout.1855487586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.2534806530 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 41772433 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534806530 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_glitch.2534806530 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.3829365385 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 77013423 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:32 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829365385 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_global_esc.3829365385 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_invalid.3129621705 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 64059397 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:28:43 AM UTC 24 |
| Finished | Sep 04 02:28:45 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129621705 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_invalid.3129621705 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.3719661515 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 512022715 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 208164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3719661515 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_lowpower_wakeup_race.3719661515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.3619719212 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 47978404 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:32 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619719212 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset.3619719212 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.385448803 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 93634926 ps |
| CPU time | 1 seconds |
| Started | Sep 04 02:28:43 AM UTC 24 |
| Finished | Sep 04 02:28:45 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385448803 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_reset_invalid.385448803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.1326811006 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 108924374 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326811006 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_ctrl_config_regwen.1326811006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.656659196 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 825612304 ps |
| CPU time | 2.09 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:34 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=656659196 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.656659196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1994973044 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 850736571 ps |
| CPU time | 2.57 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:35 AM UTC 24 |
| Peak memory | 211272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1994973044 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1994973044 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1598902073 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 65511831 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:28:30 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1598902073 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_sec_cm_rstmgr_intersig_mubi.1598902073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.2196100226 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 35877217 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:32 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196100226 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_smoke.2196100226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.3959950708 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 1586589465 ps |
| CPU time | 4.54 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:49 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3959950708 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_stress_all.3959950708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all_with_rand_reset.1105700436 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 1960957334 ps |
| CPU time | 2.94 seconds |
| Started | Sep 04 02:28:43 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 211508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1105700436 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmg r_stress_all_with_rand_reset.1105700436 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.3100737757 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 100178726 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:32 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100737757 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup.3100737757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.59061349 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 158170869 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 02:28:29 AM UTC 24 |
| Finished | Sep 04 02:28:33 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=59061349 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_202 4_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.pwrmgr_wakeup_reset.59061349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/26.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.3136854695 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 42416138 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:45 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3136854695 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_aborted_low_power.3136854695 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_disable_rom_integrity_check.445639280 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 92166366 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445639280 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_disable_rom_integrity_check.445639280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_esc_clk_rst_malfunc.1009901962 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 32632288 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 207860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009901962 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_esc_clk_rst_malfunc.1009901962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_escalation_timeout.1190566485 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 382215032 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190566485 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_escalation_timeout.1190566485 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_glitch.976407390 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 75388945 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 206032 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976407390 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_glitch.976407390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_global_esc.874992031 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 294718137 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874992031 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_global_esc.874992031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_invalid.1571256343 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 107881126 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571256343 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_invalid.1571256343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.4270954323 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 312418331 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4270954323 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_lowpower_wakeup_race.4270954323 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.3996742101 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 125499940 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:45 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996742101 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset.3996742101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset_invalid.728230366 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 183112966 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728230366 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_reset_invalid.728230366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_ctrl_config_regwen.1392877077 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 112249574 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 209824 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1392877077 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_ctrl_config_regwen.1392877077 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2969862288 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 781712979 ps |
| CPU time | 2.69 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:48 AM UTC 24 |
| Peak memory | 211280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2969862288 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2969862288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2378545777 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 793843712 ps |
| CPU time | 2.32 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2378545777 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2378545777 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_sec_cm_rstmgr_intersig_mubi.222892625 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 71688937 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=222892625 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_sec_cm_rstmgr_intersig_mubi.222892625 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.2230214387 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 104264871 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:45 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2230214387 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_smoke.2230214387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all.3982362006 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 616990664 ps |
| CPU time | 2.33 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:48 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982362006 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_stress_all.3982362006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_stress_all_with_rand_reset.786706884 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 5030592675 ps |
| CPU time | 10.79 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:56 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=786706884 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr _stress_all_with_rand_reset.786706884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.2914574428 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 145881740 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2914574428 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup.2914574428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.985279647 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 157310800 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:45 AM UTC 24 |
| Peak memory | 210736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985279647 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.pwrmgr_wakeup_reset.985279647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/27.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.4234269381 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 42720003 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234269381 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_aborted_low_power.4234269381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.3769633747 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 58612460 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769633747 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_disable_rom_integrity_check.3769633747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_esc_clk_rst_malfunc.3227421950 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 38239707 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3227421950 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_esc_clk_rst_malfunc.3227421950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.3980638722 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 112166875 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980638722 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_escalation_timeout.3980638722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_glitch.1375329546 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 39500734 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375329546 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_glitch.1375329546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_global_esc.2806309069 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 25392152 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806309069 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_global_esc.2806309069 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_invalid.3551037252 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 43694626 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551037252 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_invalid.3551037252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_lowpower_wakeup_race.937387836 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 340781169 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=937387836 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_lowpower_wakeup_race.937387836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset.1512253413 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 57151876 ps |
| CPU time | 0.85 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1512253413 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset.1512253413 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_reset_invalid.1712678572 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 112329850 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712678572 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_reset_invalid.1712678572 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_ctrl_config_regwen.1113614645 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 279206121 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1113614645 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_ctrl_config_regwen.1113614645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3379349114 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 842385021 ps |
| CPU time | 2.97 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:49 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379349114 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3379349114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.769727955 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 963808826 ps |
| CPU time | 3.14 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:49 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769727955 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.769727955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2191321340 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 170947583 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191321340 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2191321340 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_smoke.2834172406 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 31795105 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2834172406 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_smoke.2834172406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all.1905511101 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 2519752711 ps |
| CPU time | 3.55 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:49 AM UTC 24 |
| Peak memory | 211644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905511101 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_stress_all.1905511101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_stress_all_with_rand_reset.3906853310 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 1673721572 ps |
| CPU time | 3.51 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:49 AM UTC 24 |
| Peak memory | 211368 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3906853310 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmg r_stress_all_with_rand_reset.3906853310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup.2123568457 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 142717545 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123568457 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup.2123568457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_wakeup_reset.4090865059 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 684542436 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:28:44 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4090865059 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.pwrmgr_wakeup_reset.4090865059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/28.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_aborted_low_power.2405265896 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 46458485 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2405265896 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_aborted_low_power.2405265896 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_disable_rom_integrity_check.1069849143 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 59373837 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 211928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1069849143 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_disable_rom_integrity_check.1069849143 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_esc_clk_rst_malfunc.460013403 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 29394953 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460013403 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_esc_clk_rst_malfunc.460013403 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_escalation_timeout.9094339 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 591861313 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 208272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=9094339 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=p wrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_escalation_timeout.9094339 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_glitch.2771762341 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 47853924 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771762341 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_glitch.2771762341 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_global_esc.3521194647 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 27807898 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3521194647 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_global_esc.3521194647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_invalid.104596517 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 50583877 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=104596517 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_invalid.104596517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_lowpower_wakeup_race.3146238957 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 309101130 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146238957 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_lowpower_wakeup_race.3146238957 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset.306076407 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 78713217 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306076407 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset.306076407 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_reset_invalid.4066527833 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 102908226 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 219964 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4066527833 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_reset_invalid.4066527833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_ctrl_config_regwen.1174753889 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 310714459 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174753889 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_ctrl_config_regwen.1174753889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.371409477 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 916072883 ps |
| CPU time | 2.86 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:49 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=371409477 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.371409477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1170329534 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 73252417 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170329534 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_sec_cm_rstmgr_intersig_mubi.1170329534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_smoke.1143845589 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 34299567 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:46 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143845589 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_smoke.1143845589 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all.102188395 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 1665071591 ps |
| CPU time | 5.78 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:07 AM UTC 24 |
| Peak memory | 211488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102188395 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_stress_all.102188395 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_stress_all_with_rand_reset.892187582 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 2841265503 ps |
| CPU time | 8.68 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 211588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=892187582 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr _stress_all_with_rand_reset.892187582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup.1744424710 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 227904613 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 207944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744424710 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup.1744424710 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/29.pwrmgr_wakeup_reset.3020507649 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 304798019 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 02:28:45 AM UTC 24 |
| Finished | Sep 04 02:28:47 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020507649 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.pwrmgr_wakeup_reset.3020507649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/29.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_aborted_low_power.3346357342 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 36401022 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:38 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3346357342 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_aborted_low_power.3346357342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_disable_rom_integrity_check.1645534353 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 68610873 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:58 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1645534353 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_disable_rom_integrity_check.1645534353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_esc_clk_rst_malfunc.4247489618 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 29805148 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:45 AM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4247489618 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_esc_clk_rst_malfunc.4247489618 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_escalation_timeout.1771288089 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 397277140 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:58 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771288089 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_escalation_timeout.1771288089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_glitch.4237014050 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 43238404 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:58 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237014050 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_glitch.4237014050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_global_esc.962058981 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 40505435 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:45 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=962058981 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_global_esc.962058981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_invalid.1670952103 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 45156888 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:58 AM UTC 24 |
| Peak memory | 210740 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1670952103 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_invalid.1670952103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_lowpower_wakeup_race.475728544 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 263707350 ps |
| CPU time | 1.07 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:38 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475728544 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_lowpower_wakeup_race.475728544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset.1325611536 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 35804446 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325611536 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset.1325611536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_reset_invalid.3913031573 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 114068732 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:58 AM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3913031573 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_reset_invalid.3913031573 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm.4098351655 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 916648436 ps |
| CPU time | 1.55 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:59 AM UTC 24 |
| Peak memory | 236884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098351655 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm.4098351655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_ctrl_config_regwen.3149833198 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 33418562 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:45 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149833198 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_ctrl_config_regwen.3149833198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.754874486 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 2278176604 ps |
| CPU time | 1.79 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:45 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754874486 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_lc_ctrl_intersig _mubi.754874486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.47898131 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 840101452 ps |
| CPU time | 2.98 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:40 AM UTC 24 |
| Peak memory | 211212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=47898131 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rom_ctrl_intersi g_mubi.47898131 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2956667701 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 64724101 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:45 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956667701 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_sec_cm_rstmgr_intersig_mubi.2956667701 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_smoke.1828324233 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 31409931 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:26:33 AM UTC 24 |
| Finished | Sep 04 02:26:35 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828324233 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_smoke.1828324233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_stress_all.4046819790 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 2581479585 ps |
| CPU time | 3.6 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:27:01 AM UTC 24 |
| Peak memory | 211668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4046819790 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_stress_all.4046819790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup.2008592329 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 256556511 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:38 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008592329 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup.2008592329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/3.pwrmgr_wakeup_reset.1726941170 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 194539181 ps |
| CPU time | 1.05 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:38 AM UTC 24 |
| Peak memory | 210536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1726941170 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.pwrmgr_wakeup_reset.1726941170 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/3.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_aborted_low_power.3653515004 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 43670188 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3653515004 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_aborted_low_power.3653515004 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_disable_rom_integrity_check.1056973740 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 69533882 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056973740 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_disable_rom_integrity_check.1056973740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_esc_clk_rst_malfunc.2534012169 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 37738626 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 206192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2534012169 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_esc_clk_rst_malfunc.2534012169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_escalation_timeout.1728109977 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 376693617 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728109977 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_escalation_timeout.1728109977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_glitch.2631939992 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 47090547 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2631939992 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_glitch.2631939992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_global_esc.4276976559 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 27175238 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276976559 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_global_esc.4276976559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_invalid.1196973596 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 73096943 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1196973596 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_invalid.1196973596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_lowpower_wakeup_race.110991525 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 113436489 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=110991525 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_lowpower_wakeup_race.110991525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset.3594609860 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 80876927 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594609860 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset.3594609860 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_reset_invalid.1920678718 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 91926064 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920678718 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_reset_invalid.1920678718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_ctrl_config_regwen.1794601850 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 249853964 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794601850 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_ctrl_config_regwen.1794601850 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.88816392 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 888004510 ps |
| CPU time | 2.75 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:04 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=88816392 -ass ert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_lc_ctrl_intersig _mubi.88816392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4221219666 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 860474384 ps |
| CPU time | 2.65 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:04 AM UTC 24 |
| Peak memory | 211064 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4221219666 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4221219666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4172724460 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 94536596 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 208024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172724460 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_sec_cm_rstmgr_intersig_mubi.4172724460 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_smoke.2305351017 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 27203581 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:02 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305351017 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_smoke.2305351017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all.956860094 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 232847209 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956860094 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_stress_all.956860094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_stress_all_with_rand_reset.1147964955 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 6694579644 ps |
| CPU time | 9.28 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:11 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1147964955 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmg r_stress_all_with_rand_reset.1147964955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup.4012469313 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 226704608 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4012469313 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup.4012469313 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/30.pwrmgr_wakeup_reset.3215288201 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 275986173 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:29:00 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215288201 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.pwrmgr_wakeup_reset.3215288201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/30.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_aborted_low_power.3947474494 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 25408855 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947474494 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_aborted_low_power.3947474494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_disable_rom_integrity_check.516405153 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 77540925 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 211040 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=516405153 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_disable_rom_integrity_check.516405153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_esc_clk_rst_malfunc.2010455556 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 30405839 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2010455556 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_esc_clk_rst_malfunc.2010455556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_escalation_timeout.4201698596 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 331637808 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201698596 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_escalation_timeout.4201698596 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_glitch.3046804231 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 64611472 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 206596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046804231 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_glitch.3046804231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_global_esc.1781576301 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 22939570 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 206816 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1781576301 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_global_esc.1781576301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_invalid.1053601820 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 52807921 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 210836 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053601820 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_invalid.1053601820 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_lowpower_wakeup_race.3908285363 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 401647461 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 208220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3908285363 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_lowpower_wakeup_race.3908285363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset.22671971 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 39184739 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22671971 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset.22671971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_reset_invalid.3486020268 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 245479153 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3486020268 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_reset_invalid.3486020268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_ctrl_config_regwen.1649137085 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 304888191 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1649137085 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_ctrl_config_regwen.1649137085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1594722050 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 1250426074 ps |
| CPU time | 2.05 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:04 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1594722050 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1594722050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.331412671 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 1332340867 ps |
| CPU time | 2.05 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:04 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331412671 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.331412671 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1908313415 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 104218377 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1908313415 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_sec_cm_rstmgr_intersig_mubi.1908313415 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_smoke.1824010235 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 48549675 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824010235 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_smoke.1824010235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all.3059397386 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 1050017276 ps |
| CPU time | 1.95 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:11 AM UTC 24 |
| Peak memory | 210456 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3059397386 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_stress_all.3059397386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_stress_all_with_rand_reset.985950631 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 1262798169 ps |
| CPU time | 3.75 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:13 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=985950631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr _stress_all_with_rand_reset.985950631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup.3220626477 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 245933693 ps |
| CPU time | 1.09 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220626477 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup.3220626477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/31.pwrmgr_wakeup_reset.857662388 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 112490162 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:03 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=857662388 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.pwrmgr_wakeup_reset.857662388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/31.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_aborted_low_power.3792506060 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 185802091 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792506060 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_aborted_low_power.3792506060 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_disable_rom_integrity_check.6079951 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 68071811 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 209312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=6079951 -assert nopostproc +UVM_TESTNAME=pwrmgr_ base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_ regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_disable_rom_integrity_check.6079951 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_esc_clk_rst_malfunc.4172994683 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 31350597 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172994683 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_esc_clk_rst_malfunc.4172994683 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_escalation_timeout.1655830878 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 111154895 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655830878 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_escalation_timeout.1655830878 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_glitch.2740614612 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 75736790 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 206700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2740614612 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_glitch.2740614612 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_global_esc.2573146277 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 46445895 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:29:02 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2573146277 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_global_esc.2573146277 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_invalid.3955562000 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 57885024 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208988 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955562000 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_invalid.3955562000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_lowpower_wakeup_race.4281628578 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 138294388 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4281628578 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_lowpower_wakeup_race.4281628578 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset.3652275923 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 62795887 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652275923 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset.3652275923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_reset_invalid.2284916522 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 119986915 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2284916522 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_reset_invalid.2284916522 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_ctrl_config_regwen.3395527070 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 270473210 ps |
| CPU time | 1.12 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:11 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3395527070 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_ctrl_config_regwen.3395527070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2272822171 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 1111381787 ps |
| CPU time | 1.84 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:12 AM UTC 24 |
| Peak memory | 208884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2272822171 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2272822171 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4000981030 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 985228978 ps |
| CPU time | 1.88 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:12 AM UTC 24 |
| Peak memory | 208920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000981030 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.4000981030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3525699391 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 160278919 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:11 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3525699391 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_sec_cm_rstmgr_intersig_mubi.3525699391 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_smoke.3777557561 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 27941251 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777557561 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_smoke.3777557561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all.1371253135 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2382137537 ps |
| CPU time | 3.47 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:22 AM UTC 24 |
| Peak memory | 211460 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371253135 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_stress_all.1371253135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_stress_all_with_rand_reset.3518237890 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 624268590 ps |
| CPU time | 2.82 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:22 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3518237890 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmg r_stress_all_with_rand_reset.3518237890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup.2025645926 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 32041210 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:10 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2025645926 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup.2025645926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/32.pwrmgr_wakeup_reset.1107826774 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 262765434 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 02:29:01 AM UTC 24 |
| Finished | Sep 04 02:29:11 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1107826774 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.pwrmgr_wakeup_reset.1107826774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/32.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_aborted_low_power.1972159696 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 27818786 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972159696 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_aborted_low_power.1972159696 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_disable_rom_integrity_check.3912761101 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 71186991 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912761101 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_disable_rom_integrity_check.3912761101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_esc_clk_rst_malfunc.712657970 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 28908545 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 205452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=712657970 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_esc_clk_rst_malfunc.712657970 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_escalation_timeout.143425924 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 175473760 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143425924 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_escalation_timeout.143425924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_glitch.862772548 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 48525644 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862772548 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_glitch.862772548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_global_esc.1297567648 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 50791560 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297567648 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_global_esc.1297567648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_invalid.1746855434 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 69106852 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1746855434 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_invalid.1746855434 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_lowpower_wakeup_race.854087110 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 319523083 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=854087110 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_lowpower_wakeup_race.854087110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset.591563773 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 85954933 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 209468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=591563773 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset.591563773 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_reset_invalid.1948609795 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 154582274 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1948609795 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_reset_invalid.1948609795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_ctrl_config_regwen.2225595115 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 122920150 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2225595115 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_ctrl_config_regwen.2225595115 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.762685941 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 1318459376 ps |
| CPU time | 1.84 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 210384 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762685941 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.762685941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1382496694 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 1184710449 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 209920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382496694 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1382496694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2806048734 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 164110676 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806048734 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_sec_cm_rstmgr_intersig_mubi.2806048734 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_smoke.3219733076 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 30782965 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219733076 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_smoke.3219733076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all.2728794665 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 3580905296 ps |
| CPU time | 4.36 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:24 AM UTC 24 |
| Peak memory | 211640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728794665 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_stress_all.2728794665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_stress_all_with_rand_reset.2629169609 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2635186498 ps |
| CPU time | 5.42 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:25 AM UTC 24 |
| Peak memory | 211444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2629169609 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmg r_stress_all_with_rand_reset.2629169609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup.2062725169 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 157017569 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2062725169 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup.2062725169 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/33.pwrmgr_wakeup_reset.1993989493 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 52941047 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:20 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1993989493 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.pwrmgr_wakeup_reset.1993989493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/33.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_aborted_low_power.1913134099 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 67750744 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1913134099 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_aborted_low_power.1913134099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_disable_rom_integrity_check.509145549 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 92995439 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=509145549 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_disable_rom_integrity_check.509145549 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_esc_clk_rst_malfunc.37248374 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 29556728 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 206176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=37248374 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress ion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_esc_clk_rst_malfunc.37248374 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_escalation_timeout.1674670903 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 388329609 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 206160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674670903 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_escalation_timeout.1674670903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_glitch.3515567893 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 72641632 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3515567893 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_glitch.3515567893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_global_esc.1067282017 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 30626486 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1067282017 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_global_esc.1067282017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_invalid.940964976 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 43695851 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=940964976 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_invalid.940964976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_lowpower_wakeup_race.394187638 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 281490295 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=394187638 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_lowpower_wakeup_race.394187638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset.1403530226 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 82974128 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403530226 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset.1403530226 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_reset_invalid.587499868 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 273218049 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587499868 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_reset_invalid.587499868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_ctrl_config_regwen.153933767 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 278215643 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=153933767 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_ctrl_config_regwen.153933767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1211501295 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 1794478812 ps |
| CPU time | 2.07 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:22 AM UTC 24 |
| Peak memory | 211232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211501295 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1211501295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.435289969 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 1305333964 ps |
| CPU time | 2.08 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:22 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435289969 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.435289969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2893926357 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 53126698 ps |
| CPU time | 0.94 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893926357 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_sec_cm_rstmgr_intersig_mubi.2893926357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_smoke.3818107113 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 30398073 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:29:18 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3818107113 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_smoke.3818107113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all.537861725 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 1491034156 ps |
| CPU time | 3.07 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:23 AM UTC 24 |
| Peak memory | 210640 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537861725 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_stress_all.537861725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_stress_all_with_rand_reset.3716406694 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 6810255778 ps |
| CPU time | 8.91 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:29 AM UTC 24 |
| Peak memory | 211596 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3716406694 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmg r_stress_all_with_rand_reset.3716406694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup.1646408870 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 95664324 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1646408870 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup.1646408870 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/34.pwrmgr_wakeup_reset.2411595568 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 364817488 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2411595568 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.pwrmgr_wakeup_reset.2411595568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/34.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_aborted_low_power.1189702925 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 183192879 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1189702925 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_aborted_low_power.1189702925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_disable_rom_integrity_check.99100477 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 65824187 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:29:38 AM UTC 24 |
| Finished | Sep 04 02:29:40 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99100477 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_disable_rom_integrity_check.99100477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_esc_clk_rst_malfunc.1787132925 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 48229332 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1787132925 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_esc_clk_rst_malfunc.1787132925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_escalation_timeout.3310499975 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 385809202 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:29:38 AM UTC 24 |
| Finished | Sep 04 02:29:40 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3310499975 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_escalation_timeout.3310499975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_glitch.130507634 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 74397876 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:29:38 AM UTC 24 |
| Finished | Sep 04 02:29:40 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130507634 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_glitch.130507634 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_global_esc.2290461845 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 42986699 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:29:38 AM UTC 24 |
| Finished | Sep 04 02:29:40 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2290461845 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_global_esc.2290461845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_invalid.2039628030 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 51541411 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:41 AM UTC 24 |
| Peak memory | 210920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2039628030 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_invalid.2039628030 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_lowpower_wakeup_race.2994534330 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 249804595 ps |
| CPU time | 1.19 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:22 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2994534330 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_lowpower_wakeup_race.2994534330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset.3383104387 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 124161540 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 210552 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383104387 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset.3383104387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_reset_invalid.3082636102 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 151178995 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:29:39 AM UTC 24 |
| Finished | Sep 04 02:29:41 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3082636102 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_reset_invalid.3082636102 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_ctrl_config_regwen.4198172343 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 145456090 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:29:38 AM UTC 24 |
| Finished | Sep 04 02:29:40 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4198172343 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_ctrl_config_regwen.4198172343 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2146234258 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 823456991 ps |
| CPU time | 2.34 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:23 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2146234258 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2146234258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1636425751 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 832708112 ps |
| CPU time | 2.16 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:23 AM UTC 24 |
| Peak memory | 211340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1636425751 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1636425751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2791572793 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 479045002 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2791572793 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_sec_cm_rstmgr_intersig_mubi.2791572793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_smoke.3909231574 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 124239975 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909231574 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_smoke.3909231574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all.3668225888 |
| Short name | T773 |
| Test name | |
| Test status | |
| Simulation time | 2430237597 ps |
| CPU time | 3.48 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:44 AM UTC 24 |
| Peak memory | 211608 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668225888 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_stress_all.3668225888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_stress_all_with_rand_reset.3990967041 |
| Short name | T779 |
| Test name | |
| Test status | |
| Simulation time | 20988980704 ps |
| CPU time | 11.58 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:52 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3990967041 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmg r_stress_all_with_rand_reset.3990967041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup.1132489895 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 567059239 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132489895 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup.1132489895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/35.pwrmgr_wakeup_reset.393063039 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 172832050 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:29:19 AM UTC 24 |
| Finished | Sep 04 02:29:21 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=393063039 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.pwrmgr_wakeup_reset.393063039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/35.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_aborted_low_power.2856333278 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 55153153 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:41 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856333278 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_aborted_low_power.2856333278 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_disable_rom_integrity_check.1918010439 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 54475874 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1918010439 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_disable_rom_integrity_check.1918010439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_esc_clk_rst_malfunc.4033022348 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 40801786 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033022348 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_esc_clk_rst_malfunc.4033022348 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_escalation_timeout.1518721356 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 208482154 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518721356 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_escalation_timeout.1518721356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_glitch.352142047 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 41149871 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352142047 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_glitch.352142047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_global_esc.3127359111 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 40880841 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3127359111 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_global_esc.3127359111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_invalid.1275668489 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 44814011 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275668489 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_invalid.1275668489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_lowpower_wakeup_race.1367164925 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 245944842 ps |
| CPU time | 1.16 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367164925 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_lowpower_wakeup_race.1367164925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset.1141915445 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 61151723 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 210672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1141915445 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset.1141915445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_reset_invalid.3911561798 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 102060995 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 220172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3911561798 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_reset_invalid.3911561798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_ctrl_config_regwen.4044155670 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 163287061 ps |
| CPU time | 1 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044155670 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_ctrl_config_regwen.4044155670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2108679717 |
| Short name | T763 |
| Test name | |
| Test status | |
| Simulation time | 1319414853 ps |
| CPU time | 1.87 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2108679717 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2108679717 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1317960214 |
| Short name | T768 |
| Test name | |
| Test status | |
| Simulation time | 1186186023 ps |
| CPU time | 1.99 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 210416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317960214 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1317960214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_sec_cm_rstmgr_intersig_mubi.154148268 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 121152261 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154148268 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_sec_cm_rstmgr_intersig_mubi.154148268 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_smoke.1444575155 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 31446426 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:41 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444575155 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_smoke.1444575155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all.3678597892 |
| Short name | T774 |
| Test name | |
| Test status | |
| Simulation time | 901662413 ps |
| CPU time | 2.98 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:44 AM UTC 24 |
| Peak memory | 211292 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678597892 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_stress_all.3678597892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_stress_all_with_rand_reset.3698795992 |
| Short name | T780 |
| Test name | |
| Test status | |
| Simulation time | 10003007816 ps |
| CPU time | 12.3 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:54 AM UTC 24 |
| Peak memory | 211524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3698795992 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmg r_stress_all_with_rand_reset.3698795992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup.2568469767 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 321541421 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2568469767 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup.2568469767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/36.pwrmgr_wakeup_reset.3896939457 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 82049438 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896939457 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.pwrmgr_wakeup_reset.3896939457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/36.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_aborted_low_power.1722475906 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 104651242 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722475906 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_aborted_low_power.1722475906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_disable_rom_integrity_check.3030200636 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 93031517 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030200636 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_disable_rom_integrity_check.3030200636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_esc_clk_rst_malfunc.2824711029 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 32064284 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824711029 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_esc_clk_rst_malfunc.2824711029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_escalation_timeout.1323244939 |
| Short name | T760 |
| Test name | |
| Test status | |
| Simulation time | 211179080 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323244939 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_escalation_timeout.1323244939 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_glitch.2877672854 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 61382444 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877672854 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_glitch.2877672854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_global_esc.2612755889 |
| Short name | T754 |
| Test name | |
| Test status | |
| Simulation time | 91390847 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 206080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612755889 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_global_esc.2612755889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_invalid.3345627235 |
| Short name | T758 |
| Test name | |
| Test status | |
| Simulation time | 82766221 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3345627235 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_invalid.3345627235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_lowpower_wakeup_race.4101513117 |
| Short name | T755 |
| Test name | |
| Test status | |
| Simulation time | 398239126 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101513117 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_lowpower_wakeup_race.4101513117 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset.169610962 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 154227195 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=169610962 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset.169610962 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_reset_invalid.4031922021 |
| Short name | T759 |
| Test name | |
| Test status | |
| Simulation time | 127034414 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 220092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4031922021 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_reset_invalid.4031922021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_ctrl_config_regwen.2616779489 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 147787756 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616779489 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_ctrl_config_regwen.2616779489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1967793503 |
| Short name | T772 |
| Test name | |
| Test status | |
| Simulation time | 951329026 ps |
| CPU time | 2.4 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:44 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967793503 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1967793503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3408777113 |
| Short name | T775 |
| Test name | |
| Test status | |
| Simulation time | 802007462 ps |
| CPU time | 2.77 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:44 AM UTC 24 |
| Peak memory | 211404 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3408777113 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3408777113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_sec_cm_rstmgr_intersig_mubi.65086782 |
| Short name | T757 |
| Test name | |
| Test status | |
| Simulation time | 66755365 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65086782 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_sec_cm_rstmgr_intersig_mubi.65086782 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_smoke.4248134236 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 30796717 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4248134236 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_smoke.4248134236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all.3739703055 |
| Short name | T777 |
| Test name | |
| Test status | |
| Simulation time | 2027265105 ps |
| CPU time | 4.72 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:47 AM UTC 24 |
| Peak memory | 211416 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739703055 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_stress_all.3739703055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_stress_all_with_rand_reset.1203861933 |
| Short name | T778 |
| Test name | |
| Test status | |
| Simulation time | 2061722966 ps |
| CPU time | 6.07 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:48 AM UTC 24 |
| Peak memory | 211656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1203861933 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmg r_stress_all_with_rand_reset.1203861933 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup.3309625024 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 240301370 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309625024 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup.3309625024 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/37.pwrmgr_wakeup_reset.3369214193 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 199472129 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:29:40 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3369214193 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.pwrmgr_wakeup_reset.3369214193 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/37.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_aborted_low_power.670167633 |
| Short name | T765 |
| Test name | |
| Test status | |
| Simulation time | 25427665 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 210876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=670167633 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_aborted_low_power.670167633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_disable_rom_integrity_check.2196362312 |
| Short name | T783 |
| Test name | |
| Test status | |
| Simulation time | 77142821 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:01 AM UTC 24 |
| Peak memory | 210188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196362312 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_disable_rom_integrity_check.2196362312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_esc_clk_rst_malfunc.2768178629 |
| Short name | T761 |
| Test name | |
| Test status | |
| Simulation time | 28616035 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768178629 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_esc_clk_rst_malfunc.2768178629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_escalation_timeout.1455112822 |
| Short name | T785 |
| Test name | |
| Test status | |
| Simulation time | 678647739 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 205588 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1455112822 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_escalation_timeout.1455112822 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_glitch.1695502673 |
| Short name | T782 |
| Test name | |
| Test status | |
| Simulation time | 56841487 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:01 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695502673 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_glitch.1695502673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_global_esc.2451668644 |
| Short name | T781 |
| Test name | |
| Test status | |
| Simulation time | 44270046 ps |
| CPU time | 0.49 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:01 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451668644 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_global_esc.2451668644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_invalid.1566301694 |
| Short name | T784 |
| Test name | |
| Test status | |
| Simulation time | 44589253 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566301694 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_invalid.1566301694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_lowpower_wakeup_race.593410019 |
| Short name | T762 |
| Test name | |
| Test status | |
| Simulation time | 137357296 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593410019 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_lowpower_wakeup_race.593410019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset.4207858532 |
| Short name | T764 |
| Test name | |
| Test status | |
| Simulation time | 170311868 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4207858532 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset.4207858532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_reset_invalid.655026246 |
| Short name | T787 |
| Test name | |
| Test status | |
| Simulation time | 112777962 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655026246 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_reset_invalid.655026246 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_ctrl_config_regwen.1561535542 |
| Short name | T767 |
| Test name | |
| Test status | |
| Simulation time | 125133516 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561535542 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_ctrl_config_regwen.1561535542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1242481775 |
| Short name | T771 |
| Test name | |
| Test status | |
| Simulation time | 2914610756 ps |
| CPU time | 1.7 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:44 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1242481775 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1242481775 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3710236598 |
| Short name | T776 |
| Test name | |
| Test status | |
| Simulation time | 943956065 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:45 AM UTC 24 |
| Peak memory | 211192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710236598 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3710236598 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_sec_cm_rstmgr_intersig_mubi.716804817 |
| Short name | T769 |
| Test name | |
| Test status | |
| Simulation time | 137001341 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716804817 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_sec_cm_rstmgr_intersig_mubi.716804817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_smoke.671442156 |
| Short name | T756 |
| Test name | |
| Test status | |
| Simulation time | 30481750 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:42 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671442156 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_smoke.671442156 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all.2513333639 |
| Short name | T828 |
| Test name | |
| Test status | |
| Simulation time | 1340722643 ps |
| CPU time | 3.06 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:04 AM UTC 24 |
| Peak memory | 211540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513333639 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_stress_all.2513333639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_stress_all_with_rand_reset.1727300894 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 10703768214 ps |
| CPU time | 13.41 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:15 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1727300894 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmg r_stress_all_with_rand_reset.1727300894 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup.491916159 |
| Short name | T766 |
| Test name | |
| Test status | |
| Simulation time | 285386292 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=491916159 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup.491916159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/38.pwrmgr_wakeup_reset.1026725678 |
| Short name | T770 |
| Test name | |
| Test status | |
| Simulation time | 203035359 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 02:29:41 AM UTC 24 |
| Finished | Sep 04 02:29:43 AM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1026725678 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.pwrmgr_wakeup_reset.1026725678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/38.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_aborted_low_power.1397895644 |
| Short name | T789 |
| Test name | |
| Test status | |
| Simulation time | 118729869 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1397895644 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_aborted_low_power.1397895644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_disable_rom_integrity_check.919236082 |
| Short name | T798 |
| Test name | |
| Test status | |
| Simulation time | 44604432 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 210888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=919236082 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_disable_rom_integrity_check.919236082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_esc_clk_rst_malfunc.3268132147 |
| Short name | T792 |
| Test name | |
| Test status | |
| Simulation time | 38681932 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3268132147 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_esc_clk_rst_malfunc.3268132147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_escalation_timeout.2205921155 |
| Short name | T800 |
| Test name | |
| Test status | |
| Simulation time | 109086356 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2205921155 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_escalation_timeout.2205921155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_glitch.1795225409 |
| Short name | T795 |
| Test name | |
| Test status | |
| Simulation time | 41836819 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795225409 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_glitch.1795225409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_global_esc.1825289166 |
| Short name | T793 |
| Test name | |
| Test status | |
| Simulation time | 52560891 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 205828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825289166 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_global_esc.1825289166 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_invalid.2499243518 |
| Short name | T799 |
| Test name | |
| Test status | |
| Simulation time | 44939448 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2499243518 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_invalid.2499243518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_lowpower_wakeup_race.3781178813 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 99484191 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3781178813 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_lowpower_wakeup_race.3781178813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset.1667683349 |
| Short name | T786 |
| Test name | |
| Test status | |
| Simulation time | 46714380 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1667683349 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset.1667683349 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_reset_invalid.1963186647 |
| Short name | T796 |
| Test name | |
| Test status | |
| Simulation time | 192729997 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 220060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1963186647 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_reset_invalid.1963186647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_ctrl_config_regwen.3030991188 |
| Short name | T801 |
| Test name | |
| Test status | |
| Simulation time | 543042747 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030991188 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_ctrl_config_regwen.3030991188 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3772767425 |
| Short name | T814 |
| Test name | |
| Test status | |
| Simulation time | 1538568978 ps |
| CPU time | 1.57 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 210436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772767425 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3772767425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2349620807 |
| Short name | T827 |
| Test name | |
| Test status | |
| Simulation time | 1008745100 ps |
| CPU time | 2.67 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:04 AM UTC 24 |
| Peak memory | 211316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2349620807 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2349620807 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387373243 |
| Short name | T790 |
| Test name | |
| Test status | |
| Simulation time | 51718978 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 208236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1387373243 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387373243 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_smoke.2523213216 |
| Short name | T788 |
| Test name | |
| Test status | |
| Simulation time | 35521488 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523213216 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_smoke.2523213216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all.770174557 |
| Short name | T833 |
| Test name | |
| Test status | |
| Simulation time | 1502802069 ps |
| CPU time | 4.54 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:06 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=770174557 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_stress_all.770174557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_stress_all_with_rand_reset.4272267478 |
| Short name | T834 |
| Test name | |
| Test status | |
| Simulation time | 4019159507 ps |
| CPU time | 5.39 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:07 AM UTC 24 |
| Peak memory | 211468 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=4272267478 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmg r_stress_all_with_rand_reset.4272267478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup.1007484476 |
| Short name | T791 |
| Test name | |
| Test status | |
| Simulation time | 227185600 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007484476 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup.1007484476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/39.pwrmgr_wakeup_reset.786439975 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 125248903 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 02:30:00 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786439975 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.pwrmgr_wakeup_reset.786439975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/39.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_disable_rom_integrity_check.3176411783 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 65711177 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:27:42 AM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176411783 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_disable_rom_integrity_check.3176411783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_escalation_timeout.3793704490 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 432592133 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793704490 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_escalation_timeout.3793704490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_glitch.3543862718 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 47083432 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:27:42 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543862718 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_glitch.3543862718 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_global_esc.4105673946 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 40638700 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105673946 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_global_esc.4105673946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_invalid.77875135 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 46695389 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 210856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=77875135 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_invalid.77875135 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_lowpower_wakeup_race.1841555972 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 46826559 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:26:53 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841555972 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_lowpower_wakeup_race.1841555972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset.4064956294 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 26133467 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:44 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064956294 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset.4064956294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_reset_invalid.958961876 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 156804362 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958961876 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_reset_invalid.958961876 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_sec_cm.2445242731 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 897325601 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:27:47 AM UTC 24 |
| Peak memory | 236888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2445242731 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_sec_cm.2445242731 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_smoke.2327948457 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 29511804 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:26:35 AM UTC 24 |
| Finished | Sep 04 02:26:44 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2327948457 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_smoke.2327948457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_stress_all_with_rand_reset.3086070479 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 9781246144 ps |
| CPU time | 11.03 seconds |
| Started | Sep 04 02:26:38 AM UTC 24 |
| Finished | Sep 04 02:26:54 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3086070479 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr _stress_all_with_rand_reset.3086070479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/4.pwrmgr_wakeup.2617538078 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 111572527 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:26:37 AM UTC 24 |
| Finished | Sep 04 02:26:53 AM UTC 24 |
| Peak memory | 208172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2617538078 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.pwrmgr_wakeup.2617538078 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/4.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_aborted_low_power.4081583035 |
| Short name | T805 |
| Test name | |
| Test status | |
| Simulation time | 202718654 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081583035 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_aborted_low_power.4081583035 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_disable_rom_integrity_check.2109884396 |
| Short name | T813 |
| Test name | |
| Test status | |
| Simulation time | 55585473 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2109884396 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_disable_rom_integrity_check.2109884396 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_esc_clk_rst_malfunc.531366266 |
| Short name | T808 |
| Test name | |
| Test status | |
| Simulation time | 29785972 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531366266 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_esc_clk_rst_malfunc.531366266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_escalation_timeout.2102590631 |
| Short name | T811 |
| Test name | |
| Test status | |
| Simulation time | 475979481 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2102590631 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_escalation_timeout.2102590631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_glitch.588001665 |
| Short name | T804 |
| Test name | |
| Test status | |
| Simulation time | 77994665 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588001665 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_glitch.588001665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_global_esc.2952945359 |
| Short name | T810 |
| Test name | |
| Test status | |
| Simulation time | 125390193 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2952945359 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_global_esc.2952945359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_invalid.1366153657 |
| Short name | T812 |
| Test name | |
| Test status | |
| Simulation time | 52934272 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 210924 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1366153657 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_invalid.1366153657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_lowpower_wakeup_race.2937043694 |
| Short name | T806 |
| Test name | |
| Test status | |
| Simulation time | 195341159 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937043694 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_lowpower_wakeup_race.2937043694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset.1469245187 |
| Short name | T803 |
| Test name | |
| Test status | |
| Simulation time | 58718608 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1469245187 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset.1469245187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_reset_invalid.549626892 |
| Short name | T820 |
| Test name | |
| Test status | |
| Simulation time | 101597729 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=549626892 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_reset_invalid.549626892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_ctrl_config_regwen.655135315 |
| Short name | T824 |
| Test name | |
| Test status | |
| Simulation time | 267474541 ps |
| CPU time | 1.23 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=655135315 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_ctrl_config_regwen.655135315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.440943161 |
| Short name | T831 |
| Test name | |
| Test status | |
| Simulation time | 861966210 ps |
| CPU time | 2.95 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:05 AM UTC 24 |
| Peak memory | 211276 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440943161 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.440943161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3681805813 |
| Short name | T832 |
| Test name | |
| Test status | |
| Simulation time | 835388123 ps |
| CPU time | 3.06 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:05 AM UTC 24 |
| Peak memory | 211372 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3681805813 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3681805813 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4053863140 |
| Short name | T819 |
| Test name | |
| Test status | |
| Simulation time | 66487057 ps |
| CPU time | 0.92 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4053863140 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_sec_cm_rstmgr_intersig_mubi.4053863140 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_smoke.1763702726 |
| Short name | T797 |
| Test name | |
| Test status | |
| Simulation time | 29121785 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:02 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1763702726 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_smoke.1763702726 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all.2600536637 |
| Short name | T821 |
| Test name | |
| Test status | |
| Simulation time | 455021554 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600536637 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_stress_all.2600536637 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_stress_all_with_rand_reset.1300654150 |
| Short name | T835 |
| Test name | |
| Test status | |
| Simulation time | 5036919963 ps |
| CPU time | 6.26 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:09 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1300654150 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmg r_stress_all_with_rand_reset.1300654150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup.28148448 |
| Short name | T809 |
| Test name | |
| Test status | |
| Simulation time | 55114059 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28148448 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup.28148448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/40.pwrmgr_wakeup_reset.3767965432 |
| Short name | T816 |
| Test name | |
| Test status | |
| Simulation time | 656720449 ps |
| CPU time | 0.95 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3767965432 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.pwrmgr_wakeup_reset.3767965432 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/40.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_aborted_low_power.3452054274 |
| Short name | T815 |
| Test name | |
| Test status | |
| Simulation time | 172715432 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3452054274 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_aborted_low_power.3452054274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_disable_rom_integrity_check.1811605272 |
| Short name | T841 |
| Test name | |
| Test status | |
| Simulation time | 57570844 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1811605272 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_disable_rom_integrity_check.1811605272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_esc_clk_rst_malfunc.533615330 |
| Short name | T837 |
| Test name | |
| Test status | |
| Simulation time | 33055032 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:30:22 AM UTC 24 |
| Finished | Sep 04 02:30:24 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533615330 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_esc_clk_rst_malfunc.533615330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_escalation_timeout.4153445886 |
| Short name | T840 |
| Test name | |
| Test status | |
| Simulation time | 384243690 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:30:22 AM UTC 24 |
| Finished | Sep 04 02:30:24 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153445886 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_escalation_timeout.4153445886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_glitch.1188560994 |
| Short name | T839 |
| Test name | |
| Test status | |
| Simulation time | 52176332 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:30:22 AM UTC 24 |
| Finished | Sep 04 02:30:24 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188560994 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_glitch.1188560994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_global_esc.1319979543 |
| Short name | T836 |
| Test name | |
| Test status | |
| Simulation time | 156294170 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:30:22 AM UTC 24 |
| Finished | Sep 04 02:30:24 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319979543 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_global_esc.1319979543 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_invalid.31057691 |
| Short name | T843 |
| Test name | |
| Test status | |
| Simulation time | 50067873 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31057691 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_invalid.31057691 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_lowpower_wakeup_race.3092110280 |
| Short name | T825 |
| Test name | |
| Test status | |
| Simulation time | 280942780 ps |
| CPU time | 1.06 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092110280 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_lowpower_wakeup_race.3092110280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset.79178664 |
| Short name | T818 |
| Test name | |
| Test status | |
| Simulation time | 93468798 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79178664 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03 /pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset.79178664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_reset_invalid.1718281074 |
| Short name | T845 |
| Test name | |
| Test status | |
| Simulation time | 109358146 ps |
| CPU time | 1 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 219728 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718281074 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_reset_invalid.1718281074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_ctrl_config_regwen.1588061008 |
| Short name | T838 |
| Test name | |
| Test status | |
| Simulation time | 82120030 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:30:22 AM UTC 24 |
| Finished | Sep 04 02:30:24 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588061008 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_ctrl_config_regwen.1588061008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1373263149 |
| Short name | T830 |
| Test name | |
| Test status | |
| Simulation time | 1012268243 ps |
| CPU time | 2.25 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:05 AM UTC 24 |
| Peak memory | 211408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1373263149 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1373263149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.986721536 |
| Short name | T829 |
| Test name | |
| Test status | |
| Simulation time | 1019782891 ps |
| CPU time | 1.93 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:04 AM UTC 24 |
| Peak memory | 210408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=986721536 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.986721536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3999145123 |
| Short name | T823 |
| Test name | |
| Test status | |
| Simulation time | 67368661 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999145123 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_sec_cm_rstmgr_intersig_mubi.3999145123 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_smoke.1502319649 |
| Short name | T817 |
| Test name | |
| Test status | |
| Simulation time | 30690344 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502319649 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_smoke.1502319649 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all.3939703149 |
| Short name | T883 |
| Test name | |
| Test status | |
| Simulation time | 3178024002 ps |
| CPU time | 2.57 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:27 AM UTC 24 |
| Peak memory | 211424 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3939703149 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_stress_all.3939703149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_stress_all_with_rand_reset.1955745008 |
| Short name | T890 |
| Test name | |
| Test status | |
| Simulation time | 4658274477 ps |
| CPU time | 8.07 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:32 AM UTC 24 |
| Peak memory | 211060 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1955745008 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmg r_stress_all_with_rand_reset.1955745008 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup.380287736 |
| Short name | T822 |
| Test name | |
| Test status | |
| Simulation time | 222835500 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:03 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380287736 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup.380287736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/41.pwrmgr_wakeup_reset.2239401121 |
| Short name | T826 |
| Test name | |
| Test status | |
| Simulation time | 246532605 ps |
| CPU time | 1.29 seconds |
| Started | Sep 04 02:30:01 AM UTC 24 |
| Finished | Sep 04 02:30:04 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2239401121 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.pwrmgr_wakeup_reset.2239401121 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/41.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_aborted_low_power.298317826 |
| Short name | T846 |
| Test name | |
| Test status | |
| Simulation time | 75199087 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=298317826 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_aborted_low_power.298317826 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_disable_rom_integrity_check.261481675 |
| Short name | T856 |
| Test name | |
| Test status | |
| Simulation time | 137841308 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261481675 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_disable_rom_integrity_check.261481675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_esc_clk_rst_malfunc.944341750 |
| Short name | T850 |
| Test name | |
| Test status | |
| Simulation time | 29562092 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944341750 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_esc_clk_rst_malfunc.944341750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_escalation_timeout.4291289284 |
| Short name | T802 |
| Test name | |
| Test status | |
| Simulation time | 519021920 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291289284 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_escalation_timeout.4291289284 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_glitch.1704935819 |
| Short name | T852 |
| Test name | |
| Test status | |
| Simulation time | 34781224 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1704935819 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_glitch.1704935819 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_global_esc.1742988694 |
| Short name | T851 |
| Test name | |
| Test status | |
| Simulation time | 58283851 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742988694 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_global_esc.1742988694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_invalid.4213787963 |
| Short name | T794 |
| Test name | |
| Test status | |
| Simulation time | 42239410 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213787963 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_invalid.4213787963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_lowpower_wakeup_race.170223101 |
| Short name | T847 |
| Test name | |
| Test status | |
| Simulation time | 295285392 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=170223101 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_lowpower_wakeup_race.170223101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset.266880001 |
| Short name | T848 |
| Test name | |
| Test status | |
| Simulation time | 136788557 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=266880001 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset.266880001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_reset_invalid.3954743274 |
| Short name | T849 |
| Test name | |
| Test status | |
| Simulation time | 145405457 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3954743274 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_reset_invalid.3954743274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_ctrl_config_regwen.211773858 |
| Short name | T853 |
| Test name | |
| Test status | |
| Simulation time | 57972493 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211773858 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_ctrl_config_regwen.211773858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1511563725 |
| Short name | T880 |
| Test name | |
| Test status | |
| Simulation time | 856247355 ps |
| CPU time | 2.04 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:27 AM UTC 24 |
| Peak memory | 211564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1511563725 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1511563725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.629116712 |
| Short name | T882 |
| Test name | |
| Test status | |
| Simulation time | 964588240 ps |
| CPU time | 2.31 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:27 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629116712 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.629116712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1792132514 |
| Short name | T854 |
| Test name | |
| Test status | |
| Simulation time | 108076346 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1792132514 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_sec_cm_rstmgr_intersig_mubi.1792132514 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_smoke.956740327 |
| Short name | T842 |
| Test name | |
| Test status | |
| Simulation time | 38708366 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956740327 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_smoke.956740327 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all.1083473151 |
| Short name | T865 |
| Test name | |
| Test status | |
| Simulation time | 328469388 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1083473151 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_stress_all.1083473151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_stress_all_with_rand_reset.1411785363 |
| Short name | T889 |
| Test name | |
| Test status | |
| Simulation time | 6550671069 ps |
| CPU time | 5.26 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:30 AM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1411785363 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmg r_stress_all_with_rand_reset.1411785363 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup.2007741491 |
| Short name | T844 |
| Test name | |
| Test status | |
| Simulation time | 71157373 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:30:23 AM UTC 24 |
| Finished | Sep 04 02:30:25 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2007741491 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup.2007741491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/42.pwrmgr_wakeup_reset.2184259555 |
| Short name | T855 |
| Test name | |
| Test status | |
| Simulation time | 152846004 ps |
| CPU time | 0.97 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2184259555 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.pwrmgr_wakeup_reset.2184259555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/42.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_aborted_low_power.3429802905 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 31576195 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3429802905 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_aborted_low_power.3429802905 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_disable_rom_integrity_check.4002523199 |
| Short name | T872 |
| Test name | |
| Test status | |
| Simulation time | 53476539 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002523199 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_disable_rom_integrity_check.4002523199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_esc_clk_rst_malfunc.638337980 |
| Short name | T860 |
| Test name | |
| Test status | |
| Simulation time | 30051840 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=638337980 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_esc_clk_rst_malfunc.638337980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_escalation_timeout.29154050 |
| Short name | T870 |
| Test name | |
| Test status | |
| Simulation time | 204764349 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29154050 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ= pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_escalation_timeout.29154050 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_glitch.402342703 |
| Short name | T867 |
| Test name | |
| Test status | |
| Simulation time | 49182903 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402342703 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_glitch.402342703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_global_esc.3971996479 |
| Short name | T861 |
| Test name | |
| Test status | |
| Simulation time | 21539448 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 206188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971996479 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_global_esc.3971996479 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_invalid.1958167220 |
| Short name | T864 |
| Test name | |
| Test status | |
| Simulation time | 77587975 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1958167220 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_invalid.1958167220 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_lowpower_wakeup_race.3166190358 |
| Short name | T862 |
| Test name | |
| Test status | |
| Simulation time | 260423668 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 210928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166190358 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_lowpower_wakeup_race.3166190358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset.3531894785 |
| Short name | T807 |
| Test name | |
| Test status | |
| Simulation time | 51290171 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531894785 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset.3531894785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_reset_invalid.3467108038 |
| Short name | T876 |
| Test name | |
| Test status | |
| Simulation time | 116901794 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467108038 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_reset_invalid.3467108038 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_ctrl_config_regwen.4241049960 |
| Short name | T871 |
| Test name | |
| Test status | |
| Simulation time | 270078117 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4241049960 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_ctrl_config_regwen.4241049960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4178222669 |
| Short name | T884 |
| Test name | |
| Test status | |
| Simulation time | 1221950795 ps |
| CPU time | 1.97 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:27 AM UTC 24 |
| Peak memory | 210712 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4178222669 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4178222669 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2223185764 |
| Short name | T886 |
| Test name | |
| Test status | |
| Simulation time | 935843294 ps |
| CPU time | 3.1 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:29 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223185764 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2223185764 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_sec_cm_rstmgr_intersig_mubi.379602066 |
| Short name | T863 |
| Test name | |
| Test status | |
| Simulation time | 152415701 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379602066 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_sec_cm_rstmgr_intersig_mubi.379602066 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_smoke.3949778047 |
| Short name | T857 |
| Test name | |
| Test status | |
| Simulation time | 68692026 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208232 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3949778047 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_smoke.3949778047 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all.1886937721 |
| Short name | T888 |
| Test name | |
| Test status | |
| Simulation time | 3302689278 ps |
| CPU time | 3.4 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:29 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886937721 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_stress_all.1886937721 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_stress_all_with_rand_reset.3415191445 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 1704770440 ps |
| CPU time | 5.66 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:31 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3415191445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmg r_stress_all_with_rand_reset.3415191445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup.1810402969 |
| Short name | T868 |
| Test name | |
| Test status | |
| Simulation time | 429594489 ps |
| CPU time | 0.96 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1810402969 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup.1810402969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/43.pwrmgr_wakeup_reset.1422357346 |
| Short name | T879 |
| Test name | |
| Test status | |
| Simulation time | 259574463 ps |
| CPU time | 1.34 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:27 AM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422357346 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.pwrmgr_wakeup_reset.1422357346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/43.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_aborted_low_power.3993256139 |
| Short name | T877 |
| Test name | |
| Test status | |
| Simulation time | 57965720 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:30:25 AM UTC 24 |
| Finished | Sep 04 02:30:27 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993256139 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_aborted_low_power.3993256139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_disable_rom_integrity_check.126728748 |
| Short name | T894 |
| Test name | |
| Test status | |
| Simulation time | 79499831 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:48 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126728748 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_disable_rom_integrity_check.126728748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_esc_clk_rst_malfunc.308388923 |
| Short name | T893 |
| Test name | |
| Test status | |
| Simulation time | 32391877 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:48 AM UTC 24 |
| Peak memory | 206708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308388923 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_esc_clk_rst_malfunc.308388923 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_escalation_timeout.2340297752 |
| Short name | T898 |
| Test name | |
| Test status | |
| Simulation time | 391310820 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 208976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340297752 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_escalation_timeout.2340297752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_glitch.2096449342 |
| Short name | T895 |
| Test name | |
| Test status | |
| Simulation time | 71090077 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:48 AM UTC 24 |
| Peak memory | 206196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096449342 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_glitch.2096449342 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_global_esc.672265088 |
| Short name | T892 |
| Test name | |
| Test status | |
| Simulation time | 64613691 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:48 AM UTC 24 |
| Peak memory | 207480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=672265088 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_global_esc.672265088 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_invalid.131273438 |
| Short name | T896 |
| Test name | |
| Test status | |
| Simulation time | 93599613 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131273438 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_invalid.131273438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_lowpower_wakeup_race.2652067616 |
| Short name | T873 |
| Test name | |
| Test status | |
| Simulation time | 91723342 ps |
| CPU time | 0.65 seconds |
| Started | Sep 04 02:30:25 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652067616 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_lowpower_wakeup_race.2652067616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset.3941600883 |
| Short name | T874 |
| Test name | |
| Test status | |
| Simulation time | 103988936 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941600883 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset.3941600883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_reset_invalid.3527906666 |
| Short name | T902 |
| Test name | |
| Test status | |
| Simulation time | 119283586 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3527906666 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_reset_invalid.3527906666 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_ctrl_config_regwen.3966841976 |
| Short name | T900 |
| Test name | |
| Test status | |
| Simulation time | 264505295 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 209524 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3966841976 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_ctrl_config_regwen.3966841976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.258510736 |
| Short name | T887 |
| Test name | |
| Test status | |
| Simulation time | 778122766 ps |
| CPU time | 2.73 seconds |
| Started | Sep 04 02:30:25 AM UTC 24 |
| Finished | Sep 04 02:30:29 AM UTC 24 |
| Peak memory | 211376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258510736 -as sert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.258510736 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.987656180 |
| Short name | T885 |
| Test name | |
| Test status | |
| Simulation time | 1363629681 ps |
| CPU time | 2.03 seconds |
| Started | Sep 04 02:30:25 AM UTC 24 |
| Finished | Sep 04 02:30:28 AM UTC 24 |
| Peak memory | 211284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987656180 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.987656180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_sec_cm_rstmgr_intersig_mubi.78379486 |
| Short name | T878 |
| Test name | |
| Test status | |
| Simulation time | 53101735 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:30:25 AM UTC 24 |
| Finished | Sep 04 02:30:27 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78379486 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_sec_cm_rstmgr_intersig_mubi.78379486 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_smoke.820586623 |
| Short name | T866 |
| Test name | |
| Test status | |
| Simulation time | 42218336 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:30:24 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=820586623 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_smoke.820586623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all.1271128511 |
| Short name | T922 |
| Test name | |
| Test status | |
| Simulation time | 241135593 ps |
| CPU time | 1.49 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271128511 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_stress_all.1271128511 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_stress_all_with_rand_reset.1993639941 |
| Short name | T942 |
| Test name | |
| Test status | |
| Simulation time | 11926838343 ps |
| CPU time | 11.13 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:59 AM UTC 24 |
| Peak memory | 211476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1993639941 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmg r_stress_all_with_rand_reset.1993639941 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup.668193346 |
| Short name | T875 |
| Test name | |
| Test status | |
| Simulation time | 187095277 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:30:25 AM UTC 24 |
| Finished | Sep 04 02:30:26 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668193346 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup.668193346 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/44.pwrmgr_wakeup_reset.1742631037 |
| Short name | T881 |
| Test name | |
| Test status | |
| Simulation time | 481705699 ps |
| CPU time | 1.1 seconds |
| Started | Sep 04 02:30:25 AM UTC 24 |
| Finished | Sep 04 02:30:27 AM UTC 24 |
| Peak memory | 210912 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742631037 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.pwrmgr_wakeup_reset.1742631037 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/44.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_aborted_low_power.2087827493 |
| Short name | T903 |
| Test name | |
| Test status | |
| Simulation time | 129692890 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087827493 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_aborted_low_power.2087827493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_disable_rom_integrity_check.2420276979 |
| Short name | T912 |
| Test name | |
| Test status | |
| Simulation time | 65680721 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 211100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420276979 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_disable_rom_integrity_check.2420276979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_esc_clk_rst_malfunc.2984584055 |
| Short name | T906 |
| Test name | |
| Test status | |
| Simulation time | 31006266 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 206168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2984584055 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_esc_clk_rst_malfunc.2984584055 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_escalation_timeout.5741716 |
| Short name | T911 |
| Test name | |
| Test status | |
| Simulation time | 210586713 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=5741716 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=p wrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-v cs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_escalation_timeout.5741716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_glitch.3991679307 |
| Short name | T910 |
| Test name | |
| Test status | |
| Simulation time | 44683891 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991679307 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_glitch.3991679307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_global_esc.1166554617 |
| Short name | T907 |
| Test name | |
| Test status | |
| Simulation time | 43058225 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166554617 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_global_esc.1166554617 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_invalid.3758250025 |
| Short name | T913 |
| Test name | |
| Test status | |
| Simulation time | 69414053 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 210984 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758250025 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_invalid.3758250025 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_lowpower_wakeup_race.892167664 |
| Short name | T905 |
| Test name | |
| Test status | |
| Simulation time | 136180422 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=892167664 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_lowpower_wakeup_race.892167664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset.405800861 |
| Short name | T901 |
| Test name | |
| Test status | |
| Simulation time | 30005344 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 209636 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=405800861 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset.405800861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_reset_invalid.3460434364 |
| Short name | T926 |
| Test name | |
| Test status | |
| Simulation time | 101823263 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3460434364 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_reset_invalid.3460434364 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_ctrl_config_regwen.1883117791 |
| Short name | T908 |
| Test name | |
| Test status | |
| Simulation time | 259809487 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 208252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883117791 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_ctrl_config_regwen.1883117791 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4137785631 |
| Short name | T930 |
| Test name | |
| Test status | |
| Simulation time | 1076606171 ps |
| CPU time | 1.74 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 210976 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137785631 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4137785631 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1364179230 |
| Short name | T935 |
| Test name | |
| Test status | |
| Simulation time | 1791818453 ps |
| CPU time | 1.97 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1364179230 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1364179230 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2939356954 |
| Short name | T909 |
| Test name | |
| Test status | |
| Simulation time | 73420133 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2939356954 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_sec_cm_rstmgr_intersig_mubi.2939356954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_smoke.3808572991 |
| Short name | T899 |
| Test name | |
| Test status | |
| Simulation time | 168371409 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 208236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808572991 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_smoke.3808572991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all.3030288545 |
| Short name | T934 |
| Test name | |
| Test status | |
| Simulation time | 481598199 ps |
| CPU time | 1.64 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 210392 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030288545 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_stress_all.3030288545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_stress_all_with_rand_reset.3283540668 |
| Short name | T941 |
| Test name | |
| Test status | |
| Simulation time | 3851302020 ps |
| CPU time | 5.31 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:54 AM UTC 24 |
| Peak memory | 211560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3283540668 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmg r_stress_all_with_rand_reset.3283540668 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup.677265660 |
| Short name | T904 |
| Test name | |
| Test status | |
| Simulation time | 270729695 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 209820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=677265660 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup.677265660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/45.pwrmgr_wakeup_reset.2961182099 |
| Short name | T916 |
| Test name | |
| Test status | |
| Simulation time | 312032901 ps |
| CPU time | 1.31 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961182099 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.pwrmgr_wakeup_reset.2961182099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/45.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_aborted_low_power.1297407338 |
| Short name | T920 |
| Test name | |
| Test status | |
| Simulation time | 59315977 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297407338 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_aborted_low_power.1297407338 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_disable_rom_integrity_check.4233525370 |
| Short name | T921 |
| Test name | |
| Test status | |
| Simulation time | 83340357 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4233525370 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_disable_rom_integrity_check.4233525370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_esc_clk_rst_malfunc.798898553 |
| Short name | T917 |
| Test name | |
| Test status | |
| Simulation time | 30563286 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=798898553 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_esc_clk_rst_malfunc.798898553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_escalation_timeout.1458271298 |
| Short name | T928 |
| Test name | |
| Test status | |
| Simulation time | 112801555 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458271298 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_escalation_timeout.1458271298 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_glitch.1382607001 |
| Short name | T923 |
| Test name | |
| Test status | |
| Simulation time | 39500145 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1382607001 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_glitch.1382607001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_global_esc.142248921 |
| Short name | T919 |
| Test name | |
| Test status | |
| Simulation time | 54787402 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142248921 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_global_esc.142248921 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_invalid.147548331 |
| Short name | T858 |
| Test name | |
| Test status | |
| Simulation time | 37477614 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 210916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=147548331 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_invalid.147548331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_lowpower_wakeup_race.756458074 |
| Short name | T925 |
| Test name | |
| Test status | |
| Simulation time | 274168466 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 209512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756458074 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_lowpower_wakeup_race.756458074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset.3655706848 |
| Short name | T915 |
| Test name | |
| Test status | |
| Simulation time | 90069921 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 208224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655706848 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset.3655706848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_reset_invalid.1526308029 |
| Short name | T859 |
| Test name | |
| Test status | |
| Simulation time | 221651961 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1526308029 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_reset_invalid.1526308029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_ctrl_config_regwen.1225234020 |
| Short name | T918 |
| Test name | |
| Test status | |
| Simulation time | 98124313 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225234020 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_ctrl_config_regwen.1225234020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3584157969 |
| Short name | T936 |
| Test name | |
| Test status | |
| Simulation time | 1001113539 ps |
| CPU time | 1.82 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:51 AM UTC 24 |
| Peak memory | 209288 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3584157969 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.3584157969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3861489845 |
| Short name | T939 |
| Test name | |
| Test status | |
| Simulation time | 788312552 ps |
| CPU time | 2.91 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:52 AM UTC 24 |
| Peak memory | 211440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3861489845 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3861489845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3946777537 |
| Short name | T924 |
| Test name | |
| Test status | |
| Simulation time | 81223498 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946777537 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_sec_cm_rstmgr_intersig_mubi.3946777537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_smoke.3884309630 |
| Short name | T914 |
| Test name | |
| Test status | |
| Simulation time | 32834589 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:49 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3884309630 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_smoke.3884309630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all.1820163844 |
| Short name | T940 |
| Test name | |
| Test status | |
| Simulation time | 944601861 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:52 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1820163844 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_stress_all.1820163844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_stress_all_with_rand_reset.2606909706 |
| Short name | T943 |
| Test name | |
| Test status | |
| Simulation time | 16252210325 ps |
| CPU time | 15.38 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:31:05 AM UTC 24 |
| Peak memory | 211724 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2606909706 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmg r_stress_all_with_rand_reset.2606909706 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup.1065696845 |
| Short name | T927 |
| Test name | |
| Test status | |
| Simulation time | 174766988 ps |
| CPU time | 0.93 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1065696845 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup.1065696845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/46.pwrmgr_wakeup_reset.2305055237 |
| Short name | T929 |
| Test name | |
| Test status | |
| Simulation time | 509686201 ps |
| CPU time | 1.11 seconds |
| Started | Sep 04 02:30:47 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2305055237 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.pwrmgr_wakeup_reset.2305055237 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/46.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_aborted_low_power.205392853 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 21577130 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205392853 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ =pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim- vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_aborted_low_power.205392853 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_disable_rom_integrity_check.131441555 |
| Short name | T946 |
| Test name | |
| Test status | |
| Simulation time | 64556543 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131441555 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_disable_rom_integrity_check.131441555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_esc_clk_rst_malfunc.3028511412 |
| Short name | T944 |
| Test name | |
| Test status | |
| Simulation time | 30133617 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:13 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028511412 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_esc_clk_rst_malfunc.3028511412 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_escalation_timeout.1835484128 |
| Short name | T947 |
| Test name | |
| Test status | |
| Simulation time | 406312447 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1835484128 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_escalation_timeout.1835484128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_glitch.4206011291 |
| Short name | T945 |
| Test name | |
| Test status | |
| Simulation time | 77902355 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4206011291 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_glitch.4206011291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_global_esc.76475867 |
| Short name | T948 |
| Test name | |
| Test status | |
| Simulation time | 32867943 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=76475867 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_global_esc.76475867 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_invalid.3282374317 |
| Short name | T952 |
| Test name | |
| Test status | |
| Simulation time | 41368141 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3282374317 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_invalid.3282374317 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_lowpower_wakeup_race.2501600245 |
| Short name | T897 |
| Test name | |
| Test status | |
| Simulation time | 164553896 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2501600245 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_lowpower_wakeup_race.2501600245 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset.2923522179 |
| Short name | T869 |
| Test name | |
| Test status | |
| Simulation time | 90204867 ps |
| CPU time | 0.87 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923522179 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset.2923522179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_reset_invalid.408634982 |
| Short name | T950 |
| Test name | |
| Test status | |
| Simulation time | 149477122 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408634982 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_reset_invalid.408634982 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_ctrl_config_regwen.606858357 |
| Short name | T949 |
| Test name | |
| Test status | |
| Simulation time | 60811319 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606858357 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_ctrl_config_regwen.606858357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1549397926 |
| Short name | T938 |
| Test name | |
| Test status | |
| Simulation time | 1376402883 ps |
| CPU time | 2.02 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:51 AM UTC 24 |
| Peak memory | 211396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1549397926 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.1549397926 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1326842388 |
| Short name | T937 |
| Test name | |
| Test status | |
| Simulation time | 1808819887 ps |
| CPU time | 1.78 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:51 AM UTC 24 |
| Peak memory | 210444 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326842388 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.1326842388 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_sec_cm_rstmgr_intersig_mubi.503248333 |
| Short name | T933 |
| Test name | |
| Test status | |
| Simulation time | 66866333 ps |
| CPU time | 0.88 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503248333 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 9_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_sec_cm_rstmgr_intersig_mubi.503248333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_smoke.3798243936 |
| Short name | T891 |
| Test name | |
| Test status | |
| Simulation time | 63009169 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798243936 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_smoke.3798243936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all.1235097583 |
| Short name | T984 |
| Test name | |
| Test status | |
| Simulation time | 2388162216 ps |
| CPU time | 3.5 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:17 AM UTC 24 |
| Peak memory | 211448 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235097583 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_stress_all.1235097583 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_stress_all_with_rand_reset.35425023 |
| Short name | T991 |
| Test name | |
| Test status | |
| Simulation time | 7047218177 ps |
| CPU time | 9.54 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:23 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=35425023 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tgl +branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_ stress_all_with_rand_reset.35425023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup.3411072836 |
| Short name | T931 |
| Test name | |
| Test status | |
| Simulation time | 248402594 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411072836 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup.3411072836 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/47.pwrmgr_wakeup_reset.1314897409 |
| Short name | T932 |
| Test name | |
| Test status | |
| Simulation time | 165483196 ps |
| CPU time | 0.9 seconds |
| Started | Sep 04 02:30:48 AM UTC 24 |
| Finished | Sep 04 02:30:50 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314897409 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.pwrmgr_wakeup_reset.1314897409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/47.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_aborted_low_power.2267863345 |
| Short name | T957 |
| Test name | |
| Test status | |
| Simulation time | 156008898 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2267863345 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_aborted_low_power.2267863345 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_disable_rom_integrity_check.1233120768 |
| Short name | T967 |
| Test name | |
| Test status | |
| Simulation time | 55701835 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1233120768 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_disable_rom_integrity_check.1233120768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_esc_clk_rst_malfunc.1887853667 |
| Short name | T958 |
| Test name | |
| Test status | |
| Simulation time | 31026948 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887853667 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_esc_clk_rst_malfunc.1887853667 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_escalation_timeout.2628080916 |
| Short name | T962 |
| Test name | |
| Test status | |
| Simulation time | 391177013 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628080916 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_escalation_timeout.2628080916 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_glitch.398882830 |
| Short name | T960 |
| Test name | |
| Test status | |
| Simulation time | 50626501 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398882830 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_glitch.398882830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_global_esc.618638103 |
| Short name | T959 |
| Test name | |
| Test status | |
| Simulation time | 36026284 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618638103 -assert nopostproc +UVM_TESTNAME=pw rmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_global_esc.618638103 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_invalid.256983114 |
| Short name | T965 |
| Test name | |
| Test status | |
| Simulation time | 40995891 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 210796 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256983114 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_invalid.256983114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_lowpower_wakeup_race.1886490963 |
| Short name | T955 |
| Test name | |
| Test status | |
| Simulation time | 169371750 ps |
| CPU time | 0.89 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1886490963 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_lowpower_wakeup_race.1886490963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset.1418582546 |
| Short name | T953 |
| Test name | |
| Test status | |
| Simulation time | 261232894 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 210612 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1418582546 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset.1418582546 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_reset_invalid.1722959333 |
| Short name | T966 |
| Test name | |
| Test status | |
| Simulation time | 107311360 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1722959333 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_reset_invalid.1722959333 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_ctrl_config_regwen.621311275 |
| Short name | T956 |
| Test name | |
| Test status | |
| Simulation time | 154855864 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621311275 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_ctrl_config_regwen.621311275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4179395937 |
| Short name | T982 |
| Test name | |
| Test status | |
| Simulation time | 828344769 ps |
| CPU time | 2.89 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:17 AM UTC 24 |
| Peak memory | 211268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4179395937 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.4179395937 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3276720919 |
| Short name | T983 |
| Test name | |
| Test status | |
| Simulation time | 855565146 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:17 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3276720919 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.3276720919 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1871150769 |
| Short name | T961 |
| Test name | |
| Test status | |
| Simulation time | 66366141 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 207452 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871150769 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_sec_cm_rstmgr_intersig_mubi.1871150769 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_smoke.1774921954 |
| Short name | T951 |
| Test name | |
| Test status | |
| Simulation time | 130090729 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774921954 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_smoke.1774921954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all.4052428848 |
| Short name | T986 |
| Test name | |
| Test status | |
| Simulation time | 2312138235 ps |
| CPU time | 3.33 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:17 AM UTC 24 |
| Peak memory | 211356 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4052428848 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_stress_all.4052428848 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_stress_all_with_rand_reset.3324184445 |
| Short name | T988 |
| Test name | |
| Test status | |
| Simulation time | 2062179570 ps |
| CPU time | 3.83 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:18 AM UTC 24 |
| Peak memory | 211380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=3324184445 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmg r_stress_all_with_rand_reset.3324184445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup.1653192673 |
| Short name | T954 |
| Test name | |
| Test status | |
| Simulation time | 96764015 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:14 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1653192673 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup.1653192673 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/48.pwrmgr_wakeup_reset.1836890253 |
| Short name | T963 |
| Test name | |
| Test status | |
| Simulation time | 252957190 ps |
| CPU time | 0.99 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 210616 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1836890253 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.pwrmgr_wakeup_reset.1836890253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/48.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_aborted_low_power.2233958548 |
| Short name | T974 |
| Test name | |
| Test status | |
| Simulation time | 83386352 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2233958548 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_aborted_low_power.2233958548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_disable_rom_integrity_check.595387866 |
| Short name | T978 |
| Test name | |
| Test status | |
| Simulation time | 62558564 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 210980 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=595387866 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_disable_rom_integrity_check.595387866 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_esc_clk_rst_malfunc.1160461882 |
| Short name | T971 |
| Test name | |
| Test status | |
| Simulation time | 31199411 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1160461882 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_esc_clk_rst_malfunc.1160461882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_escalation_timeout.3425212098 |
| Short name | T979 |
| Test name | |
| Test status | |
| Simulation time | 200885727 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 206104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3425212098 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_escalation_timeout.3425212098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_glitch.4255265095 |
| Short name | T975 |
| Test name | |
| Test status | |
| Simulation time | 65223753 ps |
| CPU time | 0.53 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255265095 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_glitch.4255265095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_global_esc.1195467816 |
| Short name | T976 |
| Test name | |
| Test status | |
| Simulation time | 51261450 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1195467816 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_global_esc.1195467816 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_invalid.2154650633 |
| Short name | T972 |
| Test name | |
| Test status | |
| Simulation time | 64777535 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2154650633 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_invalid.2154650633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_lowpower_wakeup_race.2585936936 |
| Short name | T980 |
| Test name | |
| Test status | |
| Simulation time | 298975124 ps |
| CPU time | 1.32 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585936936 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_lowpower_wakeup_race.2585936936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset.1652327626 |
| Short name | T968 |
| Test name | |
| Test status | |
| Simulation time | 150825772 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 210492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652327626 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset.1652327626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_reset_invalid.1562275693 |
| Short name | T981 |
| Test name | |
| Test status | |
| Simulation time | 109029075 ps |
| CPU time | 0.82 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 220192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1562275693 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_reset_invalid.1562275693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_ctrl_config_regwen.2860525266 |
| Short name | T977 |
| Test name | |
| Test status | |
| Simulation time | 263611142 ps |
| CPU time | 0.83 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2860525266 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_ctrl_config_regwen.2860525266 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2145107496 |
| Short name | T985 |
| Test name | |
| Test status | |
| Simulation time | 749265679 ps |
| CPU time | 2.79 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:17 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145107496 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_lc_ctrl_inters ig_mubi.2145107496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2701754291 |
| Short name | T987 |
| Test name | |
| Test status | |
| Simulation time | 925709801 ps |
| CPU time | 3.12 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:18 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701754291 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rom_ctrl_inte rsig_mubi.2701754291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2538630158 |
| Short name | T969 |
| Test name | |
| Test status | |
| Simulation time | 83782222 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538630158 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_sec_cm_rstmgr_intersig_mubi.2538630158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_smoke.1134469874 |
| Short name | T970 |
| Test name | |
| Test status | |
| Simulation time | 28824360 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1134469874 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_smoke.1134469874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all.1200549628 |
| Short name | T990 |
| Test name | |
| Test status | |
| Simulation time | 1924876197 ps |
| CPU time | 6.55 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:21 AM UTC 24 |
| Peak memory | 211360 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1200549628 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_stress_all.1200549628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_stress_all_with_rand_reset.599760094 |
| Short name | T989 |
| Test name | |
| Test status | |
| Simulation time | 1168076457 ps |
| CPU time | 3.69 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:18 AM UTC 24 |
| Peak memory | 211304 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=599760094 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+tg l+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr _stress_all_with_rand_reset.599760094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup.1380176603 |
| Short name | T973 |
| Test name | |
| Test status | |
| Simulation time | 154522543 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:31:12 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 208260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380176603 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup.1380176603 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/49.pwrmgr_wakeup_reset.3028438541 |
| Short name | T964 |
| Test name | |
| Test status | |
| Simulation time | 69824142 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:31:13 AM UTC 24 |
| Finished | Sep 04 02:31:15 AM UTC 24 |
| Peak memory | 211152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028438541 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.pwrmgr_wakeup_reset.3028438541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/49.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_aborted_low_power.2663550699 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 59508590 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:26:40 AM UTC 24 |
| Finished | Sep 04 02:26:44 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663550699 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_aborted_low_power.2663550699 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_disable_rom_integrity_check.3129351545 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 64595224 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:26:44 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129351545 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_disable_rom_integrity_check.3129351545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_esc_clk_rst_malfunc.807648275 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 31178104 ps |
| CPU time | 0.54 seconds |
| Started | Sep 04 02:26:42 AM UTC 24 |
| Finished | Sep 04 02:26:43 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=807648275 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres sion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_esc_clk_rst_malfunc.807648275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_escalation_timeout.3932219324 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 209447914 ps |
| CPU time | 0.86 seconds |
| Started | Sep 04 02:26:44 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932219324 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_escalation_timeout.3932219324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_glitch.3272190575 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 58748181 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:26:44 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 206212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272190575 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_glitch.3272190575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_global_esc.4035464381 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 51081372 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:26:44 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035464381 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_global_esc.4035464381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_lowpower_wakeup_race.119349174 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 615233008 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:26:38 AM UTC 24 |
| Finished | Sep 04 02:26:43 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=119349174 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_lowpower_wakeup_race.119349174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset.745373334 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 58559158 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:26:38 AM UTC 24 |
| Finished | Sep 04 02:26:43 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=745373334 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset.745373334 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_reset_invalid.1058949051 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 121383460 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:26:44 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 220188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1058949051 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_reset_invalid.1058949051 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_ctrl_config_regwen.1780773007 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 409838305 ps |
| CPU time | 0.98 seconds |
| Started | Sep 04 02:26:43 AM UTC 24 |
| Finished | Sep 04 02:26:45 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780773007 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_ctrl_config_regwen.1780773007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2549082167 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 1166240688 ps |
| CPU time | 1.87 seconds |
| Started | Sep 04 02:26:40 AM UTC 24 |
| Finished | Sep 04 02:26:46 AM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2549082167 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.2549082167 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3547772087 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 817977306 ps |
| CPU time | 3.27 seconds |
| Started | Sep 04 02:26:41 AM UTC 24 |
| Finished | Sep 04 02:26:46 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547772087 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.3547772087 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3144305614 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 66320189 ps |
| CPU time | 0.84 seconds |
| Started | Sep 04 02:26:41 AM UTC 24 |
| Finished | Sep 04 02:26:43 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144305614 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_sec_cm_rstmgr_intersig_mubi.3144305614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_smoke.1078733993 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 33200267 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:26:38 AM UTC 24 |
| Finished | Sep 04 02:26:43 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078733993 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_smoke.1078733993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_stress_all.2759317422 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 956124770 ps |
| CPU time | 4.65 seconds |
| Started | Sep 04 02:26:46 AM UTC 24 |
| Finished | Sep 04 02:26:51 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2759317422 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_stress_all.2759317422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup.2877338232 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 125632764 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:26:39 AM UTC 24 |
| Finished | Sep 04 02:26:43 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2877338232 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup.2877338232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/5.pwrmgr_wakeup_reset.3731366059 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 65560107 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:26:40 AM UTC 24 |
| Finished | Sep 04 02:26:44 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731366059 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.pwrmgr_wakeup_reset.3731366059 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/5.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_aborted_low_power.2672828423 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 35534515 ps |
| CPU time | 0.81 seconds |
| Started | Sep 04 02:26:46 AM UTC 24 |
| Finished | Sep 04 02:26:48 AM UTC 24 |
| Peak memory | 210800 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2672828423 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_aborted_low_power.2672828423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_disable_rom_integrity_check.2428410814 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 87855752 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:26:48 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 210560 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2428410814 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_disable_rom_integrity_check.2428410814 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_esc_clk_rst_malfunc.2093874613 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 40552640 ps |
| CPU time | 0.52 seconds |
| Started | Sep 04 02:26:47 AM UTC 24 |
| Finished | Sep 04 02:27:42 AM UTC 24 |
| Peak memory | 206228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2093874613 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_esc_clk_rst_malfunc.2093874613 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_escalation_timeout.2463491003 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 547824049 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:26:48 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2463491003 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_escalation_timeout.2463491003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_glitch.3339506453 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 62078916 ps |
| CPU time | 0.66 seconds |
| Started | Sep 04 02:26:48 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339506453 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_glitch.3339506453 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_global_esc.2203516261 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 38582355 ps |
| CPU time | 0.56 seconds |
| Started | Sep 04 02:26:48 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 207852 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2203516261 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_global_esc.2203516261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_lowpower_wakeup_race.4202629694 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 202528773 ps |
| CPU time | 1.04 seconds |
| Started | Sep 04 02:26:46 AM UTC 24 |
| Finished | Sep 04 02:26:48 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4202629694 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_lowpower_wakeup_race.4202629694 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset.1644684741 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 55888022 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:26:46 AM UTC 24 |
| Finished | Sep 04 02:26:48 AM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1644684741 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset.1644684741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_reset_invalid.3899892208 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 166498305 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:26:48 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3899892208 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_reset_invalid.3899892208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_ctrl_config_regwen.2532707712 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 145876411 ps |
| CPU time | 0.8 seconds |
| Started | Sep 04 02:26:48 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 207928 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532707712 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_ctrl_config_regwen.2532707712 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3765574940 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 799861908 ps |
| CPU time | 2.95 seconds |
| Started | Sep 04 02:26:46 AM UTC 24 |
| Finished | Sep 04 02:26:50 AM UTC 24 |
| Peak memory | 211336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3765574940 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.3765574940 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_sec_cm_rstmgr_intersig_mubi.3982126301 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 68692965 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:26:47 AM UTC 24 |
| Finished | Sep 04 02:27:46 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3982126301 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_sec_cm_rstmgr_intersig_mubi.3982126301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all.507321110 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 968029852 ps |
| CPU time | 3.4 seconds |
| Started | Sep 04 02:26:52 AM UTC 24 |
| Finished | Sep 04 02:27:16 AM UTC 24 |
| Peak memory | 211132 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=507321110 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_stress_all.507321110 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_stress_all_with_rand_reset.2174975677 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 2296264067 ps |
| CPU time | 5.74 seconds |
| Started | Sep 04 02:26:51 AM UTC 24 |
| Finished | Sep 04 02:27:19 AM UTC 24 |
| Peak memory | 211436 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2174975677 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr _stress_all_with_rand_reset.2174975677 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup.1064880942 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 262562852 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:26:46 AM UTC 24 |
| Finished | Sep 04 02:26:48 AM UTC 24 |
| Peak memory | 208256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064880942 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup.1064880942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/6.pwrmgr_wakeup_reset.1638780917 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 184356598 ps |
| CPU time | 0.91 seconds |
| Started | Sep 04 02:26:46 AM UTC 24 |
| Finished | Sep 04 02:26:48 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1638780917 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.pwrmgr_wakeup_reset.1638780917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/6.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_aborted_low_power.3224017482 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 34284577 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:00 AM UTC 24 |
| Finished | Sep 04 02:27:14 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224017482 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_aborted_low_power.3224017482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_disable_rom_integrity_check.1206044073 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 72100082 ps |
| CPU time | 0.67 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1206044073 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_disable_rom_integrity_check.1206044073 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_esc_clk_rst_malfunc.3319695470 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 29846880 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:27:00 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 206220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319695470 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_esc_clk_rst_malfunc.3319695470 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_escalation_timeout.1916027682 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 384600914 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:27:02 AM UTC 24 |
| Finished | Sep 04 02:27:14 AM UTC 24 |
| Peak memory | 206028 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1916027682 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_escalation_timeout.1916027682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_glitch.3906403890 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 46111209 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906403890 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_glitch.3906403890 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_global_esc.2747269682 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 53376686 ps |
| CPU time | 0.51 seconds |
| Started | Sep 04 02:27:02 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 205896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2747269682 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_global_esc.2747269682 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_invalid.1756700244 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 44395974 ps |
| CPU time | 0.71 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:07 AM UTC 24 |
| Peak memory | 210864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756700244 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_invalid.1756700244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_lowpower_wakeup_race.1269177387 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 278375213 ps |
| CPU time | 1.15 seconds |
| Started | Sep 04 02:26:54 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269177387 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_lowpower_wakeup_race.1269177387 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset.355751785 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 42822579 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:26:54 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355751785 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset.355751785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_reset_invalid.1064579550 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 170292325 ps |
| CPU time | 0.68 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:14 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1064579550 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_reset_invalid.1064579550 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_ctrl_config_regwen.622421179 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 82706333 ps |
| CPU time | 0.63 seconds |
| Started | Sep 04 02:27:01 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=622421179 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_ctrl_config_regwen.622421179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1590729426 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 802985903 ps |
| CPU time | 2.49 seconds |
| Started | Sep 04 02:27:00 AM UTC 24 |
| Finished | Sep 04 02:27:16 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590729426 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.1590729426 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3898075607 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 1276544840 ps |
| CPU time | 1.96 seconds |
| Started | Sep 04 02:27:00 AM UTC 24 |
| Finished | Sep 04 02:27:16 AM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3898075607 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.3898075607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2317117111 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 196469787 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:27:00 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317117111 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_sec_cm_rstmgr_intersig_mubi.2317117111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_smoke.938451325 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 28086366 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:26:54 AM UTC 24 |
| Finished | Sep 04 02:27:03 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=938451325 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_smoke.938451325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all.856305292 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 2383289546 ps |
| CPU time | 3.01 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:10 AM UTC 24 |
| Peak memory | 211668 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=856305292 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_stress_all.856305292 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_stress_all_with_rand_reset.1376043856 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 39918716929 ps |
| CPU time | 12.47 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:19 AM UTC 24 |
| Peak memory | 211556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1376043856 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr _stress_all_with_rand_reset.1376043856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup.690639411 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 272064333 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:26:57 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690639411 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup.690639411 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/7.pwrmgr_wakeup_reset.1688107365 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 281144043 ps |
| CPU time | 1.14 seconds |
| Started | Sep 04 02:26:59 AM UTC 24 |
| Finished | Sep 04 02:27:15 AM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1688107365 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.pwrmgr_wakeup_reset.1688107365 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/7.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_aborted_low_power.3184207108 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 88134330 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:08 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184207108 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_aborted_low_power.3184207108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_disable_rom_integrity_check.2462628902 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 150999696 ps |
| CPU time | 0.6 seconds |
| Started | Sep 04 02:27:09 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2462628902 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_disable_rom_integrity_check.2462628902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_esc_clk_rst_malfunc.3466147149 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 31219713 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:27:08 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 205940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3466147149 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_esc_clk_rst_malfunc.3466147149 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_escalation_timeout.1674720927 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 109013479 ps |
| CPU time | 0.76 seconds |
| Started | Sep 04 02:27:09 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1674720927 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_escalation_timeout.1674720927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_glitch.92715544 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 50920257 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:27:09 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 208516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=92715544 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_glitch.92715544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_global_esc.2150584371 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 54538440 ps |
| CPU time | 0.5 seconds |
| Started | Sep 04 02:27:09 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150584371 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_global_esc.2150584371 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_invalid.67025151 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 84423928 ps |
| CPU time | 0.62 seconds |
| Started | Sep 04 02:27:10 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 210792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67025151 -assert nopostproc +UVM_TESTNAME=pwrmgr _base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_invalid.67025151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_lowpower_wakeup_race.3309243304 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 69440356 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:08 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309243304 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_lowpower_wakeup_race.3309243304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset.3666770660 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 66267718 ps |
| CPU time | 0.61 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:08 AM UTC 24 |
| Peak memory | 209020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3666770660 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset.3666770660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_reset_invalid.3138221547 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 144732697 ps |
| CPU time | 0.7 seconds |
| Started | Sep 04 02:27:09 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 220184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3138221547 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_reset_invalid.3138221547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_ctrl_config_regwen.143329567 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 204236790 ps |
| CPU time | 0.72 seconds |
| Started | Sep 04 02:27:08 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 208000 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143329567 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os _regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_ctrl_config_regwen.143329567 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2144896672 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 907445806 ps |
| CPU time | 2.87 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:20 AM UTC 24 |
| Peak memory | 211348 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144896672 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.2144896672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1728482756 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 857811388 ps |
| CPU time | 3.1 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:20 AM UTC 24 |
| Peak memory | 211216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1728482756 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.1728482756 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2761594924 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 103919864 ps |
| CPU time | 0.78 seconds |
| Started | Sep 04 02:27:06 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2761594924 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_sec_cm_rstmgr_intersig_mubi.2761594924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_smoke.240906438 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 29174563 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:07 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240906438 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_smoke.240906438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all.3925933478 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 2506214874 ps |
| CPU time | 4.68 seconds |
| Started | Sep 04 02:27:11 AM UTC 24 |
| Finished | Sep 04 02:27:17 AM UTC 24 |
| Peak memory | 211480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3925933478 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_stress_all.3925933478 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_stress_all_with_rand_reset.2368086697 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 9737964054 ps |
| CPU time | 6.9 seconds |
| Started | Sep 04 02:27:10 AM UTC 24 |
| Finished | Sep 04 02:27:24 AM UTC 24 |
| Peak memory | 211492 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=2368086697 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr _stress_all_with_rand_reset.2368086697 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup.2040957250 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 221589964 ps |
| CPU time | 1.08 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:08 AM UTC 24 |
| Peak memory | 210860 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2040957250 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup.2040957250 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/8.pwrmgr_wakeup_reset.3271544202 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 106596152 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:27:05 AM UTC 24 |
| Finished | Sep 04 02:27:08 AM UTC 24 |
| Peak memory | 209092 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3271544202 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.pwrmgr_wakeup_reset.3271544202 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/8.pwrmgr_wakeup_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_aborted_low_power.2123889017 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 69710756 ps |
| CPU time | 0.75 seconds |
| Started | Sep 04 02:27:13 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 210748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2123889017 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_aborted_low_power_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim -vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_aborted_low_power.2123889017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_aborted_low_power/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_disable_rom_integrity_check.3272208452 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 326075648 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 210380 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3272208452 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_disable_rom_integrity_check_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/ os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_disable_rom_integrity_check.3272208452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_disable_rom_integrity_check/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_esc_clk_rst_malfunc.3484359040 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 31548311 ps |
| CPU time | 0.55 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 206224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3484359040 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_esc_clk_rst_malfunc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre ssion_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_esc_clk_rst_malfunc.3484359040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_esc_clk_rst_malfunc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_escalation_timeout.2558461231 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 114013151 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW - licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2558461231 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SE Q=pwrmgr_escalation_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-si m-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_escalation_timeout.2558461231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_escalation_timeout/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_glitch.1952952197 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 45573947 ps |
| CPU time | 0.59 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952952197 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_glitch_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09 _03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_glitch.1952952197 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_glitch/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_global_esc.3188299823 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 47344812 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 206216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNO TES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3188299823 -assert nopostproc +UVM_TESTNAME=p wrmgr_base_test +UVM_TEST_SEQ=pwrmgr_global_esc_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_ 2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_global_esc.3188299823 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_global_esc/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_invalid.2901385382 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 57229503 ps |
| CPU time | 0.64 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 210804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901385382 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_invalid.2901385382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_lowpower_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_lowpower_wakeup_race.2543129487 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 192967537 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:27:11 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2543129487 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_lowpower_wakeup_race_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_lowpower_wakeup_race.2543129487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_lowpower_wakeup_race/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset.122684017 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 67456012 ps |
| CPU time | 0.58 seconds |
| Started | Sep 04 02:27:11 AM UTC 24 |
| Finished | Sep 04 02:27:13 AM UTC 24 |
| Peak memory | 211156 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=122684017 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_0 3/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset.122684017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_reset_invalid.769426032 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 115678998 ps |
| CPU time | 0.73 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 220120 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=769426032 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_reset_invalid_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2 024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_reset_invalid.769426032 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_reset_invalid/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_ctrl_config_regwen.3784853684 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 204718225 ps |
| CPU time | 0.69 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=50000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3784853684 -assert nopostproc +UVM_TESTNAME=pwr mgr_base_test +UVM_TEST_SEQ=pwrmgr_sec_cm_ctrl_config_regwen_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o s_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_ctrl_config_regwen.3784853684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_ctrl_config_regwen/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1288993901 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 1188544863 ps |
| CPU time | 1.9 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:19 AM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=3000000 +pwrmgr_mubi_mode=PwrmgrMubiLcCtrl +cdc_instrum entation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1288993901 -a ssert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_di r /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_lc_ctrl_intersi g_mubi.1288993901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_lc_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1620863404 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 805241741 ps |
| CPU time | 2.71 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:20 AM UTC 24 |
| Peak memory | 211400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=4000000 +pwrmgr_mubi_mode=PwrmgrMubiRomCtrl +cdc_instru mentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1620863404 - assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_repeat_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_d ir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rom_ctrl_inter sig_mubi.1620863404 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rom_ctrl_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1527364744 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 64278840 ps |
| CPU time | 0.74 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:18 AM UTC 24 |
| Peak memory | 208268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1527364744 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_sw_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_sec_cm_rstmgr_intersig_mubi.1527364744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_sec_cm_rstmgr_intersig_mubi/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_smoke.2531636185 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 27089879 ps |
| CPU time | 0.57 seconds |
| Started | Sep 04 02:27:11 AM UTC 24 |
| Finished | Sep 04 02:27:12 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2531636185 -assert nopostproc +UVM_TESTNAME=pwrm gr_base_test +UVM_TEST_SEQ=pwrmgr_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_smoke.2531636185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all.1823741574 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 2958394617 ps |
| CPU time | 3.77 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:31 AM UTC 24 |
| Peak memory | 210760 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELN OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1823741574 -assert nopostproc +UVM_TESTNAME= pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_stress_all.1823741574 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_stress_all_with_rand_reset.1153197129 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 11957397823 ps |
| CPU time | 15.71 seconds |
| Started | Sep 04 02:27:15 AM UTC 24 |
| Finished | Sep 04 02:27:43 AM UTC 24 |
| Peak memory | 210732 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq =pwrmgr_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/si m.tcl +ntb_random_seed=1153197129 -assert nopostproc +UVM_TESTNAME=pwrmgr_base_test +UVM_TEST_SEQ=pwrmgr_common_vseq +en_cov=1 -cm line+cond+fsm+t gl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr _stress_all_with_rand_reset.1153197129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup.336077232 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 426713520 ps |
| CPU time | 0.77 seconds |
| Started | Sep 04 02:27:13 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 208264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336077232 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_09_ 03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup.336077232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_wakeup/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/coverage/default/9.pwrmgr_wakeup_reset.257755960 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 249297552 ps |
| CPU time | 0.79 seconds |
| Started | Sep 04 02:27:13 AM UTC 24 |
| Finished | Sep 04 02:27:28 AM UTC 24 |
| Peak memory | 211096 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/default/simv +test_timeout_ns=1000000 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257755960 -assert nopostproc +UVM_TESTNAME=pwrmg r_base_test +UVM_TEST_SEQ=pwrmgr_wakeup_reset_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_20 24_09_03/pwrmgr-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.pwrmgr_wakeup_reset.257755960 |
| Directory | /workspaces/repo/scratch/os_regression_2024_09_03/pwrmgr-sim-vcs/9.pwrmgr_wakeup_reset/latest |
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