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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.96 98.21 96.58 99.62 96.00 96.32 100.00 99.02


Total test records in report: 1070
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html | tests19.html | tests20.html | tests21.html | tests22.html

T328 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3063924678 Sep 24 08:43:12 AM UTC 24 Sep 24 08:43:16 AM UTC 24 1261449708 ps
T329 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_ctrl_config_regwen.2250360082 Sep 24 08:43:14 AM UTC 24 Sep 24 08:43:16 AM UTC 24 414692473 ps
T330 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_escalation_timeout.770606783 Sep 24 08:43:14 AM UTC 24 Sep 24 08:43:16 AM UTC 24 115507333 ps
T331 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3602286786 Sep 24 08:43:12 AM UTC 24 Sep 24 08:43:16 AM UTC 24 958330178 ps
T332 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_smoke.4064296373 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:20 AM UTC 24 51121426 ps
T333 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_reset_invalid.2773078146 Sep 24 08:43:18 AM UTC 24 Sep 24 08:43:20 AM UTC 24 161890506 ps
T334 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset.3926690365 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 61111040 ps
T335 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_glitch.2902265168 Sep 24 08:43:18 AM UTC 24 Sep 24 08:43:21 AM UTC 24 60812091 ps
T336 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset.3794611767 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:27 AM UTC 24 90166507 ps
T337 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1790878258 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:27 AM UTC 24 1404111891 ps
T338 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all.2490944552 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:30 AM UTC 24 865503159 ps
T339 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_disable_rom_integrity_check.37395475 Sep 24 08:43:18 AM UTC 24 Sep 24 08:43:21 AM UTC 24 60569526 ps
T340 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset.805470652 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 33974685 ps
T341 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_glitch.2282792753 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 57731181 ps
T342 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup.2194938312 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 232451079 ps
T343 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_esc_clk_rst_malfunc.249722290 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 37383832 ps
T344 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_wakeup_reset.3497332054 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 409869238 ps
T345 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_wakeup_reset.640479496 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 739865568 ps
T346 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_lowpower_wakeup_race.1879466615 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 102585153 ps
T347 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_global_esc.3863837495 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 58676869 ps
T348 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rstmgr_intersig_mubi.703462738 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 53677396 ps
T349 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_aborted_low_power.3856869014 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 146838998 ps
T182 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_disable_rom_integrity_check.796122190 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 83053018 ps
T350 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_escalation_timeout.3624987629 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 108635844 ps
T351 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_smoke.1669692898 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 91604677 ps
T352 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_global_esc.409507112 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 66234636 ps
T353 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_glitch.827694178 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 59428429 ps
T354 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_reset_invalid.2426499227 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:21 AM UTC 24 114594525 ps
T355 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all.879301684 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:22 AM UTC 24 352064571 ps
T356 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_ctrl_config_regwen.3134540859 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:22 AM UTC 24 229798165 ps
T357 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all.3038949513 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:22 AM UTC 24 813197435 ps
T358 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1984468286 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:23 AM UTC 24 877528535 ps
T359 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3387894803 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:23 AM UTC 24 891420526 ps
T360 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/13.pwrmgr_stress_all_with_rand_reset.2655619642 Sep 24 08:43:18 AM UTC 24 Sep 24 08:43:24 AM UTC 24 2593591262 ps
T361 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_lowpower_wakeup_race.4292059941 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 118678593 ps
T112 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_aborted_low_power.1341491452 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 56656908 ps
T362 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_esc_clk_rst_malfunc.3167166805 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 27472156 ps
T363 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_glitch.2620410594 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 52564995 ps
T364 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_global_esc.332271165 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 30078458 ps
T365 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup.1258046521 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 97431120 ps
T183 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_disable_rom_integrity_check.2722966552 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 81904140 ps
T366 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_wakeup_reset.3679449078 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 330523782 ps
T367 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_ctrl_config_regwen.637826458 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 693113124 ps
T368 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset.2818553462 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 70678142 ps
T369 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_rstmgr_intersig_mubi.4015652700 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 69022276 ps
T370 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_smoke.622768857 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 34669431 ps
T371 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_smoke.3557563696 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 34086311 ps
T372 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_escalation_timeout.2175165728 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 404527810 ps
T373 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_reset_invalid.2493693045 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:26 AM UTC 24 125316934 ps
T374 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1321774497 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:27 AM UTC 24 896139885 ps
T144 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/12.pwrmgr_stress_all_with_rand_reset.3100888561 Sep 24 08:43:12 AM UTC 24 Sep 24 08:43:29 AM UTC 24 5596030382 ps
T375 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rstmgr_intersig_mubi.57934253 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 65918475 ps
T376 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_aborted_low_power.1018824925 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 63578223 ps
T377 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_lowpower_wakeup_race.1006219691 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 249968880 ps
T378 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup_reset.1516088934 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:50 AM UTC 24 249925952 ps
T190 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_disable_rom_integrity_check.4265693705 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 79978801 ps
T379 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_escalation_timeout.400221132 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 203086115 ps
T380 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_aborted_low_power.379363749 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 18521927 ps
T381 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_reset_invalid.3242218897 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:32 AM UTC 24 96911002 ps
T382 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/14.pwrmgr_stress_all_with_rand_reset.216063396 Sep 24 08:43:19 AM UTC 24 Sep 24 08:43:33 AM UTC 24 7137856158 ps
T383 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup_reset.4121292864 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:33 AM UTC 24 109720537 ps
T384 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_ctrl_config_regwen.3113638836 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:33 AM UTC 24 198383487 ps
T385 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_lowpower_wakeup_race.1246271089 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:33 AM UTC 24 327801155 ps
T386 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_wakeup.3812574472 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:33 AM UTC 24 296896738 ps
T387 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3516357737 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:34 AM UTC 24 837915102 ps
T388 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3976383705 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:34 AM UTC 24 989038748 ps
T389 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1442255045 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:35 AM UTC 24 895078518 ps
T390 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all.363838134 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:35 AM UTC 24 664422482 ps
T391 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_esc_clk_rst_malfunc.343765086 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:36 AM UTC 24 32446542 ps
T392 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rstmgr_intersig_mubi.3436057749 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:36 AM UTC 24 50334755 ps
T393 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_glitch.3886290019 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:36 AM UTC 24 66825313 ps
T394 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_global_esc.78769581 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:36 AM UTC 24 56522318 ps
T395 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all.189587399 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:52 AM UTC 24 2410083998 ps
T396 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_smoke.2283250347 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:36 AM UTC 24 55631214 ps
T397 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_escalation_timeout.598455580 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:36 AM UTC 24 401381420 ps
T398 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_disable_rom_integrity_check.1811036462 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:36 AM UTC 24 65421283 ps
T399 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_ctrl_config_regwen.3270101241 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:36 AM UTC 24 248767683 ps
T400 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset.3111385538 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:37 AM UTC 24 69736667 ps
T401 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_reset_invalid.2929238334 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:37 AM UTC 24 93116823 ps
T145 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/15.pwrmgr_stress_all_with_rand_reset.2373824557 Sep 24 08:43:24 AM UTC 24 Sep 24 08:43:37 AM UTC 24 7183937879 ps
T146 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all_with_rand_reset.2080610678 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:38 AM UTC 24 1072116162 ps
T402 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3221158493 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:39 AM UTC 24 961599341 ps
T403 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/17.pwrmgr_stress_all.281556072 Sep 24 08:43:34 AM UTC 24 Sep 24 08:43:41 AM UTC 24 2357820159 ps
T404 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/16.pwrmgr_stress_all_with_rand_reset.3949428473 Sep 24 08:43:30 AM UTC 24 Sep 24 08:43:41 AM UTC 24 2554787961 ps
T405 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all.1741882610 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:50 AM UTC 24 2000632751 ps
T406 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_esc_clk_rst_malfunc.2168217717 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 39979585 ps
T407 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_aborted_low_power.3349917497 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 17562989 ps
T408 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup.1883975238 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 52956876 ps
T409 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_lowpower_wakeup_race.3410865320 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 330232372 ps
T410 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_global_esc.1845241034 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 34904047 ps
T411 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_glitch.4161102288 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 45281419 ps
T412 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_smoke.3401904759 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:54 AM UTC 24 30979492 ps
T413 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_ctrl_config_regwen.1085142648 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 149858915 ps
T414 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_esc_clk_rst_malfunc.1817094969 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:52 AM UTC 24 35843502 ps
T415 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_disable_rom_integrity_check.3549132837 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 80337542 ps
T416 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_glitch.491473655 Sep 24 08:43:48 AM UTC 24 Sep 24 08:43:52 AM UTC 24 37739840 ps
T417 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_escalation_timeout.735247718 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 220043555 ps
T418 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_reset_invalid.2069520721 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 179718252 ps
T419 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_lowpower_wakeup_race.3882187623 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:50 AM UTC 24 342572735 ps
T420 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_smoke.3730025425 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 31953732 ps
T421 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset.2168567943 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 23465335 ps
T422 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rstmgr_intersig_mubi.3330837231 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:42 AM UTC 24 78224176 ps
T423 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_aborted_low_power.188541938 Sep 24 08:43:41 AM UTC 24 Sep 24 08:43:43 AM UTC 24 143106203 ps
T424 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_lowpower_wakeup_race.1221720637 Sep 24 08:43:41 AM UTC 24 Sep 24 08:43:43 AM UTC 24 165839692 ps
T425 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_wakeup_reset.2949053566 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:43 AM UTC 24 313995193 ps
T426 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup.2765476451 Sep 24 08:43:41 AM UTC 24 Sep 24 08:43:43 AM UTC 24 157908484 ps
T427 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rstmgr_intersig_mubi.3966989210 Sep 24 08:43:41 AM UTC 24 Sep 24 08:43:43 AM UTC 24 173968694 ps
T428 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_wakeup_reset.3972382313 Sep 24 08:43:41 AM UTC 24 Sep 24 08:43:43 AM UTC 24 389850892 ps
T429 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3522816284 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:44 AM UTC 24 983604209 ps
T430 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1809531258 Sep 24 08:43:41 AM UTC 24 Sep 24 08:43:44 AM UTC 24 1167966196 ps
T431 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2802731880 Sep 24 08:43:41 AM UTC 24 Sep 24 08:43:44 AM UTC 24 1024247335 ps
T432 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4015791571 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:45 AM UTC 24 836833104 ps
T433 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_esc_clk_rst_malfunc.1896704312 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:48 AM UTC 24 33003514 ps
T434 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_global_esc.360823661 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 52776741 ps
T435 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_glitch.3960121270 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 32162908 ps
T436 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1891660489 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:51 AM UTC 24 1566704079 ps
T184 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_disable_rom_integrity_check.4194876020 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 54871984 ps
T437 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_escalation_timeout.3695297568 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 391810888 ps
T438 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_reset_invalid.2792084040 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 145501473 ps
T439 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_wakeup.2174774512 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 201429617 ps
T440 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_sec_cm_ctrl_config_regwen.1255838486 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 336966600 ps
T441 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_smoke.3636908207 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 36623390 ps
T442 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_aborted_low_power.3750656258 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 52437598 ps
T443 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset.2729077311 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:49 AM UTC 24 153592657 ps
T444 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/18.pwrmgr_stress_all_with_rand_reset.42926690 Sep 24 08:43:40 AM UTC 24 Sep 24 08:43:50 AM UTC 24 3092517900 ps
T445 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_global_esc.1139285854 Sep 24 08:43:48 AM UTC 24 Sep 24 08:43:52 AM UTC 24 53349272 ps
T446 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rstmgr_intersig_mubi.2197760945 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:52 AM UTC 24 68593468 ps
T447 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_escalation_timeout.1880821257 Sep 24 08:43:48 AM UTC 24 Sep 24 08:43:52 AM UTC 24 387669884 ps
T448 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_ctrl_config_regwen.2258438290 Sep 24 08:43:48 AM UTC 24 Sep 24 08:43:53 AM UTC 24 431158948 ps
T185 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_disable_rom_integrity_check.4086460974 Sep 24 08:43:48 AM UTC 24 Sep 24 08:43:53 AM UTC 24 63859854 ps
T449 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_reset_invalid.3817794970 Sep 24 08:43:48 AM UTC 24 Sep 24 08:43:53 AM UTC 24 118008734 ps
T450 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3865417991 Sep 24 08:43:47 AM UTC 24 Sep 24 08:43:54 AM UTC 24 1256043597 ps
T451 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset_invalid.4002280793 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 101172291 ps
T452 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup.2795601141 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:55 AM UTC 24 198242365 ps
T453 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset.724011019 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 71281384 ps
T454 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_global_esc.3555046936 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:56 AM UTC 24 62361035 ps
T455 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_ctrl_config_regwen.1395064000 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:56 AM UTC 24 113256508 ps
T456 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_glitch.1586423778 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:56 AM UTC 24 60668056 ps
T457 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_escalation_timeout.2051372103 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:56 AM UTC 24 429760190 ps
T458 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all.2784866438 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:56 AM UTC 24 1168501291 ps
T459 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset.634458743 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:58 AM UTC 24 132980978 ps
T460 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_lowpower_wakeup_race.2987152676 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:58 AM UTC 24 186283735 ps
T461 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_esc_clk_rst_malfunc.2245959688 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:58 AM UTC 24 29930004 ps
T462 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_aborted_low_power.2283647834 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:58 AM UTC 24 97673981 ps
T463 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rstmgr_intersig_mubi.153043246 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:58 AM UTC 24 91798016 ps
T464 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_wakeup_reset.1934636325 Sep 24 08:43:53 AM UTC 24 Sep 24 08:43:58 AM UTC 24 268397461 ps
T465 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.773663317 Sep 24 08:43:53 AM UTC 24 Sep 24 08:44:00 AM UTC 24 838385778 ps
T466 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_global_esc.3458812138 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 32615465 ps
T467 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2638681181 Sep 24 08:43:53 AM UTC 24 Sep 24 08:44:00 AM UTC 24 764605400 ps
T468 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_disable_rom_integrity_check.3555785421 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 64514770 ps
T469 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_smoke.2661978664 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 57279616 ps
T470 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset.977540040 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 132388194 ps
T471 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_lowpower_wakeup_race.3630994303 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 90068215 ps
T472 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all.2940765611 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:13 AM UTC 24 1323043038 ps
T473 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_glitch.1237669570 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:16 AM UTC 24 69572067 ps
T474 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup.4262349581 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 62836598 ps
T475 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_reset_invalid.4146385547 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 148481954 ps
T476 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/19.pwrmgr_stress_all_with_rand_reset.20503611 Sep 24 08:43:47 AM UTC 24 Sep 24 08:44:01 AM UTC 24 3165368628 ps
T477 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rstmgr_intersig_mubi.3672646551 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 89381728 ps
T478 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_aborted_low_power.2088675670 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 47500333 ps
T479 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_esc_clk_rst_malfunc.2050195744 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 29955740 ps
T480 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_global_esc.2786304527 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 39188859 ps
T481 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_wakeup_reset.1119623305 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 465231292 ps
T482 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_glitch.2631773254 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 61892816 ps
T483 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_disable_rom_integrity_check.3918674825 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 64892488 ps
T484 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_escalation_timeout.3480692523 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 114985847 ps
T485 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_reset_invalid.177667115 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 110250557 ps
T486 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_ctrl_config_regwen.1034859285 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:01 AM UTC 24 235130734 ps
T487 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.1463795594 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:02 AM UTC 24 3534928488 ps
T488 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.1743837021 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:03 AM UTC 24 879183677 ps
T489 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all_with_rand_reset.2557053836 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:04 AM UTC 24 4594613123 ps
T490 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/21.pwrmgr_stress_all.1581516838 Sep 24 08:43:59 AM UTC 24 Sep 24 08:44:04 AM UTC 24 3035457509 ps
T491 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.3755541722 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:10 AM UTC 24 1360343483 ps
T80 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all_with_rand_reset.69697666 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:13 AM UTC 24 1379253929 ps
T492 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_smoke.1400314207 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:08 AM UTC 24 64177277 ps
T493 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset.849261320 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:08 AM UTC 24 78663123 ps
T494 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_aborted_low_power.2869676820 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:08 AM UTC 24 67558200 ps
T495 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_smoke.1030223854 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 30889279 ps
T496 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_global_esc.342708607 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:08 AM UTC 24 213676134 ps
T497 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_esc_clk_rst_malfunc.2414983112 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:08 AM UTC 24 29804737 ps
T498 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_glitch.749865291 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:08 AM UTC 24 24761249 ps
T499 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup.3352278033 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:08 AM UTC 24 308198868 ps
T500 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_rstmgr_intersig_mubi.3056213300 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:08 AM UTC 24 98614705 ps
T501 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_ctrl_config_regwen.2704569523 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:08 AM UTC 24 134215776 ps
T502 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_lowpower_wakeup_race.3222096512 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:09 AM UTC 24 367794865 ps
T503 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_wakeup_reset.2760239673 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:09 AM UTC 24 354658045 ps
T504 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_disable_rom_integrity_check.84474048 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:09 AM UTC 24 73685409 ps
T505 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_global_esc.3719775743 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 43401035 ps
T506 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup.561710463 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:09 AM UTC 24 47813156 ps
T507 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_smoke.1461832521 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:09 AM UTC 24 64026947 ps
T508 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_escalation_timeout.2490437851 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:09 AM UTC 24 389669793 ps
T509 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_reset.3379638694 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:09 AM UTC 24 69559479 ps
T510 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_reset_invalid.3600863052 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:09 AM UTC 24 96111316 ps
T511 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_wakeup_reset.4148626443 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:09 AM UTC 24 278878614 ps
T512 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_lowpower_wakeup_race.1568298849 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:09 AM UTC 24 222117225 ps
T81 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/20.pwrmgr_stress_all_with_rand_reset.458733781 Sep 24 08:43:52 AM UTC 24 Sep 24 08:44:10 AM UTC 24 10531007624 ps
T513 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.2092759563 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:10 AM UTC 24 947741707 ps
T514 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/22.pwrmgr_stress_all.22869580 Sep 24 08:44:06 AM UTC 24 Sep 24 08:44:11 AM UTC 24 1573522456 ps
T515 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_esc_clk_rst_malfunc.2135597522 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:16 AM UTC 24 33098299 ps
T516 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_ctrl_config_regwen.2973959398 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 157699941 ps
T517 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rstmgr_intersig_mubi.850953957 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 159289819 ps
T518 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_aborted_low_power.2749674718 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 27689413 ps
T519 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_disable_rom_integrity_check.1821912683 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 140281879 ps
T520 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_escalation_timeout.2811973190 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 404843997 ps
T521 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_lowpower_wakeup_race.3371052368 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 642570055 ps
T522 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_esc_clk_rst_malfunc.3786839288 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 44804827 ps
T523 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_aborted_low_power.2702658640 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 52839323 ps
T524 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_ctrl_config_regwen.1606545340 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 275034761 ps
T525 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rstmgr_intersig_mubi.1387619881 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 191669355 ps
T526 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_glitch.2866122987 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 49884622 ps
T527 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup.1438226655 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 236151667 ps
T528 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_wakeup_reset.2986957826 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 261774080 ps
T529 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_escalation_timeout.2164222151 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:17 AM UTC 24 470346547 ps
T530 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.4256437844 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:18 AM UTC 24 1011549745 ps
T531 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all.438034750 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:18 AM UTC 24 1052812527 ps
T532 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.4152428088 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:18 AM UTC 24 908455448 ps
T533 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3424476073 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:19 AM UTC 24 895826498 ps
T534 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.711737199 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:20 AM UTC 24 813073328 ps
T535 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/23.pwrmgr_stress_all_with_rand_reset.1007101928 Sep 24 08:44:07 AM UTC 24 Sep 24 08:44:20 AM UTC 24 17920893598 ps
T536 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_disable_rom_integrity_check.3143555878 Sep 24 08:44:24 AM UTC 24 Sep 24 08:44:26 AM UTC 24 70362987 ps
T537 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_reset_invalid.2464614910 Sep 24 08:44:24 AM UTC 24 Sep 24 08:44:26 AM UTC 24 161648355 ps
T538 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_sec_cm_rstmgr_intersig_mubi.2937165630 Sep 24 08:44:34 AM UTC 24 Sep 24 08:44:36 AM UTC 24 164845225 ps
T539 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_smoke.3228425897 Sep 24 08:44:24 AM UTC 24 Sep 24 08:44:26 AM UTC 24 30629333 ps
T540 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_aborted_low_power.3904679785 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:26 AM UTC 24 25447267 ps
T541 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_disable_rom_integrity_check.651466216 Sep 24 08:44:34 AM UTC 24 Sep 24 08:44:36 AM UTC 24 61874345 ps
T542 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset.3379596717 Sep 24 08:44:24 AM UTC 24 Sep 24 08:44:26 AM UTC 24 104721780 ps
T543 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_esc_clk_rst_malfunc.685044077 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:26 AM UTC 24 38905224 ps
T544 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup.615371054 Sep 24 08:44:24 AM UTC 24 Sep 24 08:44:26 AM UTC 24 76610156 ps
T545 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_global_esc.2988590521 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:26 AM UTC 24 39443098 ps
T546 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_lowpower_wakeup_race.3638159544 Sep 24 08:44:24 AM UTC 24 Sep 24 08:44:27 AM UTC 24 339557936 ps
T547 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rstmgr_intersig_mubi.3930125613 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 90743577 ps
T548 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_smoke.3496308880 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 32759705 ps
T549 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_glitch.985828804 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 76309050 ps
T550 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_aborted_low_power.718795183 Sep 24 08:44:34 AM UTC 24 Sep 24 08:44:36 AM UTC 24 45975793 ps
T551 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_disable_rom_integrity_check.2574001779 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 67067384 ps
T552 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_ctrl_config_regwen.1713529372 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 384809735 ps
T553 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_escalation_timeout.1281765320 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 114530324 ps
T554 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_wakeup_reset.3003445965 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 225231955 ps
T555 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_reset_invalid.1806040541 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 100023297 ps
T556 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_aborted_low_power.899010044 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 72121347 ps
T557 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_lowpower_wakeup_race.2490122869 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 204062846 ps
T558 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup_reset.3751812145 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 96726567 ps
T559 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_reset.1020576784 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 110021773 ps
T560 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/27.pwrmgr_wakeup.317245439 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:27 AM UTC 24 240597545 ps
T561 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_lc_ctrl_intersig_mubi.3133239346 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:28 AM UTC 24 1198716955 ps
T562 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_sec_cm_rom_ctrl_intersig_mubi.2290515674 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:28 AM UTC 24 1307143539 ps
T563 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/24.pwrmgr_stress_all_with_rand_reset.1323356549 Sep 24 08:44:15 AM UTC 24 Sep 24 08:44:28 AM UTC 24 3134247235 ps
T564 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/25.pwrmgr_stress_all.2446350912 Sep 24 08:44:24 AM UTC 24 Sep 24 08:44:29 AM UTC 24 2579983001 ps
T565 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/28.pwrmgr_escalation_timeout.1972556891 Sep 24 08:44:34 AM UTC 24 Sep 24 08:44:36 AM UTC 24 398587866 ps
T566 /workspaces/repo/scratch/os_regression_2024_09_23/pwrmgr-sim-vcs/coverage/default/26.pwrmgr_stress_all.1360671730 Sep 24 08:44:25 AM UTC 24 Sep 24 08:44:32 AM UTC 24 2671742551 ps
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